TWM472292U - Dual port SRAM - Google Patents

Description

Double-click static random access memory

The present invention relates to a double random static random access memory (SRAM), especially a double-turning operation capable of high reliability and high stability even at high memory capacity. Static random access memory, which not only solves the problem of the conventional double-SRAM write logic 1 with a single write bit line, but also can avoid unnecessary power by charge recycling. Loss.

Memory plays an indispensable role in the computer industry. Generally, the memory can be classified into non-volatile memory and volatile memory, non-volatile memory, and stored according to whether it can save data after the power is turned off. It will not disappear due to power off or interruption, and the data stored in volatile memory will be eliminated as the power is turned off or interrupted. Common volatile memory types are dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory (DRAM) has the advantages of small area and low price, but it must be refreshed from time to time to prevent data from being lost due to leakage current, resulting in high speed and power consumption. Missing. Conversely, the operation of the static random access memory (SRAM) is simple and does not require an update operation, so it has the advantages of high speed and low power consumption.

The semiconductor memory devices currently used in mobile electronic devices represented by mobile phones are mainly SRAM.

A conventional static random access memory (SRAM), as shown in FIG. 1a, mainly includes a memory array, which is composed of a plurality of memory blocks (MB ₁ , MB). _2, etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells, each column The memory cell and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL _{2 ,} etc.), each word line corresponding to a plurality of columns of memory crystals One of the cells; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _{m ,} etc.), each bit line pair corresponding to one of the plurality of rows of memory cells And each bit line pair is composed of one bit line (BL ₁ ... BL _m ) and one complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b shows the circuit diagram of a 6T static random access memory (SRAM) cell. The PMOS transistors (P1) and (P2) are called load transistors and NMOS transistors (M1). And (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is word line, and BL and BLB They are a bit line and a complementary bit line, respectively. Since the SRAM cell requires six transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, the cell ratio) The cell ratio is usually set between 2.2 and 3.5, resulting in the difficulty of high integration and high price.

The HSPICE transient analysis simulation results of the 6T SRAM cell in the write operation shown in Figure 1b, as shown in Figure 2, are simulated in a level 49 model using TSMC 0.18 micron CMOS process parameters. .

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line. Compared with the 6T SRAM cell of Figure 1, the 5T static random access memory. The bulk cell has one transistor and one less bit line than the 6T SRAM cell, but the 5T SRAM cell does not change the PMOS transistors P11 and P12 and the NMOS transistor M11, M12 and M13 In the case of the channel width to length ratio (the purpose of not changing the channel width to length ratio of the PMOS transistors P11 and P12 and the NMOS transistors M11, M12, and M13 is to maintain the same static noise margin as the 6T static random access memory ( Static Noise Margin, SNM)) The problem of writing logic 1 is quite difficult. Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is modeled using the level 49 model using TSMC 0.18 micron CMOS process parameters. Simulation, from the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.

To date, many techniques have been proposed for a 5T SRAM cell with a single bit line, such as Non-Patent Document 1 (I. Carlson et al., "A high density, low leakage, 5T SRAM for embedded caches". , "Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, pp. 215-218, 2004.) The 5T SRAM is due to the redesign of the two of the unit cell, the two-load transistor And accessing the channel width-to-length ratio of the transistor to solve the problem of writing logic 1 is difficult, thereby causing damage to the symmetry relationship between the driving transistor and the load transistor in the original unit cell and thus being susceptible to process variation and Lower SNM; Non-Patent Document 2 (M. Wieckowski et al., "A novel five-transistor (5T) SRAM cell for high performance cache," IEEE Conference on SOC, pp. 1001-1002, 2005.) The 5T SRAM has a problem of reducing the access speed by setting a long channel length access transistor between the two load transistors in the unit cell to solve the problem of writing logic 1; Patent Document 3 (98) "Writed by TW M358390 on June 1, the year of the year" In the operation of the power supply voltage to reduce the static random access memory (the main representative figure as shown in Figure 5), although it can effectively solve the problem of writing logic 1 difficult, but the write operation, due to the lack of effective The discharge path must use dual supply voltages (HV _DD , LV _DD ), resulting in a complicated circuit structure and a lack of low write speed at high memory capacity and/or high speed operation. Patent Document 4 (No. TW M391711, November 1, 1999), "SRAM with discharge path" (the main representative figure is shown in Fig. 6), although a discharge path is provided to effectively solve the write. The logic 1 is difficult, but the circuit structure is still slightly complicated due to the need to use dual power supply voltages (HV _DD , LV _DD ). The "Memory System" proposed in Patent Document 5 (No. 7,706,062 B2, April 27, 1999) (the main representative of which is shown in Fig. 7) can effectively solve the problem of writing logic 1 and is provided with The discharge path, but during the write operation, since the discharge path is constantly turned on, that is, the NMOS transistors M24 and M21 located between the power supply voltage and the ground during the writing operation have a constant DC current flowing, thereby causing unnecessary power loss. Missing.

In view of this, the main purpose of the present invention is to propose a double-埠 static random access memory that provides a discharge path only at an initial time of one of the write operations, and after the initial time, the discharge is originally to be performed. The path is discharged by a recycling charge to avoid unnecessary power consumption.

The second objective of this creation is to propose a double-turn static random access memory that does not require the use of dual power supply voltages to avoid the lack of complex circuit structures.

A further object of the present invention is to provide a dual-band static random access memory capable of effectively avoiding the problem of writing logic 1 by a control circuit to effectively avoid the presence of a double-bit SRAM cell having a single bit line.

The present invention proposes a double-埠 static random access memory body, which mainly comprises a memory array, a plurality of word lines, a plurality of bit lines, and a plurality of control circuits (2), wherein the memory array is composed of a plurality of columns The memory cell is composed of a plurality of memory cells, each column of memory cells is provided with a control circuit (2), and each memory cell (1) includes a first inverter (by a first a PMOS transistor P1 and a first NMOS transistor M1), a second inverter (composed of a second PMOS transistor P2 and a second NMOS transistor M2), an access transistor ( A third NMOS transistor M3), a first and second read transistor (M4 and M5). The control circuit (2) discharges the potential of a high voltage node (VH) by a predetermined time when the corresponding write control signal (CTL) is at a logic high level representing the write mode, so as to the high node ( The potential of VH) is lowered by a power supply voltage supply voltage (V _DD ) to a voltage level at which the power supply voltage (V _DD ) is deducted by a V _TM24 (the threshold voltage of the seventh NMOS transistor (M24)). The problem of difficulty in writing logic 1 is effectively avoided in the write mode, wherein the write control signal (CTL) is a write enable (WE) signal and a corresponding write word line ( WWL) signal AND gate operation result, at this time, the write control signal is only when the write enable WE signal and the corresponding write word line (WWL) signal are both logic high level ( CTL) is logically high.

P1‧‧‧First PMOS transistor

P2‧‧‧Second PMOS transistor

M1‧‧‧First NMOS transistor

M2‧‧‧Second NMOS transistor

M3‧‧‧ third NMOS transistor

M4‧‧‧first read transistor

M5‧‧‧Second reading transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

V _DD ‧‧‧Power supply voltage

WBL‧‧‧Write bit line

WWL‧‧‧write word line

RBL‧‧‧Reading bit line

RWL‧‧‧Read word line

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

P21‧‧‧ Third PMOS transistor

P22‧‧‧4th PMOS transistor

1‧‧‧SRAM cell

2‧‧‧Control circuit

CTL‧‧‧ write control signal

VH‧‧‧ high voltage node

Figure 1a shows a conventional static random access memory; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; and Fig. 2 shows a conventional 6T static random access memory cell. The write operation timing chart; the third figure shows the circuit diagram of the conventional 5T static random access memory unit cell; the fourth figure shows the write operation timing chart of the conventional 5T static random access memory unit cell; 5 is a circuit diagram showing a 5T static random access memory cell of the conventional TW M358390; and FIG. 6 is a circuit diagram showing a 5T static random access memory cell of the conventional TW M391711; Fig. 7 is a circuit diagram showing a 5T static random access memory cell of the conventional US Pat. No. 7,706,062 B2; and Fig. 8 is a circuit diagram showing the preferred embodiment of the present invention.

According to the above main object, the present invention proposes a double-twist static random access memory, which mainly comprises a memory array, which is composed of a plurality of columns of memory cells and complex A plurality of rows of memory cells, each column of memory cells and each row of memory cells includes a plurality of memory cells (1); a plurality of control circuits (2), one column of each memory cell Control circuit (2).

For convenience of explanation, the double-chip static random access memory shown in FIG. 8 has only one memory cell (1), one write word line (WWL), and one write bit line ( WBL) and a control circuit (2) are described as examples. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P1 and a first NMOS transistor M1) and a second inverter (by a second PMOS) a crystal P2 and a second NMOS transistor M2), a third NMOS transistor (M3), a first read transistor (M4), and a second read transistor (M5), wherein The first inverter and the second inverter are connected in an alternating coupling manner, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the second The output of the phase converter (ie, node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store data of the SRAM cell, and the second inverter The output (node B) is used to store the inverted data of the SRAM cell.

Referring to FIG. 8, the third NMOS transistor (M3) is connected between the output of the first inverter (node A) and a corresponding one of the write bit lines (WBL), and the gate is connected. To correspond to one of the write word lines (WWL), the source, the gate and the drain of the second read transistor (M5) are respectively connected to the ground voltage and the output of the second inverter ( a node B) and a source of the first read transistor (M4); a source, a gate and a drain of the first read transistor (M4) are respectively connected to the second read power The drain of the crystal (M5), a read word line (RWL) and a read bit line (RBL).

Referring again to FIG. 8, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS device. The crystal (M24), a third PMOS transistor (P21), a fourth PMOS transistor (P22), and a write control signal (CTL) are formed. The fourth NMOS transistor (M21) and the third PMOS transistor (P21) form a third inverter connected between a power supply voltage (V _DD ) and a ground voltage, the third inverter The input is for receiving the write control signal (CTL); the source, the gate and the drain of the fifth NMOS transistor (M22) are respectively connected to the drain of the sixth NMOS transistor (M23), An output of the third inverter and a drain of the fourth PMOS transistor (P22); a source, a gate and a drain of the sixth NMOS transistor (M23) are respectively connected to a ground voltage, and the write control a signal (CTL) and a source of the fifth NMOS transistor (M22); a drain of the seventh NMOS transistor (M24) is connected to the gate and connected to the power supply voltage (V _DD ), and the source The pole is connected to the drain of the fifth NMOS transistor (M22) and the drain of the fourth PMOS transistor (P22); the source, the gate and the drain of the fourth PMOS transistor (P22) respectively Connected to the power supply voltage (V _DD ), the write control signal (CTL), and the drain of the fifth NMOS transistor (M22).

The control circuit (2) is designed to control the voltage level of the high voltage node (VH) according to different operation modes, that is, the control circuit (2) writes a representative write control signal (CTL) The logic high timing of the mode is discharged by discharging a potential of a high voltage node (VH) for a predetermined time to lower the potential of the high voltage node (VH) from the power supply voltage (V _DD ) to the power supply voltage ( V _DD ) _deducts the voltage level of a V _{TM 24} (the threshold voltage of the seventh NMOS transistor (M24)), thereby effectively avoiding the problem of writing logic 1 in the write mode, wherein the writing The control signal (CTL) is an AND gate operation result of a Write Enable (WE) signal and a corresponding write word line (WWL) signal, and only the write is performed at this time. When the enable WE signal and the corresponding write write word line (WWL) signal are both at a logic high level, the write control signal (CTL) side is at a logic high level.

The working principle of the preferred embodiment of the present invention is as follows:

(I) write mode

The write control signal (CTL) is at a logic low level before the start of the write operation, so that the third PMOS transistor (P21), the fourth PMOS transistor (P22), and the fifth NMOS transistor (M22) All of them are in an ON state, and the fourth NMOS transistor (M21), the sixth NMOS transistor (M23), and the seventh NMOS transistor (M24) are both turned OFF, so the height is high. The voltage level of the voltage node (VH) is equal to the power supply voltage (V _DD ).

And during an initial period of the write mode (the initial period is approximately equal to when the write control signal (CTL) is converted from the logic low level to the logic high level, until the third inverter falls to be sufficient to turn off the fifth NMOS During the period of the transistor M22, the write control signal (CTL) is at a logic high level, and the third PMOS transistor (P21) and the fourth PMOS transistor (P22) are both turned off, and the fourth NMOS is turned off. The crystal (M21) and the sixth NMOS transistor (M23) are both turned on. Since the fifth NMOS transistor (M22) is still turned on at this time, the high voltage node (VH) can be supplied with the voltage from the power source ( V _DD) towards the voltage level _{(R M22 + R M23) /} (R M22 + R M23 + R M24) is multiplied by the power supply voltage (V _DD) voltage level of the start of discharge, wherein the second represents the R _M22 The on-resistance equivalent resistance of the five NMOS transistor (M22), the R _M23 represents the on-resistance equivalent of the sixth NMOS transistor (M23), and the R _M24 represents the on-equivalent equivalent of the seventh NMOS transistor (M24) The resistor, thereby effectively preventing the problem of writing logic 1 difficult.

Finally, after the initial period, since the write control signal (CTL) is still at a logic high level, the fourth NMOS transistor (M21) and the sixth NMOS transistor (M23) are still turned on, but The fifth NMOS transistor (M22) is turned off, so that the charge to be discharged through the discharge path of the fifth NMOS transistor (M22) and the sixth NMOS transistor (M23) is recovered, and the high voltage is restored. The node (VH) is deducted from the power supply voltage (V _DD ) by a voltage level of a V _{TM 24} (the threshold voltage of the seventh NMOS transistor (M24)).

Next, the preferred embodiment of the present invention of FIG. 8 illustrates how the write operation is completed in accordance with the four write states of the SRAM static random access memory cell.

(1) Node A originally stores a logic 0, but now wants to write a logic 0:

Before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M1) is turned "ON". Since the first NMOS transistor (M11) is ON, the write word line (WWL) is turned from Low (ground voltage) to High (power supply voltage V _DD ) when the write operation starts. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned off (OFF) To be ON, at this time, since the write bit line (WBL) is the ground voltage, the node (A) maintains the ground voltage until the end of the write cycle.

(2) Node A originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M1) is turned "ON". Since the first NMOS transistor (M11) is ON, when the write operation starts, the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), the node The voltage of (A) rises following the voltage of the write word line (WWL).

When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON. Because the write bit line (WBL) is High (the power supply voltage V _DD ), and because the first NMOS transistor (M1) is still ON and the node (B) is still at a voltage level is close At the initial state of the voltage level of the power supply voltage (V _DD ), the first PMOS transistor P1 is still turned off (OFF), and the node (A) is rapidly charged toward a divided voltage level. The divided voltage level is equal to R _M3 /(R _M3 +R _M1 ) multiplied by the power supply voltage (V _DD ), wherein the R _M3 represents the on-resistance equivalent resistance of the third NMOS transistor (M13), the R _M1 Indicates the on-resistance equivalent resistance of the first NMOS transistor (M11).

It is worth noting here that if the high voltage node (VH) is still the power supply voltage (V _DD ) at this time, the result will be as shown in FIG. 4 of the 5T static random access memory cell unit. There is a lack of difficulty in writing logic 1 in simulation. Fortunately, this high voltage node (VH) will be at the voltage level of the power supply voltage (V _DD ) toward (R _M22 +R _M23 )/(R _M22 +R _M23 + R _M24 ) multiplied by the voltage level discharge of the power supply voltage (V _DD ). During the discharge of the high voltage node (VH), the node (B) is also gradually discharged to a lower voltage level, the node The lower voltage level of (B) causes the on-resistance equivalent (R _M1 ) of the first NMOS transistor ( _M1 ) to exhibit a higher resistance value, which will result in a higher voltage at node A. Level, the higher voltage level of the node (A) is again via the second inverter (composed of the second PMOS transistor P2 and the second NMOS transistor M2), so that the node (B) gets more The low voltage level, the lower voltage level of the node (B) is again via the first inverter (composed of the first PMOS transistor P1 and the first NMOS transistor M1), so that the node (A) Obtained Higher voltage level, and so the cycle, to the node (A) charged to the power supply voltage (V _DD) deduct the seventh NMOS transistor (M24) of the threshold voltage _(V TM24) the voltage level, The logic 1 write operation is completed.

(3) Node A originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the write word line (WWL) is greater than the third NMOS transistor (M13) When the threshold voltage is applied, the third NMOS transistor (M13) is turned from OFF to ON; at this time, since the write bit line (WBL) is High (the power supply voltage V _DD ) And because the first PMOS transistor (P11) is still ON, the voltage of the node (A) is maintained at the power supply voltage (V _DD ) minus the threshold voltage of the seventh NMOS transistor (M24) ( The voltage level of V _TM24 ) is reached until the end of the write cycle. It is worth noting here that after the end of the write cycle, the node (A) will continue to charge to the voltage level of the power supply voltage (V _DD ).

(4) Node A originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor P1 is turned ON, and the write word line (WWL) is turned from Low (ground voltage) to High. (high power supply voltage HV _DD ), and the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M3), and the third NMOS transistor (M3) is turned from OFF (off) It is ON. At this time, since the bit line (BL) is Low (ground voltage), the node (A) is discharged to complete the logic 0 write operation until the end of the write cycle. It is worth noting here that the high voltage node (VH) has the power supply voltage (V _DD ) at the initial stage of writing to deduct the voltage level of the threshold voltage (V _TM24 ) of the seventh NMOS transistor (M24). And at the end of the write cycle, it has the level of the power supply voltage (V _DD ).

(II) Read mode (read mode)

According to the two stored data states of the double-sink SRAM cell, the preferred embodiment of the present invention of FIG. 8 performs the reading operation.

(1) Node A stores logic 0:

Before the read operation occurs (the read word line (RWL) is the ground voltage), the write word line (WWL) is the ground voltage, and the second NMOS transistor (M2) is turned (off), and the second The PMOS transistor (P2) is ON (on) and the node B is High (power supply voltage V _DD ). When the read operation starts, the read word line RWL is turned from the ground voltage to High (power supply voltage V _DD ), and when the read word line (RWL) voltage is greater than the first read power When the threshold voltage of the crystal (M4) is reached, the first read transistor (M4) is turned from OFF (turned off) to turned "on", and at this time, since the node B is High, the second read transistor (M5) is ON (conduction), therefore, a current path is formed between the read bit line (RBL), the first read transistor (M4), the second read transistor (M5), and the ground. That is, the voltage level of the read bit line (RBL) is lowered, thereby sensing that node A stores the data of logic 0 and completes the logic 0 read operation.

(2) Node A stores logic 1:

Before the read operation occurs (the read word line (RWL) is the ground voltage), the write word line (WWL) is the ground voltage, the second NMOS transistor (M2) is ON (on), and the second The PMOS transistor (P2) is OFF (off) and the node B is Low (ground voltage). When the read operation starts, the read word line (RWL) is turned from the ground voltage to High (power supply voltage V _DD ), and when the read word line (RWL) voltage is greater than the first read When the threshold voltage of the transistor (M4) is used, the first read transistor (M4) is turned from OFF (off) to ON (on), and at this time, since the node B is Low (ground voltage), the second read Since the transistor (M5) is OFF (off), it is not in the read bit line (RBL), the first read transistor (M4), and the second read transistor (M5). As a result, a current path is formed between the grounds. As a result, the voltage level of the read bit line (RBL) can be smoothly maintained in the High state, thereby sensing the data of the node A storing the logic 1 and completing the logic 1 Read action.

(III) Hold mode (hold mode)

In the hold mode, since the high voltage node (VH) has the voltage level of the power supply voltage (V _DD ), the operation principle is the same as that of the 5T SRAM of FIG. 7 and will not be described here.

[Creation effect]

The double-static static random access memory proposed by the present invention has the following effects: (1) low power consumption during writing: since the double-twist static random access memory cell proposed by the present invention is only written One of the initial operations of the input operation provides a discharge path, and after the initial time, the charge charge that would otherwise be discharged through the discharge path is used to avoid unnecessary power consumption, and thus is relatively high during writing. Low power consumption; (2) Avoiding the difficulty of writing logic 1: The double-click static random access memory proposed in the present invention can be high at the initial time of one of the write operations during the write operation. voltage of the node voltage level (VH) of the power supply voltage (V _DD) of the quasi toward _{(R M22 + R M23) /} (R M22 + R M23 + R M24) is multiplied by the power supply voltage (V _DD) of the voltage level The discharge is started to effectively lower the voltage level of the high voltage node (VH), thereby improving the on-resistance equivalent resistance (R _M3 ) of the third NMOS transistor (M13), and effectively avoiding a single position The line of the static random access memory cell is written Problems Series 1 difficulties; (3) a simple circuit structure: Because of this proposed creation of dual-port static random-access memory without using dual power supply voltages, the circuit configuration can be deleted to avoid complication.

P1‧‧‧First PMOS transistor

P2‧‧‧Second PMOS transistor

M1‧‧‧First NMOS transistor

M2‧‧‧Second NMOS transistor

M3‧‧‧ third NMOS transistor

M4‧‧‧first read transistor

M5‧‧‧Second reading transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

V _DD ‧‧‧Power supply voltage

WBL‧‧‧Write bit line

WWL‧‧‧write word line

RBL‧‧‧Reading bit line

RWL‧‧‧Read word line

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

P21‧‧‧ Third PMOS transistor

P22‧‧‧4th PMOS transistor

1‧‧‧SRAM cell

2‧‧‧Control circuit

CTL‧‧‧ write control signal

VH‧‧‧ high voltage node

Claims (2)

A double-click static random access memory, comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each row of memory The unit cell comprises a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); wherein each memory cell (1) further comprises A first inverter is composed of a first PMOS transistor (P1) and a first NMOS transistor (M1) connected to a power supply voltage (V _DD ) and Between the ground voltages; a second inverter consisting of a second PMOS transistor (P2) and a second NMOS transistor (M2) connected to the power supply voltage ( V _DD ) is between the ground voltage; a storage node (A) is formed by the output of the first inverter; and an inverting storage node (B) is output from the second inverter Formed at the end; a third NMOS transistor (M3) is connected between the storage node (A) and a corresponding write bit line (WBL), and the gate is connected Corresponding to one of the write word lines (WWL); a first read transistor (M4), the source, the gate and the drain of the first read transistor (M4) are respectively connected to one a drain of the second read transistor (M5), a read word line (RWL) and a read bit line (RBL); and the second read transistor (M5), a source, a gate and a drain of the second read transistor (M5) are respectively connected to a ground voltage, a source of the inverting storage node (B) and the first read transistor (M4); The first inverter and the second inverter are connected in an alternating coupling manner, that is, the output end of the first inverter (ie, the storage node A) is connected to the input end of the second inverter. The output of the second inverter (ie, the inverting storage node B) is connected to the input end of the first inverter; and each control circuit (2) further comprises: a fourth NMOS transistor ( M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), a third PMOS transistor (P21), and a fourth PMOS transistor ( P22); wherein the fourth NMOS transistor (M21) and the third PMOS Crystals (of P21) formed in a line connected to the power supply voltage (V _DD) and a third inverter connected between the ground voltage, the input system of the third inverter for receiving the write control signal corresponding to (the CTL); The source, the gate and the drain of the fifth NMOS transistor (M22) are respectively connected to the drain of the sixth NMOS transistor (M23), the output of the third inverter, and the fourth PMOS transistor. a drain of (P22); a source, a gate and a drain of the sixth NMOS transistor (M23) are respectively connected to a ground voltage, corresponding to the write control signal (CTL) and the fifth NMOS transistor ( a source of M22); a drain of the seventh NMOS transistor (M24) is connected to the gate and connected to the power supply voltage (V _DD ), and a source is connected to the fifth NMOS transistor (M22) a drain of the fourth PMOS transistor (P22); a source, a gate and a drain of the fourth PMOS transistor (P22) are respectively connected to the power supply voltage (V _DD ), corresponding to The write control signal (CTL) and the drain of the fifth NMOS transistor (M22). The double-click static random access memory according to claim 1, wherein the write control signal (CTL) is a write enable (WE) signal and each column of memory cells. The AND gate operation result of the corresponding write word line (WWL) signal, that is, only the write enable (WE) signal and the corresponding write word line (WWL) signal When the logic high level is on time, the write control signal (CTL) side is a logic high level.