TWI556238B - 7t dual port static random access memory (2) - Google Patents
7t dual port static random access memory (2) Download PDFInfo
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本發明係有關於一種7T雙埠(dual port)靜態隨機存取記憶體(Static Random Access Memory,簡稱SRAM),尤指一種有效提高7T雙埠SRAM之待機效能,並能有效提高讀取速度與有效降低漏電流(leakage current)且能解決習知具單一位元線之雙埠SRAM寫入邏輯1困難之7T雙埠SRAM。 The invention relates to a 7T dual port static random access memory (SRAM), in particular to an effective improvement of the standby performance of the 7T dual-SRAM SRAM, and can effectively improve the reading speed and It effectively reduces the leakage current and can solve the 7T dual-SRAM SRAM which is difficult to write to the logic 1 with a single bit line.
習知之單埠靜態隨機存取記憶體(SRAM)如第1a圖所示,其主要包括一記憶體陣列(memory array),該記憶體陣列係由複數個記憶體區塊(memory block,MB1、MB2等)所組成,每一記憶體區塊更由複數列記憶體晶胞(a plurality of rows of memory cells)與複數行記憶體晶胞(a plurality of columns of memory cells)所組成,每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞;複數條字元線(word line,WL1、WL2等),每一字元線對應至複數列記憶體晶胞中之一列;以及複數位元線對(bit line pairs,BL1、BLB1...BLm、BLBm等),每一位元線對係對應至複數行記憶體晶胞中之一行,且每一位元線對係由一位元線(BL1...BLm)及一互補位元線(BLB1...BLBm)所組成。 As is shown in FIG. 1a, the static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of memory blocks (memory block, MB 1). , MB 2 , etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL 1 , WL 2 , etc.), each word line corresponding to a plurality of columns of memory One of the body cells; and a plurality of bit line pairs (BL 1 , BLB 1 ... BL m , BLB m , etc.), each bit line pair corresponding to a plurality of rows of memory cells One row, and each bit line pair is composed of one bit line (BL 1 ... BL m ) and one complementary bit line (BLB 1 ... BLB m ).
第1b圖所示即是6T單埠靜態隨機存取記憶體(SRAM)晶胞之電路示意圖,其中,PMOS電晶體(P1)和(P2)稱為負載電晶體(load transistor),NMOS電晶體(M1)和(M2)稱為驅動電晶體(driving transistor),NMOS電晶體(M3)和(M4)稱為存取電晶體(access transistor),WL為字元線(word line),而BL及BLB分別為位元線(bit line)及互補位元線(complementary bit line),由於該單埠SRAM晶胞需要6個電晶體,且驅動電晶體與存取電晶體間的電流驅動能力比(即單元比率,cell ratio)通常設定在2.2至3.5之間,而導致存在有高集積化困難及價格高等缺失。 Figure 1b is a schematic diagram of a 6T單埠 SRAM cell, in which PMOS transistors (P1) and (P2) are called load transistors, NMOS transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is word line, and BL And BLB are respectively a bit line and a complementary bit line. Since the 單埠SRAM cell requires six transistors, and the current driving capability between the driving transistor and the access transistor is greater than (ie, the cell ratio) is usually set between 2.2 and 3.5, resulting in the difficulty of high integration and high price.
第1b圖所示6T單埠靜態隨機存取記憶體晶胞於寫入操作時之HSPICE暫態分析模擬結果,如第2圖所示,其係使用TSMC 90奈米CMOS製程參數加以模擬。 The HSPICE transient analysis results of the 6T單埠 SRAM cell shown in Figure 1b during the write operation, as shown in Figure 2, are simulated using the TSMC 90 nm CMOS process parameters.
用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5T單埠靜態隨機存取記憶體晶胞之電路示意圖,與第1b圖之6T單埠靜態隨機存取記憶體晶胞相比,此種5T靜態隨機存取記憶體晶胞比6T靜態隨機存取記憶體晶胞少一個電晶體及少一條位元線,惟該5T單埠靜態隨機存取記憶體晶胞在不變更PMOS電晶體P1和P2以及NMOS電晶體M1、M2和M3的通道寬長比以維持靜態雜訊邊際(Static Noise Margin,SNM)的情況下存在寫入邏輯1相當困難之問題。茲考慮記憶晶胞左側節點A原本儲存邏輯0的情況,由於節點A之電荷僅單獨自位元線(BL)傳送,因此很難將節點A中先前寫入的邏輯0蓋寫成邏輯1。第3圖所示5T靜態隨機存取記憶體晶胞,於寫入操作時之HSPICE暫態分析模擬結果,如第4圖所示,其係使用TSMC 90奈米CMOS 製程參數加以模擬,由該模擬結果可証實,具單一位元線之5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T 單埠 SRAM cell with only a single bit line, compared to the 6T 單埠 SRAM cell of Figure 1b. The random access memory cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T單埠 SRAM cell does not change the PMOS transistors P1 and P2. And the channel width-to-length ratio of the NMOS transistors M1, M2, and M3 is relatively difficult to write logic 1 in the case of maintaining a static noise margin (SNM). Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 3 shows the HSPICE transient analysis simulation results of the 5T SRAM cell during write operation. As shown in Figure 4, it uses TSMC 90 nm CMOS. The process parameters are simulated. From the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.
接下來討論靜態隨機存取記憶體(SRAM)之單埠及雙埠架構,第1b圖之6T靜態隨機存取記憶體(SRAM)晶胞即是單埠靜態隨機存取記憶體(SRAM)晶胞之一例,其係使用兩條位元線BL及BLB做讀寫的動作,也就是讀與寫均是經由同樣的一對位元線來達成,是以在同一時間內只能進行讀或寫的動作,因此,當欲設計具有同時讀寫能力之雙埠靜態隨機存取記憶體時,便需要多加入兩顆存取電晶體以及另一對位元線(請參考第5圖所示電路,其中WBL及WBLB為寫入用位元線對、RBL及RBLB為讀取用位元線對、WWL為寫入用字元線、RWL為讀取用字元線),這使得記憶晶胞的面積大大地增加,如果我們能夠簡化記憶晶胞的架構,使得一條位元線負責讀取的動作,而另一條位元線負責寫入的動作,則在設計雙埠靜態隨機存取記憶體時,記憶晶胞便不需要多加入兩顆電晶體及一對位元線,這樣記憶晶胞的面積便會減小許多,傳統的雙埠靜態隨機存取記憶體晶胞之所以不採用這種方法,是因為如前所述存在寫入邏輯1相當困難之問題。 Next, we discuss the static random access memory (SRAM) and double-ended architecture. The 6T static random access memory (SRAM) cell in Figure 1b is the static random access memory (SRAM) crystal. One example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, both reading and writing are achieved through the same pair of bit lines, so that only reading or reading can be performed at the same time. The action of writing, therefore, when designing a dual-static SRAM with simultaneous read and write capabilities, it is necessary to add two access transistors and another pair of bit lines (please refer to Figure 5). a circuit in which WBL and WBLB are write bit line pairs, RBL and RBLB are read bit line pairs, WWL is a write word line, and RWL is a read word line), which makes the memory crystal The area of the cell is greatly increased. If we can simplify the structure of the memory cell, so that one bit line is responsible for the reading action, and the other bit line is responsible for the writing action, then the double-click static random access memory is designed. When you are in the body, the memory cell does not need to add two transistors and a pair of bit lines. Memory cell area will be reduced a lot, the conventional dual-port static random-access memory cell is not the reason why this approach is quite difficult because of the problem of writing a logic 1 is present as described above.
迄今,有許多具單一位元線之7T雙埠靜態隨機存取記憶體晶胞之技術被提出,例如專利文獻1(103年6月11日第TWI441178號)所提出之「雙埠靜態隨機存取記憶體」、專利文獻2(103年6月11日第TWI441179號)所提出之「具放電路徑之雙埠SRAM」、專利文獻3(103年5月6日第US8717807 B2號)所提出之「Independently-controlled-gate SRAM」、專利文獻4(103年4月1日第TWI433152號)所提出之「7T雙埠SRAM」、專利文獻5(103年2月1日第TWI425509號)所提出之「具放電路徑之雙埠靜態隨機存 取記憶體」、專利文獻6(103年1月11日第TWI423257號)所提出之「寫入操作時降低電源電壓之雙埠SRAM」、專利文獻7(103年1月11日第TWI423258號)所提出之「寫入操作時提高寫入用字元線電壓位準之雙埠靜態隨機存取記憶體」、專利文獻8(102年6月21日第TWI399748號)、專利文獻9(98年6月22日第US20090161410 A1號)所提出之「SEVEN TRANSISTOR SRAM CELL」、專利文獻10(97年6月10日第US7385840 B2號)所提出之「SRAM cell with independent static noise margin,trip voltage,and read current optimization」及專利文獻11(93年6月15日第US6751151 B2號)所提出之「Ultra high-speed DDP-SRAM cache」,該等專利雖可有效解決寫入邏輯1困難之問題,惟由於該等專利均未考慮到45奈米操作電壓將降為1.1±30%時所造成讀取速度降低之問題,因此仍有改進空間。 So far, many techniques have been proposed for a 7T double-squat static random access memory cell with a single bit line, for example, "Double-band static random memory" proposed in Patent Document 1 (TWI441178, June 11, 103) "Responsive memory", Patent Document 2 (TWI441179, June 11, 103), "Double-band SRAM with discharge path", and Patent Document 3 (No. 8717807 B2, May 6, 103) "Independently-controlled-gate SRAM", "7T Double SRAM" proposed in Patent Document 4 (TWI433152, April 1, 103), and Patent Document 5 (TWI425509, February 1, 103) "Double static random storage with discharge path "Responsive memory", Patent Document 6 (TWI 423257, January 11, 103), "Double-埠 SRAM for reducing power supply voltage during write operation", Patent Document 7 (TWI 423258, January 11, 103) The proposed "double-click static random access memory for increasing the voltage level of the write word line during the write operation", Patent Document 8 (TWI399748, June 21, 102), Patent Document 9 (98) "SVEN cell with independent static noise margin, trip voltage, and" proposed by "SEVEN TRANSISTOR SRAM CELL", No. US20090161410 A1, June 22, and Patent Document 10 (No. US7385840 B2, June 10, 1997) "reading current optimization" and "Ultra high-speed DDP-SRAM cache" proposed in Patent Document 11 (US Pat. No. 6,751,511 B2, June 15, 1993), although these patents can effectively solve the problem of writing logic 1 difficult, Since these patents do not take into account the problem of reduced reading speed when the 45 nm operating voltage is reduced to 1.1 ± 30%, there is still room for improvement.
有鑑於此,本發明之主要目的係提出一種7T雙埠靜態隨機存取記憶體,其能藉由控制電路以有效提高讀取速度。 In view of the above, the main object of the present invention is to provide a 7T double-pin static random access memory capable of effectively improving the reading speed by the control circuit.
本發明之次要目的係提出一種7T雙埠靜態隨機存取記憶體,其能藉由二階段的讀取控制以於提高讀取速度的同時,亦能避免無謂的功率耗損。 A secondary object of the present invention is to provide a 7T double-pin static random access memory capable of improving read speed while avoiding unnecessary power consumption while maintaining read speed by two stages.
本發明之再一目的係提出一種7T雙埠靜態隨機存取記憶體,其能藉由待機啟動電路以有效促使SRAM快速進入待機模式,並因而有效提高SRAM之待機效能。 A further object of the present invention is to provide a 7T dual-chirpson static random access memory capable of effectively causing the SRAM to quickly enter the standby mode by the standby enable circuit, thereby effectively improving the standby performance of the SRAM.
本發明之又一目的係提出一種7T雙埠靜態隨機存取記憶體,其能藉由控制電路以有效降低待機模式之漏電流。 Another object of the present invention is to provide a 7T double-pin static random access memory capable of effectively reducing leakage current in a standby mode by a control circuit.
本發明提出一種7T雙埠靜態隨機存取記憶體,其主要包括一記憶體陣列(1)、複數個控制電路(2)、複數個預充電電路(3)以及一待機啟動電路(4),該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成,每一列記憶體晶胞設置一個控制電路,且每一記憶體晶胞(1)係包括一第一反相器(由一第一PMOS電晶體P11與一第一NMOS電晶體M11所組成)、一第二反相器(由一第二PMOS電晶體P12與一第二NMOS電晶體M12所組成)、一存取電晶體(由第三NMOS電晶體M13所組成)、一第一讀取用電晶體(M14)以及一第二讀取用電晶體(M15)。每一控制單元(2)係連接至對應列記憶體晶胞中之每一記憶體晶胞的該第一NMOS電晶體(M11)的源極以及該第二NMOS電晶體(M12)的源極,以便因應不同操作模式而控制該第一NMOS電晶體(M11)的源極電壓以及該第二NMOS電晶體(M12)的源極電壓,藉此於寫入模式時,可有效防止寫入邏輯1困難之問題,於讀取模式時,可於提高讀取速度的同時,亦避免無謂的功率耗損,於待機模式時,可有效降低漏電流,而於保持模式時則可維持原有的電氣特性。再者,藉由該待機啟動電路(4)的設計,以有效促使7T雙埠靜態隨機存取記憶體快速進入待機模式,並因而有效提高7T雙埠靜態隨機存取記憶體之待機效能。 The present invention provides a 7T dual-static static random access memory, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby start circuit (4). The memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells is provided with a control circuit, and each memory cell (1) includes a first inversion. a second inverter (composed of a second PMOS transistor P12 and a second NMOS transistor M12), a second inverter (composed of a first PMOS transistor P11 and a second NMOS transistor M12) The access transistor (consisting of the third NMOS transistor M13), a first read transistor (M14), and a second read transistor (M15). Each control unit (2) is connected to a source of the first NMOS transistor (M11) of each memory cell of the corresponding column memory cell and a source of the second NMOS transistor (M12) In order to control the source voltage of the first NMOS transistor (M11) and the source voltage of the second NMOS transistor (M12) in response to different operation modes, thereby effectively preventing the write logic in the write mode 1 difficult problem, in the read mode, can improve the reading speed, but also avoid unnecessary power consumption, in the standby mode, can effectively reduce the leakage current, while maintaining the original electrical mode characteristic. Furthermore, the standby start circuit (4) is designed to effectively cause the 7T dual-static SRAM to quickly enter the standby mode, thereby effectively improving the standby performance of the 7T dual-static SRAM.
BLB1...BLBm‧‧‧互補位元線 BLB 1 ...BLB m ‧‧‧complementary bit line
BLB‧‧‧互補位元線 BLB‧‧‧complementary bit line
MB1...MBk‧‧‧記憶體區塊 MB 1 ... MB k ‧‧‧ memory block
WL1...WLn‧‧‧字元線 WL 1 ... WL n ‧‧‧ character line
BL1...BLm‧‧‧位元線 BL 1 ...BL m ‧‧‧ bit line
I1、I2、I3‧‧‧漏電流 I 1 , I 2 , I 3 ‧‧‧ leakage current
1‧‧‧SRAM晶胞 1‧‧‧SRAM cell
2‧‧‧控制電路 2‧‧‧Control circuit
3‧‧‧預充電電路 3‧‧‧Precharge circuit
4‧‧‧待機啟動電路 4‧‧‧Standby start circuit
P11‧‧‧第一PMOS電晶體 P11‧‧‧First PMOS transistor
P12‧‧‧第二PMOS電晶體 P12‧‧‧Second PMOS transistor
M11‧‧‧第一NMOS電晶體 M11‧‧‧First NMOS transistor
M12‧‧‧第二NMOS電晶體 M12‧‧‧Second NMOS transistor
M13‧‧‧第三NMOS電晶體 M13‧‧‧ Third NMOS transistor
A‧‧‧儲存節點 A‧‧‧ storage node
B‧‧‧反相儲存節點 B‧‧‧ Inverting storage node
VDD‧‧‧電源供應電壓 V DD ‧‧‧Power supply voltage
M14‧‧‧第一讀取用電晶體 M14‧‧‧First read transistor
M15‧‧‧第二讀取用電晶體 M15‧‧‧Second reading transistor
S‧‧‧待機模式控制信號 S‧‧‧Standby mode control signal
/S‧‧‧反相待機模式控制信號 /S ‧‧‧Inverted standby mode control signal
VL1‧‧‧第一低電壓節點 VL1‧‧‧ first low voltage node
VL2‧‧‧第二低電壓節點 VL2‧‧‧ second low voltage node
M21‧‧‧第四NMOS電晶體 M21‧‧‧4th NMOS transistor
M22‧‧‧第五NMOS電晶體 M22‧‧‧ Fifth NMOS transistor
M23‧‧‧第六NMOS電晶體 M23‧‧‧ sixth NMOS transistor
M24‧‧‧第七NMOS電晶體 M24‧‧‧ seventh NMOS transistor
M25‧‧‧第八NMOS電晶體 M25‧‧‧8th NMOS transistor
M26‧‧‧第九NMOS電晶體 M26‧‧‧Ninth NMOS transistor
M27‧‧‧第十NMOS電晶體 M27‧‧‧ tenth NMOS transistor
P21‧‧‧第三PMOS電晶體 P21‧‧‧ Third PMOS transistor
RC‧‧‧讀取控制信號 RC‧‧‧ read control signal
RGND‧‧‧加速讀取電壓 RGND‧‧‧Accelerated reading voltage
WC‧‧‧寫入控制信號 WC‧‧‧ write control signal
C‧‧‧節點 C‧‧‧ node
INV‧‧‧第三反相器 INV‧‧‧ third inverter
D1‧‧‧第一延遲電路 D1‧‧‧First delay circuit
P31‧‧‧第四NMOS電晶體 P31‧‧‧4th NMOS transistor
P‧‧‧預充電信號 P‧‧‧Precharge signal
M41‧‧‧第十一NMOS電晶體 M41‧‧11 eleventh NMOS transistor
P41‧‧‧第五PMOS電晶體 P41‧‧‧ Fifth PMOS transistor
WBL‧‧‧寫入用位元線 WBL‧‧‧Write bit line
WWL‧‧‧寫入用字元線 WWL‧‧‧write word line
RBL‧‧‧讀取用位元線 RBL‧‧‧Reading bit line
RWL‧‧‧讀取用字元線 RWL‧‧‧Read word line
D2‧‧‧第二延遲電路 D2‧‧‧second delay circuit
第1a圖 係顯示習知之靜態隨機存取記憶體;第1b圖 係顯示習知6T靜態隨機存取記憶體晶胞之電路示意圖;第2圖 係顯示習知6T靜態隨機存取記憶體晶胞之寫入動作時序圖; 第3圖 係顯示習知5T靜態隨機存取記憶體晶胞之電路示意圖;第4圖 係顯示習知5T靜態隨機存取記憶體晶胞之寫入動作時序圖;第5圖 係顯示習知8T雙埠靜態隨機存取記憶體晶胞之電路示意圖;第6圖 係顯示本發明較佳實施例所提出之電路示意圖;第7圖 係顯示第6圖之本發明較佳實施例於寫入邏輯1期間之簡化電路圖;第8圖 係顯示第6圖之本發明較佳實施例之寫入動作時序圖;第9圖 係顯示第6圖之本發明較佳實施例於讀取期間之簡化電路圖;第10圖 係顯示第6圖之本發明較佳實施例於待機期間之簡化電路圖。 Figure 1a shows a conventional static random access memory; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; and Fig. 2 shows a conventional 6T static random access memory cell. Write action timing diagram; 3 is a circuit diagram showing a conventional 5T static random access memory cell; FIG. 4 is a timing chart showing a write operation of a conventional 5T static random access memory cell; FIG. 5 is a conventional display FIG. 6 is a schematic circuit diagram of a preferred embodiment of the present invention; FIG. 7 is a circuit diagram showing a preferred embodiment of the present invention in FIG. Simplified circuit diagram during logic 1; Fig. 8 is a timing chart showing the write operation of the preferred embodiment of the invention in Fig. 6; and Fig. 9 is a simplified view showing the preferred embodiment of the invention in Fig. 6 during reading BRIEF DESCRIPTION OF THE DRAWINGS Fig. 10 is a simplified circuit diagram showing a preferred embodiment of the present invention in FIG. 6 during standby.
根據上述之主要目的,本發明提出一種7T雙埠靜態隨機存取記憶體,其主要包括一記憶體陣列,該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成,每一列記憶體晶胞與每一行記憶體晶胞均包括有複數個記憶體晶胞(1);複數個控制電路(2),每一列記憶晶胞設置一個控制電路(2);複數個預充電電路(3),每一行記憶晶胞設置一個預充電電路(3);以及一待機啟動電路(4),該待機啟動電路(4)係促使7T雙埠SRAM快速進入待機模式,以有效提高7T雙埠SRAM之待機效能。 According to the above main object, the present invention provides a 7T binary anti-static random access memory, which mainly comprises a memory array, which is composed of a plurality of memory cells and a plurality of memory cells. Each column of memory cells and each row of memory cells includes a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a charging circuit (3), each row of memory cells is provided with a pre-charging circuit (3); and a standby starting circuit (4), which causes the 7T dual-SRAM to quickly enter the standby mode to effectively improve 7T dual-chip SRAM standby performance.
為了便於說明起見,第6圖所示之7T雙埠靜態隨機存取記憶體僅以一個記憶體晶胞(1)、一條寫入用字元線(WWL)、一條寫入用位元線(WBL)、一條讀取用字元線(RWL)、一條讀取用位元線(RBL)、一控制電路(2)、一預充電電路(3)以及一待機啟動電路(4)做為實施例來說明。該記憶體晶胞(1)係包括一第一反相器(由一第一PMOS電晶體 P11與一第一NMOS電晶體M11所組成)、一第二反相器(由一第二PMOS電晶體P12與一第二NMOS電晶體M12所組成)、一第三NMOS電晶體(M13)、一第一讀取用電晶體(M14)以及一第二讀取用電晶體(M15),其中,該第一反相器及該第二反相器係呈交互耦合連接,亦即該第一反相器之輸出(即節點A)係連接該第二反相器之輸入,而該第二反相器之輸出(即節點B)則連接該第一反相器之輸入,並且該第一反相器之輸出(節點A)係用於儲存SRAM晶胞之資料,而該第二反相器之輸出(節點B)則用於儲存SRAM晶胞之反相資料。 For convenience of explanation, the 7T double-chip static random access memory shown in FIG. 6 has only one memory cell (1), one write word line (WWL), and one write bit line. (WBL), a read word line (RWL), a read bit line (RBL), a control circuit (2), a precharge circuit (3), and a standby start circuit (4) as The embodiment is explained. The memory cell (1) includes a first inverter (by a first PMOS transistor) P11 is composed of a first NMOS transistor M11, a second inverter (composed of a second PMOS transistor P12 and a second NMOS transistor M12), a third NMOS transistor (M13), a first read transistor (M14) and a second read transistor (M15), wherein the first inverter and the second inverter are connected in an alternating manner, that is, the first The output of the inverter (ie node A) is connected to the input of the second inverter, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the first The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell.
該記憶體晶胞(1)之該第一反相器(由該第一PMOS電晶體P11與該第一NMOS電晶體M11所組成)係連接在一電源供應電壓(VDD)與一第一低電壓節點(VL1)之間,該第二反相器(由該第二PMOS電晶體P12與該第二NMOS電晶體M12所組成)係連接在該電源供應電壓(VDD)與一第二低電壓節點(VL2)之間,該第一讀取用電晶體(M4)之源極、閘極與汲極係分別連接至該第二讀取用電晶體(M5)之汲極、該讀取用字元線(RWL)與該讀取用位元線(RBL),而該第二讀取用電晶體(M15)之源極、閘極與汲極則分別連接至第二低電壓節點(VL2)、該第二反相器之輸出(節點B)與該第一讀取用電晶體(M4)之源極。 The first inverter of the memory cell (1) (composed of the first PMOS transistor P11 and the first NMOS transistor M11) is connected to a power supply voltage (V DD ) and a first Between the low voltage nodes (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected to the power supply voltage (V DD ) and a second Between the low voltage nodes (VL2), the source, the gate and the drain of the first read transistor (M4) are respectively connected to the drain of the second read transistor (M5), the read The word line (RWL) and the read bit line (RBL) are taken, and the source, the gate and the drain of the second read transistor (M15) are respectively connected to the second low voltage node. (VL2), the output of the second inverter (node B) and the source of the first read transistor (M4).
請再參考第6圖,該控制電路(2)係由一第四NMOS電晶體(M21)、一第五NMOS電晶體(M22)、一第六NMOS電晶體(M23)、一第七NMOS電晶體(M24)、一第八NMOS電晶體(M25)、一第九NMOS電晶體(M26)、一第十NMOS電晶體(M27)、一第三PMOS電晶體(P21)、一讀取控制信號(RC)、一第三反相器(INV)、一第一延遲電路(D1)、 一加速讀取電壓(RGND)、一寫入控制信號(WC)、一待機模式控制信號(S)以及一反相待機模式控制信號(/S)所組成。該第四NMOS電晶體(M21)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與該第二低電壓節點(VL2);該第五NMOS電晶體(M22)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該待機模式控制信號(S)與該第二低電壓節點(VL2);該第六NMOS電晶體(M23)之源極係連接至接地電壓,而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1);該第七NMOS電晶體(M24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M25)之汲極、該讀取控制信號(RC)與該第二低電壓節點(VL2);該第八NMOS電晶體(M25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、該第一延遲電路(D1)之輸出與該第七NMOS電晶體(M24)之源極;該第一延遲電路(D1)係連接在該第三反相器(INV)之輸出與該第八NMOS電晶體(M25)之閘極之間;該第三反相器(INV)之輸入係供接收該讀取控制信號(RC),而輸出則連接至該第一延遲電路(D1)之輸入;該第九NMOS電晶體(M26)之源極、閘極與汲極係分別連接至接地電壓、該第十NMOS電晶體(M27)之汲極與該第一低電壓節點(VL1);該第十NMOS電晶體(M27)之源極、閘極與汲極係分別連接至接地電壓、該寫入控制信號(WC)與該第九NMOS電晶體(M26)之閘極;而該第三PMOS電晶體(P21)之源極、閘極與汲極係分別連接至該反相待機模式控制信號(/S)、該寫入控制信號(WC)與該第十NMOS電晶體(M27)之汲極。在此值得注意的是,該反相待機模式控制信號(/S)係由該待機模式控制信號(S)經一反相器而獲得。 Referring again to FIG. 6, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS device. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), An accelerated read voltage (RGND), a write control signal (WC), a standby mode control signal (S), and an inverted standby mode control signal (/S). a source, a gate and a drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the reverse standby mode control signal (/S) and the second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) The gate and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); the eighth NMOS transistor (M25) a source, a gate and a drain are respectively connected to the accelerated read voltage (RGND), an output of the first delay circuit (D1), and a source of the seventh NMOS transistor (M24); the first a delay circuit (D1) is coupled between an output of the third inverter (INV) and a gate of the eighth NMOS transistor (M25); an input of the third inverter (INV) is for receiving the Read control signal ( RC), and the output is connected to the input of the first delay circuit (D1); the source, the gate and the drain of the ninth NMOS transistor (M26) are respectively connected to a ground voltage, the tenth NMOS transistor a drain of (M27) and the first low voltage node (VL1); a source, a gate and a drain of the tenth NMOS transistor (M27) are respectively connected to a ground voltage, and the write control signal (WC) And a gate of the ninth NMOS transistor (M26); and a source, a gate and a drain of the third PMOS transistor (P21) are respectively connected to the inverted standby mode control signal (/S), Write the control signal (WC) and the drain of the tenth NMOS transistor (M27). It is worth noting here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter.
該控制電路(2)係設計成可因應不同操作模式而控制該第一低電壓節點(VL1)與該第二低電壓節點(VL2)之電壓位準,於寫入模式時,將選定晶胞中較接近該寫入用位元線(WBL)之驅動電晶體(即該第一NMOS電晶體M11)的源極電壓(即該第一低電壓節點VL1)設定成較接地電壓為高之一預定電壓(即該第六NMOS電晶體(M23)之閘源極電壓VGS(M23))且將選定晶胞中另一驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成接地電壓,以便防止寫入邏輯1困難之問題。 The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage of the driving transistor (ie, the first NMOS transistor M11) closer to the writing bit line (WBL) is set to be higher than the ground voltage. Predetermining a voltage (ie, a gate-source voltage V GS (M23) of the sixth NMOS transistor (M23)) and selecting a source voltage of another driving transistor (ie, the second NMOS transistor M12) in the selected cell ( That is, the second low voltage node VL2) is set to the ground voltage in order to prevent the problem of writing logic 1 difficult.
於讀取模式之第一階段時,將選定晶胞中較接近讀取用位元線(RBL)之驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成呈較接地電壓為低之該加速讀取電壓(RGND),該較接地電壓為低之該加速讀取電壓(RGND)可有效提高讀取速度,而於讀取模式之第二階段時,將選定晶胞中較接近讀取用位元線(RBL)之驅動電晶體(即該第二NMOS電晶體M12)的源極電壓設定回接地電壓,以便減少無謂的功率消耗,其中該讀取模式之該第二階段與該第一階段相隔之時間,係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算,並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間,其值可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。 In the first phase of the read mode, the source voltage of the driving transistor (ie, the second NMOS transistor M12) that is closer to the read bit line (RBL) in the selected cell (ie, the second low) The voltage node VL2) is set to be the accelerated read voltage (RGND) which is lower than the ground voltage, and the accelerated read voltage (RGND) which is lower than the ground voltage can effectively improve the read speed, and in the read mode In the second stage, the source voltage of the driving transistor (ie, the second NMOS transistor M12) in the selected cell closer to the read bit line (RBL) is set back to the ground voltage to reduce unnecessary power consumption. The time between the second phase of the read mode and the first phase is equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the eighth NMOS transistor ( The gate voltage of M25) is sufficient to turn off the eighth NMOS transistor (M25), and the value thereof can be provided by the first delay circuit (D1) by the falling delay time of the third inverter (INV) The delay time is adjusted.
於待機模式時,將所有記憶晶胞中之驅動電晶體的源極電壓設定成較接地電壓為高之該預定電壓,以便降低漏電流;而於保持模式時則將記憶晶胞中之驅動電晶體的源極電壓設定成接地電壓,以便維持原來 之保持特性,其詳細工作電壓位準如表1所示。 In the standby mode, the source voltage of the driving transistor in all the memory cells is set to the predetermined voltage higher than the ground voltage to reduce the leakage current; and in the hold mode, the driving power in the memory cell is The source voltage of the crystal is set to the ground voltage to maintain the original The retention characteristics, the detailed working voltage level is shown in Table 1.
表1中之該寫入控制信號(WC)係為一寫入致能(Write Enable,簡稱WE)信號與對應之寫入用字元線(WWL)信號的及閘(AND gate)運算結果,此時僅於該寫入致能(WE)信號與該對應之寫入用字元線(WWL)信號均為邏輯高位準時,該寫入控制信號(WC)方為邏輯高位準;該讀取控制信號(RC)為一讀取致能(Read Enable,簡稱RE)信號與對應之讀取用字元線(RWL)信號的及閘運算結果。在此值得注意的是,對於非選定字元線及非選定位元線係設定為浮接(floating)狀態,而對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準,以防止該第七NMOS電晶體(M24)之漏電流。 The write control signal (WC) in Table 1 is an AND gate operation result of a Write Enable (WE) signal and a corresponding write word line (WWL) signal. At this time, when the write enable (WE) signal and the corresponding write word line (WWL) signal are both at a logic high level, the write control signal (WC) is a logic high level; the read The control signal (RC) is the result of the AND operation of a Read Enable (RE) signal and a corresponding Read Word Line (RWL) signal. It is worth noting here that the unselected word line and the unselected positioning element line are set to a floating state, and the read control signal (RC) is set to the acceleration during the non-read mode. The level of the read voltage (RGND) is read to prevent leakage current of the seventh NMOS transistor (M24).
請參考第6圖,該預充電電路(3)係由一第四PMOS電晶體(P31)以及一預充電信號(P)所組成,該第四PMOS電晶體(P31)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該預充電信號(P) 與相對應之讀取用位元線(RBL),以便於預充電期間,藉由邏輯低位準之該預充電信號(P),以將相對應之讀取用位元線(RBL)預充電至該電源供應電壓(VDD)之位準。 Referring to FIG. 6, the precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P), and the source and gate of the fourth PMOS transistor (P31). And the drain system are respectively connected to the power supply voltage (V DD ), the precharge signal (P) and the corresponding read bit line (RBL), so as to be during the precharge period, by the logic low level Precharge signal (P) to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V DD ).
請再參考第6圖,該待機啟動電路(4)係由一第五PMOS電晶體(P41)、一第十一NMOS電晶體(M41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成。該第五PMOS電晶體(P41)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該反相待機模式控制信號(/S)與該第十一NMOS電晶體(M41)之汲極;該第十一NMOS電晶體(M41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第五PMOS電晶體(P41)之汲極;該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S),而該延遲電路(D1)之輸出則連接至該第十一NMOS電晶體(M41)之閘極。 Referring again to FIG. 6, the standby starting circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2), and the reverse standby. The mode control signal (/S) is composed of. a source, a gate and a drain of the fifth PMOS transistor (P41) are respectively connected to the power supply voltage (V DD ), the inverted standby mode control signal (/S) and the eleventh NMOS transistor a drain of (M41); a source, a gate and a drain of the eleventh NMOS transistor (M41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) And a drain of the fifth PMOS transistor (P41); an input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and an output of the delay circuit (D1) is connected to The gate of the eleventh NMOS transistor (M41).
茲依單埠SRAM之工作模式說明第6圖之本發明較佳實施例的工作原理如下: The working principle of the preferred embodiment of the present invention in the sixth diagram is as follows:
(I)寫入模式(write mode) (I) write mode
於寫入操作開始前,該寫入控制信號(WC)為邏輯低位準,使得該第三PMOS電晶體(P21)導通(ON),並使得該第十NMOS電晶體(M27)截止(OFF),於是該第三PMOS電晶體(P21)之汲極呈邏輯高位準,該邏輯高位準之該第三PMOS電晶體(P21)之汲極會導通該第九NMOS電晶體(M26),並使得該第一低電壓節點(VL1)呈接地電壓。 Before the start of the write operation, the write control signal (WC) is at a logic low level, such that the third PMOS transistor (P21) is turned "ON", and the tenth NMOS transistor (M27) is turned off (OFF). Therefore, the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) of the logic high level turns on the ninth NMOS transistor (M26), and The first low voltage node (VL1) is at a ground voltage.
而於寫入操作期間內,該寫入控制信號(WC)為邏輯高位 準,使得該第三PMOS電晶體(P21)截止,該第十NMOS電晶體(M27)導通,並使得該第三PMOS電晶體(P21)之汲極呈邏輯低位準,該邏輯低位準之該第三PMOS電晶體(P21)之汲極會使得該第九NMOS電晶體(M26)截止,並使得該第一低電壓節點(VL1)等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M26),藉此得以有效防止寫入邏輯1困難之問題。第7圖所示為第6圖之本發明較佳實施例於寫入期間之簡化電路圖。 During the write operation, the write control signal (WC) is at a logic high level, such that the third PMOS transistor (P21) is turned off, the tenth NMOS transistor (M27) is turned on, and the third PMOS is turned on. The drain of the transistor (P21) is at a logic low level, and the logic low level of the drain of the third PMOS transistor (P21) causes the ninth NMOS transistor (M26) to be turned off, and the first low voltage is made The node (VL1) is equal to the gate-source voltage V GS (M26 ) of the sixth NMOS transistor (M23 ) , whereby the problem of difficulty in writing the logic 1 is effectively prevented. Figure 7 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 6 during writing.
接下來依單埠SRAM之4種寫入狀態來說明第7圖之本發明較佳實施例如何完成寫入動作。 Next, how the write operation of the preferred embodiment of the present invention in FIG. 7 is completed depends on the four write states of the SRAM.
(一)節點A原本儲存邏輯0,而現在欲寫入邏輯0: (1) Node A originally stores a logic 0, but now wants to write a logic 0:
在寫入動作發生前(該寫入用字元線WWL為接地電壓),該第一NMOS電晶體(M11)為導通(ON)。因為該第一NMOS電晶體(M11)為ON,所以當寫入動作開始時,該寫入用字元線(WWL)由Low(接地電壓)轉High(電源供應電壓VDD)。當該寫入用字元線(WWL)的電壓大於該第三NMOS電晶體(M13)(即存取電晶體)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為寫入用位元線(WBL)是接地電壓,所以會將該節點A放電,而完成邏輯0的寫入動作,直到寫入週期結束。 Before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M11) is turned "ON". Since the first NMOS transistor (M11) is ON, the write word line (WWL) is turned from Low (ground voltage) to High (power supply voltage V DD ) when the write operation starts. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned off (OFF) To be ON, at this time, since the write bit line (WBL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle.
(二)節點A原本儲存邏輯0,而現在欲寫入邏輯1: (2) Node A originally stores logic 0, but now wants to write logic 1:
在寫入動作發生前(該寫入用字元線WWL為接地電壓),該第一NMOS電晶體(M11)為導通(ON)。在此值得注意的是,因為該第一NMOS電晶體(M11)為ON,所以當寫入動作開始時,該寫入用字元線(WWL) 由Low(接地電壓)轉High(該電源供應電壓VDD),該節點A的電壓會由於寄生電容耦合效應而跟隨該寫入用字元線(WWL)的電壓呈現些微上升。 Before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M11) is turned "ON". It is worth noting here that since the first NMOS transistor (M11) is ON, when the write operation starts, the write word line (WWL) is turned from Low (ground voltage) to High (the power supply) Voltage V DD ), the voltage of this node A will slightly increase with the voltage following the write word line (WWL) due to the parasitic capacitance coupling effect.
當該寫入用字元線(WWL)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為該寫入用位元線(WBL)是High(該電源供應電壓VDD),並且因為該第一NMOS電晶體(M11)仍為ON且該節點B仍處於電壓位準為接近於該電源供應電壓(VDD)之電壓位準的初始狀態,所以該第一PMOS電晶體(P11)仍為截止(OFF),而該節點A則會朝一分壓電壓位準快速充電,該分壓電壓位準等於(RM11+RM23)/(RM13+RM11+RM23)乘以該電源供應電壓(VDD),其中該RM13表示該第三NMOS電晶體(M13)之導通等效電阻,該RM11表示該第一NMOS電晶體(M11)之導通等效電阻,而該RM23表示該第六NMOS電晶體(M23)之導通等效電阻,此時因為第三NMOS電晶體(M13)仍工作於飽和區(saturation region)且該第一NMOS電晶體(M11)仍工作於線性區(triode region),雖然該第三NMOS電晶體(M13)之導通等效電阻(RM13)會遠大於該第一NMOS電晶體(M11)之導通等效電阻(RM11),但由於該第六NMOS電晶體(M23)係呈二極體連接,因此可於該第一低電壓節點(VL1)處提供一等於該第六NMOS電晶體(M23)之閘-源極電壓VGS(M23)之電壓位準,結果節點A所呈現的該分壓電壓位準,其電壓值會比第4圖之習知5T靜態隨機存取記憶體晶胞之該節點A之電壓位準還要高許多。該還要高許多之分壓電壓位準足以使該第二NMOS電晶體(M12)導通,於是使得節點B放電至一較低電壓位準,該節點B之較低電壓位準會 使得該第一NMOS電晶體(M11)之導通等效電阻(RM11)呈現較高的電阻值,該第一NMOS電晶體(M11)之該較高的電阻值會於該節點A獲得較高電壓位準,該節點A之較高電壓位準又會經由該第二反相器(由第二PMOS電晶體P12與第二NMOS電晶體M12所組成),而使得該節點B呈現更低電壓位準,該節點B之更低電壓位準又會經由該第一反相器(由第一PMOS電晶體P11與第一NMOS電晶體M11所組成),而使得該節點A獲得更高電壓位準,依此循環,即可將該節點A充電至該電源供應電壓(VDD),而完成邏輯1的寫入動作。 When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON. Because the write bit line (WBL) is High (the power supply voltage V DD ), and because the first NMOS transistor (M11) is still ON and the node B is still at a voltage level close to the The initial state of the voltage level of the power supply voltage (V DD ), so the first PMOS transistor (P11) is still off (OFF), and the node A is quickly charged toward a divided voltage level, the partial voltage The voltage level is equal to (R M11 + R M23 ) / (R M13 + R M11 + R M23 ) multiplied by the power supply voltage (V DD ), wherein the R M13 represents the conduction of the third NMOS transistor (M13), etc. The effective resistance, the R M11 represents the on-resistance equivalent resistance of the first NMOS transistor (M11), and the R M23 represents the on-resistance equivalent resistance of the sixth NMOS transistor (M23), at this time because of the third NMOS transistor (M13) still operates in the saturation region and the first NMOS transistor (M11) still operates in the triode region, although the third NMOS transistor (M13) is turned on equivalently (R M13) is considerably greater than the first NMOS transistor (M11) is turned the equivalent resistance (R M11), but since the sixth NMOS transistor (M23) diodes is connected as a system, it is possible in the first A voltage level equal to the gate-source voltage V GS (M23) of the sixth NMOS transistor (M23) is provided at the low voltage node (VL1), and the voltage voltage level presented by the node A is the voltage. The value will be much higher than the voltage level of the node A of the conventional 5T SRAM cell of Figure 4. The much higher voltage division voltage level is sufficient to turn on the second NMOS transistor (M12), thus causing the node B to discharge to a lower voltage level, and the lower voltage level of the node B causes the first The on-resistance equivalent (R M11 ) of an NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) obtains a higher voltage level at the node A. The higher voltage level of the node A is again caused by the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level. The lower voltage level of the node B is again passed through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level. In this cycle, the node A can be charged to the power supply voltage (V DD ), and the logic 1 write operation is completed.
在此值得注意的是,該第一低電壓節點VL1於節點A原本儲存邏輯0,而正寫入邏輯1之期間,係具有等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M23)的電壓位準,而於寫入邏輯1後,又會因經由該第九NMOS電晶體(M26)放電而具有接地電壓之位準。 It should be noted here that the first low voltage node VL1 originally stores a logic 0 at the node A, and has a gate source voltage V GS equal to the sixth NMOS transistor (M23) while the logic 1 is being written. The voltage level of (M23) , after writing logic 1, will have the level of the ground voltage due to discharge through the ninth NMOS transistor (M26).
(三)節點A原本儲存邏輯1,而現在欲寫入邏輯1: (3) Node A originally stores logic 1, but now wants to write logic 1:
在寫入動作發生前(該寫入用字元線WWL為接地電壓),該第一PMOS電晶體(P11)為導通(ON)。當該寫入用字元線(WWL)由Low(接地電壓)轉High(該電源供應電壓VDD),且該寫入用字元線(WWL)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON);此時因為該寫入用位元線(WBL)是High(該電源供應電壓VDD),並且因為該第一PMOS電晶體(P11)仍為ON,所以該節點A的電壓會維持於該電源供應電壓(VDD)之電壓位準,直到寫入週期結束。 Before the write operation occurs (the write word line WWL is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V DD ), and the voltage of the write word line (WWL) is greater than the third NMOS transistor (M13) When the threshold voltage is applied, the third NMOS transistor (M13) is turned from OFF to ON; at this time, since the write bit line (WBL) is High (the power supply voltage V DD ) And because the first PMOS transistor (P11) is still ON, the voltage of the node A is maintained at the voltage level of the power supply voltage (V DD ) until the end of the write cycle.
(四)節點A原本儲存邏輯1,而現在欲寫入邏輯0: (4) Node A originally stores logic 1, but now wants to write logic 0:
在寫入動作發生前(該寫入用字元線WWL為接地電壓),該第一PMOS電晶體(P11)為導通(ON)。當該寫入用字元線(WWL)由Low(接地電壓)轉High(該電源供應電壓VDD),且該寫入用字元線(WWL)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為該寫入用位元線(WBL)是Low(接地電壓),所以會將該節點A以及該第一低電壓節點(VL1)放電而完成邏輯0的寫入動作,直到寫入週期結束。 Before the write operation occurs (the write word line WWL is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V DD ), and the voltage of the write word line (WWL) is greater than the third NMOS transistor (M13) When the threshold voltage is applied, the third NMOS transistor (M13) is turned from OFF to ON. At this time, since the write bit line (WBL) is Low (ground voltage), The node A and the first low voltage node (VL1) are discharged to complete the logic 0 write operation until the end of the write cycle.
第7圖所示之本發明較佳實施例,於寫入操作時之HSPICE暫態分析模擬結果,如第8圖所示,其係使用TSMC 90奈米CMOS製程參數加以模擬,由該模擬結果可証實,本發明所提出之7T雙埠靜態隨機存取記憶體,能藉由寫入期間提高該第一低電壓節點(VL1)之電壓位準,以有效避免習知具單一位元線之雙埠靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 In the preferred embodiment of the present invention shown in FIG. 7, the HSPICE transient analysis simulation result at the time of the write operation is as shown in FIG. 8, which is simulated using the TSMC 90 nm CMOS process parameters, from which the simulation result is obtained. It can be confirmed that the 7T double-chip static random access memory proposed by the present invention can improve the voltage level of the first low voltage node (VL1) during the writing period, thereby effectively avoiding the conventional single bit line. It is quite difficult to write a logic 1 in a double-埠 static random access memory cell.
(II)讀取模式(read mode) (II) Read mode (read mode)
於讀取操作開始前,該讀取控制信號(RC)、寫入控制信號(WC)及該待機模式控制信號(S)均為邏輯低位準,使得該第三PMOS電晶體(P13)導通,並使得該第十NMOS電晶體(M27)截止,於是該第三PMOS電晶體(P13)之汲極呈邏輯高位準,邏輯高位準之該第三PMOS電晶體(P13)之汲極會導通第九NMOS電晶體(M26),並使得該第一低電壓節點(VL1)呈接地電壓。 另一方面,由於該讀取控制信號(RC)為邏輯低位準,使得該第七NMOS電晶體(M24)截止(OFF),並使得該第八NMOS電晶體(M25)導通(ON)。 Before the reading operation starts, the read control signal (RC), the write control signal (WC), and the standby mode control signal (S) are both logic low levels, so that the third PMOS transistor (P13) is turned on. And the tenth NMOS transistor (M27) is turned off, so that the drain of the third PMOS transistor (P13) is at a logic high level, and the logic of the third PMOS transistor (P13) is turned on. Nine NMOS transistors (M26) and the first low voltage node (VL1) is grounded. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned "ON".
在此值得注意的是,於讀取操作開始前之預充電期間,該預充電信號(P)係為邏輯低位準,藉此以將相對應之讀取用位元線(RBL)預充電至該電源供應電壓(VDD)之位準,惟由於例如45奈米以下製程技術之操作電壓將降為1.1±30%以下,此時將造成讀取速度降低而無法滿足規範之問題,因此,本發明提出二階段的讀取控制以於提高讀取速度並滿足規範的同時,亦避免無謂的功率耗損。 It is worth noting here that during pre-charging before the start of the read operation, the pre-charge signal (P) is at a logic low level, thereby pre-charging the corresponding read bit line (RBL) to The power supply voltage (V DD ) is level, but the operating voltage of the process technology such as 45 nm or less will be reduced to 1.1 ± 30% or less, which will cause the reading speed to be lowered to meet the specification problem. The present invention proposes a two-stage read control to improve read speed and meet specifications while avoiding unnecessary power consumption.
第6圖所示之本發明較佳實施例係藉由二階段的讀取控制以於提高讀取速度的同時,亦避免無謂的功率耗損,於讀取操作之第一階段,該讀取控制信號(RC)為邏輯高位準,使得該第七NMOS電晶體(M24)導通,由於此時該第八NMOS電晶體(M25)仍導通,於是該第二低電壓節點(VL2)呈較接地電壓為低之該加速讀取電壓(RGND),該較接地電壓為低之該加速讀取電壓(RGND)可有效提高讀取速度。 The preferred embodiment of the present invention shown in FIG. 6 is controlled by two stages to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the reading operation, the reading control The signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the second low voltage node (VL2) is at a ground voltage. To lower the accelerated read voltage (RGND), the accelerated read voltage (RGND), which is lower than the ground voltage, can effectively increase the read speed.
而於讀取操作之第二階段,雖然該讀取控制信號(RC)仍為邏輯高位準,使得該第七NMOS電晶體(M24)仍為導通,惟由於此時該第八NMOS電晶體(M25)截止,於是該第二低電壓節點(VL2)會經由導通的該第四NMOS電晶體(M21)而呈接地電壓(由於讀取操作期間該反相待機模式控制信號(/S)為邏輯高位準),藉此可有效減少無謂的功率消耗。在此值得注意的是,該讀取操作之該第二階段與該第一階段相隔之時間,係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算,並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之 時間,其值可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。再者,無論於讀取操作之第一階段抑是第二階段,該第四NMOS電晶體(M21)均呈導通狀態(由於讀取操作期間該反相待機模式控制信號(/S)為邏輯高位準)。第9圖所示為第6圖之本發明較佳實施例於讀取期間之簡化電路圖。 In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but since the eighth NMOS transistor (at this time) M25) is turned off, and then the second low voltage node (VL2) is grounded via the turned-on fourth NMOS transistor (M21) (due to the inverted standby mode control signal (/S) during the read operation is logic High level), which can effectively reduce unnecessary power consumption. It is worth noting here that the second phase of the read operation is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the The gate voltage of the eight NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25) The value of time can be adjusted by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1). Furthermore, the fourth NMOS transistor (M21) is in an on state regardless of the first phase of the read operation or the second phase (due to the inverted standby mode control signal (/S) being logic during the read operation High level). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 6 during reading.
(III)待機模式(standby mode) (III) Standby mode
首先,說明第6圖之待機啟動電路(4)如何促使單埠SRAM快速進入待機模式,以有效提高SRAM之待機效能:(1)於進入待機模式之前,該反相待機模式控制信號(/S)為邏輯High,該邏輯High之反相待機模式控制信號(/S)使得該第五PMOS電晶體(P41)截止(OFF),並使得該第十一NMOS電晶體(M41)導通(ON);(2)而於進入待機模式後,該反相待機模式控制信號(/S)為邏輯Low,該邏輯Low之反相待機模式控制信號(/S)使得該第五PMOS電晶體(P41)導通(ON),惟於待機模式之初始期間內(該初始期間係等於該反相待機模式控制信號(/S)由邏輯High轉變為邏輯Low起算,至該第十一NMOS電晶體(M41)之閘極電壓足以關閉該第十一NMOS電晶體(M41)為止之時間,其可藉由該第二延遲電路(D2)所提供之一延遲時間來調整),該第十一NMOS電晶體(M41)仍導通(ON),於是可對該第一低電壓節點(VL1)快速充電到達該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準,亦即7T雙埠SRAM可快速進入待機模式。在此值得注意的是,於待機模式之初始期間後,該第十一NMOS電晶體(M41)關閉並停止供應電流。 First, how the standby start circuit (4) of Fig. 6 causes the 單埠SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: (1) the reverse standby mode control signal (/S) before entering the standby mode. Is logic High, the logic high inversion standby mode control signal (/S) causes the fifth PMOS transistor (P41) to be turned off (OFF), and causes the eleventh NMOS transistor (M41) to be turned on (ON) (2) After entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fifth PMOS transistor (P41) ON (ON), but in the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from logic High to logic Low, to the eleventh NMOS transistor (M41) The gate voltage is sufficient to turn off the eleventh NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2), the eleventh NMOS transistor ( M41) is still turned on (ON), so the first low voltage node (VL1) can be quickly charged to reach the sixth NMOS transistor (M2) 3) The voltage level of the threshold voltage (V TM23 ), that is, the 7T dual-turn SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the eleventh NMOS transistor (M41) is turned off and the supply current is stopped.
請參考第6圖,於待機模式時,該待機模式控制信號(S)為邏輯高位準,而該反相待機模式控制信號(/S)為邏輯低位準,該邏輯低位準之該反相待機模式控制信號(/S)可使得該控制電路(2)中之該第四NMOS電晶體(M21)截止(OFF),而該邏輯高位準之該待機模式控制信號(S)則使得該第五NMOS電晶體(M22)導通(ON),此時該第五NMOS電晶體(M22)係作為等化器(equalizer)使用,因此可藉由呈導通狀態之該第五NMOS電晶體(M22),以使得該第一低電壓節點(VL1)之電壓位準相等於該第二低電壓節點(VL2)之電壓位準,且該等電壓位準均會等於該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準。第10圖所示為第6圖之本發明較佳實施例於待機期間之簡化電路圖。 Please refer to FIG. 6 . In the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (M21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (M22) is turned on (ON), and the fifth NMOS transistor (M22) is used as an equalizer, so that the fifth NMOS transistor (M22) in an on state can be used. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V TM23 ). Figure 10 is a simplified circuit diagram of the preferred embodiment of the present invention in Figure 6 during standby.
接下來說明本發明於待機模式(standby mode)時如何減少漏電流,請參考第10圖,第10圖描述有本發明實施例處於待機模式時所產生之各漏電流(subthreshold leakage current)I1、I2、I3、I4,其中假設SRAM晶胞中之該第一反相器之輸出(即節點A)為邏輯Low(在此值得注意的是,由於待機模式時該第二低電壓節點(VL2)之電壓位準係維持在該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準,因此節點A為邏輯Low之電壓位準亦維持在該VTM23的電壓位準),而該第二反相器之輸出(即節點B)為邏輯High(電源供應電壓VDD)。請參考第5圖之傳統8T雙埠SRAM與第10圖之本發明實施例,來說明本發明所提出之7T雙埠靜態隨機存取記憶體與第5圖之傳統8T雙埠SRAM於漏電流方面之比較,首先關於流經該第三NMOS電晶體(M13)之漏電流I1,由於本發明於待機模式時節點A之電壓位準係維持在該VTM23的電壓位準,且假設該寫入用字元線(WWL)於 待機模式時係設定成接地電壓,而該寫入用位元線(WBL)於待機模式時則設定為該電源供應電壓(VDD),因此本發明之第三NMOS電晶體(M13)的閘源極電壓(VGS)為負值,反觀於待機模式時第5圖之傳統8T雙埠SRAM之NMOS電晶體(M3)的閘源極電壓(VGS)等於0,根據閘極引發汲極洩漏(Gate Induced Drain Leakage,簡稱GIDL)效應或2005年3月8日第US6865119號專利案第3(A)及3(B)圖之結果可知,對於NMOS電晶體而言,閘源極電壓為-0.1伏特時之次臨界電流約為閘源極電壓為0伏特時之次臨界電流的1%,因此導因於GIDL效應所引發之流經本發明之該第三NMOS電晶體(M13)之漏電流I1遠小於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M3)者;再者,本發明該第三NMOS電晶體(M13)之汲源極電壓(VDS)為該電源供應電壓(VDD)扣減該VTM23的電壓位準,反觀於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M3)之汲源極電壓(VDS)係等於該電源供應電壓(VDD),根據汲極引發能障下跌(Drain-Induced Barrier Lowering,簡稱DIBL)效應,由於DIBL效應所引發之流經本發明之該第三NMOS電晶體(M13)之漏電流I1亦小於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M3)者;結果,流經本發明之該第三NMOS電晶體(M13)之漏電流I1遠小於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M3)者。 Next, how to reduce leakage current in the standby mode of the present invention is described. Referring to FIG. 10, FIG. 10 depicts a leakage current I 1 generated when the embodiment of the present invention is in the standby mode. I 2 , I 3 , I 4 , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage is due to the standby mode) The voltage level of the node (VL2) is maintained at the voltage level of the threshold voltage (V TM23 ) of the sixth NMOS transistor (M23), so the voltage level of the node A is the logic Low and the voltage of the V TM23 is also maintained. The level of the output of the second inverter (ie, node B) is a logic high (power supply voltage V DD ). Please refer to the conventional 8T dual-SRAM SRAM of FIG. 5 and the embodiment of the present invention of FIG. 10 to illustrate the leakage current of the 7T dual-static static random access memory proposed by the present invention and the conventional 8T dual-turn SRAM of FIG. In comparison, firstly, regarding the leakage current I 1 flowing through the third NMOS transistor (M13), since the voltage level of the node A in the standby mode is maintained at the voltage level of the V TM23 , and the The write word line (WWL) is set to the ground voltage in the standby mode, and the write bit line (WBL) is set to the power supply voltage (V DD ) in the standby mode, so the present invention The gate-source voltage (V GS ) of the third NMOS transistor (M13) is a negative value, and the gate-source voltage of the NMOS transistor (M3) of the conventional 8T dual-SRAM SRAM of FIG. 5 in the standby mode (V GS) ) is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect or the results of Figures 3 (A) and 3 (B) of US Pat. No. 6,865,119, March 8, 2005, for NMOS In the case of a transistor, the subcritical current when the gate source voltage is -0.1 volt is about 1% of the subcritical current when the gate source voltage is 0 volts. Therefore, the leakage current I 1 of the third NMOS transistor (M13) flowing through the present invention caused by the GIDL effect is much smaller than that of the conventional 8T double-SRAM NMOS transistor (M3) of FIG. 5; The 汲 source voltage (V DS ) of the third NMOS transistor (M13) of the present invention deducts the voltage level of the V TM23 from the power supply voltage (V DD ), and the conventional 8T double 第 in FIG. 5 The 汲 source voltage (V DS ) of the SRAM NMOS transistor (M3) is equal to the power supply voltage (V DD ), which is based on the Drain-Induced Barrier Lowering (DIBL) effect due to the DIBL effect. The induced leakage current I 1 flowing through the third NMOS transistor (M13) of the present invention is also smaller than the NMOS transistor (M3) of the conventional 8T double-turn SRAM of FIG. 5; as a result, the third of the present invention flows through The leakage current I 1 of the NMOS transistor (M13) is much smaller than that of the conventional 8T double-SRAM NMOS transistor (M3) of FIG.
接著關於流經該第一PMOS電晶體(P11)之漏電流I2,由於待機模式時該第一PMOS電晶體(P11)之源極係為該電源供應電壓(VDD),而該第一PMOS電晶體(P11)之汲極係維持在該VTM23的電壓位準,因此本發明之該第一PMOS電晶體(P11)之源汲極電壓(VSD)為該電源供應電壓(VDD)扣減該VTM23的電壓位準,反觀於第5圖之傳統8T雙埠SRAM之 PMOS電晶體(P1)之源汲極電壓(VSD)係等於該電源供應電壓(VDD),根據DIBL效應,因此流經本發明之該第一PMOS電晶體(P11)之漏電流I2會小於第1b圖先前技藝之PMOS電晶體(P1)者。 Next, regarding the leakage current I 2 flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (V DD ) due to the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the VTM23 , so the source drain voltage (V SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V DD ) Deducting the voltage level of the V TM23 , the source drain voltage (V SD ) of the PMOS transistor (P1) of the conventional 8T dual-SRAM SRAM of FIG. 5 is equal to the power supply voltage (V DD ), according to The DIBL effect, therefore, the leakage current I 2 flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P1) of Figure 1b.
然後,關於流經該第二NMOS電晶體(M12)之漏電流I3,由於待機模式時該第二低電壓節點(VL2)之電壓位準係維持在該VTM23的電壓位準,節點A之電壓位準亦維持在該VTM23的電壓位準,而節點B之電壓位準係等於該電源供應電壓(VDD)且該第二NMOS電晶體(M12)之基底為接地電壓,因此本發明之該第二NMOS電晶體(M12)的基源極電壓(VBS)為負值,且該第二NMOS電晶體(M12)之汲源極電壓(VDS)為該電源供應電壓(VDD)扣減該VTM23的電壓位準,反觀於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M2)的基源極電壓(VBS)等於0,且NMOS電晶體(M2)之汲源極電壓(VDS)等於該電源供應電壓(VDD),根據本體效應(body effect)及DIBL效應可知,流經本發明之該第二NMOS電晶體(M12)之漏電流I3遠小於第5圖之傳統8T雙埠SRAM之NMOS電晶體(M2)者。 Then, regarding the leakage current I 3 flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V TM23 in the standby mode, the node A The voltage level is also maintained at the voltage level of the V TM23 , and the voltage level of the node B is equal to the power supply voltage (V DD ) and the base of the second NMOS transistor (M12) is the ground voltage, so The base-source voltage (V BS ) of the second NMOS transistor (M12) of the invention is a negative value, and the 汲 source voltage (V DS ) of the second NMOS transistor (M12) is the power supply voltage (V) DD ) deducting the voltage level of the V TM23 , and the base-source voltage (V BS ) of the NMOS transistor (M2) of the conventional 8T double-turn SRAM of FIG. 5 is equal to 0, and the NMOS transistor (M2) The source voltage (V DS ) is equal to the power supply voltage (V DD ). According to the body effect and the DIBL effect, the leakage current I 3 flowing through the second NMOS transistor (M12) of the present invention is much smaller than Figure 5 is a conventional 8T dual-SRAM NMOS transistor (M2).
最後,關於流經該第一讀取用電晶體(M14)之漏電流I4,由於本發明與第5圖之傳統8T雙埠SRAM之讀取方式不同,且本發明待機模式下之讀取用位元線(RBL)可設定成接地電壓,而第5圖之傳統8T雙埠SRAM為了防止節點B之電壓位準下降,待機模式下之讀取用位元線對(RBL、RBLB)係設定成電源供應電壓,因此無從比較流經該第一讀取用電晶體(M14)之漏電流I4。綜合以上分析可知,本發明所提出之7T雙埠靜態隨機存取記憶體與第5圖之傳統8T雙埠SRAM相較具有較低之漏電流。 Finally, regarding the leakage current I 4 flowing through the first read transistor (M14), since the present invention is different from the conventional 8T dual-turn SRAM of FIG. 5, and the reading is performed in the standby mode of the present invention. The bit line (RBL) can be set to the ground voltage, and the conventional 8T double-turn SRAM of FIG. 5 is used to prevent the voltage level of the node B from falling. The read bit line pair (RBL, RBLB) in the standby mode is Since the power supply voltage is set, it is not possible to compare the leakage current I 4 flowing through the first read transistor (M14). Based on the above analysis, the 7T dual-static SRAM of the present invention has a lower leakage current than the conventional 8T dual-SRAM SRAM of FIG.
(IV)保持模式(hold mode) (IV) hold mode
保持模式時,由於該第一低電壓節點(VL1)與該第二低電壓節點(VL2)均設定成接地電壓,其工作原理相同於傳統具單一位元線之雙埠SRAM晶胞,於此不再累述。 In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to ground voltage, the working principle is the same as that of the conventional double-bit SRAM cell with a single bit line. No longer said.
本發明所提出之7T雙埠靜態隨機存取記憶體,具有如下功效: The 7T double-click static random access memory proposed by the invention has the following effects:
(1)高讀取速度並避免無謂的功率消耗:本發明所提出之7T雙埠靜態隨機存取記憶體係採用二階段讀取操作,於讀取操作之第一階段藉由將該第二低電壓節點(VL2)設定成較接地電壓為低之該加速讀取電壓(RGND)以有效提高讀取速度,而於讀取操作之第二階段則藉由將該第二低電壓節點(VL2)設定回接地電壓,以便減少無謂的功率消耗;(2)快速進入待機模式:由於本發明所提出之7T雙埠靜態隨機存取記憶體設置有待機啟動電路(4)以促使SRAM快速進入待機模式,並藉此以謀求提高7T雙埠SRAM之待機效能;(3)避免寫入邏輯1困難之問題:本發明所提出之7T雙埠靜態隨機存取記憶體於寫入操作時,可藉由提高該第一低電壓節點(VL1)之電壓位準以有效避免習知具單一位元線之雙埠SRAM存在寫入邏輯1相當困難之問題;(4)低待機電流:由於本發明所提出之7T雙埠靜態隨機存取記憶體於待機模式時,可藉由呈導通狀態之該第五NMOS電晶體(M22),以使得該第一低電壓節點(VL1)之電壓位準相等於該第二低電壓節點(VL2)之電壓位準,並使得該等電壓位準均等於該第六NMOS電晶體(M23)之臨界電壓的位準,因此本發明所提出之7T雙埠靜態隨機存取記憶體亦具備低待機電流之功效;(5)有效降低半選定晶胞干擾:本發明所提出之7T雙埠靜態隨機存取記憶體由於使用分離的讀/寫路徑,且該讀取路徑係設計成將該第一和第二 讀取用電晶體(M14和M15)串聯連接在該讀取用位元線(RBL)與該第二低電壓節點(VL2)之間,並將該反相儲存節點(B)連接至該第二讀取用電晶體(M15)的閘極,因此可有效降低半選定晶胞干擾(half-selected cell disturbance),其中半選定晶胞係指被該讀取用字元線(RWL)選定但未被該讀取用位元線(RBL)選定之晶胞。 (1) High read speed and avoiding unnecessary power consumption: The 7T dual-static static random access memory system proposed by the present invention employs a two-stage read operation, in the first stage of the read operation, by the second low The voltage node (VL2) is set to be lower than the ground voltage by the accelerated read voltage (RGND) to effectively increase the read speed, and in the second phase of the read operation by the second low voltage node (VL2) Set back ground voltage to reduce unnecessary power consumption; (2) Quickly enter standby mode: Since the 7T dual-static SRAM memory proposed by the present invention is provided with a standby start circuit (4) to prompt the SRAM to quickly enter standby mode And in order to improve the standby performance of the 7T dual-SRAM SRAM; (3) to avoid the difficulty of writing logic 1: the 7T dual-static static random access memory proposed by the present invention can be used in the write operation Increasing the voltage level of the first low voltage node (VL1) to effectively avoid the problem that it is difficult to write the logic 1 in the double-turn SRAM with a single bit line; (4) low standby current: due to the present invention 7T double-click static random access memory In the standby mode, the voltage of the first low voltage node (VL1) is equal to the voltage of the second low voltage node (VL2) by the fifth NMOS transistor (M22) in an on state. The level is such that the voltage levels are equal to the level of the threshold voltage of the sixth NMOS transistor (M23), so the 7T dual-static SRAM of the present invention also has the effect of low standby current. (5) Effectively reducing half-selected cell interference: The 7T double-click static random access memory proposed by the present invention uses separate read/write paths, and the read path is designed to be the first and second Reading transistors (M14 and M15) are connected in series between the read bit line (RBL) and the second low voltage node (VL2), and the inverting storage node (B) is connected to the first Reading the gate of the transistor (M15), thereby effectively reducing the half-selected cell disturbance, wherein the half-selected cell is selected by the read word line (RWL) but A cell selected by the read bit line (RBL).
(6)低電晶體數:對於具有1024列1024行之SRAM陣列而言,傳統第5圖之8T雙埠SRAM陣列共需1024×1024×8=8,388,608顆電晶體,而本發明所提出之7T雙埠靜態隨機存取記憶體僅至少需1024×1024×7+1024×16+6=7,356,422顆電晶體,其減少12.3%之電晶體數。 (6) Low number of transistors: For an SRAM array having 1024 columns and 1024 rows, the 8T dual-SRAM array of the conventional FIG. 5 requires a total of 1024×1024×8=8,388,608 transistors, and the 7T proposed by the present invention The double-埠 static random access memory requires only at least 1024 × 1024 × 7 + 1024 × 16 + 6 = 7,356, 422 transistors, which reduces the number of transistors by 12.3%.
雖然本發明特別揭露並描述了所選之較佳實施例,但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本發明的精神與範圍。因此,所有相關技術範疇內之改變都包括在本發明之申請專利範圍內。 While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.
1‧‧‧SRAM晶胞 1‧‧‧SRAM cell
2‧‧‧控制電路 2‧‧‧Control circuit
3‧‧‧預充電電路 3‧‧‧Precharge circuit
4‧‧‧待機啟動電路 4‧‧‧Standby start circuit
P11‧‧‧第一PMOS電晶體 P11‧‧‧First PMOS transistor
P12‧‧‧第二PMOS電晶體 P12‧‧‧Second PMOS transistor
M11‧‧‧第一NMOS電晶體 M11‧‧‧First NMOS transistor
M12‧‧‧第二NMOS電晶體 M12‧‧‧Second NMOS transistor
M13‧‧‧第三NMOS電晶體 M13‧‧‧ Third NMOS transistor
A‧‧‧儲存節點 A‧‧‧ storage node
B‧‧‧反相儲存節點 B‧‧‧ Inverting storage node
VDD‧‧‧電源供應電壓 V DD ‧‧‧Power supply voltage
M14‧‧‧第一讀取用電晶體 M14‧‧‧First read transistor
M15‧‧‧第二讀取用電晶體 M15‧‧‧Second reading transistor
WBL‧‧‧寫入用位元線 WBL‧‧‧Write bit line
WWL‧‧‧寫入用字元線 WWL‧‧‧write word line
RBL‧‧‧讀取用位元線 RBL‧‧‧Reading bit line
RWL‧‧‧讀取用字元線 RWL‧‧‧Read word line
S‧‧‧待機模式控制信號 S‧‧‧Standby mode control signal
/S‧‧‧反相待機模式控制信號 /S ‧‧‧Inverted standby mode control signal
VL1‧‧‧第一低電壓節點 VL1‧‧‧ first low voltage node
VL2‧‧‧第二低電壓節點 VL2‧‧‧ second low voltage node
M21‧‧‧第四NMOS電晶體 M21‧‧‧4th NMOS transistor
M22‧‧‧第五NMOS電晶體 M22‧‧‧ Fifth NMOS transistor
M23‧‧‧第六NMOS電晶體 M23‧‧‧ sixth NMOS transistor
M24‧‧‧第七NMOS電晶體 M24‧‧‧ seventh NMOS transistor
M25‧‧‧第八NMOS電晶體 M25‧‧‧8th NMOS transistor
M26‧‧‧第九NMOS電晶體 M26‧‧‧Ninth NMOS transistor
M27‧‧‧第十NMOS電晶體 M27‧‧‧ tenth NMOS transistor
P21‧‧‧第三PMOS電晶體 P21‧‧‧ Third PMOS transistor
RC‧‧‧讀取控制信號 RC‧‧‧ read control signal
RGND‧‧‧加速讀取電壓 RGND‧‧‧Accelerated reading voltage
WC‧‧‧寫入控制信號 WC‧‧‧ write control signal
C‧‧‧節點 C‧‧‧ node
INV‧‧‧第三反相器 INV‧‧‧ third inverter
D1‧‧‧第一延遲電路 D1‧‧‧First delay circuit
P31‧‧‧第四NMOS電晶體 P31‧‧‧4th NMOS transistor
P‧‧‧預充電信號 P‧‧‧Precharge signal
M41‧‧‧第十一NMOS電晶體 M41‧‧11 eleventh NMOS transistor
P41‧‧‧第五PMOS電晶體 P41‧‧‧ Fifth PMOS transistor
D2‧‧‧第二延遲電路 D2‧‧‧second delay circuit
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI573138B (en) * | 2015-05-08 | 2017-03-01 | 修平學校財團法人修平科技大學 | 7t dual port static random access memory (7) |
TWI573137B (en) * | 2016-02-24 | 2017-03-01 | 修平學校財團法人修平科技大學 | 7t dual port static random access memory |
TWI573139B (en) * | 2015-10-07 | 2017-03-01 | 修平學校財團法人修平科技大學 | Single port static random access memory |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7986571B2 (en) * | 2008-06-09 | 2011-07-26 | International Business Machines Corporation | Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines |
US8760958B2 (en) * | 2012-03-15 | 2014-06-24 | Memoir Systems, Inc. | Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist |
TW201426753A (en) * | 2012-12-27 | 2014-07-01 | Univ Hsiuping Sci & Tech | Static random access memory with five transistors |
WO2014149504A1 (en) * | 2013-03-15 | 2014-09-25 | Intel Corporation | Dual-port static random access memory (sram) |
US8879305B2 (en) * | 2011-12-16 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell |
-
2014
- 2014-12-01 TW TW103141646A patent/TWI556238B/en not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7986571B2 (en) * | 2008-06-09 | 2011-07-26 | International Business Machines Corporation | Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines |
US8879305B2 (en) * | 2011-12-16 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell |
US8760958B2 (en) * | 2012-03-15 | 2014-06-24 | Memoir Systems, Inc. | Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist |
TW201426753A (en) * | 2012-12-27 | 2014-07-01 | Univ Hsiuping Sci & Tech | Static random access memory with five transistors |
WO2014149504A1 (en) * | 2013-03-15 | 2014-09-25 | Intel Corporation | Dual-port static random access memory (sram) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI573138B (en) * | 2015-05-08 | 2017-03-01 | 修平學校財團法人修平科技大學 | 7t dual port static random access memory (7) |
TWI573139B (en) * | 2015-10-07 | 2017-03-01 | 修平學校財團法人修平科技大學 | Single port static random access memory |
TWI573137B (en) * | 2016-02-24 | 2017-03-01 | 修平學校財團法人修平科技大學 | 7t dual port static random access memory |
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