TWI660364B - Seven transistor dual port static random access memory - Google Patents

Abstract

The invention proposes a 7T dual-port static random access memory, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start circuit (4), A plurality of high-voltage level control circuits (5) and a plurality of write driving circuits (6). The memory array is composed of a plurality of rows of memory cell units and a plurality of rows of memory unit cells, and each column of memory cell units A control circuit (2) and a high-voltage level control circuit (5) are provided, and a precharge circuit (3) and a write drive circuit (6) are provided for each row of memory cells. Therefore, in the write mode, the plurality of control circuits (2) and the plurality of write driving circuits (6) can be used to effectively prevent the difficulty of writing the logic 1 while increasing the speed of writing the logic 1 In the reading mode, the plurality of control circuits (2) and the plurality of high-voltage level control circuits (5) can be used to improve the reading speed while avoiding unnecessary power consumption. In the standby mode At this time, the plurality of control circuits (2) can effectively reduce the leakage current, and the design of the standby start circuit (4) can effectively promote the 7T dual-port static random access memory to quickly enter the standby mode.

Description

7T dual-port static random access memory

The invention relates to a 7T dual port static random access memory (SRAM), in particular to a 7T SRAM which can effectively improve the standby performance of the 7T SRAM and can effectively improve the reading speed and the writing speed. SRAM, which can effectively reduce leakage current, reduce half-selected cell interference during reading, and avoid unnecessary power loss.

As shown in Figure 1a, the conventional static random access memory (SRAM) in the port includes a memory array. The memory array is composed of a plurality of memory blocks (MB _1). , MB ₂ etc.), each memory block is further composed of a plurality of rows of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word lines, WL ₁ , WL _2, etc.), each character line corresponds to a plurality of rows of memory One column in the unit cell; and multiple bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _m, etc.), each bit line pair corresponds to the multiple row memory cell One row, and each bit line pair is composed of a bit line (BL ₁ ... BL _m ) and a complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b is a schematic circuit diagram of a 6T port static random access memory (SRAM) cell. Among them, the PMOS transistors (P1) and (P2) are called load transistors and NMOS transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL BLB and BLB are bit line and complementary bit line, respectively. Since this port SRAM cell requires 6 transistors, and to read the logic 0, in order to avoid the initial instant of the read operation (initial instant) Another driving transistor is turned on, and the initial instantaneous voltage (V _AR ) read by node A must satisfy equation (1): V _AR = V _DD × (R _M1 ) / (R _M1 + R _M3 ) <V _TM2 (1) to prevent half-selected cell disturbance during reading, where V _AR represents the initial instantaneous voltage of node A and R _M1 and R _M3 respectively represent the NMOS transistor (M1 ) and the NMOS transistor (M3) of the on-resistance, and V _DD and V _TM2 represent the power supply voltage and the threshold voltage of the NMOS transistor (M2), the driving voltage which results in The current drive capability ratio (ie, the cell ratio) between the body and the access transistor is usually set between 2.2 and 3.5 (please refer to US Patent No. US76060B2 of October 20, 1998, column 2 columns 8-10 Row).

Figure 1b shows the simulation results of HSPICE transient analysis during the write operation of the 6T-port static random access memory cell. As shown in Figure 2, it is simulated using TSMC 90nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a circuit diagram of a 5T SRAM cell with a single bit line. Compared with the 6T SRAM cell in Figure 1b, this 5T static The RAM cell has one transistor and one bit line less than the 6T SRAM cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2. And in the case of the channel width-to-length ratio of the NMOS transistors M1, M2, and M3, there is a problem that it is quite difficult to write a logic 1. Consider the case where node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transferred from the bit line (BL), the logic 0 previously written in node A is overwritten by the logic 1 The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 ) / (R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of node A, R _M1 and R _M3 represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3), respectively. Comparing equation (1) and equation (2), it can be seen that the initial instantaneous voltage (V _AW ) is less than the NMOS transistor (M2 ) Threshold voltage (V _TM2 ), so the operation of writing logic 1 cannot be completed. The simulation results of HSPICE transient analysis during the write operation of the 5T SRAM cell shown in Figure 3, as shown in Figure 4, are simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that the 5T SRAM cell with a single bit line has the problem of writing logic 1 quite difficult.

Next, we discuss the SRAM and dual-port architecture. The 6T SRAM cell in Figure 1b is the SRAM static-access memory (SRAM) crystal. For example, it uses two bit lines BL and BLB for reading and writing, that is, reading and writing are achieved through the same pair of bit lines, so that only reading or writing can be performed at the same time. Write operation, therefore, when you want to design dual-port static random access memory with simultaneous read and write capabilities, you need to add two more access transistors and another pair of bit lines (refer to Figure 5) Circuit, where WBL and WBLB are bit line pairs for writing, RBL and RBLB are bit line pairs for reading, WWL is a word line for writing, and RWL is a word line for reading), which makes the memory The area of the cell is greatly increased. If we can simplify the structure of the memory cell, The bit line is responsible for reading, and the other bit line is responsible for writing. When designing a dual-port static random access memory, the memory cell does not need to add two additional transistors and a pair. Bit line, so the area of the memory cell will be reduced a lot. The traditional dual-port static random access memory cell does not use this method because it is very difficult to write logic 1 as described above. Problem.

To date, many technologies for dual-port static random access memory cells with a single bit line have been proposed, such as the "7T dual-port static random access memory" proposed in Patent Document 1 (TWI541802 on July 11, 105). "Access Memory (1)", "Dual write wordline memory cell" proposed in Patent Document 2 (US9336863B2, May 10, 105), and Patent Document 3 (US 9275724B2, March 1, 105) "Method of writing to and reading data from a three-dimensional two port register file", "Dual-Port Static Random Access Memory" proposed by Patent Document 4 (June 11, 103, TWI441178), Patent Document No. 5 (US8737117B2, May 27, 103), "System and method to read a memory cell with a complementary metal-oxide-semiconductor (CMOS) read transistor", Patent Document 6 (No. 6, May 103, US8717807B2) "Independently-controlled-gate SRAM", Patent Document 7 (April 1, 103, TWI433152), "7T Dual-Port SRAM", Patent Document 8 (February 1, 103 TWI425509) proposed `` dual port with discharge path State random access memory ", Patent Document 9 (TWI423257 of January 11, 103)," Dual-port SRAM with reduced power supply voltage during write operation ", Patent Document 10 (No. 11 of January 103, 103 TWI423258) proposed "Dual-port static random access memory to increase the voltage level of the word line for writing during writing operation". Although these patents can effectively solve the problem of writing logic 1, And other patents have not considered the system When the operating voltage below 20 nanometers is reduced to less than 1 volt, the write speed and read speed are reduced, so there is still room for improvement.

In view of this, the main purpose of the present invention is to propose a 7T dual-port static random access memory, which can effectively improve the reading speed by a dual mechanism of a control circuit and a high voltage level control circuit.

A secondary object of the present invention is to propose a 7T dual-port static random access memory, which can effectively prevent write logic by pulling the bit line voltage level higher than the power supply voltage of the write drive circuit. At the same time, it can effectively improve the writing speed.

Another object of the present invention is to provide a 7T dual-port static random access memory, which can improve the reading speed through two-stage read control while avoiding unnecessary power consumption.

The invention proposes a 7T dual-port static random access memory, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start circuit (4), A plurality of high-voltage level control circuits (5) and a plurality of write driving circuits (6). The memory array is composed of a plurality of rows of memory cell units and a plurality of rows of memory unit cells, and each column of memory cell units A control circuit (2) and a high-voltage level control circuit (5) are provided, and a precharge circuit (3) and a write drive circuit (6) are provided for each row of memory cells. Therefore, in the write mode, the plurality of control circuits (2) and the plurality of write driving circuits (6) can be used to effectively prevent the difficulty of writing the logic 1 while increasing the speed of writing the logic 1 In the reading mode, the plurality of control circuits (2) and the plurality of high voltage level control circuits (5) can be used to improve the reading speed while avoiding unnecessary power Consumption, in standby mode, the plurality of control circuits (2) can be used to effectively reduce leakage current, and the standby start circuit (4) can be used to effectively promote 7T static random access memory to quickly enter Standby mode.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧ pre-charge circuit

4‧‧‧ Standby start circuit

5‧‧‧high voltage level control circuit

6‧‧‧write drive circuit

P11‧‧‧The first PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧The first NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧Third NMOS transistor

A‧‧‧Storage Node

B‧‧‧ Inverted Storage Node

C‧‧‧node

M14‧‧‧First reading transistor

M15‧‧‧Second reading transistor

WBL‧‧‧Bit line for writing

WWL‧‧‧writing character line

RBL‧‧‧Bit line for reading

RWL‧‧‧Read Character Line

S‧‧‧Standby mode control signal

/ S ‧‧‧ Inverted standby mode control signal

VL1‧‧‧The first low voltage node

VL2‧‧‧Second Low Voltage Node

M21‧‧‧Fourth NMOS transistor

M22‧‧‧Fifth NMOS transistor

M23‧‧‧sixth NMOS transistor

M24‧‧‧Seventh NMOS transistor

M25‧‧‧eighth NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧Tenth NMOS Transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

INV‧‧‧Third Inverter

D1‧‧‧first delay circuit

P31‧‧‧Third PMOS transistor

P‧‧‧Pre-charge signal

M41‧‧‧ Eleventh NMOS transistor

P41‧‧‧Fourth PMOS transistor

D2‧‧‧Second Delay Circuit

V _DD ‧‧‧ Power supply voltage

V _DDH1 ‧‧‧ Highest power supply voltage

V _DDH2 ‧‧‧ the second highest power supply voltage

P51‧‧‧Fifth PMOS transistor

P52‧‧‧Sixth PMOS transistor

I53‧‧‧Fourth inverter

VH‧‧‧High Voltage Node

P61‧‧‧Seventh PMOS transistor

P62‧‧‧eighth PMOS transistor

P63‧‧‧9th PMOS transistor

P64‧‧‧Tenth PMOS transistor

M61‧‧‧Thirteenth NMOS Transistor

M62‧‧‧ Fourteenth NMOS Transistor

I63‧‧‧Fifth inverter

Din‧‧‧Enter data

/ WC‧‧‧ Inverted write control signal

BLB ₁ ^… BLB _m ‧‧‧ complementary bit line

BLB‧‧‧ Complementary Bit Line

MB ₁ ^… MB _k ‧‧‧Memory block

WL ₁ ^… WL _n ‧‧‧Character line

BL ₁ ^… BL _m ‧‧‧bit line

M1 ^… M4‧‧‧NMOS transistor

P1 ^… P2‧‧‧PMOS transistor

I ₁ , I ₂ , I ₃ , I ₄ ‧‧‧ Leakage current

WC‧‧‧ write control signal

Figure 1a shows a conventional static random access memory cell; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; Figure 2 shows a conventional 6T static random access memory cell Figure 3 is a timing diagram of a conventional 5T SRAM cell; Figure 4 is a timing diagram of a conventional 5T SRAM cell; FIG. 5 is a circuit diagram showing a conventional 8T dual-port static random access memory cell; FIG. 6 is a circuit diagram showing a circuit proposed by a preferred embodiment of the present invention; FIG. 7 is a diagram showing the present invention of FIG. 6 A simplified circuit diagram of the preferred embodiment during a write logic 1; FIG. 8 is a timing diagram of the write operation of the preferred embodiment of the present invention in FIG. 6; FIG. 9 is a preferred implementation of the present invention in FIG. 6 Example is a simplified circuit diagram during reading; Figure 10 is a simplified circuit diagram of the preferred embodiment of the present invention shown in Figure 6 during standby.

According to the above main object, the present invention proposes a 7T dual-port static random access memory, which mainly includes a memory array, the memory array is composed of a plurality of rows of memory cell units and a plurality of rows of memory unit cells, Each column of memory cell and each row of memory cell includes a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells A control circuit (2) is provided; a plurality of pre-charging circuits (3), a pre-charging circuit (3) is provided for each row of memory cells; a standby start-up circuit (4), the standby start-up circuit (4) promotes 7T The dual-port SRAM quickly enters the standby mode to effectively improve the standby performance of the 7T dual-port SRAM; a plurality of high-voltage level control circuits (5), each column of memory cells is provided with a high-voltage level control circuit (5), The read speed is further improved when the logic 0 is read; and a plurality of write drive circuits (6), one write drive circuit (6) is provided for each row of memory cells.

For ease of explanation, the 7T dual-port static random access memory shown in Figure 6 consists of only one memory cell (1), one writing word line (WWL), and one writing bit line. (WBL), a read word line (RWL), a read bit line (RBL), a control circuit (2), a precharge circuit (3), a standby start circuit (4), a The high voltage level control circuit (5) and a write driving circuit (6) are described as examples. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor) Crystal P12 and a second NMOS transistor M12), a third NMOS transistor (M13), a first reading transistor (M14), and a second reading transistor (M15), among which, The first inverter and the second inverter are connected by mutual coupling, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the second inverter The output of the phase inverter (node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the second inverter The output (node B) is used to store the inverted data of the SRAM cell.

The first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11) of the memory cell (1) is connected to a power supply voltage (V _DD ) and a first Between the low voltage node (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected between a high voltage node (VH) and a second low Between the voltage node (VL2), the source, gate and drain of the first reading transistor (M14) are connected to the drain and reading of the second reading transistor (M15), respectively. A word line (RWL) and the read bit line (RBL) are used, and a source, a gate, and a drain of the second read transistor (M15) are respectively connected to the second low-voltage node (VL2), the output of the second inverter (ie, node B) and the source of the first reading transistor (M14).

Please refer to FIG. 6 again. The control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control Signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), an inverted write control signal ( / WC), a standby mode control signal (S), and an inverted standby mode control signal (/ S). The source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverting standby mode control signal (/ S) and the second low voltage node (VL2); the fifth The source, gate, and drain of the NMOS transistor (M22) are connected to the first low-voltage node (VL1), the standby mode control signal (S), and the second low-voltage node (VL2); the first The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) The gate, the drain and the drain are connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2) respectively; the eighth NMOS The source, gate and drain of the transistor (M25) are connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24), respectively. The first delay circuit (D1) is connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (M25); The input is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the source, gate and drain of the ninth NMOS transistor (M26) are connected separately To the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27) are connected to the Write control signal (WC), the standby mode control signal (S) and the gate of the ninth NMOS transistor (M26); and the source, gate, and drain of the eleventh NMOS transistor (M28) It is respectively connected to the gates of the inverted write control signal (/ WC), the inverted standby mode control signal (/ S) and the ninth NMOS transistor (M26). It is worth noting here that the inverted standby mode control signal (/ S) is obtained by the standby mode control signal (S) via an inverter, and the inverted write control signal (/ WC) is obtained by A write control signal (WC) is obtained via another inverter.

It is worth noting here that the drain of the eleventh NMOS transistor (M28), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together. A node (C) is formed. When the standby mode control signal (S) is at a logic low level, the voltage level of the node (C) is the logic level of the inverted write control signal (/ WC), and When the standby mode control signal (S) is at a logic high level, the voltage level of the node (C) is the logic level of the write control signal (WC), thereby effectively preventing undesired conditions in the standby mode. Factors caused by erroneous writing; moreover, the logic high level of the node (C) is the power supply voltage (V _DD ) _{minus a} threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28) Voltage level of the node, so when the 7T dual-port static random access memory is in a non-write mode (the corresponding write control signal (/ WC) is logic high), the node (C) the power supply voltage line (V _DD) deduct the eleventh NMOS transistor (M28) of the threshold voltage (V _TM28) voltage level, rather than the power supply voltage (V _DD) for the Voltage level, so it can have lower power consumption; and when it enters the write mode subsequently (at this time the corresponding inverted write control signal (/ WC) is a logic low level), it can be quickly stored in The charge of the node (C) is discharged through the eleventh NMOS transistor (M28) enough to turn off the ninth NMOS transistor (M26) with the node (C) as the gate, so it can enter the write faster Into the mode.

The control circuit (2) is designed to control the voltage levels of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes. In the write mode, the unit cell is selected. The source voltage (that is, the first low-voltage node VL1) of the driving transistor (that is, the first NMOS transistor M11) that is closer to the bit line (WBL) for writing is set to be one higher than the ground voltage The predetermined voltage (i.e., the gate-source voltage V _{GS (M23) of} the sixth NMOS transistor (M23)) and the source voltage of another driving transistor (i.e., the second NMOS transistor M12) in the selected cell ( That is, the second low voltage node VL2) is set to a ground voltage in order to prevent the problem of writing logic 1 from being difficult.

In the first stage of the read mode, the source voltage (that is, the second lowest value) of the driving transistor (that is, the second NMOS transistor M12) that is closer to the read bit line (RBL) in the selected cell is selected. The voltage node VL2) is set to a voltage lower than the ground voltage. The second low-voltage node VL2, which is lower than the ground voltage, can effectively improve the reading speed. During the second stage of the reading mode, the crystal is selected. The source voltage of the driving transistor (ie, the second NMOS transistor M12) that is closer to the read bit line (RBL) in the cell is set back to the ground voltage in order to reduce unnecessary power consumption. The time interval between the second phase and the first phase of the read mode is equal to that when the read control signal (RC) changes from a logic low level to a logic high level, and reaches the eighth NMOS transistor (M25). The gate voltage is long enough to turn off the eighth NMOS transistor (M25), and its value can be determined by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1) To adjust.

In the standby mode, the source voltages of the driving transistors in all memory cells are set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current; while in the hold mode, the voltages in the memory cells are set to The source voltage of the driving transistor is set to the ground voltage in order to maintain the original holding characteristics. The detailed operating voltage level is shown in Table 1 above.

The inverted write control signal (/ WC) in Table 1 is the inverted signal of the write control signal (WC), and the write control signal (WC) is a write signal (W) and the The result of the AND gate operation of the word line (WL) signal. At this time, only when the write signal (W) signal and the word line (WL) signal are at a logic high level, the write control signal ( WC) The side is a logic high level; the read control signal (RC) is the result of the AND operation of a read enable (RE) signal and a corresponding read word line (RWL) signal. It is worth noting here that, for non-selected word lines and non-selected positioning element lines, the floating state is set, and the read control signal (RC) during the non-read mode is set to the acceleration. The level of the voltage (RGND) is read to prevent the leakage current of the seventh NMOS transistor (M24).

Please refer to Fig. 6. The precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P). The source and gate of the third PMOS transistor (P31) And the drain are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit line (RBL), in order to facilitate the precharge period, The precharge signal (P) is used to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V _DD ).

Please refer to FIG. 6 again, the standby start circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2), and the inverting standby Mode control signal (/ S). The source, gate, and drain of the fourth PMOS transistor (P41) are connected to the power supply voltage (V _DD ), the inverting standby mode control signal (/ S), and the twelfth NMOS transistor. The drain of (M41); the source, gate and drain of the twelfth NMOS transistor (M41) are connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) respectively And the drain of the fourth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/ S), and the output of the second delay circuit (D2) is Connected to the gate of the twelfth NMOS transistor (M41).

Please refer to FIG. 6 again. The high-voltage level control circuit (5) is composed of a fifth PMOS transistor (P51), a sixth PMOS transistor (P52), and a fourth inverter (I53). , Wherein the source, gate and drain of the fifth PMOS transistor (P51) are connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH), respectively, The source, gate and drain of the sixth PMOS transistor (P52) are connected to a first high power supply voltage (V _DDH1 ), the output of the fourth inverter (I63) and the high voltage node, respectively. (VH), and the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the drain of the sixth PMOS transistor (P52). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage Between the node (VH) and the second low voltage node (VL2).

Please refer to FIG. 6 again, the write driving circuit (6) is composed of a seventh PMOS transistor (P61), an eighth PMOS transistor (P62), a ninth PMOS transistor (P63), and a tenth PMOS transistor (P64), a thirteenth NMOS transistor (M61), a fourteenth NMOS transistor (M62), a fifth inverter (I63), an input data (Din), and a second high Power supply voltage (V _DDH2 ), where the source, gate and drain of the seventh PMOS transistor (P61) are connected to the second high power supply voltage (V _DDH2 ), the input data (Din ) And the drain of the thirteenth NMOS transistor (M61), and the source, gate and drain of the eighth PMOS transistor (P62) are connected to the second high power supply voltage (V _DDH2 ), The drain of the fourteenth NMOS transistor (M62) is connected to the drain of the thirteenth NMOS transistor (M61), and the source, gate and drain of the ninth PMOS transistor (P63) are connected respectively. To the second high power supply voltage (V _DDH2 ), the drain of the thirteenth NMOS transistor (M61) and the drain of the fourteenth NMOS transistor (M62), and the tenth PMOS transistor (P64 ) 'S source, gate and drain are connected to The second high power supply voltage (V _DDH2 ), the output of the fifth inverter (I63) and the drain of the fourteenth NMOS transistor (M62), and the source of the thirteenth NMOS transistor (M61) The electrode, gate and drain are connected to the ground voltage, the input data (Din) and the drain of the seventh PMOS transistor (P61), and the source and gate of the fourteenth NMOS transistor (M62). The pole and the drain are respectively connected to the ground voltage, the output of the fifth inverter (I63) and the drain of the tenth PMOS transistor (P64), and the input of the fifth inverter (I63) is For receiving the input data (Din), and the output is connected to the gate of the tenth PMOS transistor (P64) and the gate of the fourteenth NMOS transistor (M62), wherein the ninth PMOS transistor The drain of (P63), the drain of the tenth PMOS transistor (P64) and the drain of the fourteenth NMOS transistor (M62) are all connected to the write bit line (WBL), and the write The input bit line (WBL) is the level of the ground voltage when logic 0 is written, and the level of the second high power supply voltage (V _DDH2 ) when logic 1 is written. It is worth noting here that the voltage level of the second high power supply voltage (V _DDH2 ) is designed to be higher than the voltage level of the power supply voltage (V _DD ) to accelerate the speed of writing to logic one.

The working principle of the preferred embodiment of the present invention shown in FIG. 6 is as follows:

(I) write mode

Before the write operation starts, the standby mode control signal (S) is at a logic low level, so that the eleventh NMOS transistor (M28) is turned on, and the tenth NMOS transistor (M27) is turned off (OFF) ), Because the inverted write control signal (/ WC) is at a logic high level, the drain of the eleventh NMOS transistor (M28) is at a logic high level, and the eleventh NMOS at the logic high level The drain of the transistor (M28) will turn on the ninth NMOS transistor (M26) and make the first low voltage node (VL1) a ground voltage.

During the writing operation, the inverted writing control signal (/ WC) is at a logic low level, so that the drain of the eleventh NMOS transistor (M28) is at a logic low level, and the logic low level is at the logic low level. The drain of the eleven NMOS transistor (M28) will turn off the ninth NMOS transistor (M26), and make the first low voltage node (VL1) equal to the gate-source voltage of the sixth NMOS transistor (M23). V _{GS (M26)} , which can effectively prevent the difficulty of writing logic 1. FIG. 7 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during a writing period.

The following describes how the writing operation of the preferred embodiment of the present invention shown in FIG. 7 is completed according to four writing states.

(1) Node A originally stored logic 0, but now wants to write logic 0:

Before the writing operation occurs (the writing word line WWL is a ground voltage), the first NMOS transistor (M11) is turned on. Since the first NMOS transistor (M11) is ON, when the writing operation is started, the writing word line (WWL) changes from Low (ground voltage) to High (power supply voltage V _DD ). When the voltage of the writing word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13) (that is, the access transistor), the third NMOS transistor (M13) transitions from OFF. In order to be turned on, the write bit line (WBL) is grounded at this time, so the node A will be discharged, and a logic 0 write operation is completed until the write cycle ends.

(2) Node A originally stored logic 0, but now wants to write logic 1:

Before the writing operation occurs (the writing word line WWL is a ground voltage), the first NMOS transistor (M11) is turned on. It is worth noting here that because the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line (WWL) changes from Low (ground voltage) to High (the power supply Voltage V _DD ), the voltage of the node A will follow the writing word line (WWL) voltage slightly due to the parasitic capacitance coupling effect. When the voltage of the word line for writing (WWL) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. Because the write bit line (WBL) is the voltage level of the second high power supply voltage (V _DDH2 ), and because the first NMOS transistor (M11) is still ON and the node B is still at voltage The level is the initial state close to the voltage level of the power supply voltage (V _DD ), so the first PMOS transistor (P11) is still OFF, and the initial instantaneous voltage (V) written by the node A _AWI ) satisfies equation (3): V _AWI = V _DDH2 × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 )> V _TM12 (3) where, V _AWI represents the initial moment of node A writing Voltage, R _M13 represents the on-resistance of the third NMOS transistor (M13), R _M11 represents the on-resistance of the first NMOS transistor (M11), R _M23 represents the on-resistance of the sixth NMOS transistor (M23), V _DDH2 and V _TM12 represent the second high power supply voltage (V _DDH2 ) and the threshold voltage of the second NMOS transistor (M12), respectively. Because the voltage level of the second high power supply voltage (V _DDH2 ) is designed to be higher than the voltage level of the power supply voltage (V _DD ), and a voltage equal to the voltage level at the first low voltage node (VL1) is provided. The voltage level of the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23), so the voltage level of the node A can be easily set to be higher than the conventional 5T static random access memory of FIG. 4 The voltage level of the node A of the bulk cell is much higher. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), so that the node B is discharged to a lower voltage level. The lower voltage level of the node B will make the The on-resistance (R _M11 ) of the first NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A Standard, the higher voltage level of the node A will pass through the second inverter (consisting of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B presents a lower voltage level , The lower voltage level of the node B will pass through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, According to this cycle, the node A can be charged to the power supply voltage (V _DD ), and the writing operation of the logic 1 is completed.

It is worth noting here that the first low-voltage node VL1 originally stores logic 0 at node A, and during the writing of logic 1, it has a gate-source voltage V _GS equal to the sixth NMOS transistor (M23). _(M23) , and after the logic 1 is written, it will have a ground voltage level due to discharge through the ninth NMOS transistor (M26).

(3) Node A originally stored logic 1, but now wants to write logic 1:

Before the writing operation occurs (the writing word line WWL is a ground voltage), the first PMOS transistor (P11) is turned on. When the writing word line (WWL) changes from Low (ground voltage) to High (the power supply voltage V _DD ), since the node A is the voltage level of the power supply voltage (V _DD ), and the write The bit line (WBL) is used as the voltage level of the second high power supply voltage (V _DDH2 ), so the third NMOS transistor (M13) will remain in the OFF state. The PMOS transistor (P11) is still ON, so the voltage of the node A will be maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stored logic 1, but now wants to write logic 0:

Before the writing operation occurs (the writing word line WWL is a ground voltage), the first PMOS transistor (P11) is turned on. When the writing word line (WWL) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the writing word line (WWL) is greater than the third NMOS transistor (M13) ), The third NMOS transistor (M13) changes from OFF to ON. At this time, because the write bit line (WBL) is Low (ground voltage), The node A and the first low voltage node (VL1) are discharged to complete a logic 0 writing operation until the writing cycle ends.

The HSPICE transient analysis simulation result during the write operation of the preferred embodiment of the invention shown in FIG. 7 is shown in FIG. 8, which is simulated using TSMC 90 nm CMOS process parameters. It can be confirmed that the dual-port static random access memory proposed by the present invention can increase the voltage level of the first low voltage node (VL1) during the writing period, and cooperate with the writing bit line (WBL ) The write driving circuit (6) whose voltage level is higher than the power supply voltage (V _DD ) can effectively prevent writing logic 1 from being difficult, and can also effectively improve the writing speed.

(II) read mode

Before the read operation starts, the standby mode control signal (S) is at a logic low level, and the inverted write control signal (/ WC) and the inverted standby mode control signal (/ S) are at a logic high level. The eleventh NMOS transistor (M28) is turned on, and the tenth NMOS transistor (M27) is turned off, so the drain of the eleventh NMOS transistor (M28) is at a logic high level, and the logic high level should be The drain of the eleventh NMOS transistor (M28) will turn on the ninth NMOS transistor (M26) and make the first low voltage node (VL1) a ground voltage. On the other hand, due to the read control The signal (RC) is a logic low level, so that the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned on (ON).

It is worth noting here that during the pre-charging period before the read operation starts, the pre-charging signal (P) is at a logic low level, thereby pre-charging the corresponding read bit line (RBL) to The level of the power supply voltage (V _DD ), but because the operating voltage of the process technology below 20 nanometers will fall below 1 volt, the reading speed will be reduced and the specification cannot be met. Therefore, the present invention proposes two Phased read control is used to increase read speed and meet specifications while avoiding unnecessary power loss.

The preferred embodiment of the present invention shown in FIG. 6 uses a two-stage read control to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the read operation, the read control The signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the second low voltage node (VL2) is approximately grounded. The accelerated read voltage (RGND) whose voltage is low, and the accelerated read voltage (RGND) which is lower than the ground voltage can effectively improve the reading speed.

In the second phase of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still on, but at this time the eighth NMOS transistor ( M25) is turned off, so the second low voltage node (VL2) will be grounded via the fourth NMOS transistor (M21) that is turned on (because the inverting standby mode control signal (/ S) is logic during read operation) High level), which can effectively reduce unnecessary power consumption. It is worth noting here that the time interval between the second stage and the first stage of the read operation is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level. The gate voltage of the eight NMOS transistor (M25) is sufficient to shut down the eight NMOS transistor (M25). The time can be adjusted by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1). Furthermore, the fourth NMOS transistor (M21) is in a conducting state regardless of whether it is the first stage or the second stage of the read operation (because the inverted standby mode control signal (/ S) is logic during the read operation High level). FIG. 9 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during reading.

The following describes how the preferred embodiment of the present invention shown in FIG. 9 uses the control circuit (2) and the high-voltage level control circuit (5) to improve the reading speed while avoiding uselessness according to two read states. Power consumption.

(1) Read logic 1 (node A stores logic 1):

Before the read operation occurs, the first NMOS transistor (M11) is OFF and the second NMOS transistor (M12) is ON. The node A and the node B are the power supply voltages, respectively. (V _DD ) and ground voltage, and the read bit line (RBL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading period, since the node B is at the ground voltage, the second reading transistor (M15) is turned off, thereby effectively maintaining the reading bit line (RBL) as the power supply voltage ( V _DD ) until the end of the read cycle, the read logic 1 operation is successfully completed. It is worth noting here that in the first stage of the read operation, the initial instantaneous voltage (V _RVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy equation (4): V _RVL2I = RGND × R _M21 / (R _M21 + R _M24 + R _M25 )>-V _TM12 (4) to effectively prevent half-selected cell interference during reading, where V _RVL2I represents the second low voltage node ( VL2) read the initial instantaneous voltage when reading logic 1, RGND represents the accelerated read voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), and R _M24 represents the seventh NMOS transistor (M24) ), R _M25 represents the on resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12); and in the second stage of the read operation, The voltage (V _RVL2 ) of the second low-voltage node (VL2) can be represented by equation (5). V _RVL2 = ground voltage (5). This can effectively reduce unnecessary power consumption. Furthermore, in order to effectively reduce the half-selected cell interference and effectively reduce the leakage current during reading, the accelerated reading voltage (RGND), which is lower than the ground voltage, must be set to the value of the second low voltage node (VL2). The voltage level is lower than the threshold voltage (V _TM12 ) of the second NMOS transistor (M12), and the accelerated read voltage (RGND), which is lower than the ground voltage, can be set more strictly than the second NMOS transistor. The threshold voltage (V _TN12 ) of the crystal (M12), that is, | RGND | <V _TM12 (6), where | RGND | and V _TM12 respectively represent the absolute value of the accelerated read voltage and the second NMOS transistor (M12 ).

Furthermore, the first high power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the threshold voltage of the second PMOS transistor (P12). The sum of the absolute values | V _TP12 |, that is, V _DD <V _DDH1 <V _DD + | V _TP12 | (7) where | V _TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12).

(2) Read logic 0 (node A stores logic 0):

Before the read operation occurs, the first NMOS transistor (M11) is ON and the second NMOS transistor (M12) is OFF. The node A and the node B are ground voltage and the The power supply voltage (V _DD ), and the read bit line (RBL) is equal to the first high power supply voltage (V _DDH1 ) due to the precharge circuit (3). During the reading period, since the node B is the first high power supply voltage (V _DDH1 ), and the second low voltage node (VL2) is a voltage lower than the ground voltage, because the first high power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ). Therefore, the reading speed can be increased by increasing the conduction degree of the second reading transistor (M15). This second low voltage node (VL2) further improves the read speed.

(III) Standby mode

First, explain how the standby startup circuit (4) in Figure 6 promotes the dual-port SRAM to enter the standby mode quickly, so as to effectively improve the standby performance of the SRAM: first, before entering the standby mode, the inverted standby mode control signal (/ S) It is logic High. The inverted standby mode control signal (/ S) of the logic High turns off the fourth PMOS transistor (P41) and turns on the twelfth NMOS transistor (M41). After entering the standby mode, the inverting standby mode control signal (/ S) is logic Low, and the inverting standby mode control signal (/ S) of logic low causes the fourth PMOS transistor (P41) to be turned on (ON) , But in the initial period of the standby mode (the initial period is equal to the inversion of the standby mode control signal (/ S) from logic High to logic Low counting from the gate voltage to the twelfth NMOS transistor (M41) The time until the twelfth NMOS transistor (M41) is turned off, which can be adjusted by a delay time provided by the second delay circuit (D2)), the twelfth NMOS transistor (M41) is still on (ON), so that the first low-voltage node (VL1) can be quickly charged to the sixth NMOS transistor The voltage level of the threshold voltage (V _TM23 ) of the body (M23), that is, the dual-port SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (M41) is turned off and stops supplying current.

Please refer to FIG. 6. In the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/ S) is a logic low level. The logic low level is the inverted standby The mode control signal (/ S) can turn off the fourth NMOS transistor (M21) in the control circuit (2), and the standby mode control signal (S) at the logic high level makes the fifth The NMOS transistor (M22) is turned on. At this time, the fifth NMOS transistor (M22) is used as an equalizer. Therefore, the fifth NMOS transistor (M22) can be turned on. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are all equal to the voltage levels of the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V _TM23 ). FIG. 10 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during the standby period.

Next, how to reduce the leakage current in the standby mode of the present invention will be described. Please refer to FIG. 10, which describes the respective leakage currents (I ₁ ) generated when the embodiment of the present invention is in the standby mode. , I ₂ , I ₃ , I ₄ , where it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is logic Low (It is worth noting here that due to the first low voltage in the standby mode The voltage levels of the node (VL1) and the second low voltage node (VL2) are maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so node A is a logic low voltage The level is also maintained at the voltage level of the V _TM23 ), and the output of the second inverter (ie, node B) is logic High (power supply voltage V _DD ). Please refer to the conventional 8T dual-port SRAM in FIG. 5 and the embodiment of the present invention in FIG. 10 to explain the leakage current of the dual-port static random access memory proposed in the present invention and the conventional 8T dual-port SRAM in FIG. 5. For comparison, first, regarding the leakage current I ₁ flowing through the third NMOS transistor (M13), since the voltage level of the node A is maintained at the voltage level of the V _TM23 in the standby mode of the present invention, and it is assumed that the write The input word line (WWL) is set to the ground voltage in the standby mode, and the write bit line (WBL) is set to the power supply voltage (V _DD ) in the standby mode. The gate-source voltage (V _GS ) of the three NMOS transistor (M13) is negative. In contrast, in the standby mode, the gate-source voltage (V _GS ) of the NMOS transistor (M3) of the traditional 8T dual-port SRAM shown in Figure 5 It is equal to 0. According to the Gate Induced Drain Leakage (GIDL) effect or the results of Figure 3 (A) and 3 (B) of US6865119 patent case on March 8, 2005, it can be known that for NMOS power For the crystal, the sub-critical current when the gate-source voltage is -0.1 volts is about 1% of the sub-critical current when the gate-source voltage is 0 volts Thus due to conduction caused by the effects of GIDL flow through the third NMOS transistor (M13) of the present invention is much smaller than the drain current I ₁ of the FIG. 5 8T conventional dual-port SRAM of the NMOS transistor (M3) are; Furthermore, According to the present invention, the drain-source voltage (V _DS ) of the third NMOS transistor (M13) is the power supply voltage (V _DD ) _minus the voltage level of the V _TM23 , in contrast to the traditional 8T dual-port SRAM in FIG. 5. The drain-source voltage (V _DS ) of the NMOS transistor (M3) is equal to the power supply voltage (V _DD ). According to the Drain-Induced Barrier Lowering (DIBL) effect caused by the drain, due to the DIBL effect, The induced leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention is also smaller than that of the conventional 8T dual-port SRAM NMOS transistor (M3) of FIG. 5; as a result, the third NMOS transistor of the present invention flows The leakage current I _{1 of the} transistor (M13) is much smaller than the NMOS transistor (M3) of the conventional 8T dual-port SRAM in FIG. 5.

Then regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), since the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) in the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V _TM23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V _DD ) The voltage level of the V _TM23 is deducted. In contrast, the source-drain voltage (V _SD ) of the PMOS transistor (P1) of the traditional 8T dual-port SRAM in Figure 5 is equal to the power supply voltage (V _DD ). DIBL effect, so the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the PMOS transistor (P1) of the prior art in FIG. 1b.

Then, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V _TM23 in the standby mode, the node A The voltage level of V _TM23 is also maintained, and the voltage level of node B is equal to the power supply voltage (V _DD ) and the substrate of the second NMOS transistor (M12) is ground voltage. The base-source voltage (V _BS ) of the second NMOS transistor (M12) is negative, and the drain-source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V _DD ) The V _TM23 voltage level is deducted. In contrast, the base-source voltage (V _BS ) of the NMOS transistor (M2) of the traditional 8T dual-port SRAM in FIG. 5 is equal to 0, and the NMOS transistor (M2) The drain-source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and DIBL effect, it can be known that the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than Figure 5 shows the NMOS transistor (M2) of a conventional 8T dual-port SRAM.

Finally, regarding the leakage current I ₄ flowing through the first reading transistor (M14), the present invention is different from the conventional 8T dual-port SRAM in FIG. 5 in the reading method, and the reading in the standby mode of the present invention The bit line (RBL) can be set to ground voltage. In order to prevent the voltage level of node B from dropping, the conventional 8T dual-port SRAM in Figure 5 uses read bit line pairs (RBL, RBLB) in standby mode. Since the power supply voltage is set, the leakage current I ₄ flowing through the first reading transistor (M14) cannot be compared. Based on the above analysis, it can be seen that the dual-port static random access memory proposed by the present invention has a lower leakage current than the conventional 8T dual-port SRAM of FIG. 5.

(IV) Retension mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to the ground voltage, the working principle is the same as that of a conventional dual-port SRAM cell with a single bit line. No more repetition.

[Effect of Invention]

The 7T dual-port static random access memory proposed by the present invention has the following effects:

(1) High read speed and avoid unnecessary power consumption: The 7T dual-port static random access memory system proposed by the present invention uses a two-stage read operation. The low voltage node (VL2) is set to a voltage lower than the ground voltage, and the node B is set to the first high power supply voltage (V _DDH1 ) which is higher than the power supply voltage (V _DD ). Double mechanism to effectively improve the reading speed, and in the second stage of reading logic 0, the second low voltage node (VL2) is set back to the ground voltage in order to reduce unnecessary power consumption;

(2) Quickly enter standby mode: As the 7T dual-port static random access memory proposed by the present invention is provided with a standby startup circuit (4) to prompt the SRAM to enter the standby mode quickly, and thereby seek to improve the Standby efficiency

(3) Improve the speed of writing logic 1 and avoid the problem of writing logic 1. The present invention can use the plurality of control circuits (2) and the plurality of write driving circuits (6) during the writing operation. ) In order to effectively prevent the difficulty of writing logic 1, it also increases the speed of writing logic 1;

(4) Low standby current: Due to the 7T dual-port static random access memory proposed in the present invention in the standby mode In the formula, the fifth NMOS transistor (M22) can be turned on to make the voltage level of the first low voltage node (VL1) equal to the voltage level of the second low voltage node (VL2). And make these voltage levels equal to the threshold voltage level of the sixth NMOS transistor (M23), so the 7T dual-port static random access memory proposed by the present invention also has the effect of low standby current;

(5) Effectively reduce semi-selected cell interference: The 7T dual-port static random access memory proposed by the present invention uses a separate read / write path, and the read path is designed to make the first and second read An access transistor (M14 and M15) is connected in series between the read bit line (RBL) and the second low voltage node (VL2), and the inverting storage node (B) is connected to the second The gate of the reading transistor (M15) can effectively reduce half-selected cell disturbance, where the half-selected cell is selected by the read word line (RWL) but A memory cell not selected by the read bit line (RBL).

(6) Low transistor count: For a SRAM array with 1024 columns and 1024 rows, the traditional 8T dual-port SRAM array shown in Figure 5 requires a total of 1024 × 1024 × 8 = 8,388,608 transistors, and the 7T proposed by the present invention The dual-port static random access memory only needs at least 1024 × 1024 × 7 + 1024 × 20 + 6 = 7,360,518 transistors, which reduces the number of transistors by 12.3%.

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or detail may be changed without departing from the spirit and scope of the present invention. Therefore, all changes in the related technical scope are included in the scope of patent application of the present invention.

Claims (10)

A 7T dual-port static random access memory includes: a memory array, the memory array is composed of a plurality of rows of memory cells and a plurality of rows of memory cells, each row of memory cells and each row of memories The unit cell contains a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory The unit cell is provided with a pre-charging circuit (3); a standby start-up circuit (4), the standby start-up circuit (4) prompts the 7T dual-port static random access memory to quickly enter the standby mode to effectively improve the 7T dual The standby performance of the port's static random access memory; a plurality of high voltage level control circuits (5), and a high voltage level control circuit (5) is provided for each column of memory cells to improve the read when logic 0 is read Taking speed; and a plurality of write drive circuits (6), each row of memory cell is provided with a write drive circuit (6) to increase the write speed when logic 1 is written; wherein each memory cell (1) It further includes: a first inverter, which is composed of a first PM An OS transistor (P11) and a first NMOS transistor (M11), the first inverter is connected between a power supply voltage (V _DD ) and a first low voltage node (VL1); The second inverter is composed of a second PMOS transistor (P12) and a second NMOS transistor (M12). The second inverter is connected between a high voltage node (VH) and a second Between a low voltage node (VL2); a storage node (A) formed by the output terminal of the first inverter; an inverting storage node (B) formed by the output terminal of the second inverter Formed; a third NMOS transistor (M13) is connected between the storage node (A) and a corresponding writing bit line (WBL), and the gate is connected to a corresponding writing word Element line (WWL); a first reading transistor (M14), the source, gate and drain of the first reading transistor (M14) are respectively connected to a second reading transistor The drain of (M15), a word line for reading (RWL) and a bit line for reading (RBL); and the second reading transistor (M15), the second reading transistor (M15) The source, gate and drain are connected to the second low voltage The voltage node (VL2), the inverting storage node (B) and the source of the first reading transistor (M14); wherein the first inverter and the second inverter are connected in an interactive coupling That is, the output terminal of the first inverter (that is, the storage node A) is connected to the input terminal of the second inverter, and the output terminal of the second inverter (that is, the inverting storage node B) ) Is connected to the input terminal of the first inverter; and each control circuit (2) further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor Crystal (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS Transistor (M28), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC ), An inverted write control signal (/ WC), a standby mode control signal (S), and an inverted standby mode control signal (/ S); wherein the source of the fourth NMOS transistor (M21), The gate and drain are connected to a ground voltage, The inverting standby mode control signal (/ S) and the second low voltage node (VL2); the source, gate and drain of the fifth NMOS transistor (M22) are connected to the first low voltage node ( VL1), the standby mode control signal (S) and the second low voltage node (VL2); the source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate and the drain are connected together And connected to the first low voltage node (VL1); the source, gate and drain of the seventh NMOS transistor (M24) are respectively connected to the drain of the eighth NMOS transistor (M25), the read The control signal (RC) and the second low voltage node (VL2); the source, gate and drain of the eighth NMOS transistor (M25) are connected to the accelerated read voltage (RGND), the first The output of a delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to the output of the third inverter (INV) and the eighth NMOS circuit The gate of the crystal (M25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); The ninth NMOS power The source, gate, and drain of the body (M26) are respectively connected to the ground voltage, the drain of the tenth NMOS transistor (M27), and the first low-voltage node (VL1); the tenth NMOS transistor The source, gate and drain of (M27) are respectively connected to the gate of the write control signal (WC), the standby mode control signal (S) and the ninth NMOS transistor (M26); the tenth The source, gate and drain of an NMOS transistor (M28) are connected to the inverted write control signal (/ WC), the inverted standby mode control signal (/ S), and the ninth NMOS transistor, respectively. The gate of (M26); among them, the drain of the eleventh NMOS transistor (M28), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected A node (C) is formed together. When the standby mode control signal (S) is at a logic low level, the voltage level of the node (C) is the logic level of the inverted write control signal (/ WC). , And when the standby mode control signal (S) is a logic high level, the voltage level of the node (C) is the logic level of the write control signal (WC), thereby effectively preventing the cause in the standby mode. Unexpected Su erroneous writing occurs; Furthermore, the power supply voltage (V _DD) deduct the eleventh NMOS transistor (M28) the threshold voltage (V _TM28) one of the logical high level of the node line (C) for the Voltage level of the node, so when the 7T dual-port static random access memory is in a non-write mode (the corresponding write control signal (/ WC) is logic high), the node (C) Is the voltage level of the power supply voltage (V _DD ) _minus the threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28), not the voltage level of the power supply voltage (V _DD ), Therefore, it can have a lower power consumption; and when it subsequently enters the write mode (at this time, the corresponding inverted write control signal (/ WC) is a logic low level), it can be quickly stored in the node (C The charge of) is discharged through the eleventh NMOS transistor (M28) enough to turn off the ninth NMOS transistor (M26) with the node (C) as the gate, so it can enter the write mode more quickly; where For the non-read mode, the read control signal (RC) is set to the level of the accelerated read voltage (RGND) to prevent the seventh NMOS transistor (M24) Leakage current during non-read mode; further, the standby start circuit (4) is designed to quickly charge the parasitic capacitance at the first low voltage node (VL1) to The voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23); finally, each high voltage level control circuit (5) further includes: a fifth PMOS transistor (P51), a sixth The PMOS transistor (P52) and a fourth inverter (I53). The source, gate, and drain of the fifth PMOS transistor (P51) are connected to the power supply voltage (V _DD ), the The read control signal (RC) and the high voltage node (VH), the source, gate and drain of the sixth PMOS transistor (P52) are respectively connected to a first high power supply voltage (V _DDH1 ), The output of the fourth inverter (I53) and the high voltage node (VH), and the input of the fourth inverter (I53) is for receiving the read control signal (RC), and the output is connected to The gate of the sixth PMOS transistor (P52). The 7T dual-port static random access memory according to item 1 of the scope of patent application, wherein the first NMOS transistor (M11) and the second NMOS transistor in each memory cell (1) (M12) has the same channel width-to-length ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also have the same channel width-to-length ratio. The 7T dual-port static random access memory described in item 2 of the patent application scope, wherein each precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P). The source, gate, and drain of the third PMOS transistor (P31) are connected to the power supply voltage (V _DD ), the precharge signal (P), and the corresponding read bit, respectively. Element line (RBL), so that during a precharge period, the corresponding precharge signal (P) at a logic low level is used to precharge the corresponding read bit line (RBL) to the power supply voltage (V _DD ). The 7T dual-port static random access memory described in item 3 of the scope of patent application, wherein the standby startup circuit (4) is composed of a fourth PMOS transistor (P41) and a twelfth NMOS transistor (M41). ), A second delay circuit (D2) and the inverting standby mode control signal (/ S); wherein the source, gate and drain of the fourth PMOS transistor (P41) are connected to the Power supply voltage (V _DD ), the inverted standby mode control signal (/ S) and the drain of the eleventh NMOS transistor (M41); the source and gate of the twelfth NMOS transistor (M41) And the drain are respectively connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fourth PMOS transistor (P41); the second delay circuit (D2) An input is connected to the inverted standby mode control signal (/ S), and an output of the second delay circuit (D2) is connected to the gate of the twelfth NMOS transistor (M41). The 7T dual-port static random access memory described in item 4 of the scope of patent application, wherein each write driving circuit (6) is composed of a seventh PMOS transistor (P61) and an eighth PMOS transistor ( P62), a ninth PMOS transistor (P63), a tenth PMOS transistor (P64), a thirteenth NMOS transistor (M61), a fourteenth NMOS transistor (M62), a fifth inversion Device (I63), an input data (Din), and a second high power supply voltage (V _DDH2 ), wherein the source, gate and drain of the seventh PMOS transistor (P61) are connected to the The second highest power supply voltage (V _DDH2 ), the input data (Din) and the drain of the thirteenth NMOS transistor (M61), and the source, gate and drain of the eighth PMOS transistor (P62) Connected to the second high power supply voltage (V _DDH2 ), the drain of the fourteenth NMOS transistor (M62) and the drain of the thirteenth NMOS transistor (M61), and the ninth PMOS transistor The source, gate and drain of (P63) are connected to the second high power supply voltage (V _DDH2 ), the drain of the thirteenth NMOS transistor (M61) and the fourteenth NMOS transistor ( M62), the tenth PMOS The source, gate and drain of the transistor (P64) are connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (I63) and the fourteenth NMOS transistor ( M62), the source, gate, and drain of the thirteenth NMOS transistor (M61) are connected to the ground voltage, the input data (Din), and the seventh PMOS transistor (P61) respectively. Drain, the source, gate, and drain of the fourteenth NMOS transistor (M62) are connected to the ground voltage, the output of the fifth inverter (I63), and the tenth PMOS transistor (P64) ), And the input of the fifth inverter (I63) is for receiving the input data (Din), and the output is connected to the gate of the tenth PMOS transistor (P64) and the fourteenth The gate of the NMOS transistor (M62), wherein the drain of the ninth PMOS transistor (P63), the drain of the tenth PMOS transistor (P64), and the drain of the fourteenth NMOS transistor (M62) The poles are commonly connected to the corresponding writing bit line (WBL). The corresponding writing bit line (WBL) is at the level of the ground voltage when writing logic 0, and the writing logic 1 o'clock is the second highest power supply Voltage _(V DDH2) of the level, the second high power supply voltage _(V DDH2) the voltage level of the system designed to be higher than the power supply voltage (V _DD) of the voltage level, in order to accelerate the write speed of the logic 1 . The 7T dual-port static random access memory described in item 5 of the scope of patent application, wherein the storage node (A) originally stores logic 0, and the initial instantaneous voltage (V _AWI ) satisfies the following equation: V _AWI = V _DDH2 × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 )> V _TM12 where V _AWI indicates that the storage node (A) is written by storage logic 0 The initial instantaneous voltage written into logic 1, R _M11 , R _M13 and R _M23 represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor (M23) respectively. On-resistance, and V _DDH2 and V _TM12 represent the second high power supply voltage (V _DDH2 ) and the threshold voltage of the second NMOS transistor (M12), respectively. The 7T dual-port static random access memory described in item 6 of the scope of the patent application, wherein the read operation can be further subdivided into two phases. In the first phase of one of the read operations, the first The second low voltage node (VL2) is set to a voltage lower than the ground voltage to effectively improve the reading speed, and in the second stage of the read operation, the second low voltage node (VL2) is set back to The ground voltage in order to reduce unnecessary power consumption, wherein the time interval between the second phase and the first phase of the read operation is equal to the transition of the read control signal (RC) from a logic low level to a logic high level From the time until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), it can be reduced by a delay time of one of the third inverters (INV) and A delay time provided by the first delay circuit (D1) is dynamically adjusted. The 7T dual-port static random access memory according to item 7 of the scope of patent application, wherein, in the first stage of the read operation, the second low-voltage node (VL2) is read when the logic 1 is read The initial instantaneous voltage (V _RVL2I ) must satisfy the following equation: V _RVL2I = RGND × R _M21 / (R _M21 + R _M24 + R _M25 )>-V _TM12 to effectively prevent half-selected cell interference during reading, where , V _RVL2I represents the initial instantaneous voltage of the second low voltage node (VL2) when reading logic 1, RGND represents the accelerated read voltage, and R _M21 represents the on-resistance of the fourth NMOS transistor (M21) R _M24 represents the on-resistance of the seventh NMOS transistor (M24), R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12) . The 7T dual-port static random access memory according to item 1 of the scope of patent application, wherein the accelerated read voltage (RGND) in each control circuit (2) is set to be lower than each memory The threshold voltage (V _TM12 ) of the second NMOS transistor (M12) in the unit cell (1), and the first high power supply voltage (V _DDH1 ) is set higher than the power supply voltage (V _DD ) but Below the sum of the absolute value of the power supply voltage (V _DD ) and the threshold voltage of the second PMOS transistor (P12) | V _TP12 |, that is, V _DD <V _DDH1 <V _DD + | V _TP12 |. According to the 7T dual-port static random access memory described in item 1 of the scope of the patent application, the initial low-voltage read (V _RVL2I ) of the second low-voltage node (VL2) when reading logic 1 must satisfy the following Equation: V _RVL2I = RGND × R _M21 / (R _M21 + R _M24 + R _M25 )>-V _TM12 to effectively prevent half-selected cell interference when reading logic 1, where V _RVL2I represents the second lowest The initial instantaneous voltage of the voltage node (VL2) when reading logic 1, RGND represents the accelerated reading voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), and R _M24 represents the seventh NMOS The on-resistance of the transistor (M24), R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12).