TW201614652A - 7T dual port static random access memory - Google Patents

Abstract

This invention provides a 7T dual port static random access memory, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of pre-charging circuits (3), and a standby startup circuit (4). The memory array consists of a plurality of rows of memory cells and a plurality of columns of memory cells. Each row of memory cells is provided with one control circuit. Each memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor P12 and a second NMOS transistor M12), an access transistor (composed of a third NMOS transistor M13), a first read access transistor (M14), and a second read access transistor (M15). Each control unit (2) is connected to the source of the first NMOS transistor (M11) and the source of the second NMOS transistor (M12) of each memory cell of the corresponding row of memory cells for controlling a source voltage of the first NMOS transistor (M11) and a source voltage of the second NMOS transistor (M12) in response to different operating modes. In a writing mode, problem of difficult to write into logic 1 can be prevented effectively; in a reading mode, the reading speed can be increased while unnecessary power consumption is avoided; in a standby mode, a leakage current can be reduced effectively; and in a holding mode, the original electrical characteristics can be maintained. Moreover, the design of the standby startup circuit (4) can promote the 7T dual port static random access memory to enter standby mode efficiently and thus, enhances standby performance of the 7T dual port static random access memory.