IN2014CN04993A - - Google Patents

Info

Publication number
IN2014CN04993A
IN2014CN04993A IN4993CHN2014A IN2014CN04993A IN 2014CN04993 A IN2014CN04993 A IN 2014CN04993A IN 4993CHN2014 A IN4993CHN2014 A IN 4993CHN2014A IN 2014CN04993 A IN2014CN04993 A IN 2014CN04993A
Authority
IN
India
Prior art keywords
wwl
field effect
low
channel field
effect transistors
Prior art date
Application number
Inventor
Joshua L Puckett
Manish Garg
Harish Shankar
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014CN04993A publication Critical patent/IN2014CN04993A/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

In low power CPUs the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an 8T cell (450) which has read stability immunity in order to operate at low voltages. An embodiment of the disclosure determines when a write wordline (WWL 410) rises. If the determination (header pFET 430) shows that the WWL has risen at least one of the plurality of p channel field effect transistors (pFETS 432 434) is disconnected from a voltage supply and the at least one plurality of n channel field effect transistors (nFET) pass gate transistors (440 442) are opened.
IN4993CHN2014 2012-01-23 2013-01-23 IN2014CN04993A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261589570P 2012-01-23 2012-01-23
US13/746,528 US9093125B2 (en) 2012-01-23 2013-01-22 Low voltage write speed bitcell
PCT/US2013/022777 WO2013126172A1 (en) 2012-01-23 2013-01-23 Improved low voltage write speed bitcell

Publications (1)

Publication Number Publication Date
IN2014CN04993A true IN2014CN04993A (en) 2015-09-18

Family

ID=48797076

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4993CHN2014 IN2014CN04993A (en) 2012-01-23 2013-01-23

Country Status (8)

Country Link
US (1) US9093125B2 (en)
EP (1) EP2807649B1 (en)
JP (1) JP6038956B2 (en)
KR (1) KR101601827B1 (en)
CN (1) CN104067345B (en)
IN (1) IN2014CN04993A (en)
TW (1) TWI537945B (en)
WO (1) WO2013126172A1 (en)

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US9335775B2 (en) * 2014-06-23 2016-05-10 International Business Machines Corporation Integrated circuit having regulated voltage island power system
US9251875B1 (en) * 2014-09-26 2016-02-02 Qualcomm Incorporated Register file circuit and method for improving the minimum operating supply voltage
US9384825B2 (en) * 2014-09-26 2016-07-05 Qualcomm Incorporated Multi-port memory circuits
US9583180B2 (en) * 2015-06-05 2017-02-28 Cisco Technology, Inc. Low-power row-oriented memory write assist circuit
US9646681B1 (en) 2016-04-25 2017-05-09 Qualcomm Incorporated Memory cell with improved write margin
US10163524B2 (en) 2016-06-22 2018-12-25 Darryl G. Walker Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor
US10049727B2 (en) 2016-06-22 2018-08-14 Darryl G. Walker Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits
US9786364B1 (en) * 2016-12-16 2017-10-10 Stmicroelectronics International N.V. Low voltage selftime tracking circuitry for write assist based memory operation
KR102021601B1 (en) * 2017-09-22 2019-09-16 경북대학교 산학협력단 Ultra-low voltage memory device and operating method thereof
US10446223B1 (en) * 2018-08-29 2019-10-15 Bitfury Group Limited Data storage apparatus, and related systems and methods
US11074966B2 (en) 2018-10-31 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd Method and system to balance ground bounce
US11183234B2 (en) * 2019-11-25 2021-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Bitcell supporting bit-write-mask function
CN111951849A (en) * 2020-08-20 2020-11-17 海光信息技术有限公司 Memory cell, random static memory and register file
US11955171B2 (en) 2021-09-15 2024-04-09 Mavagail Technology, LLC Integrated circuit device including an SRAM portion having end power select circuits

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Also Published As

Publication number Publication date
JP2015504228A (en) 2015-02-05
KR101601827B1 (en) 2016-03-09
TWI537945B (en) 2016-06-11
KR20140120919A (en) 2014-10-14
TW201346907A (en) 2013-11-16
CN104067345B (en) 2017-05-03
EP2807649B1 (en) 2020-02-19
JP6038956B2 (en) 2016-12-07
WO2013126172A1 (en) 2013-08-29
US9093125B2 (en) 2015-07-28
CN104067345A (en) 2014-09-24
US20130188434A1 (en) 2013-07-25
EP2807649A1 (en) 2014-12-03

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