TWI582580B - Memory storage apparatus and operating method thereof - Google Patents

Description

Memory storage device and method of operating same

The present invention relates to a storage device and method of operating the same, and more particularly to a memory storage device and method of operation thereof.

Dynamic random access memory (DRAM) is a "1" or "0" that uses a charge stored in a capacitor to represent a binary bit, so each memory cell of the DRAM uses at least one capacitor and one switch ( Or a transistor) to store data. In actual operation, the capacitance in the DRAM may leak, and the potential difference of the capacitor is insufficient, so that the data stored in the DRAM disappears. Therefore, the DRAM must enter a refresh mode to periodically refresh all the memory cells. (Also known as data charging / data refresh) operation to ensure the correctness of information stored in DRAM. However, the use of portable devices is becoming more and more popular, and low-power devices have been highly valued. Therefore, how to provide a memory storage device and an operation method that can save power and maintain data is one of the important issues for those skilled in the art.

The invention provides a memory storage device and a method of operating the same, which save power and maintain data.

The memory storage device of the present invention has a variety of modes of operation. The memory storage device includes a memory control circuit and a memory cell array circuit. The memory control circuit is used to control the operation of the memory storage device in one of a plurality of operating modes. The memory cell array circuit is electrically connected to the memory control circuit. The memory cell array circuit is used to store data. The memory storage device receives power to operate in one of the operational modes. The memory control circuit controls the memory storage device to operate in the first mode of operation and to control the memory storage device to switch from the first mode of operation to the second mode of operation to refresh the stored data in the memory cell array circuit. The memory storage device operates in a third mode of operation to refresh stored data in the memory storage device. The operating voltage of the memory storage device operating in the second mode of operation is less than the operating voltage of the memory storage device operating in the third mode of operation.

In an embodiment of the invention, the memory control circuit controls the memory storage device to switch from the first operating mode to the third operating mode to refresh the stored data in the memory storage device.

In an embodiment of the invention, the switching time of the memory storage device switching from the second operation mode back to the first operation mode is greater than the switching time of the memory storage device switching from the third operation mode to the first operation mode.

In an embodiment of the invention, the memory control circuit controls the memory storage device to switch from the first mode of operation to the fourth mode of operation. In the fourth mode of operation, the stored data in the memory storage device is not refreshed.

In an embodiment of the invention, the switching time of the memory storage device switching from the second operating mode back to the first operating mode is less than the switching time of the memory storage device switching from the fourth operating mode to the first operating mode.

In an embodiment of the invention, when the memory storage device operates in the first mode of operation, a plurality of memory banks in the memory cell array circuit have been precharged.

In an embodiment of the invention, the operating voltage is selected from the group consisting of a main voltage, a bit line equalization control voltage, a word line enable high voltage, and an absolute P-type well voltage. At least one of the values.

In an embodiment of the invention, when the memory storage device is operated in the second operation mode, the reference voltage of the input/output circuit in the memory storage device is disabled and the bit line equalization control voltage is generated. The reference voltage is disabled.

The operating method of the memory storage device of the present invention includes: turning on a power of the memory storage device to operate the memory storage device in the first operation mode; and switching the memory storage device from the first operation mode to the second operation mode To refresh the stored data in the memory storage device. The memory storage device operates in a third mode of operation to refresh stored data in the memory storage device. The operating voltage of the memory storage device operating in the second mode of operation is less than the operating voltage of the memory storage device operating in the third mode of operation.

In an embodiment of the invention, the operating voltage is selected from at least one of a core voltage, a bit line equalization control voltage, a word line enable high voltage, and an absolute value of the P-type well voltage. When the memory storage device is operated in the second mode of operation, the reference voltage of the input and output circuits in the memory storage device is disabled and the reference voltage for generating the bit line equalization control voltage is disabled.

Based on the above, in an exemplary embodiment of the present invention, the operating voltage of the memory storage device operating in the second operating mode is less than the operating voltage of the memory storage device operating in the third operating mode. Therefore, the memory storage device and its operating method save power and maintain data.

The above described features and advantages of the invention will be apparent from the following description.

The invention is illustrated by the following examples, but the invention is not limited to the illustrated embodiments. Further combinations are also allowed between the embodiments. The term "coupled" as used throughout the specification (including the scope of the patent application) may be used in any direct or indirect connection. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. In addition, the term "signal" may refer to at least one current, voltage, charge, temperature, data, electromagnetic wave or any other one or more signals.

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. 2 is a schematic diagram showing the memory cell array circuit of the embodiment of FIG. 1. Referring to FIG. 1 to FIG. 2 , the memory storage device 100 of the embodiment includes a memory control circuit 110 , a memory cell array circuit 120 , and an input and output circuit 140 . In this embodiment, the memory control circuit 110 is configured to control the memory storage device 100 to operate in one of a plurality of operating modes. The memory cell array circuit 120 is electrically connected to the memory control circuit 110. The memory cell array circuit 120 is used to store data. The input and output circuit 140 is electrically connected to the memory control circuit 110 and the memory cell array circuit 120. The input/output circuit 140 is configured to receive data to be written or output data to be read.

In the present embodiment, the memory control circuit 110 includes a plurality of different circuit functional blocks. For example, the memory control circuit 110 includes, for example, a clock buffer circuit, a command decoder circuit, a control signal oscillator circuit, and an access buffer circuit. , a mode register circuit, a refresh counter circuit, a column counter circuit, a data buffer circuit, and a data control circuit to control the memory The circuit function block of the data access of the cell array circuit 120. In an embodiment, the various circuits exemplified above may be implemented, for example, by an architecture of a logic circuit, and perform corresponding circuit function operations in accordance with a core voltage VINT used by the logic circuit. Thus, in FIG. 1, memory control circuit 110 receives core voltage VINT to control memory storage device 100 to operate in one of a plurality of modes of operation.

In the present embodiment, the core voltage VINT is generated, for example, by the voltage generator circuit 130 in accordance with the reference signal VREFxx. Voltage generator circuit 130 includes, for example, one or more voltage generators. The voltage generator circuit 130 can be disposed within or outside the memory storage device 100, and the invention is not limited thereto. In the present embodiment, the input/output circuit 140 performs operations such as data output input according to the reference signal VREFxx. The reference signal VREFxx includes, for example, a reference voltage of the input and output circuit 140.

Referring to FIG. 2, in the present embodiment, the memory cell array circuit 120 includes, for example, four memory blocks 122_1 to 122_4, the number of which is for illustrative purposes only, and the present invention is not limited thereto. Taking the memory block 122_1 as an example, the operating voltage is the voltage signal V4. The operating voltages of the row decoder and the column decoder of the memory block 122_1 are, for example, voltage signals V1, V2, respectively. In the present embodiment, the memory block 122_1 is disposed, for example, in a P-type well region of its substrate, and the substrate and its P-type well region receive the voltage signal V3.

In the present embodiment, the voltage signals (operating voltages) V1 to V4 are generated, for example, by the voltage generator circuit 130 in accordance with the reference signal VREFxx. In the present embodiment, the voltage signal V1 includes, for example, a word line enable high voltage. The voltage signals V2 and V3 include, for example, a bit line equalize control voltage and a bit line high level voltage. The voltage signal V4 includes, for example, a bit line equalization control voltage, a p-type well voltage, and a bit line high level voltage.

In the present embodiment, the operating voltages of the circuits in the memory control circuit 110 and the memory cell array circuit 120 are generated, for example, according to different reference voltages. Therefore, the reference signal VREFxx includes, for example, a reference voltage of the input-output circuit 140, a reference voltage for generating a bit line equalization control voltage, a reference voltage for generating a core voltage VINT, and a bit line-enabled high voltage for generating a word line. Reference voltage and similar reference voltage. For example, to stabilize the memory chip, the reference voltages of the circuits are generated, for example, by a plurality of different reference voltage sources that do not affect each other. However, the manner in which the reference voltage is generated is not intended to limit the invention.

In this embodiment, the circuit architectures of the memory control circuit 110, the memory cell array circuit 120, the voltage generator circuit 130, and the various circuit functional blocks among the input and output circuits 140 can be respectively adapted to any one of the technical fields. The circuit is implemented and the invention is not limited. The detailed steps and implementations thereof may be adequately taught, suggested, and implemented by the ordinary knowledge in the art, and therefore will not be described again.

FIG. 3 is a schematic diagram showing the switching of the memory storage device of the embodiment of FIG. 1 between different modes. Referring to FIG. 1 to FIG. 3, the memory storage device 100 of the present embodiment operates in one of a plurality of operation modes. In an embodiment, the multiple modes of operation include, but are not limited to, an idle mode, a deep self refresh mode (DSR mode), a self refresh mode (SR mode), and a depth. Power mode (deep power down mode, DPD mode). The standby mode, the deep self refresh mode, the self refresh mode, and the deep power saving mode are exemplified as examples of the first operation mode, the second operation mode, the third operation mode, and the fourth operation mode, respectively.

In the present embodiment, the memory storage device 100 receives power and enters a power-on state to operate in one of the plurality of operating modes. After the power is turned on, the memory control circuit 110 performs a precharge operation on the memory cell array circuit 120 to precharge the memory block and activate the memory block before accessing the memory block. After the precharge operation, the memory control circuit 110 performs a mode register set (MRS) on the memory cell array circuit 120. In an embodiment, for example, a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) dynamic random access memory, the memory control circuit 110 is further directed to a memory cell array. The circuit 120 performs an extended mode register set (EMRS). After the mode register is set, the memory control circuit 110 controls the memory storage device 100 to operate in the first mode of operation, that is, the standby mode. Among the first modes of operation, a plurality of memory blocks in the memory cell array circuit 120 have been precharged. In the first mode of operation, the memory control circuit 110 performs mode register setting on the memory storage device 100, for example, in accordance with the command MRS.

In this embodiment, the memory control circuit 110 switches the memory storage device 100 to different operating modes according to different instructions. For example, the memory control circuit 110 switches the memory storage device 100 from the first mode of operation to the second mode of operation, that is, the deep self-refresh mode, for example, in accordance with the command DSRS. In the second mode of operation, the memory control circuit 110 refreshes the stored data in the memory cell array circuit 120. In the second mode of operation, the memory control circuit 110 switches the memory storage device 100 from the second mode of operation back to the first mode of operation, for example, in accordance with the command DSRSX, with a switching time of, for example, 20 microseconds (μs). However, the length of the switching time is only for illustration, and the present invention is not limited thereto.

In the present embodiment, the memory control circuit 110 switches the memory storage device 100 from the first mode of operation to the third mode of operation, that is, the self-refresh mode, for example, according to the command REFS. In the third mode of operation, the memory control circuit 110 refreshes the stored data in the memory cell array circuit 120. In the third mode of operation, the memory control circuit 110 switches the memory storage device 100 from the third mode of operation back to the first mode of operation, for example, in accordance with the command REFSX, with a switching time of, for example, 0.12 microseconds. However, the length of the switching time is only for illustration, and the present invention is not limited thereto. Therefore, in the embodiment, the switching time of the memory storage device 100 switching from the second operation mode back to the first operation mode is greater than the switching time of the memory storage device 100 switching from the third operation mode to the first operation mode.

In the present embodiment, the memory control circuit 110 switches the memory storage device 100 from the first operating mode to the fourth operating mode, that is, the deep power saving mode, for example, according to the command DPDS. In the fourth mode of operation, the memory control circuit 110 does not refresh the stored data in the memory cell array circuit 120. That is to say, when the memory cell array circuit 120 is not needed for a while, the memory storage device 100 enters a sleep state without refreshing the stored data. In the fourth mode of operation, the memory control circuit 110 switches the memory storage device 100 from the fourth mode of operation back to the first mode of operation, for example, in accordance with the instruction DPDSX, with a switching time of, for example, 200 microseconds. However, the length of the switching time is only for illustration, and the present invention is not limited thereto. During the switching of the fourth operation mode back to the first operation mode, the memory storage device 100 switches back to the first operation mode after the power-on state, the pre-charge operation, and the mode register setting. Therefore, in the present embodiment, the switching time of the memory storage device 100 switching from the second operation mode back to the first operation mode is less than the switching time of the memory storage device 100 switching from the fourth operation mode to the first operation mode.

In this embodiment, the operating voltage of the memory storage device 100 operating in the second operating mode is smaller than the operating voltage of the memory storage device 100 operating in the third operating mode, compared to the third operating mode. For example, the core voltage VINT of the memory storage device 100 in the second mode of operation is less than the core voltage VINT of the memory storage device 100 in the third mode of operation. Alternatively, the memory storage device 100 equalizes the control voltage in the bit line of the second mode of operation to be equal to the bit line equalization control voltage of the memory storage device 100 in the third mode of operation. Alternatively, the word line enable high voltage of the memory storage device 100 in the second mode of operation is less than the word line enable high voltage of the memory storage device 100 in the third mode of operation. Alternatively, the absolute value of the P-well voltage of the memory storage device 100 in the second mode of operation is less than the absolute value of the P-well voltage of the memory storage device 100 in the third mode of operation. The setting of the down-regulating operating voltage in the second mode of operation may be performed at the same time, and the invention is not limited thereto. Therefore, the memory storage device 100 of the present embodiment saves power and can maintain data.

In the present embodiment, in the second mode of operation, the reference voltage of the input-output circuit 140 is disabled and the reference voltage used to generate the bit line equalization control voltage is disabled in the second mode of operation. Therefore, the memory storage device 100 of the present embodiment saves power and can maintain data. In the present embodiment, in the second operation mode, the bit line equalization control voltage and the bit line high level voltage can be set to a floating state compared to the third operation mode. Therefore, the memory storage device 100 of the present embodiment saves power and can maintain data.

In general, memory chips are usually provided with a safety mechanism circuit. When the external voltage (such as the power supply) of the memory chip is too low, the safety mechanism circuit automatically restarts according to the power on block signal to ensure that the internal signal setting of the memory chip is not wrong. In an embodiment, the power-on barrier signal is, for example, turned off in the second mode of operation compared to the third mode of operation. Therefore, the memory storage device 100 of the present embodiment saves power and can maintain data.

4 is a flow chart showing the steps of an operation method of a memory storage device according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 4, the method for operating the memory storage device of the present embodiment is at least applicable to the memory storage device 100 of FIG. 1, but the invention is not limited thereto. Taking the memory storage device 100 of FIG. 1 as an example, in step S100, the power of the memory storage device 100 is turned on to operate the memory storage device 100 in the first operation mode. In step S110, the memory storage device 100 is switched from the first operation mode to the second operation mode to refresh the stored data in the memory storage device 100. In this embodiment, the operating voltage of the memory storage device 100 operating in the second operating mode is less than the operating voltage of the memory storage device 100 operating in the third operating mode.

In addition, the operation method of the memory storage device of the embodiment of the present invention can be sufficiently taught, suggested, and implemented by the description of the embodiment of FIG. 1 to FIG. 3, and therefore will not be described again.

In summary, in an exemplary embodiment of the present invention, a second mode of operation different from the third mode of operation is established. In the second operation mode, the setting of the down-regulation operating voltage may be performed at the same time, so that the operating voltage of the memory storage device operating in the second operating mode is smaller than the operation of the memory storage device operating in the third operating mode. Voltage. Also, in the second mode of operation, a portion of the reference voltage can also be selectively turned off. Therefore, the memory storage device and its operating method save power and maintain data.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory storage device
110‧‧‧Memory Control Circuit
120‧‧‧Memory cell array circuit
122_1, 122_2, 122_3, 122_4‧‧‧ memory blocks
130‧‧‧Voltage generator circuit
140‧‧‧Input and output circuits
VINT‧‧‧ core voltage
VREFxx‧‧‧ reference signal
V1, V2, V3, V4‧‧‧ voltage signals
MRS, DSRS, DSRSX, REFS, REFSX, DPDS, DPDSX‧‧‧ directives
S100, S110‧‧‧ steps

FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. 2 is a schematic diagram showing the memory cell array circuit of the embodiment of FIG. 1. FIG. 3 is a schematic diagram showing the switching of the memory storage device of the embodiment of FIG. 1 between different modes. 4 is a flow chart showing the steps of an operation method of a memory storage device according to an embodiment of the present invention.

S100, S110‧‧‧ steps

Claims (10)

A memory storage device having a plurality of operation modes, and the memory storage device includes: a memory control circuit for controlling operation of the memory storage device in one of the operation modes; and a memory cell array a circuit electrically connected to the memory control circuit for storing data, wherein the memory storage device receives power to operate in one of the operation modes, and the memory control circuit controls the memory storage device to operate in a a first mode of operation, and controlling the memory storage device to switch from the first mode of operation to a second mode of operation to refresh stored data in the memory cell array circuit, wherein the memory device operates in a The three modes of operation are to refresh the stored data in the memory storage device, and the operating voltage of the memory storage device operating in the second mode of operation is less than the operating voltage of the memory storage device operating in the third mode of operation. The memory storage device of claim 1, wherein the memory control circuit controls the memory storage device to switch from the first operation mode to the third operation mode to refresh the memory storage device. Store data. The memory storage device of claim 2, wherein the switching time of the memory storage device switching from the second operation mode back to the first operation mode is greater than the memory storage device switching from the third operation mode The switching time of the first operation mode is returned. The memory storage device of claim 1, wherein the memory control circuit controls the memory storage device to switch from the first operating mode to a fourth operating mode, wherein in the fourth operating mode The stored data in the memory storage device is not refreshed. The memory storage device of claim 4, wherein the switching time of the memory storage device switching from the second operation mode back to the first operation mode is smaller than the memory storage device switching from the fourth operation mode The switching time of the first operation mode is returned. The memory storage device of claim 1, wherein when the memory storage device operates in the first mode of operation, a plurality of memory blocks in the memory cell array circuit are precharged . The memory storage device of claim 1, wherein the operating voltage is selected from a core voltage, a bit line equalization control voltage, a word line enable high voltage, and an absolute value of a P-type well voltage. one. The memory storage device of claim 1, wherein the reference voltage of the input/output circuit in the memory storage device is disabled and used when the memory storage device operates in the second operation mode The reference voltage that produces the bit line equalization control voltage is disabled. A method of operating a memory storage device, wherein the memory storage device has a plurality of operating modes, the operating method comprising: turning on a power of the memory storage device to operate the memory storage device in a first mode of operation; And switching the memory storage device from the first mode of operation to a second mode of operation to refresh the stored data in the memory storage device, wherein the memory storage device operates in a third mode of operation to refresh the memory The stored data in the bulk storage device and the operating voltage of the memory storage device operating in the second mode of operation are less than the operating voltage of the memory storage device operating in the third mode of operation. The operating method of claim 9, wherein the operating voltage is selected from at least one of a core voltage, a bit line equalization control voltage, a word line enable high voltage, and an absolute value of a P-type well voltage. And when the memory storage device operates in the second mode of operation, the reference voltage of the input/output circuit in the memory storage device is disabled and the reference voltage for generating the bit line equalization control voltage is disabled .