TWI609373B - Dual port static random access memory - Google Patents

Description

Double-click static random access memory

The invention relates to a 7T dual port static random access memory (SRAM), in particular to an effective improvement of the standby performance of the 7T dual-SRAM SRAM, and can effectively improve the reading speed and It effectively reduces the leakage current and can solve the 7T dual-SRAM SRAM which is difficult to write to the logic 1 with a single bit line.

As is shown in FIG. 1a, the static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of memory blocks (memory block, MB _1). , MB _{2 ,} etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL _{2 ,} etc.), each word line corresponding to a plurality of columns of memory One of the body cells; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _{m ,} etc.), each bit line pair corresponding to a plurality of rows of memory cells One row, and each bit line pair is composed of one bit line (BL ₁ ... BL _m ) and one complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b is a schematic diagram of a 6T單埠 SRAM cell, in which PMOS transistors (P1) and (P2) are called load transistors, NMOS transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is word line, and BL And BLB are a bit line and a complementary bit line, respectively, since the 單埠SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) Another driving transistor is turned on, and the initial instantaneous voltage (V _AR ) of the node A must satisfy the equation (1): V _AR = V _DD × (R _M1 ) / (R _M1 + R _M3 ) < V _TM2 (1) to prevent half-selected cell disturbance when reading, wherein V _AR represents the initial instantaneous voltage of the reading of node A, and R _M1 and RM ₃ respectively represent the NMOS transistor (M1) And the on-resistance of the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply voltage and the threshold voltage of the NMOS transistor (M2), which results in driving the transistor The current drive capability ratio between the body and the access transistor (ie, the cell ratio) is usually set between 2.2 and 3.5 (refer to US Patent No. US76060B2, No. 2, No. 8-10, October 20, 1998). Row).

The HSPICE transient analysis results of the 6T單埠 SRAM cell shown in Figure 1b during the write operation, as shown in Figure 2, are simulated using the TSMC 90 nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T 單埠 SRAM cell with only a single bit line, compared to the 6T 單埠 SRAM cell of Figure 1b. The random access memory cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T單埠 SRAM cell does not change the PMOS transistors P1 and P2. In the case of the channel width to length ratio of the NMOS transistors M1, M2, and M3, there is a problem that writing logic 1 is quite difficult. Considering that the node A on the left side of the memory cell originally stores a logic 0, since the charge of the node A is transmitted only from the bit line (BL) alone, the logic 0 previously written in the node A is overwritten with a logic 1 write. The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 ) / (R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of the write of node A, R _M1 And RM ₃ respectively indicate the on-resistances of the NMOS transistor (M1) and the NMOS transistor (M3). Comparing equations (1) and (2), the initial transient voltage (V _AW ) is smaller than the NMOS transistor (M2). The threshold voltage (V _TM2 ), and thus the operation of writing logic 1 cannot be completed. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is simulated using the TSMC 90 nm CMOS process parameters. The simulation results confirm that it is quite difficult to write logic 1 in a 5T SRAM cell with a single bit line.

Next, we discuss the static random access memory (SRAM) and double-ended architecture. The 6T static random access memory (SRAM) cell in Figure 1b is the static random access memory (SRAM) crystal. One example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, both reading and writing are achieved through the same pair of bit lines, so that only reading or reading can be performed at the same time. The action of writing, therefore, when designing a dual-static SRAM with simultaneous read and write capabilities, it is necessary to add two access transistors and another pair of bit lines (please refer to Figure 5). a circuit in which WBL and WBLB are write bit line pairs, RBL and RBLB are read bit line pairs, WWL is a write word line, and RWL is a read word line), which makes the memory crystal The area of the cell is greatly increased if we can simplify the structure of the memory cell, making a bit The line is responsible for the read action, and the other bit line is responsible for the write operation. When designing the dual-squat static random access memory, the memory cell does not need to add two transistors and a pair of bit lines. Thus, the area of the memory cell is much reduced. The conventional double-squeezing SRAM cell does not use this method because it is quite difficult to write logic 1 as described above.

So far, many techniques have been proposed for a double-squat static random access memory cell with a single bit line, for example, "Double-埠 Static Random Access" proposed in Patent Document 1 (TWI441178, June 11, 103) "Memory", "Double-埠 SRAM with discharge path" proposed in Patent Document 2 (TWI441179, June 11, 103), and Patent Document 3 (US Pat. No. 8717807 B2, May 6, 103) "7-Twin SRAM" proposed by Independently-controlled-gate SRAM, Patent Document 4 (TWI433152, April 1, 103), and Patent Document 5 (TWI425509, February 1, 103) "Double-band static random access memory with discharge path", Patent Document 6 (TWI 423257, January 11, 103), "Double-埠 SRAM for reducing power supply voltage during write operation", Patent Document 7 (103) "Double-Static Static Random Access Memory for Increasing the Voltage Level of Write Word Lines During Write Operation", No. TWI423258, January 11, 2011, Patent Document 8 (TWI399748, June 21, 102) No.), "SEVEN TRANSISTOR SRAM CELL" proposed in Patent Document 9 (US20090161410 A1, June 22, 1998) "SRAM cell with independent static noise margin, trip voltage, and read current optimization" and Patent Document 11 (US Pat. No. 6,751,151 B2, June 15, 1993) No.) "Ultra high-speed DDP-SRAM cache", these patents can effectively solve the problem of writing logic 1 difficult, but because these patents do not consider the operating voltage below 20 nm will be reduced to There is still a problem of reduced reading speed when the voltage is below 1 volt, so there is still room for improvement.

In view of this, the main object of the present invention is to provide a dual-turn static random access memory capable of effectively improving the reading speed by a dual mechanism of a control circuit and a high voltage level control circuit.

A secondary object of the present invention is to provide a dual-band static random access memory that can be controlled by two stages to improve read speed while avoiding unnecessary power consumption.

Still another object of the present invention is to provide a dual-turn static random access memory capable of effectively causing the SRAM to quickly enter the standby mode by the standby enable circuit, thereby effectively improving the standby performance of the SRAM.

Another object of the present invention is to provide a dual-turn static random access memory capable of effectively reducing leakage current in a standby mode by a control circuit.

The invention provides a double-埠 static random access memory, which mainly comprises a memory array (1), a plurality of control circuits (2), a plurality of pre-charge circuits (3), a standby start circuit (4) and a plurality a high voltage level control circuit (5), the memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells is provided with a control circuit, and each memory cell The cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11) and a second inverter (by a second PMOS transistor P12 and a The second NMOS transistor M12 is composed of an access transistor (composed of the third NMOS transistor M13), a first read transistor (M14), and a second read transistor (M15). . Each control unit (2) is connected to a source of the first NMOS transistor (M11) of each of the memory cells of the corresponding column memory cell and the second NMOS a source of the crystal (M12) to control a source voltage of the first NMOS transistor (M11) and a source voltage of the second NMOS transistor (M12) in response to different operation modes, thereby being in a write mode It can effectively prevent the difficulty of writing logic 1. In the read mode, it can improve the reading speed and avoid unnecessary power consumption. In standby mode, the leakage current can be effectively reduced, while in the hold mode. It can maintain the original electrical characteristics. Moreover, the standby start circuit (4) is designed to effectively cause the dual-squat static random access memory to quickly enter the standby mode, thereby effectively improving the standby performance of the dual-static static random access memory. In addition, the design of the plurality of high voltage level control circuits (5) is such that when the logic 0 is read, the degree of conduction of the second read transistor (M15) is increased to further increase the read speed.

BLB ₁ ...BLB _m ‧‧‧complementary bit line

BLB‧‧‧complementary bit line

MB ₁ ... MB _k ‧‧‧ memory block

WL ₁ ... WL _n ‧‧‧ character line

BL ₁ ...BL _m ‧‧‧ bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

C‧‧‧ node

M14‧‧‧First read transistor

M15‧‧‧Second reading transistor

S‧‧‧Standby mode control signal

/S ‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

M41‧‧‧12th NMOS transistor

P41‧‧‧4th PMOS transistor

WBL‧‧‧Write bit line

WWL‧‧‧write word line

RBL‧‧‧Reading bit line

RWL‧‧‧Read word line

D2‧‧‧second delay circuit

5‧‧‧High voltage level control circuit

V _DD ‧‧‧Power supply voltage

HV _DD ‧‧‧High power supply voltage

P51‧‧‧ Fifth PMOS transistor

P52‧‧‧6th PMOS transistor

I53‧‧‧4th inverter

VH‧‧‧ high voltage node

WC‧‧‧ write control signal

/WC‧‧‧Inverted write control signal

Figure 1a shows a conventional static random access memory; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; and Fig. 2 shows a conventional 6T static random access memory cell. The write operation timing chart; the third figure shows the circuit diagram of the conventional 5T static random access memory unit cell; the fourth figure shows the write operation timing chart of the conventional 5T static random access memory unit cell; 5 is a circuit diagram showing a conventional 8T dual-static static random access memory cell; FIG. 6 is a schematic circuit diagram showing a preferred embodiment of the present invention; and FIG. 7 is a view showing the invention of FIG. The preferred embodiment is a simplified circuit diagram during the writing of logic 1; FIG. 8 is a timing chart showing the writing operation of the preferred embodiment of the present invention in FIG. 6; and FIG. 9 is a preferred embodiment of the present invention showing FIG. A simplified circuit diagram during the reading period; FIG. 10 is a simplified circuit diagram showing the preferred embodiment of the present invention in the sixth embodiment during standby.

According to the above main object, the present invention provides a double-twist static random access memory, which mainly includes a memory array composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each A column of memory cells and each row of memory cells include a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharges Circuit (3), each row of memory cells is provided with a pre-charging circuit (3); a standby starting circuit (4), which causes the double-turn SRAM to quickly enter standby mode to effectively improve the double-turn SRAM Standby performance: and a plurality of high voltage level control circuits (5), each column of memory cells is provided with a high voltage level control circuit (5) to further increase the reading speed when logic 0 is read.

For convenience of explanation, the double-chip static random access memory shown in FIG. 6 has only one memory cell (1), one write word line (WWL), and one write bit line ( WBL), a read word line (RWL), a read bit line (RBL), a control circuit (2), a precharge circuit (3), a standby start circuit (4), and a high The voltage level control circuit (5) is explained as an embodiment. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11) and a second inverter (by a second PMOS) a crystal P12 and a second NMOS transistor M12, a third NMOS transistor (M13), a first read transistor (M14), and a second read transistor (M15), wherein The first inverter and the second inverter are connected in an alternating coupling manner, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the second The output of the phase converter (ie, node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store data of the SRAM cell, and the second inverter It The output (Node B) is used to store the inverted data of the SRAM cell.

The first inverter of the memory cell (1) (composed of the first PMOS transistor P11 and the first NMOS transistor M11) is connected to a power supply voltage (V _DD ) and a first Between the low voltage nodes (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected to a high voltage node (VH) and a second low Between the voltage nodes (VL2), the source, the gate and the drain of the first read transistor (M14) are respectively connected to the drain of the second read transistor (M15), the reading Using a word line (RWL) and the read bit line (RBL), and a source, a gate and a drain of the second read transistor (M15) are respectively connected to the second low voltage node (VL2), the output of the second inverter (node B) and the source of the first read transistor (M14).

Referring again to FIG. 6, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS device. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control Signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), an inverted write control signal (/WC), a standby mode control signal (S) and an inverted standby mode control signal (/S). a source, a gate and a drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the reverse standby mode control signal (/S) and the second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate is connected to the drain and connected to The first low voltage node (VL1); the source, the gate and the drain of the seventh NMOS transistor (M24) are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); the source, the gate and the drain of the eighth NMOS transistor (M25) are respectively connected to the accelerated read voltage (RGND), the first delay circuit An output of (D1) and a source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to an output of the third inverter (INV) and the eighth NMOS transistor (M25) Between the gates; the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); a source, a gate and a drain of the NMOS transistor (M26) are respectively connected to a ground voltage, a drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the tenth NMOS a source, a gate and a drain of the crystal (M27) are respectively connected to a ground voltage, the standby mode control signal (S) and a gate of the ninth NMOS transistor (M26); and the eleventh NMOS transistor (M28) source, gate A drain respectively connected to the inverted write control signal (/ WC), the inverted standby mode control signal (/ S) and the gate of the ninth NMOS transistor (M26) of the pole. It should be noted here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter, and the inverted write control signal (/WC) is A write control signal (WC) is obtained via another inverter.

It is worth noting here that the drain of the eleventh NMOS transistor (M28), the drain of the tenth NMOS transistor (M27), and the gate of the ninth NMOS transistor (M26) are connected together. And forming a node (C), when the standby mode control signal (S) is logic low level, the voltage level of the node (C) is the logic level of the inverted write control signal (/WC), and When the standby mode control signal (S) is at a logic high level, the voltage level of the node (C) is a ground voltage, thereby having a stable standby mode (since the voltage level of the node C during the write operation is constant Ground voltage); further, the logic high level of the node (C) is the power supply voltage (V _DD ) deducting the voltage level of one of the threshold voltages (V _TM28 ) of the eleventh NMOS transistor (M28) Therefore, when the dual-static SRAM is in the non-write mode (when the inverted write control signal (/WC) is at a logic high level), the node (C) is the power supply. the threshold voltage (V _TM28) voltage (V _DD) deduct the eleventh NMOS transistor (M28) of the voltage level, rather than the power supply voltage (V _DD) of voltage Precise, so it can have lower power consumption; and when it enters the write mode (in this case, the inverted write control signal (/WC) is a logic low level), it can be quickly stored in the node. The charge of (C) is discharged through the eleventh NMOS transistor (M28) to the ninth NMOS transistor (M26) sufficient to turn off the node (C) as a gate, so that the write mode can be entered relatively quickly. .

The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage of the driving transistor (ie, the first NMOS transistor M11) closer to the writing bit line (WBL) is set to be higher than the ground voltage. Predetermining a voltage (ie, a gate-source voltage V _{GS (M23) of} the sixth NMOS transistor (M23)) and selecting a source voltage of another driving transistor (ie, the second NMOS transistor M12) in the selected cell ( That is, the second low voltage node VL2) is set to the ground voltage in order to prevent the problem of writing logic 1 difficult.

In the first phase of the read mode, the source voltage of the driving transistor (ie, the second NMOS transistor M12) that is closer to the read bit line (RBL) in the selected cell (ie, the second low) The voltage node VL2) is set to be the accelerated read voltage (RGND) which is lower than the ground voltage, The accelerated read voltage (RGND), which is lower than the ground voltage, can effectively increase the read speed, and in the second stage of the read mode, the selected cell is closer to the read bit line (RBL). The source voltage of the driving transistor (ie, the second NMOS transistor M12) is set back to the ground voltage to reduce unnecessary power consumption, wherein the second phase of the read mode is separated from the first phase by The read control signal (RC) is converted from a logic low level to a logic high level, and until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), The value can be adjusted by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1).

In the standby mode, the source voltage of the driving transistor in all the memory cells is set to the predetermined voltage higher than the ground voltage to reduce the leakage current; and in the hold mode, the driving power in the memory cell is The source voltage of the crystal is set to the ground voltage in order to maintain the original retention characteristics, and the detailed operating voltage level is as shown in Table 1 above.

The inverted write control signal (/WC) in Table 1 is the write control signal (WC) an inverted signal, and the write control signal (WC) is an AND gate operation result of the write signal (W) and the word line (WL) signal, at this time only When the write signal (W) signal and the word line (WL) signal are both at a logic high level, the write control signal (WC) is a logic high level; the read control signal (RC) is a read enable The result of the AND operation of the (Read Enable, RE for short) signal and the corresponding read word line (RWL) signal. It is worth noting here that the unselected word line and the unselected positioning element line are set to a floating state, and the read control signal (RC) is set to the acceleration during the non-read mode. The level of the read voltage (RGND) is read to prevent leakage current of the seventh NMOS transistor (M24).

Referring to FIG. 6, the precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P). The source and gate of the third PMOS transistor (P31) And the drain system are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit line (RBL), so as to be in a logic low level during precharge Precharge signal (P) to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V _DD ).

Referring to FIG. 6, the standby starting circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2), and the reverse standby. The mode control signal (/S) is composed of. a source, a gate and a drain of the fourth PMOS transistor (P41) are respectively connected to the power supply voltage (V _DD ), the inverted standby mode control signal (/S) and the twelfth NMOS transistor a drain of (M41); a source, a gate and a drain of the twelfth NMOS transistor (M41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) And a drain of the fourth PMOS transistor (P41); an input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and an output of the second delay circuit (D2) is Connected to the gate of the twelfth NMOS transistor (M41).

Referring again to FIG. 6, the high voltage level control circuit (5) is composed of a fifth PMOS transistor (P51), a sixth PMOS transistor (P52), and a fourth inverter (I53). The source, the gate and the drain of the fifth PMOS transistor (P51) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH), The source, the gate and the drain of the sixth PMOS transistor (P52) are respectively connected to a high power supply voltage (HV _DD ), the output of the fourth inverter (I63) and the high voltage node (VH) And the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the drain of the sixth PMOS transistor (P52). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage. Between the node (VH) and the second low voltage node (VL2).

The working principle of the preferred embodiment of the invention illustrated in Figure 6 is as follows:

(I) write mode

Before the start of the write operation, the standby mode control signal (S) is at a logic low level, such that the eleventh NMOS transistor (M28) is turned "ON", and the tenth NMOS transistor (M27) is turned off (OFF) ), since the inverted write control signal (/WC) is at a logic high level, the drain of the eleventh NMOS transistor (M28) is at a logic high level, and the logic IF is the eleventh NMOS. The drain of the transistor (M28) turns on the ninth NMOS transistor (M26) and causes the first low voltage node (VL1) to assume a ground voltage.

During the write operation period, the inverted write control signal (/WC) is at a logic low level, such that the drain of the eleventh NMOS transistor (M28) is at a logic low level, and the logic low level is the first The drain of the eleven NMOS transistor (M28) causes the ninth NMOS transistor (M26) to be turned off, and the low voltage node (VL1) is equal to the gate voltage V _{GS of} the sixth NMOS transistor (M23) _(M26) , thereby effectively preventing the problem of writing logic 1 difficult. Figure 7 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 6 during writing.

Next, how the write operation of the preferred embodiment of the present invention in FIG. 7 is completed in accordance with four write states.

(1) Node A originally stores a logic 0, but now wants to write a logic 0:

Before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M11) is turned "ON". Since the first NMOS transistor (M11) is ON, the write word line (WWL) is turned from Low (ground voltage) to High (power supply voltage V _DD ) when the write operation starts. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned off (OFF) To be ON, at this time, since the write bit line (WBL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle.

(2) Node A originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M11) is turned "ON". It is worth noting here that since the first NMOS transistor (M11) is ON, when the write operation starts, the write word line (WWL) is turned from Low (ground voltage) to High (the power supply) Voltage V _DD ), the voltage of this node A will slightly increase with the voltage following the write word line (WWL) due to the parasitic capacitance coupling effect.

When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON. Because the write bit line (WBL) is High (the power supply voltage V _DD ), and because the first NMOS transistor (M11) is still ON and the node B is still at a voltage level close to the The initial state of the voltage level of the power supply voltage (V _DD ), so the first PMOS transistor (P11) is still OFF (OFF), and the initial transient voltage (V _AW ) of the node A satisfies the equation (3) ): V _AW = V _DD × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 ) > V _TM12 (3) where V _AW represents the initial transient voltage of the write of the node A, and R _M13 represents the The on-resistance of the third NMOS transistor (M13), R _M11 represents the on-resistance of the first NMOS transistor (M11), R _M23 represents the on-resistance of the sixth NMOS transistor (M23), and V _DD and V _TM12 Representing the power supply voltage and the threshold voltage of the second NMOS transistor (M12), respectively, because the third NMOS transistor (M13) is still operating in the saturation region and the first NMOS transistor (M11) still For the linear region (triode region), while guiding the third NMOS transistor (M13) through the equivalent resistance (R _M13) is considerably greater than the first NMOS transistor (M11) is turned the equivalent resistance (R _M11), However, since the sixth NMOS transistor (M23) is diode-connected, a gate-source voltage V equal to the sixth NMOS transistor (M23) can be provided at the first low voltage node (VL1). The voltage level of _{GS (M23)} , the resulting initial write voltage (V _AW ) of node A will be higher than the voltage level of the node A of the conventional 5T static random access memory cell of FIG. It is much higher. The much higher voltage division level is sufficient to turn on the second NMOS transistor (M12), thereby causing the node B to discharge to a lower voltage level, and the lower voltage level of the node B causes the The on-resistance equivalent (R _M11 ) of the first NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) obtains a higher voltage level at the node A. The higher voltage level of the node A will pass through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level. The lower voltage level of the node B is again caused by the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level. According to this cycle, the node A can be charged to the power supply voltage (V _DD ), and the logic 1 write operation is completed.

It should be noted here that the first low voltage node VL1 originally stores a logic 0 at the node A, and has a gate-source voltage V _GS equal to the sixth NMOS transistor (M23) during the writing of the logic 1. The voltage level of _(M23) , after writing logic 1, will have the level of the ground voltage due to discharge through the ninth NMOS transistor (M26).

(3) Node A originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the write word line (WWL) is greater than the third NMOS transistor (M13) When the threshold voltage is applied, the third NMOS transistor (M13) is turned from OFF to ON; at this time, since the write bit line (WBL) is High (the power supply voltage V _DD ) And because the first PMOS transistor (P11) is still ON, the voltage of the node A is maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the write word line WWL is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the write word line (WWL) is greater than the third NMOS transistor (M13) When the threshold voltage is applied, the third NMOS transistor (M13) is turned from OFF to ON. At this time, since the write bit line (WBL) is Low (ground voltage), The node A and the first low voltage node (VL1) are discharged to complete the logic 0 write operation until the end of the write cycle.

In the preferred embodiment of the present invention shown in FIG. 7, the HSPICE transient analysis simulation result at the time of the write operation is as shown in FIG. 8, which is simulated using the TSMC 90 nm CMOS process parameters, from which the simulation result is obtained. It can be confirmed that the double-turn static random access memory proposed by the present invention can improve the voltage level of the first low voltage node (VL1) during writing to effectively avoid the conventional write bit line. It is quite difficult to write the logic 1 in the double-squat static random access memory cell.

(II) Read mode (read mode)

Before the start of the read operation, the standby mode control signal (S) is a logic low level, and the inverted write control signal (/WC) and the inverted standby mode control signal (/S) are both logic high levels. Making the eleventh NMOS transistor (M28) turned on, and making the tenth NMOS transistor (M27) Therefore, the drain of the eleventh NMOS transistor (M28) is at a logic high level, and the drain of the eleventh NMOS transistor (M28) of the logic high level turns on the ninth NMOS transistor (M26), and The first low voltage node (VL1) is brought to a ground voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned "ON".

It is worth noting here that during pre-charging before the start of the read operation, the pre-charge signal (P) is at a logic low level, thereby pre-charging the corresponding read bit line (RBL) to The power supply voltage (V _DD ) is at a level, but since the operating voltage of, for example, a process technology of 20 nm or less is reduced to less than 1 volt, the reading speed is lowered and the specification cannot be satisfied. Therefore, the present invention proposes two Phase read control is used to improve read speed and meet specifications while avoiding unnecessary power consumption.

The preferred embodiment of the present invention shown in FIG. 6 is controlled by two stages to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the reading operation, the reading control The signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the second low voltage node (VL2) is approximately grounded. The accelerated read voltage (RGND) is low, and the accelerated read voltage (RGND), which is lower than the ground voltage, can effectively increase the read speed.

In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but since the eighth NMOS transistor (at this time) M25) is turned off, and then the second low voltage node (VL2) is grounded via the turned-on fourth NMOS transistor (M21) (due to the inverted standby mode control signal (/S) during the read operation is logic High level), which can effectively reduce unnecessary power consumption. At this value It should be noted that the second phase of the read operation is separated from the first phase by the equalization of the read control signal (RC) from the logic low level to the logic high level, and to the eighth NMOS. The gate voltage of the transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), and the value thereof can be decreased by the delay time of the third inverter (INV) and the first delay circuit (D1) The delay time provided is adjusted. Furthermore, the fourth NMOS transistor (M21) is in an on state regardless of the first phase of the read operation or the second phase (due to the inverted standby mode control signal (/S) being logic during the read operation High level). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 6 during reading.

Next, how to set the accelerated read voltage (RGND) and how to increase the read speed in the preferred embodiment of the present invention in FIG. 9 will be described in terms of two read states.

(1) Read logic 1 (node A stores logic 1):

Before the reading operation occurs, the first NMOS transistor (M11) is turned off (OFF) and the second NMOS transistor (M12) is turned on (ON), and the node A and the node B are respectively the power supply voltage (V _DD ) and the ground voltage, and the read bit line (RBL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading, since the node B is a ground voltage, the second read transistor (M15) is turned off (OFF), thereby effectively maintaining the read bit line (RBL) as the power supply voltage ( V _DD ) The operation of reading logic 1 is successfully completed until the end of the read cycle. It is worth noting here that in the first phase of the read operation, the read initial transient voltage (V _RVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy equation (4) V _RVL2I = RGND × R _M21 / (R _M21 + R _M24 + R _M25 ) > -V _TM12 (4) to effectively prevent half-selected cell disturbance at the time of reading, where V _RVL2I indicates The second low voltage node (VL2) reads the initial instantaneous voltage when reading logic 1, RGND represents the accelerated read voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), and R _M24 represents the first The on-resistance of the seven NMOS transistor (M24), R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12); In the second phase, the voltage of the second low voltage node (VL2) (V _RVL2 ) can be expressed by equation (5) V _RVL2 = ground voltage (5), thereby effectively reducing unnecessary power consumption. Furthermore, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, the accelerated read voltage (RGND) lower than the ground voltage must be set such that the second low voltage node (VL2) The voltage level is smaller than the threshold voltage (V _TM12 ) of the second NMOS transistor (M12), and the accelerated read voltage (RGND) lower than the ground voltage can be set more strictly below the second NMOS power. The threshold voltage (V _TN12 ) of the crystal (M12), that is, | RGND | < V _TM12 (6) where | RGND | and V _TM12 respectively represent the absolute value of the accelerated read voltage and the second NMOS transistor (M12) The threshold voltage.

(2) Read logic 0 (node A stores logic 0):

Before the reading operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF), and the node A and the node B are respectively grounded voltage and The power supply voltage (V _DD ), and the read bit line (RBL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading, since the node B is the high power supply voltage (HV _DD ), and the second low voltage node (VL2) is approximately at a higher than the ground voltage, the accelerated read voltage (RGND) is due to the high power supply. The supply voltage (HV _DD ) is set higher than the power supply voltage (V _DD ), so that the read speed of the second read transistor (M15) can be increased to increase the read speed, and at the same time The grounding voltage is low for the accelerated read voltage (RGND) to further increase the read speed. It is worth noting here that the high power supply voltage (HV _DD ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the second PMOS transistor (P12) The absolute value of the threshold voltage | V _TP12 |, that is, V _DD <HV _DD <V _DD +| V _TP12 | (7) where | V _TP12 | represents the absolute voltage of the second PMOS transistor (P12) value.

(III) Standby mode

First, how the standby start circuit (4) of Fig. 6 causes the dual-slide SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: first, the reverse standby mode control signal (/S) before entering the standby mode. Is logic High, the logic high inversion standby mode control signal (/S) causes the fourth PMOS transistor (P41) to be turned off (OFF), and the twelfth NMOS transistor (M41) is turned on (ON); Then, after entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fourth PMOS transistor (P41) to be turned on (ON). However, during the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from the logic High to the logic Low, to the gate voltage of the twelfth NMOS transistor (M41) The time until the twelfth NMOS transistor (M41) is turned off, which can be adjusted by a delay time provided by the second delay circuit (D2), and the twelfth NMOS transistor (M41) is still turned on. (ON), then the first low voltage node (VL1) can be quickly charged to reach the sixth NMOS transistor The voltage level of the threshold voltage (V _TM23 ) of the body (M23), that is, the double-turn SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (M41) is turned off and the supply current is stopped.

Please refer to FIG. 6 . In the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (M21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (M22) is turned on (ON), and the fifth NMOS transistor (M22) is used as an equalizer, so that the fifth NMOS transistor (M22) in an on state can be used. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V _TM23 ). Figure 10 is a simplified circuit diagram of the preferred embodiment of the present invention in Figure 6 during standby.

Next, how to reduce leakage current in the standby mode of the present invention is described. Referring to FIG. 10, FIG. 10 depicts a leakage current I ₁ generated when the embodiment of the present invention is in the standby mode. , I ₂ , I ₃ , I ₄ , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting that the first low voltage is due to the standby mode) The voltage level of the node (VL1) and the second low voltage node (VL2) are maintained at the voltage level of the threshold voltage ( _VTM23 ) of the sixth NMOS transistor (M23), so the node A is the voltage of the logic Low. The level is also maintained at the voltage level of the _VTM23 , and the output of the second inverter (ie, node B) is a logic high (power supply voltage V _DD ). Referring to the conventional 8T dual-SRAM SRAM of FIG. 5 and the embodiment of the present invention of FIG. 10, the double-turn static random access memory proposed by the present invention and the conventional 8T dual-turn SRAM of FIG. 5 are described in terms of leakage current. For comparison, first of all, regarding the leakage current I ₁ flowing through the third NMOS transistor (M13), since the voltage level of the node A in the standby mode is maintained at the voltage level of the V _TM23 , and the write is assumed The input word line (WWL) is set to the ground voltage in the standby mode, and the write bit line (WBL) is set to the power supply voltage (V _DD ) in the standby mode, so the present invention three NMOS transistor (M13) the gate-source voltage (V _GS) is negative, on the other hand, when a conventional stand-by mode of FIG. 5 8T two-port SRAM of the NMOS transistor (M3) of the gate-source voltage (V _GS) Equivalent to 0, according to the Gate Induced Drain Leakage (GIDL) effect or the results of Figures 3 (A) and 3 (B) of US Pat. No. 6,865,119, March 8, 2005, for NMOS In the case of a crystal, the subcritical current at a gate-to-source voltage of -0.1 volt is about 1% of the subcritical current at a gate-source voltage of 0 volts. Thus due to conduction caused by the effects of GIDL flow through the third NMOS transistor (M13) of the present invention is much smaller than the drain current I ₁ of the FIG. 5 8T conventional dual-port SRAM of the NMOS transistor (M3) are; Furthermore, The 汲 source voltage (V _DS ) of the third NMOS transistor (M13) of the present invention _deducts the voltage level of the V _TM23 from the power supply voltage (V _DD ), and is _similar to the conventional 8T double _埠 SRAM of FIG. The 汲 source voltage (V _DS ) of the NMOS transistor (M3) is equal to the power supply voltage (V _DD ), which is based on the Drain-Induced Barrier Lowering (DIBL) effect due to the DIBL effect. The leakage current I ₁ of the third NMOS transistor (M13) flowing through the present invention is also smaller than the NMOS transistor (M3) of the conventional 8T dual-SRAM of FIG. 5; as a result, the third NMOS flowing through the present invention The leakage current I _{1 of the} transistor (M13) is much smaller than that of the conventional 8T double-SRAM NMOS transistor (M3) of FIG.

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) due to the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the _VTM23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V _{DD ) Deducting} the voltage level of the V _TM23 , the source drain voltage (V _SD ) of the PMOS transistor (P1) of the conventional 8T dual-SRAM SRAM of FIG. 5 is equal to the power supply voltage (V _DD ), according to The DIBL effect, therefore, the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P1) of Figure 1b.

Then, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V _TM23 in the standby mode, the node A The voltage level is also maintained at the voltage level of the V _TM23 , and the voltage level of the node B is equal to the power supply voltage (V _DD ) and the base of the second NMOS transistor (M12) is the ground voltage, so The base-source voltage (V _BS ) of the second NMOS transistor (M12) of the invention is a negative value, and the 汲 source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V) _DD ) deducting the voltage level of the V _TM23 , and the base-source voltage (V _BS ) of the NMOS transistor (M2) of the conventional 8T double-turn SRAM of FIG. 5 is equal to 0, and the NMOS transistor (M2) The source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and the DIBL effect, the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than Figure 5 is a conventional 8T dual-SRAM NMOS transistor (M2).

Finally, regarding the leakage current I ₄ flowing through the first read transistor (M14), since the present invention is different from the conventional 8T dual-turn SRAM of FIG. 5, and the reading is performed in the standby mode of the present invention. The bit line (RBL) can be set to the ground voltage, and the conventional 8T double-turn SRAM of FIG. 5 is used to prevent the voltage level of the node B from falling. The read bit line pair (RBL, RBLB) in the standby mode is Since the power supply voltage is set, it is not possible to compare the leakage current I ₄ flowing through the first read transistor (M14). Based on the above analysis, the double-twist static random access memory proposed by the present invention has a lower leakage current than the conventional 8T dual-turn SRAM of FIG.

(IV) hold mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to ground voltage, the working principle is the same as that of the conventional double-bit SRAM cell with a single bit line. No longer said.

【Effects of invention】

The double-twist static random access memory proposed by the invention has the following effects:

(1) High read speed and avoiding unnecessary power consumption: The dual-stub static random access memory system proposed by the present invention employs a two-stage read operation, in the first stage of reading logic 0 by the second low node voltage (VL2) is set to be lower than a ground voltage to the acceleration of the read voltage (RGND), and the node B is set to the high power supply voltage is higher than the power supply voltage (V _DD) of (HV _DD), Therefore, the dual mechanism can be used to effectively increase the reading speed, and in the second phase of the read logic 0, the second low voltage node (VL2) is set back to the ground voltage to reduce unnecessary power consumption;

(2) Quick entry standby mode: Since the double-chip static random access memory proposed by the present invention is provided with a standby start circuit (4) to prompt the SRAM to quickly enter the standby mode, and thereby seek to improve the standby of the 7T dual-SRAM efficacy;

(3) The problem of avoiding the difficulty of writing logic 1: The double-click static random access memory proposed by the present invention can be effectively activated by increasing the voltage level of the first low voltage node (VL1) during a write operation. It is quite difficult to avoid the existence of double-埠 SRAM with a single bit line. question;

(4) Low standby current: Since the double-pin static random access memory proposed by the present invention is in the standby mode, the fifth low-voltage transistor (M22) in an on state can be used to make the first low voltage The voltage level of the node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the level of the threshold voltage of the sixth NMOS transistor (M23), thus The double-twist static random access memory proposed by the invention also has the effect of low standby current;

(5) Effectively reducing half-selected cell interference: the double-twist static random access memory proposed by the present invention uses a separate read/write path, and the read path is designed to read the first and second read A transistor (M14 and M15) is connected in series between the read bit line (RBL) and the second low voltage node (VL2), and the inverting storage node (B) is connected to the second read. The gate of the transistor (M15) is taken, so that the half-selected cell disturbance can be effectively reduced, wherein the half-selected cell is selected by the read word line (RWL) but not The cell cell selected by the bit line (RBL) is read.

(6) Low transistor number: For an SRAM array having 1024 columns and 1024 rows, the conventional 8T dual-SRAM array of FIG. 5 requires 1024×1024×8=8,388,608 transistors, and the double proposed by the present invention埠 Static random access memory requires only at least 1024 × 1024 × 7 + 1024 × 20 + 6 = 7,360,518 transistors, which reduces the number of transistors by 12.3%.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

C‧‧‧ node

M14‧‧‧First read transistor

M15‧‧‧Second reading transistor

WBL‧‧‧Write bit line

WWL‧‧‧write word line

RBL‧‧‧Reading bit line

RWL‧‧‧Read word line

S‧‧‧Standby mode control signal

/S ‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

M41‧‧11 eleventh NMOS transistor

P41‧‧‧4th PMOS transistor

D2‧‧‧second delay circuit

5‧‧‧High voltage level control circuit

V _DD ‧‧‧Power supply voltage

HV _DD ‧‧‧High power supply voltage

P51‧‧‧ PMOS transistor

P52‧‧‧6th PMOS transistor

I63‧‧‧ fifth inverter

VH‧‧‧ high voltage node

/WC‧‧‧Inverted write control signal

Claims (10)

A double-click static random access memory, comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each row of memory The unit cell comprises a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory crystals The cell is provided with a pre-charging circuit (3); a standby starting circuit (4), the standby starting circuit (4) prompts the dual-static static random access memory to quickly enter the standby mode, so as to effectively improve the double-static static random storage. Taking the standby performance of the memory; and a plurality of high voltage level control circuits (5), each column of memory cells is provided with a high voltage level control circuit (5) to increase the reading speed when reading logic 0; Each memory cell (1) further includes: a first inverter composed of a first PMOS transistor (P11) and a first NMOS transistor (M11), the first inverter Connected to a power supply voltage (V _DD ) and a first low voltage node (VL1) a second inverter consisting of a second PMOS transistor (P12) and a second NMOS transistor (M12) connected to a high voltage node (VH) Between a second low voltage node (VL2); a storage node (A) formed by the output of the first inverter; and an inverting storage node (B) by the second inversion Formed at the output end of the device; a third NMOS transistor (M13) is connected between the storage node (A) and a corresponding write bit line (WBL), and the gate is connected to a corresponding Write word line (WWL); a first read transistor (M14), the source, gate and drain of the first read transistor (M14) are respectively connected to a second read Taking a drain of the transistor (M15), a read word line (RWL) and a read bit line (RBL); and the second read transistor (M15), the second read a source, a gate and a drain of the transistor (M15) are respectively connected to the second low voltage node (VL2), the reverse storage node (B) and the first read transistor (M14) a source; wherein the first inverter and the second inverter are in interaction a coupling connection, that is, an output end of the first inverter (ie, the storage node A) is connected to an input end of the second inverter, and an output end of the second inverter (ie, the reverse phase storage Node B) is connected to the input end of the first inverter; and each control circuit (2) further comprises: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), and a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), and a tenth An NMOS transistor (M28), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), and an inverting write a control signal (/WC), a standby mode control signal (S), and an inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fourth NMOS transistor (M21) are respectively Connected to a ground voltage, the inverted standby mode control signal (/S) and the second low voltage node (VL2); the source, gate and drain of the fifth NMOS transistor (M22) are respectively connected to The first low voltage node (VL1), a standby mode control signal (S) and the second low voltage node (VL2); a source of the sixth NMOS transistor (M23) is connected to the ground voltage, and a gate is connected to the drain and connected to the gate a first low voltage node (VL1); a source, a gate and a drain of the seventh NMOS transistor (M24) are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal ( RC) and the second low voltage node (VL2); the source, the gate and the drain of the eighth NMOS transistor (M25) are respectively connected to the accelerated read voltage (RGND), the first delay circuit ( An output of D1) and a source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to an output of the third inverter (INV) and the eighth NMOS transistor (M25) Between the gates; the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the ninth NMOS a source, a gate and a drain of the transistor (M26) are respectively connected to the ground voltage, a drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the tenth NMOS Source of crystal (M27) a pole, a gate and a drain are respectively connected to the ground voltage, the standby mode control signal (S) and a gate of the ninth NMOS transistor (M26); a source of the eleventh NMOS transistor (M28) The gate and the drain are respectively connected to the inverted write control signal (/WC), the inverted standby mode control signal (/S) and the gate of the ninth NMOS transistor (M26); Note that the drain of the tenth NMOS transistor (M27), the drain of the eleventh NMOS transistor (M28), and the gate of the ninth NMOS transistor (M26) are connected together to form a gate. Node (C), when the standby mode control signal (S) is at a logic low level, the voltage level of the node (C) is the logic level of the inverted write control signal (/WC), and when the standby When the mode control signal (S) is logic high, the voltage level of the node (C) is the ground voltage, thereby having a stable standby mode (the voltage level of the node C is always the ground voltage during the write operation). ); in addition, the node (C) of the logic high level voltage line for power supply (V _DD) deduct the one eleventh NMOS transistor threshold voltage (M28) (V _TM28) of Pressing the level, so when the double-chip static random access memory is in the non-write mode (in this case, the inverted write control signal (/WC) is a logic high level), the node (C) is The power supply voltage (V _DD ) _deducts the voltage level of the threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28) instead of the voltage level of the power supply voltage (V _DD ). Having lower power consumption; and when subsequently entering the write mode (in this case, the inverted write control signal (/WC) is a logic low level), since it can be quickly stored in the node (C) The charge is discharged through the eleventh NMOS transistor (M28) to the ninth NMOS transistor (M26) sufficient to turn off the node (C) as a gate, so that the write mode can be entered relatively quickly; The read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent leakage current of the seventh NMOS transistor (M24) during the non-read mode; Furthermore, the standby starting circuit (4) is designed to be sent to the first low voltage node (VL1) during an initial period of entering the standby mode. Fast charging capacitor to the sixth NMOS transistor (M23) of the threshold voltage (V _TM23) voltage level; Finally, each of the high voltage level control circuit (5) further comprises: a fifth PMOS transistor (P51) a sixth PMOS transistor (P52) and a fourth inverter (I53), wherein the source, the gate and the drain of the fifth PMOS transistor (P51) are respectively connected to the power supply voltage (V) _DD ), the read control signal (RC) and the high voltage node (VH), the source, the gate and the drain of the sixth PMOS transistor (P52) are respectively connected to a high power supply voltage (HV _DD) The output of the fourth inverter (I63) is connected to the high voltage node (VH), and the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to The drain of the sixth PMOS transistor (P52). The double 埠 static random access memory according to claim 1, wherein the first NMOS transistor (M11) and the second NMOS transistor in each memory cell (1) M12) has the same channel aspect ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also have the same channel width to length ratio. The read control signal (RC) is a read enable (RE) signal and the corresponding read character, as claimed in claim 2, wherein the read control signal (RC) is a read enable (RE) signal. The result of the AND gate operation of the line (RWL) signal, that is, only when the read enable (RE) signal and the corresponding read word line (RWL) signal are both at a logic high level, the read Take the control signal (RC) side to the logic high level. The double-chip static random access memory according to claim 3, wherein each pre-charging circuit (3) is composed of a third PMOS transistor (P31) and a pre-charge signal (P). Wherein the source, the gate and the drain of the third PMOS transistor (P31) are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit a line (RBL) for precharging the corresponding read bit line (RBL) to the power supply voltage (V _DD ) by a logic low level precharge signal (P) during a precharge period ) The standard. The double-chip static random access memory according to claim 4, wherein the standby start circuit (4) is a fourth PMOS transistor (P41) and a twelfth NMOS transistor (M41). a second delay circuit (D2) and the inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fourth PMOS transistor (P41) are respectively connected to the power source a supply voltage (V _DD ), a reverse standby mode control signal (/S) and a drain of the eleventh NMOS transistor (M41); a source and a gate of the twelfth NMOS transistor (M41) The drain is connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fourth PMOS transistor (P41); the second delay circuit (D2) The input is coupled to the inverting standby mode control signal (/S), and the output of the second delay circuit (D2) is coupled to the gate of the twelfth NM]OS transistor (M41). The double-chip static random access memory according to claim 5, wherein the initial period of the standby start circuit (4) entering the standby mode is equal to the inverted standby mode control signal (/S) by logic The high level is converted to a logic low level, until the gate voltage of the twelfth NMOS transistor (M41) is sufficient to turn off the twelfth NMOS transistor (M41), which can be performed by the second delay circuit ( D2) One of the delay times provided to dynamically adjust. The double-click static random access memory according to claim 6, wherein the read operation system can be further subdivided into two stages, and the second stage of the read operation is performed by the second low The voltage node (VL2) is set to be lower than the ground voltage by the accelerated read voltage (RGND) to effectively increase the read speed, and in the second phase of the read operation by the second low voltage node ( VL2) Set back to this ground voltage to reduce unnecessary power consumption. The double 埠 static random access memory according to claim 7, wherein the time between the second phase of the read operation and the first phase is equal to the read control signal (RC) The logic low level transitions to a logic high level, until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), which can be performed by the third inverter ( One of the falling delay times of INV) is dynamically adjusted with a delay time provided by the first delay circuit (D1). The double-chip static random access memory according to claim 8, wherein the accelerated read voltage (RGND) in each control circuit (2) is set lower than each memory crystal. a threshold voltage (V _TM12 ) of the second NMOS transistor (M12) in the cell (1), and the level of the high power supply voltage (HV _DD ) is set higher than the power supply voltage (V _DD ) The level is lower than the sum of the power supply voltage (V _DD ) and the absolute value of the second PMOS transistor (P12) threshold voltage (V _TP12 ) (| V _TP12 |). The double-chip static random access memory according to claim 9, wherein the second low voltage node (VL2) reads the initial instantaneous voltage (V _RVL2I ) when reading logic 1 must satisfy the following equation : V _RVL2I = RGND × R _M21 / (R _M21 + R _M24 + R _M25 ) > -V _TM12 to effectively prevent half-selected cell disturbance when reading logic 1, where V _RVL2I indicates that the second low voltage node (VL2) reads the initial instantaneous voltage when reading logic 1, RGND indicates the accelerated read voltage, and R _M21 indicates the on-resistance of the fourth NMOS transistor (M21), R _M24 Indicates the on-resistance of the seventh NMOS transistor (M24), R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12).