TWI556239B - 7t dual port static random access memory (3) - Google Patents

Description

7T double-click static random access memory (3)

The invention relates to a 7T dual port static random access memory (SRAM), in particular to an effective improvement of the standby performance of the 7T dual-SRAM SRAM, and can effectively improve the reading speed and It effectively reduces the leakage current and can solve the 7T dual-SRAM SRAM which is difficult to write to the logic 1 with a single bit line.

As is shown in FIG. 1a, the static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of memory blocks (memory block, MB _1). , MB _{2 ,} etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL _{2 ,} etc.), each word line corresponding to a plurality of columns of memory One of the body cells; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _{m ,} etc.), each bit line pair corresponding to a plurality of rows of memory cells One row, and each bit line pair is composed of one bit line (BL ₁ ... BL _m ) and one complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b shows a 6T單埠 static random access memory (SRAM) cell A circuit diagram in which PMOS transistors (P1) and (P2) are called load transistors, NMOS transistors (M1) and (M2) are called driving transistors, and NMOS transistors ( M3) and (M4) are called access transistors, WL is a word line, and BL and BLB are bit lines and complementary bit lines, respectively. Since the 單埠SRAM cell requires six transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, the cell ratio) is usually set between 2.2 and 3.5, resulting in the presence of Difficulties in high concentration and high prices.

Figure 6b shows the 6T單埠 SRAM cell during write operation The HSPICE transient analysis simulation results, as shown in Figure 2, were simulated using TSMC 90 nm CMOS process parameters.

Used to reduce the number of transistors in a 6T static random access memory (SRAM) cell One way is disclosed in Figure 3. Figure 3 shows a circuit diagram of a 5T 單埠 SRAM cell with only a single bit line, compared to the 6T 單埠 SRAM cell of Figure 1b. The random access memory cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T單埠 SRAM cell does not change the PMOS transistors P1 and P2. And the channel width-to-length ratio of the NMOS transistors M1, M2, and M3 is relatively difficult to write logic 1 in the case of maintaining a static noise margin (SNM). Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 3 shows the HSPICE transient analysis simulation results of the 5T SRAM cell during write operation. As shown in Figure 4, it uses TSMC 90 nm CMOS. The process parameters are simulated. From the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.

Next, we will discuss the static random access memory (SRAM) and double truss. The 6T static random access memory (SRAM) cell of Figure 1b is an example of a static random access memory (SRAM) cell, which uses two bit lines BL and BLB for reading and writing. The action, that is, both reading and writing, is achieved through the same pair of bit lines, so that only reading or writing can be performed at the same time. Therefore, when designing a dual static with simultaneous literacy In random access memory, you need to add two access transistors and another pair of bit lines (please refer to the circuit shown in Figure 5, where WBL and WBLB are write bit line pairs, RBL and RBLB). For reading the bit line pair, WWL is the write word line, and RWL is the read word line), which greatly increases the area of the memory cell, if we can simplify the memory cell structure, One bit line is responsible for the reading action, and the other bit line is responsible for the writing action. When designing the double-click static random access memory, the memory cell does not need to add two transistors and a pair. The bit line, so that the area of the memory cell will be reduced a lot, the traditional double-twist static random The reason why the memory cell does not take this approach, it is quite difficult problem because writing a logic 1 is present as described above.

So far, there are many 7T double-static static random access memories with a single bit line. The technology of the unit cell is proposed, for example, "Double-埠 Static Random Access Memory" proposed in Patent Document 1 (TWI441178, June 11, 103), Patent Document 2 (TWI441179, June 11, 103) "Independently-controlled-gate SRAM" proposed in the patent document 3 (US Pat. No. 8717807 B2, May 6, 103), Patent Document 4 (April 1, 103, 1st) "7T double 埠SRAM" proposed by TWI433152), "Protection of double 埠 static random storage with discharge path" proposed in Patent Document 5 (TWI425509, February 1, 103) "Responsive memory", Patent Document 6 (TWI 423257, January 11, 103), "Double-埠 SRAM for reducing power supply voltage during write operation", Patent Document 7 (TWI 423258, January 11, 103) The proposed "double-click static random access memory for increasing the voltage level of the write word line during the write operation", Patent Document 8 (TWI399748, June 21, 102), Patent Document 9 (98) "SVEN cell with independent static noise margin, trip voltage, and" proposed by "SEVEN TRANSISTOR SRAM CELL", No. US20090161410 A1, June 22, and Patent Document 10 (No. US7385840 B2, June 10, 1997) "reading current optimization" and "Ultra high-speed DDP-SRAM cache" proposed in Patent Document 11 (US Pat. No. 6,751,511 B2, June 15, 1993), although these patents can effectively solve the problem of writing logic 1 difficult, Since these patents do not take into account the problem of reduced reading speed when the 45 nm operating voltage is reduced to 1.1 ± 30%, there is still room for improvement.

In view of this, the main object of the present invention is to propose a 7T double-cylinder static random storage. The memory is taken, which can effectively increase the reading speed by controlling the circuit.

A secondary object of the present invention is to provide a 7T double-twist static random access memory, The two-stage read control can be used to increase the reading speed while avoiding unnecessary power consumption.

A further object of the present invention is to provide a 7T double-twist static random access memory, The standby start circuit can effectively cause the SRAM to quickly enter the standby mode, thereby effectively improving the standby performance of the SRAM.

Another object of the present invention is to provide a 7T double-twist static random access memory, The leakage current can be effectively reduced by the control circuit to effectively reduce the standby mode.

The invention provides a 7T double-twist static random access memory, which mainly comprises a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby start circuit (4), wherein the memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory Formed by a unit cell, each column of memory cells is provided with a control circuit, and each memory cell (1) includes a first inverter (from a first PMOS transistor P11 and a first NMOS transistor) M11 is composed of a second inverter (composed of a second PMOS transistor P12 and a second NMOS transistor M12), an access transistor (composed of a third NMOS transistor M13), and a The first read transistor (M14) and the second read transistor (M15). Each control unit (2) is connected to a source of the first NMOS transistor (M11) of each memory cell of the corresponding column memory cell and a source of the second NMOS transistor (M12) In order to control the source voltage of the first NMOS transistor (M11) and the source voltage of the second NMOS transistor (M12) in response to different operation modes, thereby effectively preventing the write logic in the write mode 1 difficult problem, in the read mode, can improve the reading speed, but also avoid unnecessary power consumption, in the standby mode, can effectively reduce the leakage current, while maintaining the original electrical mode characteristic. Furthermore, the standby start circuit (4) is designed to effectively cause the 7T dual-static SRAM to quickly enter the standby mode, thereby effectively improving the standby performance of the 7T dual-static SRAM.

BLB ₁ ^... BLB _m ‧‧‧complementary bit line

BLB‧‧‧complementary bit line

MB ₁ ^... MB _k ‧‧‧ memory block

WL ₁ ^... WL _n ‧‧‧ wordline

BL ₁ ^... BL _m ‧‧‧ bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

V _DD ‧‧‧Power supply voltage

M14‧‧‧First read transistor

M15‧‧‧Second reading transistor

S‧‧‧Standby mode control signal

/S ‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

WC‧‧‧ write control signal

/WC‧‧‧Inverted write control signal

C‧‧‧ node

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

M41‧‧‧12th NMOS transistor

P41‧‧‧4th PMOS transistor

D2‧‧‧second delay circuit

WBL‧‧‧Write bit line

WWL‧‧‧write word line

RBL‧‧‧Reading bit line

RWL‧‧‧Read word line

GND‧‧‧ Grounding voltage

Figure 1a shows a conventional static random access memory; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; and Fig. 2 shows a conventional 6T static random access memory cell. Write action timing diagram; 3 is a circuit diagram showing a conventional 5T static random access memory cell; FIG. 4 is a timing chart showing a write operation of a conventional 5T static random access memory cell; FIG. 5 is a conventional display FIG. 6 is a schematic circuit diagram of a preferred embodiment of the present invention; FIG. 7 is a circuit diagram showing a preferred embodiment of the present invention in FIG. Simplified circuit diagram during logic 1; Fig. 8 is a timing chart showing the write operation of the preferred embodiment of the invention in Fig. 6; and Fig. 9 is a simplified view showing the preferred embodiment of the invention in Fig. 6 during reading BRIEF DESCRIPTION OF THE DRAWINGS Fig. 10 is a simplified circuit diagram showing a preferred embodiment of the present invention in FIG. 6 during standby.

According to the above main object, the present invention provides a 7T binary anti-static random access memory, which mainly comprises a memory array, which is composed of a plurality of memory cells and a plurality of memory cells. Each column of memory cells and each row of memory cells includes a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a charging circuit (3), each row of memory cells is provided with a pre-charging circuit (3); and a standby starting circuit (4), which causes the 7T dual-SRAM to quickly enter the standby mode to effectively improve 7T dual-chip SRAM standby performance.

For convenience of explanation, the 7T double-chip static random access memory shown in FIG. 6 has only one memory cell (1), one write word line (WWL), and one write bit line. (WBL), a read word line (RWL), a read bit line (RBL), a control circuit (2), a precharge circuit (3), and a standby start circuit (4) as The embodiment is explained. The memory cell (1) includes a first inverter (by a first PMOS transistor) P11 is composed of a first NMOS transistor M11, a second inverter (composed of a second PMOS transistor P12 and a second NMOS transistor M12), a third NMOS transistor (M13), a first read transistor (M14) and a second read transistor (M15), wherein the first inverter and the second inverter are connected in an alternating manner, that is, the first The output of the inverter (ie node A) is connected to the input of the second inverter, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the first The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell.

The memory cell (1) of the first inverter (by the first PMOS transistor P11 composed of the first NMOS transistor M11) is connected to a system power supply voltage (V _DD) and a first Between the low voltage nodes (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected to the power supply voltage (V _DD ) and a second Between the low voltage nodes (VL2), the source, the gate and the drain of the first read transistor (M14) are respectively connected to the drain of the second read transistor (M15), the read The word line (RWL) and the read bit line (RBL) are taken, and the source, the gate and the drain of the second read transistor (M15) are respectively connected to the second low voltage node. (VL2), the output of the second inverter (node B) and the source of the first read transistor (M14).

Referring again to FIG. 6, the control circuit (2) is composed of a fourth NMOS transistor. (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), and a ninth NMOS transistor. (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control signal (RC), a third inverter (INV), a first delay Circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), an inverted write control signal (/WC), a standby mode control signal (S), and an inverted standby mode control The signal (/S) is composed of. a source, a gate and a drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the reverse standby mode control signal (/S) and the second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) The gate and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); the eighth NMOS transistor (M25) a source, a gate and a drain are respectively connected to the accelerated read voltage (RGND), an output of the first delay circuit (D1), and a source of the seventh NMOS transistor (M24); the first a delay circuit (D1) is coupled between an output of the third inverter (INV) and a gate of the eighth NMOS transistor (M25); an input of the third inverter (INV) is for receiving the Read control signal ( RC), and the output is connected to the input of the first delay circuit (D1); the source, the gate and the drain of the ninth NMOS transistor (M26) are respectively connected to a ground voltage, the tenth NMOS transistor a drain of (M27) and the first low voltage node (VL1); a source, a gate and a drain of the tenth NMOS transistor (M27) are respectively connected to the inverted standby mode control signal (/S) The inverted write control signal (/WC) and the gate of the ninth NMOS transistor (M26); and the source, the gate and the drain of the eleventh NMOS transistor (M28) are respectively connected to The standby mode control signal (S), the write control signal (WC), and the drain of the tenth NMOS transistor (M27). It is worth noting here that the inverted standby mode control signal (/S) and the inverted write The control signal (/WC) is obtained by each of the standby mode control signal (S) and the write control signal (WC) via an inverter.

The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage of the driving transistor (ie, the first NMOS transistor M11) closer to the writing bit line (WBL) is set to be higher than the ground voltage. Predetermining a voltage (ie, a gate-source voltage V _{GS (M23) of} the sixth NMOS transistor (M23)) and selecting a source voltage of another driving transistor (ie, the second NMOS transistor M12) in the selected cell ( That is, the second low voltage node VL2) is set to the ground voltage in order to prevent the problem of writing logic 1 difficult.

In the first phase of the read mode, the selected cell is closer to the read bit The source voltage of the driving transistor of the line (RBL) (ie, the second NMOS transistor M12) (ie, the second low voltage node VL2) is set to be the accelerated reading voltage (RGND) lower than the ground voltage, The accelerated read voltage (RGND), which is lower than the ground voltage, can effectively increase the read speed, and in the second stage of the read mode, the selected cell is closer to the read bit line (RBL). The source voltage of the driving transistor (ie, the second NMOS transistor M12) is set back to the ground voltage to reduce unnecessary power consumption, wherein the second phase of the read mode is separated from the first phase by The read control signal (RC) is converted from a logic low level to a logic high level, and until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), The value can be adjusted by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1).

In standby mode, the source voltage of the drive transistor in all memory cells The predetermined voltage is set higher than the ground voltage to reduce the leakage current; and in the hold mode, the source voltage of the driving transistor in the memory cell is set to the ground voltage, so as to maintain the original retention characteristic, the details thereof The working voltage level is shown in Table 1.

The write control signal (WC) in Table 1 is a write enable (Write) Enable, abbreviated as WE) signal and the AND gate operation result of the corresponding write word line (WWL) signal, at this time only the write enable (WE) signal and the corresponding write word The signal line (WWL) is a logic high level, and the write control signal (WC) is a logic high level; the read control signal (RC) is a read enable (RE) signal and corresponding The result of the gate operation of the read word line (RWL) signal. It is worth noting here that the unselected word line and the unselected positioning element line are set to a floating state, and the read control signal (RC) is set to the acceleration during the non-read mode. The level of the read voltage (RGND) is read to prevent leakage current of the seventh NMOS transistor (M24).

Referring to FIG. 6, the precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P). The source and gate of the third PMOS transistor (P31) And the drain system are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit line (RBL), so as to be in a logic low level during precharge Precharge signal (P) to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V _DD ).

Referring to FIG. 6, the standby starting circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2), and the reverse standby. The mode control signal (/S) is composed of. a source, a gate and a drain of the fourth PMOS transistor (P41) are respectively connected to the power supply voltage (V _DD ), the inverted standby mode control signal (/S) and the twelfth NMOS transistor a drain of (M41); a source, a gate and a drain of the twelfth NMOS transistor (M41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) And a drain of the fourth PMOS transistor (P41); an input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and an output of the second delay circuit (D2) is Connected to the gate of the twelfth NMOS transistor (M41).

The working principle of the preferred embodiment of the present invention in the sixth diagram is as follows:

(I) write mode

Before the start of the write operation, the standby mode control signal (S) and the write control signal (WC) are at a logic low level, such that the tenth NMOS transistor (M27) is turned "ON" and the eleventh is made The NMOS transistor (M28) is turned off (OFF), so that the drain of the tenth NMOS transistor (M27) is at a logic high level, and the logic high level is the drain of the tenth NMOS transistor (M27) The ninth NMOS transistor (M26) is turned on, and the first low voltage node (VL1) is grounded.

During the write operation period, the standby mode control signal (S) is a logic low level and the write control signal (WC) is a logic high level, so that the eleventh NMOS transistor (M28) is turned into a logic a low level, the logic low level of the eleventh NMOS transistor (M28) of the drain causes the ninth NMOS transistor (M26) to be turned off, and the first low voltage node (VL1) is equal to the sixth NMOS The gate-source voltage V _{GS (M23) of the} transistor (M23) is thereby effectively prevented from being difficult to write to the logic 1. Figure 7 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 6 during writing.

Next, how the write operation of the preferred embodiment of the present invention in FIG. 7 is completed depends on the four write states of the SRAM.

(1) Node A originally stores a logic 0, and now wants to write a logic 0: before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M11) is turned on ( ON). Since the first NMOS transistor (M11) is ON, the write word line (WWL) is turned from Low (ground voltage) to High (power supply voltage V _DD ) when the write operation starts. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned off (OFF) To be ON, at this time, since the write bit line (WBL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle.

(2) Node A originally stores a logic 0, and now wants to write a logic 1: before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M11) is turned on ( ON). It is worth noting here that since the first NMOS transistor (M11) is ON, when the write operation starts, the write word line (WWL) is turned from Low (ground voltage) to High (the power supply) Voltage V _DD ), the voltage of this node A will slightly increase with the voltage following the write word line (WWL) due to the parasitic capacitance coupling effect.

When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON. Because the write bit line (WBL) is High (the power supply voltage V _DD ), and because the first NMOS transistor (M11) is still ON and the node B is still at a voltage level close to the The initial state of the voltage level of the power supply voltage (V _DD ), so the first PMOS transistor (P11) is still off (OFF), and the node A is quickly charged toward a divided voltage level, the partial voltage The voltage level is equal to (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 ) multiplied by the power supply voltage (V _DD ), wherein the R _M13 represents the conduction of the third NMOS transistor (M13), etc. The effective resistance, the R _M11 represents the on-resistance equivalent resistance of the first NMOS transistor (M11), and the R _M23 represents the on-resistance equivalent resistance of the sixth NMOS transistor (M23), at this time because of the third NMOS transistor (M13) still operates in the saturation region and the first NMOS transistor (M11) still operates in the triode region, although the third NMOS transistor (M13) is turned on equivalently (R _M13) is considerably greater than the first NMOS transistor (M11) is turned the equivalent resistance (R _M11), but since the sixth NMOS transistor (M23) diodes is connected as a system, it is possible in the first A voltage level equal to the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23) is provided at the low voltage node (VL1), and the voltage voltage level presented by the node A is the voltage. The value will be much higher than the voltage level of the node A of the conventional 5T SRAM cell of Figure 4. The much higher voltage division voltage level is sufficient to turn on the second NMOS transistor (M12), thus causing the node B to discharge to a lower voltage level, and the lower voltage level of the node B causes the first The on-resistance equivalent (R _M11 ) of an NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) obtains a higher voltage level at the node A. The higher voltage level of the node A is again caused by the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level. The lower voltage level of the node B is again passed through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level. In this cycle, the node A can be charged to the power supply voltage (V _DD ), and the logic 1 write operation is completed.

It should be noted here that the first low voltage node VL1 originally stores a logic 0 at the node A, and has a gate source voltage V _GS equal to the sixth NMOS transistor (M23) while the logic 1 is being written. The voltage level of _(M23) , after writing logic 1, will have the level of the ground voltage due to discharge through the ninth NMOS transistor (M26).

(3) Node A originally stores logic 1, and now wants to write logic 1: Before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor (P11) is turned on ( ON). When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the write word line (WWL) is greater than the third NMOS transistor (M13) When the threshold voltage is applied, the third NMOS transistor (M13) is turned from OFF to ON; at this time, since the write bit line (WBL) is High (the power supply voltage V _DD ) And because the first PMOS transistor (P11) is still ON, the voltage of the node A is maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stores logic 1, and now wants to write logic 0: before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor (P11) is turned on ( ON). When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the write word line (WWL) is greater than the third NMOS transistor (M13) When the threshold voltage is applied, the third NMOS transistor (M13) is turned from OFF to ON. At this time, since the write bit line (WBL) is Low (ground voltage), The node A and the first low voltage node (VL1) are discharged to complete the logic 0 write operation until the end of the write cycle.

In the preferred embodiment of the present invention shown in FIG. 7, the HSPICE transient analysis simulation result at the time of the write operation is as shown in FIG. 8, which is simulated using the TSMC 90 nm CMOS process parameters, from which the simulation result is obtained. It can be confirmed that the 7T double-chip static random access memory proposed by the present invention can improve the voltage level of the first low voltage node (VL1) during the writing period, thereby effectively avoiding the conventional single bit line. It is quite difficult to write a logic 1 in a double-埠 static random access memory cell.

(II) Read mode (read mode)

The read control signal (RC), the write control signal (WC), and the wait before the start of the read operation The machine mode control signal (S) is at a logic low level, such that the tenth NMOS transistor (M27) is turned on, and the eleventh NMOS transistor (M28) is turned off, so that the tenth NMOS transistor (M27) The drain is at a logic high level, and the drain of the tenth NMOS transistor (M27) of the logic high level turns on the ninth NMOS transistor (M26), and causes the first low voltage node (VL1) to be grounded. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned "ON".

It is worth noting here that during pre-charging before the start of the read operation, the pre-charge signal (P) is at a logic low level, thereby pre-charging the corresponding read bit line (RBL) to The power supply voltage (V _DD ) is level, but the operating voltage of the process technology such as 45 nm or less will be reduced to 1.1 ± 30% or less, which will cause the reading speed to be lowered to meet the specification problem. The present invention proposes a two-stage read control to improve read speed and meet specifications while avoiding unnecessary power consumption.

The preferred embodiment of the invention illustrated in Figure 6 is controlled by two stages of read control. In order to improve the reading speed, the unnecessary power consumption is also avoided. In the first stage of the reading operation, the read control signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on due to At this time, the eighth NMOS transistor (M25) is still turned on, and then the second low voltage node (VL2) is at an accelerated read voltage (RGND) lower than the ground voltage, and the accelerated read voltage is lower than the ground voltage. Taking the voltage (RGND) can effectively improve the reading speed.

In the second phase of the read operation, although the read control signal (RC) is still logic The high level is such that the seventh NMOS transistor (M24) is still turned on, but since the eighth NMOS transistor (M25) is turned off at this time, the second low voltage node (VL2) is turned on. The fourth NMOS transistor (M21) is grounded (since the inverted standby mode control signal (/S) is at a logic high level during the read operation), thereby effectively reducing unnecessary power consumption. It is worth noting here that the second phase of the read operation is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the The gate voltage of the eight NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), and the value thereof can be decreased by the delay time of the third inverter (INV) and the first delay circuit. (D1) The delay time provided is adjusted. Furthermore, the fourth NMOS transistor (M21) is in an on state regardless of the first phase of the read operation or the second phase (due to the inverted standby mode control signal (/S) being logic during the read operation High level). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 6 during reading.

(III) Standby mode

First, how the standby start circuit (4) of Fig. 6 causes the 單埠SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: (1) the reverse standby mode control signal (/S) before entering the standby mode. Is logic High, the logic high inversion standby mode control signal (/S) causes the fourth PMOS transistor (P41) to be turned off (OFF), and causes the twelfth NMOS transistor (M41) to be turned on (ON) (2) After entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fourth PMOS transistor (P41) Turned on (ON), but during the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from logic High to logic Low, to the twelfth NMOS transistor (M41) The gate voltage is sufficient to turn off the twelfth NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2), the twelfth NMOS transistor ( M41) is still turned on (ON), so the first low voltage node (VL1) can be quickly charged to reach the sixth NMOS transistor (M2) 3) The voltage level of the threshold voltage (V _TM23 ), that is, the 7T dual-turn SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (M41) is turned off and the supply current is stopped.

Please refer to FIG. 6 . In the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (M21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (M22) is turned on (ON), and the fifth NMOS transistor (M22) is used as an equalizer, so that the fifth NMOS transistor (M22) in an on state can be used. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V _TM23 ). Figure 10 is a simplified circuit diagram of the preferred embodiment of the present invention in Figure 6 during standby.

Next, how to reduce leakage current in the standby mode of the present invention is described. Referring to FIG. 10, FIG. 10 depicts a leakage current I ₁ generated when the embodiment of the present invention is in the standby mode. I ₂ , I ₃ , I ₄ , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage is due to the standby mode) The voltage level of the node (VL2) is maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so the voltage level of the node A is the logic Low and the voltage of the V _TM23 is also maintained. The level of the output of the second inverter (ie, node B) is a logic high (power supply voltage V _DD ). Please refer to the conventional 8T dual-SRAM SRAM of FIG. 5 and the embodiment of the present invention of FIG. 10 to illustrate the leakage current of the 7T dual-static static random access memory proposed by the present invention and the conventional 8T dual-turn SRAM of FIG. In comparison, firstly, regarding the leakage current I ₁ flowing through the third NMOS transistor (M13), since the voltage level of the node A in the standby mode is maintained at the voltage level of the V _TM23 , and the The write word line (WWL) is set to the ground voltage in the standby mode, and the write bit line (WBL) is set to the power supply voltage (V _DD ) in the standby mode, so the present invention The gate-source voltage (V _GS ) of the third NMOS transistor (M13) is a negative value, and the gate-source voltage of the NMOS transistor (M3) of the conventional 8T dual-SRAM SRAM of FIG. 5 in the standby mode (V _GS) ) is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect or the results of Figures 3 (A) and 3 (B) of US Pat. No. 6,865,119, March 8, 2005, for NMOS In the case of a transistor, the subcritical current when the gate source voltage is -0.1 volt is about 1% of the subcritical current when the gate source voltage is 0 volts. Therefore, the leakage current I ₁ of the third NMOS transistor (M13) flowing through the present invention caused by the GIDL effect is much smaller than that of the conventional 8T double-SRAM NMOS transistor (M3) of FIG. 5; The 汲 source voltage (V _DS ) of the third NMOS transistor (M13) of the present invention _deducts the voltage level of the V _TM23 from the power supply voltage (V _DD ), and the conventional 8T double 第 in FIG. 5 The 汲 source voltage (V _DS ) of the SRAM NMOS transistor (M3) is equal to the power supply voltage (V _DD ), which is based on the Drain-Induced Barrier Lowering (DIBL) effect due to the DIBL effect. The induced leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention is also smaller than the NMOS transistor (M3) of the conventional 8T double-turn SRAM of FIG. 5; as a result, the third of the present invention flows through The leakage current I _{1 of the} NMOS transistor (M13) is much smaller than that of the conventional 8T double-SRAM NMOS transistor (M3) of FIG.

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) due to the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the _VTM23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V _{DD ) Deducting} the voltage level of the V _TM23 , the source drain voltage (V _SD ) of the PMOS transistor (P1) of the conventional 8T dual-SRAM SRAM of FIG. 5 is equal to the power supply voltage (V _DD ), according to The DIBL effect, therefore, the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P1) of Figure 1b.

Then, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the _VTM23 due to the standby mode, node A The voltage level is also maintained at the voltage level of the V _TM23 , and the voltage level of the node B is equal to the power supply voltage (V _DD ) and the base of the second NMOS transistor (M12) is the ground voltage, so The base-source voltage (V _BS ) of the second NMOS transistor (M12) of the invention is a negative value, and the 汲 source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V) _DD ) deducting the voltage level of the V _TM23 , and the base-source voltage (V _BS ) of the NMOS transistor (M2) of the conventional 8T double-turn SRAM of FIG. 5 is equal to 0, and the NMOS transistor (M2) The source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and the DIBL effect, the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than Figure 5 is a conventional 8T dual-SRAM NMOS transistor (M2).

Finally, regarding the leakage current I ₄ flowing through the first read transistor (M14), since the present invention is different from the conventional 8T dual-SRAM SRAM of FIG. 5, and reading in the standby mode of the present invention The bit line (RBL) can be set to the ground voltage, and the conventional 8T double-turn SRAM of FIG. 5 is used to prevent the voltage level of the node B from falling. The read bit line pair (RBL, RBLB) in the standby mode is Since the power supply voltage is set, it is not possible to compare the leakage current I ₄ flowing through the first read transistor (M14). Based on the above analysis, the 7T dual-static SRAM of the present invention has a lower leakage current than the conventional 8T dual-SRAM SRAM of FIG.

(IV) hold mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to ground voltage, the working principle is the same as that of the conventional double-bit SRAM cell with a single bit line. No longer said.

【Effects of invention】

The 7T double-click static random access memory proposed by the invention has the following effects:

(1) High read speed and avoiding unnecessary power consumption: The 7T dual-static static random access memory system proposed by the present invention employs a two-stage read operation, in the first stage of the read operation, by the second low The voltage node (VL2) is set to be lower than the ground voltage by the accelerated read voltage (RGND) to effectively increase the read speed, and in the second phase of the read operation by the second low voltage node (VL2) Set back to ground voltage to reduce unnecessary power consumption;

(2) Quick entry standby mode: Since the 7T dual-static SRAM (s) proposed by the present invention is provided with a standby start circuit (4) to prompt the SRAM to quickly enter the standby mode, and thereby seek to improve the 7T dual-SRAM Standby performance

(3) The problem of avoiding the difficulty of writing logic 1: The 7T dual-static static random access memory proposed by the present invention can improve the voltage level of the first low voltage node (VL1) during the write operation. Effectively avoiding the problem that it is quite difficult to write a logic 1 with a double-bit SRAM with a single bit line;

(4) Low standby current: the 7T dual-static static random access memory proposed by the present invention is in standby In the mode, the fifth NMOS transistor (M22) in an on state can be made such that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2). And making the voltage levels equal to the level of the threshold voltage of the sixth NMOS transistor (M23), so the 7T dual-static SRAM of the present invention also has the effect of low standby current;

(5) Effectively reducing the half-selected cell interference: the 7T double-chip static random access memory proposed by the present invention uses a separate read/write path, and the read path is designed to be the first and second read A transistor (M14 and M15) is connected in series between the read bit line (RBL) and the second low voltage node (VL2), and the inverting storage node (B) is connected to the second Reading the gate of the transistor (M15), thus effectively reducing the half-selected cell disturbance, wherein the half-selected cell means is selected by the read word line (RWL) but not A unit cell selected by the read bit line (RBL).

(6) Low number of transistors: For an SRAM array having 1024 columns and 1024 rows, the 8T dual-SRAM array of the conventional FIG. 5 requires a total of 1024×1024×8=8,388,608 transistors, and the 7T proposed by the present invention The double-埠 static random access memory requires only at least 1024 × 1024 × 7 + 1024 × 18 + 6 = 7,358,470 transistors, which reduces the number of transistors by 12.3%.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

V _DD ‧‧‧Power supply voltage

M14‧‧‧First read transistor

M15‧‧‧Second reading transistor

WBL‧‧‧Write bit line

WWL‧‧‧write word line

RBL‧‧‧Reading bit line

RWL‧‧‧Read word line

S‧‧‧Standby mode control signal

/S ‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

WC‧‧‧ write control signal

/WC‧‧‧Inverted write control signal

C‧‧‧ node

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

M41‧‧‧12th NMOS transistor

P41‧‧‧4th PMOS transistor

D2‧‧‧second delay circuit

GND‧‧‧ Grounding voltage

Claims (9)

A 7T double-click static random access memory, comprising: a memory array, the memory array is composed of a plurality of memory cells and a plurality of memory cells, each column of memory cells and each row of memory The body cells each comprise a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory The unit cell is provided with a pre-charging circuit (3); and a standby starting circuit (4) for causing the dual-static static random access memory to quickly enter the standby mode to effectively improve the static state The standby performance of the random access memory; wherein each memory cell (1) further comprises: a first inverter, comprising a first PMOS transistor (P11) and a first NMOS transistor (M11) The first inverter is connected between a power supply voltage (V _DD ) and a first low voltage node (VL1); and a second inverter is connected by a second PMOS transistor ( P12) is composed of a second NMOS transistor (M12) connected to the power supply Voltage (V _DD) between the node and a second low voltage (VL2); a storage node (A), is formed out of an output terminal of the first inverter; inverting a storage node (B), by the Department of Forming an output of the second inverter; a third NMOS transistor (M13) is connected between the storage node (A) and a corresponding write bit line (WBL), and the gate Connected to a corresponding write word line (WWL); a first read transistor (M14), the source, gate and drain of the first read transistor (M14) are respectively connected a drain of a second read transistor (M15), a read word line (RWL) and a read bit line (RBL); and the second read transistor (M15) The source, the gate and the drain of the second read transistor (M15) are respectively connected to the second low voltage node (VL2), the inverted storage node (B) and the first read a source of the transistor (M14); wherein the first inverter and the second inverter are connected in an alternating coupling manner, that is, an output end of the first inverter (ie, the storage node A) is connected To the input of the second inverter, and the input of the second inverter The end (ie, the inverting storage node B) is connected to the input end of the first inverter; and each control circuit (2) further comprises: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), and a tenth NMOS transistor. (M27), an eleventh NMOS transistor (M28), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), and an accelerated read voltage (RGND) a write control signal (WC), an inverted write control signal (/WC), a standby mode control signal (S), and an inverted standby mode control signal (/S); wherein the fourth NMOS The source, the gate and the drain of the transistor (M21) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and the second low voltage node (VL2); the fifth NMOS transistor a source, a gate and a drain of (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); the sixth NMOS The source of the crystal (M23) is connected to the connection a ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); the source, the gate and the drain of the seventh NMOS transistor (M24) are respectively connected to the eighth a drain of the NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); the source, the gate and the drain of the eighth NMOS transistor (M25) are respectively connected Up to the accelerated read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to the third inversion The output of the inverter (INV) is between the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to An input of the first delay circuit (D1); a source, a gate and a drain of the ninth NMOS transistor (M26) are respectively connected to the ground voltage, and a drain of the tenth NMOS transistor (M27) The first low voltage node (VL1); the source, the gate and the drain of the tenth NMOS transistor (M27) are respectively connected to the inverted standby mode control signal (/S), and the inverted write control Signal (/WC) and the first a gate of a nine-NMOS transistor (M26); a source, a gate and a drain of the eleventh NMOS transistor (M28) are respectively connected to the standby mode control signal (S) and a write control signal (WC) And a drain of the tenth NMOS transistor (M27); wherein the read control signal (RC) during the non-read mode is set to a level of the accelerated read voltage (RGND) to prevent the first The leakage current of the seven NMOS transistors (M24) during the non-read mode; further, the standby start circuit (4) is designed to enter the standby mode during one of the initial periods, the first low voltage node (VL1) The parasitic capacitance at the point is quickly charged to the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23). The 7T dual-static SRAM according to claim 1, wherein the inverted standby mode control signal (/S) and the inverted write control signal (/WC) are in the standby mode. The control signal (S) and the write control signal (WC) are each obtained via an inverter. The write control signal (WC) is a write enable (WE) signal and the corresponding write word, as in the 7T dual-static SRAM described in claim 2 of the patent application. The result of the AND gate operation of the line (WWL) signal, that is, only when the write enable (WE) signal and the corresponding write word line (WWL) signal are both at a logic high level, The write control signal (WC) is at a logic high level. The read control signal (RC) is a read enable (RE) signal and the corresponding read word, as in the 7T dual-static static random access memory according to claim 3 of the patent application. The result of the AND gate operation of the line (RWL) signal, that is, only when the read enable (RE) signal and the corresponding read word line (RWL) signal are both at a logic high level, The read control signal (RC) is at a logic high level. The 7T dual-static SRAM according to claim 4, wherein each pre-charging circuit (3) is composed of a third PMOS transistor (P31) and a pre-charging signal (P). The source, the gate and the drain of the third PMOS transistor (P31) are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit a line (RBL) for precharging the corresponding read bit line (RBL) to the power supply voltage (V) by a logic low level (P) during a precharge period _{The level of DD} ). The 7T dual-static SRAM according to claim 5, wherein the standby starting circuit (4) is a fourth PMOS transistor (P41) and a twelfth NMOS transistor (M41). a second delay circuit (D2) and the inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fourth PMOS transistor (P41) are respectively connected to the a power supply voltage (V _DD ), the reverse standby mode control signal (/S) and a drain of the twelfth NMOS transistor (M41); a source and a gate of the twelfth NMOS transistor (M41) And the drain circuit is respectively connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fourth PMOS transistor (P41); the second delay circuit (D2) The input is connected to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) is connected to the gate of the twelfth NMOS transistor (M41). The 7T dual-static SRAM according to claim 6, wherein the initial period of the standby start circuit (4) entering the standby mode is equal to the inverted standby mode control signal (/S) The logic high level transitions to a logic low level, until the gate voltage of the twelfth NMOS transistor (M41) is sufficient to turn off the twelfth NMOS transistor (M41), which can be used by the second delay circuit (D2) One of the delay times provided to adjust. The 7T dual-static SRAM according to claim 7, wherein the read operation can be subdivided into two stages, and the second stage of the read operation is performed by the second The low voltage node (VL2) is set to the accelerated read voltage (RGND) lower than the ground voltage to effectively increase the read speed, and in the second phase of the read operation, the second low voltage node is (VL2) Set back to this ground voltage to reduce unnecessary power consumption. The 7T dual-static SRAM according to claim 8, wherein the second phase of the read operation is equal to the read control signal (RC). From the logic low level to the logic high level, until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), which can be used by the third inverter One of the (INV) falling delay times and the first delay circuit (D1) One delay time to adjust.