TW202004761A - Seven-transistor dual port static random access memory with fast read/write speed - Google Patents

Abstract

The present invention provides a 7T (seven-transistor) dual port static random access memory with fast read/write speed, which comprises a memory array (1), a plurality of control circuits (2), a plurality of pre-charge circuits (3), a standby start-up circuit (4), a plurality of high voltage level control circuits (5), a plurality of writing word line control circuits (6), and a plurality of reading word line control circuits (7). Therefore, in a writing mode, the plurality of control circuits (2) and the plurality of writing word line control circuits (6) can be combined to avoid difficulty in writing logic 1, and also effectively improve the writing speed. In a reading mode, the plurality of control circuits (2), the plurality of high voltage level control circuits (5) and the plurality of reading word line control circuits (7) are combined to increase the reading speed while avoiding unnecessary power consumption.

Description

7T dual-port static random access memory with high read/write speed

The present invention relates to a 7T dual port Static Random Access Memory (SRAM) with high read/write speed, in particular, it effectively improves the standby performance of 7T SRAM and can Effectively improve the read speed and write speed, and can effectively reduce leakage current (leakage current), reduce the semi-selected cell interference during reading and avoid unnecessary power consumption of SRAM.

The conventional static random access memory (SRAM) is shown in Figure 1a, which mainly includes a memory array. The memory array is composed of a plurality of memory blocks (memory block, MB ₁ , MB ₂ etc.), each memory block is further composed of a plurality of rows of memory cells and a plurality of rows of memory cells, Each row of memory cells and each row of memory cells includes a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL ₂ etc.), each word line corresponds to a plurality of row memory One row in the unit cell; and plural bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _m, etc.), each bit line pair corresponds to the plural row memory cell One row, and each bit line pair is composed of a bit line (BL ₁ ... BL _m ) and a complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b shows the circuit schematic diagram of the 6T SRAM cell, where PMOS transistors (P1) and (P2) are called load transistors and NMOS transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL And BLB are bit line and complementary bit line, because the SRAM cell of this port requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) The other driving transistor is turned on, and the initial voltage (V _AR ) of node A must meet the equation (1): V _AR = V _DD × (R _M1 )/(R _M1 + R _M3 )<V _TM2 (1) to prevent half-selected cell disturbance during reading, where V _AR represents the initial instantaneous voltage of reading at node A, and R _M1 and R _M3 respectively represent the NMOS transistor (M1 ) And the on-resistance of the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply voltage and the threshold voltage of the NMOS transistor (M2), which results in the current between the driving transistor and the access transistor The drive capability ratio (ie, cell ratio) is usually set between 2.2 and 3.5 (please refer to the second column of US76060B2 Patent Specification No. US76060B2, 1998, lines 8-10).

Figure 1b shows the HSPICE transient analysis simulation results of the 6T-port static random access memory cell during a write operation. As shown in Figure 2, it is simulated using TSMC90 nanometer CMOS process parameters.

One way to reduce the number of transistors in the 6T static random access memory (SRAM) cell is shown in Figure 3. Figure 3 shows a schematic circuit diagram of a 5T static random access memory cell with only a single bit line. Compared with the 6T static random access memory cell of Figure 1b, this 5T static The random access memory cell has one transistor and one bit line less than that of the 6T static random access memory cell, but the 5T static random access memory cell does not change the PMOS transistors P1 and P2 And in the case of the channel width-to-length ratio of NMOS transistors M1, M2, and M3, there is a problem that it is quite difficult to write logic 1. Consider the case where the node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transferred from the bit line (BL), the logic 0 previously written in node A is overwritten by the logic 1 The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 )/(R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of node A, R _M1 and R _M3 represent the on-resistance of NMOS transistor (M1) and NMOS transistor (M3) respectively. Comparing equation (1) and equation (2), we can see that the initial instantaneous voltage (V _AW ) is less than that of NMOS transistor (M2) ) Of the threshold voltage (V _TM2 ), so the operation of writing logic 1 cannot be completed. The simulation results of the HSPICE transient analysis of the 5T static random access memory cell shown in Figure 3 during the write operation. As shown in Figure 4, it is simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that the 5T static random access memory cell with a single bit line has a problem that it is quite difficult to write logic 1.

Next, we will discuss the dual-port and static random access memory (SRAM) ports. The 6T static random access memory (SRAM) cell in Figure 1b is the static random access memory (SRAM) cell. An example of a cell, which uses two bit lines BL and BLB to perform read and write operations, that is, read and write are achieved through the same pair of bit lines, so only read or Write action, therefore, when you want to design a dual-port static random access memory with simultaneous read and write capabilities, you need to add two additional access transistors and another pair of bit lines (please refer to Figure 5 Circuit, where WBL and WBLB are bit line pairs for writing, RBL and RBLB are bit line pairs for reading, WWL is word line for writing, and RWL is word line for reading), which makes the memory The area of the cell is greatly increased. If we can simplify the structure of the memory cell so that one bit line is responsible for the read operation and the other bit line is responsible for the write operation, then the dual-port static random storage is designed. When taking the memory, the memory cell does not need to add two more transistors and a pair of bit lines, so the area of the memory cell will be reduced a lot, the traditional dual-port static random access memory cell The reason why this method is not adopted is that it is quite difficult to write logic 1 as described above.

So far, many technologies of dual-port static random access memory cells with a single read bit line have been proposed, such as the "Dual write wordline memory cell" proposed in Patent Document 1 (No. US9336863B2, May 105 Granted to Qualcomm Corporation on the 10th. It uses a two-stage write operation to avoid the difficulty of writing logic 1 due to the use of a single write bit line. Write logic 1 in advance in the first stage of the write operation , And in the second stage of the writing operation, it depends on the actual written data to decide whether to discharge the pre-written logic 1 to logic 0; Patent Document 2 proposed "Method of writing to and reading data from a three -dimensional two port register file" (No. US 9275724B2, granted to TSMC Corporation on March 1, 105), which uses two dedicated read NMOS transistors to achieve a single read bit line SRAM cell read Fetch operation, and because of the use of two access transistors and the need for complementary write bit lines during the write operation, a large number of SRAM cell transistors are missing; the "dual port static random access" proposed in Patent Document 3 "Retrieve memory" (No. TW I605551B, awarded to Shuiping University of Science and Technology on November 11, 106), which is designed by the combination of control circuit and high voltage level control circuit, using the control circuit in the first stage of the reading operation Lower the potential of the original ground voltage node to less than the ground voltage, and cooperate with the high voltage level control circuit to reduce the resistance of the read path, and accelerate the discharge of the charge of a single read bit line to increase the reading speed of the SRAM In the second phase of the read operation, the voltage lower than the ground voltage is changed back to the ground voltage to avoid unnecessary power consumption. Although these patents can effectively solve the problem of the difficulty of writing logic 1 caused by the use of a single write bit line, these patents do not consider that the SRAM operating voltage will drop below 0.9 volts. At this time, it is easy to process-voltage- Changes in temperature (PVT) may cause the write operation to fail to complete within the specified time, so there is still room for improvement.

In view of this, the main object of the present invention is to propose a 7T dual-port static random access memory with high read/write speed, which can be controlled by a two-stage writing word line control circuit (6) Effectively solve the problem that when the operating voltage of SRAM below 10 nanometers drops below 0.9V, the write time cannot meet the specifications. The write word line control circuit (6) is responsible for the corresponding write word line (WWL). In the first stage of power, the word line control signal (WWLC) for writing is set to the second highest power supply voltage (V _DDH2 ) higher than the power supply voltage (V _DD ) to effectively increase the writing speed. In the second stage after the first stage, the corresponding write word line control signal (WWLC) is pulled back to the power supply voltage (V _DD ) to slow down the write interference.

The secondary object of the present invention is to propose a 7T dual-port static random access memory with high read/write speed, which can be used to correspond to the read word by the read word line control circuit (7) In the first stage of enabling the element line (RWL), the corresponding word line control signal for reading (RWLC) is set to the second highest power supply voltage (V _DDH2 ) that is higher than the power supply voltage (V _DD ) , To further reduce the resistance of the read path, and accelerate the discharge of the charge on the read bit line (RWL) to effectively increase the reading speed, and in the second stage after the first stage, the corresponding The word line control signal (RWLC) for reading is pulled back to the power supply voltage (V _DD ) to alleviate reading interference.

The present invention provides a 7T dual-port static random access memory with high read/write speed, which mainly includes a memory array (1), a plurality of control circuits (2), and a plurality of precharge circuits (3) , A standby start circuit (4), a plurality of high voltage level control circuits (5), a plurality of writing word line control circuits (6), and a plurality of reading word line control circuits (7). In this way, in the writing mode, the combination of the plurality of control circuits (2) and the plurality of writing word line control circuits (6) can prevent writing logic 1 from being difficult, and effectively improve The writing speed, and in the reading mode, by the plurality of control circuits (2), the plurality of high voltage level control circuits (5) and the plurality of read word line control circuits (7) In order to improve the reading speed, it also avoids unnecessary power consumption.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧ Standby start circuit

5‧‧‧High voltage level control circuit

6‧‧‧ Writing word line control circuit

7‧‧‧Character line control circuit for reading

WC‧‧‧Inverse write control signal

P11‧‧‧The first PMOS transistor

P12‧‧‧ Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧storage node

B‧‧‧Inverted storage node

C‧‧‧Node

M14‧‧‧ First reading transistor

M15‧‧‧ Second reading transistor

WBL‧‧‧Bit line for writing

WWL‧‧‧Character line for writing

RBL‧‧‧bit line for reading

RWL‧‧‧Character line for reading

WWLC‧‧‧Character line control signal for writing

RWL‧‧‧Character line control signal for reading

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

VL1‧‧‧The first low voltage node

VL2‧‧‧second low voltage node

M21‧‧‧ Fourth NMOS transistor

M22‧‧‧Fifth NMOS transistor

M23‧‧‧Sixth NMOS transistor

M24‧‧‧NMOS transistor

M25‧‧‧Eighth NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧Tenth NMOS transistor

P21‧‧‧The third PMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

INV3‧‧‧third inverter

D1‧‧‧ First delay circuit

P31‧‧‧The fourth PMOS transistor

P‧‧‧Precharge signal

M41‧‧‧Eleventh NMOS transistor

P41‧‧‧ fifth PMOS transistor

D2‧‧‧second delay circuit

V _DD ‧‧‧ Power supply voltage

V _{DDH1 ‧‧‧The} highest power supply voltage

V _{DDH2 ‧‧‧The} second highest power supply voltage

P51‧‧‧Sixth PMOS transistor

P52‧‧‧The seventh PMOS transistor

INV4‧‧‧ fourth inverter

VH‧‧‧High voltage node

P61‧‧‧Eighth PMOS transistor

P62‧‧‧Ninth PMOS transistor

P63‧‧‧Tenth PMOS transistor

M61‧‧‧Twelfth NMOS transistor

INV5‧‧‧fifth inverter

INV6‧‧‧ sixth inverter

P71‧‧‧Eleventh PMOS transistor

P72‧‧‧12th PMOS transistor

P73‧‧‧Thirteenth PMOS transistor

M71‧‧‧Thirteenth NMOS transistor

INV7‧‧‧ seventh inverter

INV8‧‧‧ Eighth inverter

BLB‧‧‧Complementary bit line

BLB ₁ ^… BLB _m ‧‧‧ complementary bit line

MB ₁ ^… MB _k ‧‧‧ memory block

WL ₁ ^… WL _n ‧‧‧ character line

BL ₁ ^… BL _m ‧‧‧ bit line

M1 ^… M4‧‧‧‧NMOS transistor

P1 ^… P2‧‧‧PMOS transistor

I ₁ , I ₂ , I ₃ , I ₄ ‧‧‧ leakage current

Figure 1a shows the conventional static random access memory; Figure 1b shows the schematic circuit diagram of the conventional 6T static random access memory cell; Figure 2 shows the conventional 6T static random access memory cell Figure 3 is a circuit diagram of the conventional 5T static random access memory cell; Figure 4 is a circuit diagram of the conventional 5T static random access memory cell; Figure 5 is a schematic circuit diagram of a conventional 8T dual-port static random access memory cell; Figure 6 is a schematic circuit diagram of the preferred embodiment of the present invention; Figure 7 is a schematic diagram of the present invention of Figure 6 Simplified circuit diagram of the preferred embodiment during writing; Fig. 8 is a simplified circuit diagram of the preferred embodiment of the invention of Fig. 6 during reading; Fig. 9 is a preferred embodiment of the invention of Fig. 6 Simplified circuit diagram during standby.

According to the above main purpose, the present invention proposes a 7T static random access memory with high read/write speed, which mainly includes a memory array consisting of a plurality of rows of memory cells and a plurality of rows The memory cells are composed of each row of memory cells and each row of memory cells including a plurality of memory cells (1); a plurality of control circuits (2), each row of memory cells is provided with a control Circuit (2); a plurality of precharge circuits (3), each row of memory cells is provided with a precharge circuit (3); a standby start circuit (4), the standby start circuit (4) is to promote 7T dual port SRAM Quickly enter the standby mode to effectively improve the standby performance of the 7T dual-port SRAM; a plurality of high voltage level control circuits (5), each row of memory cells is equipped with a high voltage level control circuit (5), in order to read Logic 0 reduces the resistance of the read path to increase the read speed; a plurality of writing word line control circuits (6), each row of memory cells is provided with a writing word line control circuit (6), to When logic 1 is written by logic 0 or logic 1 is written by logic 1, the corresponding write word line control signal (WWLC) is set in the first stage of enabling the corresponding write word line (WWL) Into the second highest power supply voltage (V _DDH2 ) which is higher than the power supply voltage (V _DD ) to effectively increase the writing speed; and a plurality of read word line control circuits (7), each row of memory crystals The cell is provided with a read word line control circuit (7), so that when the logic 0 is read, the corresponding read word line is enabled in the first stage of enabling the corresponding read word line (RWL) The control signal (RWLC) is set to the second highest power supply voltage (V _DDH2 ) that is higher than the power supply voltage (V _DD ) to further reduce the resistance of the read path and accelerate the read bit line (RWL) The discharge of the charge effectively improves the reading speed.

For ease of explanation, the 7T static random access memory shown in Figure 6 only has one memory cell (1), one word line for writing (WWL), and one bit line for writing (WBL ), a read word line (RWL), a read bit line (RBL), a control circuit (2), a precharge circuit (3), a standby start circuit (4), a high voltage The level control circuit (5), a word line control circuit (6) for writing, and a word line control circuit (7) for reading are described as embodiments. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), and a second inverter (composed of a second PMOS transistor Composed of a crystal P12 and a second NMOS transistor M12), a third NMOS transistor (M13), a first reading transistor (M14) and a second reading transistor (M15), wherein, The first inverter and the second inverter are alternately coupled, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the second inverter The output of the phase inverter (ie, node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the second inverter The output (node B) is used to store the inverted data of the SRAM cell.

The first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11) of the memory cell (1) is connected to a power supply voltage (V _DD ) and a first Between the low voltage node (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected to a high voltage node (VH) and a second low voltage node Between the voltage node (VL2), the source, gate and drain of the first reading transistor (M14) are connected to the drain and reading of the second reading transistor (M15), respectively The word line (RWL) and the read bit line (RBL) are used, and the source, gate and drain of the second read transistor (M15) are respectively connected to the second low voltage node (VL2), the output of the second inverter (ie, node B) and the source of the first read transistor (M14).

Please refer to FIG. 6 again. The control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control Signal (RC), a third inverter (INV3), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a standby mode control signal (S) And an inverse standby mode control signal (/S). The source, gate, and drain of the fourth NMOS transistor (M21) are connected to the ground voltage, the inverted standby mode control signal (/S), and the second low voltage node (VL2); the fifth The source, gate and drain of the NMOS transistor (M22) are connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); the first The source of the six NMOS transistors (M23) is connected to the ground voltage, and the gate and the drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) , The gate and the drain are connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); the eighth NMOS transistor (M25) ) Source, gate and drain are connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first The delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV3) is for receiving The read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the source, gate, and drain of the ninth NMOS transistor (M26) are connected to the ground voltage, The drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27) are respectively connected to the standby mode control signal (S), the write control signal (WC) and the gate of the ninth NMOS transistor (M26); and the source, gate and drain of the third PMOS transistor (P21) are respectively connected to the The gate of the ninth NMOS transistor (M26), the write control signal (WC) and the inverted standby mode control signal (/S). Wherein, the inverted standby mode control signal (/S) is obtained from the standby mode control signal (S) through an inverter.

Among them, the drain of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C ), when the write control signal (WC) is a logic low level, the voltage level of the node (C) is the logic level of the inverse standby mode control signal (/S), and when the write control signal (WC) is the logic high level, the voltage level of the node (C) is the logic level of the standby mode control signal (S), thereby effectively preventing the erroneous writing caused by unexpected factors in the standby mode Into.

The control circuit (2) is designed to control the voltage levels of the first low-voltage node (VL1) and the second low-voltage node (VL2) according to different operation modes. The source voltage of the drive transistor (i.e. the first NMOS transistor M11) closer to the write bit line (WBL) is set to one higher than the ground voltage A predetermined voltage (ie, the gate-source voltage V _{GS(M23) of} the sixth NMOS transistor (M23)) and the source voltage of the other driving transistor (ie, the second NMOS transistor M12) in the selected cell ( That is, the second low-voltage node VL2) is set to the ground voltage in order to prevent the difficulty of writing logic 1.

In the first stage of the read mode, the source voltage (ie, the second lowest voltage) of the driving transistor (ie, the second NMOS transistor M12) in the selected cell closer to the read bit line (RBL) is selected The voltage node VL2) is set to a lower voltage than the ground voltage. The second low voltage node (VL2) which is lower than the ground voltage can effectively improve the reading speed. In the second stage of the reading mode, the The source voltage of the driving transistor (ie, the second NMOS transistor M12) closer to the read bit line (RBL) in the selected cell is set back to the ground voltage in order to reduce unnecessary power consumption, wherein the read mode The time between the second phase and the first phase is equal to the read control signal (RC) from the logic low level to the logic high level, and to the eighth NMOS transistor (M25) gate voltage The time enough to turn off the eighth NMOS transistor (M25) can be adjusted by the falling delay time of the third inverter (INV3) and the delay time provided by the first delay circuit (D1).

In the standby mode, the source voltage of the driving transistors in all memory cells is set to the predetermined voltage higher than the ground voltage in order to reduce the leakage current; in the hold mode, the source voltage in the memory cells The source voltage of the driving transistor is set to the ground voltage in order to maintain the original retention characteristics. The first low voltage node (VL1) and the second low voltage node VL2 are in write mode, read mode, standby mode and hold mode The detailed working voltage level is shown in Table 1 below.

The write control signal (WC) in Table 1 is the AND gate operation result of a write enable signal (WE) and corresponding write word line (WWL) signal, At this time, only when the write enable signal (WE) and the corresponding write word line (WWL) signal are at a logic high level, the write control signal (WC) is at a logic low level; the read The control signal (RC) is the result of the sum operation of a read enable signal (Read Enable, RE for short) and the corresponding read word line (RWL) signal. It is worth noting here that for non-selected word lines and non-selected positioning element lines, the floating state is set, and for the non-read mode, the read control signal (RC) is set to the acceleration Read the voltage (RGND) level to prevent the leakage current of the seventh NMOS transistor (M24).

Please refer to FIG. 6, the precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P), the source and gate of the fourth PMOS transistor (P31) And the drain are connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit line (RBL), so that during the precharge period, the logic low level of the Precharge signal (P) to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V _DD ).

Please refer to FIG. 6 again, the standby start circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2), and the reverse standby Mode control signal (/S). The source, gate, and drain of the fifth PMOS transistor (P41) are connected to the power supply voltage (V _DD ), the inverted standby mode control signal (/S), and the eleventh NMOS transistor, respectively (M41) drain; the source, gate and drain of the eleventh NMOS transistor (M41) are connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) respectively And the drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) is Connect to the gate of the eleventh NMOS transistor (M41).

Please refer to FIG. 6 again, the high voltage level control circuit (5) is composed of a sixth PMOS transistor (P51), a seventh PMOS transistor (P52), and a fourth inverter (INV4) Where the source, gate and drain of the sixth PMOS transistor (P51) are connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH), The source, gate and drain of the seventh PMOS transistor (P52) are respectively connected to a first high power supply voltage (V _DDH1 ), the output of the fourth inverter (INV4) and the high voltage node (VH), and the input of the fourth inverter (INV4) is for receiving the read control signal (RC), and the output is connected to the drain of the seventh PMOS transistor (P52). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage Between the node (VH) and the second low voltage node (VL2).

Please refer to FIG. 6 again, the write word line control circuit (6) is composed of an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), and a tenth PMOS transistor (P63) , A twelfth NMOS transistor (M61), a fifth inverter (INV5), a sixth inverter (INV6), a second highest power supply voltage (V _DDH2 ), a writing character Line (WWL) and a write word line control signal (WWLC). The source, gate and drain of the eighth PMOS transistor (P61) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (INV5) and the ninth PMOS The source of the transistor (P62); the source, gate and drain of the ninth PMOS transistor (P62) are respectively connected to the drain of the eighth PMOS transistor (P61) and the sixth inverter (INV6) output and the write word line control signal (WWLC); the source, gate and drain of the tenth PMOS transistor (P63) are connected to the power supply voltage (V _DD ), The output of the fifth inverter (INV5) and the write word line control signal (WWLC); the source, gate and drain of the twelfth NMOS transistor (M61) are connected to the ground respectively Voltage, the output of the fifth inverter (INV5) and the write word line control signal (WWLC); the input of the fifth inverter (INV5) is for receiving the write word line (WWL) ), and the input of the sixth inverter (INV6) is connected to the output of the fifth inverter (INV5).

The word line control circuit (6) for writing uses a two-stage operation when it is enabled to effectively solve the problem that the writing time cannot meet the specification when the SRAM operating voltage below 10 nanometers drops below 0.9. In the first phase of enabling word line (WWL) enablement, the write word line control signal (WWLC) is set to the second highest power supply voltage (V _DD ) higher than the power supply voltage (V _DD ) V _DDH2 ) to effectively increase the writing speed, and in the second stage after the first stage, the write word line control signal (WWLC) is pulled back to the power supply voltage (V _DD ), In order to slow down the write interference; wherein, the time between the second phase and the first phase of the write word line control circuit (6) is equal to the output of the fifth inverter (INV5) enough to turn on the The time of the eighth PMOS transistor (P61) is calculated, and the time until the output of the sixth inverter (INV6) is sufficient to turn off the ninth PMOS transistor (P62), the value of which can be determined by the sixth inversion (INV6) to adjust the rising delay time.

Please refer to FIG. 6 again. The read word line control circuit (7) is composed of an eleventh PMOS transistor (P71), a twelfth PMOS transistor (P72), and a thirteenth PMOS transistor (P73), a thirteenth NMOS transistor (M71), a seventh inverter (INV7), an eighth inverter (INV8), the second highest power supply voltage (V _DDH2 ), a read It is composed of a word line (RWL) and a read word line control signal (RWLC). The source, gate and drain of the eleventh PMOS transistor (P71) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the seventh inverter (INV7) and the tenth The source of the two PMOS transistors (P72); the source, gate and drain of the twelfth PMOS transistor (P72) are connected to the drain of the eleventh PMOS transistor (P71), the The output of the eighth inverter (INV8) and the read word line control signal (RWLC); the source, gate and drain of the thirteenth PMOS transistor (P73) are respectively connected to the power supply voltage (V _DD ), the output of the seventh inverter (INV7) and the read word line control signal (RWLC); the source, gate and drain of the thirteenth NMOS transistor (M71) Connected to the ground voltage, the output of the seventh inverter (INV7) and the read word line control signal (RWLC) respectively; the input of the seventh inverter (INV7) is for receiving the read The word line (RWL), and the input of the eighth inverter (INV8) is connected to the output of the seventh inverter (INV7).

The read word line control circuit (7) adopts two-stage operation when it is enabled, and in the first stage of the read word line (RWL) enable, the read word line control signal (RWLC) is set to the second highest power supply voltage (V _DDH2 ) that is higher than the power supply voltage (V _DD ) to effectively increase the reading speed, while in the second stage after the first stage, then The read word line control signal (RWLC) is pulled back to the power supply voltage (V _DD ) to slow the read disturbance; wherein, the second of the read word line control circuit (7) The time between the phase and the first phase is equal to the time when the output of the seventh inverter (INV7) is sufficient to turn on the eleventh PMOS transistor (P71), and to the eighth inverter (INV8) The output is sufficient to turn off the twelfth PMOS transistor (P72), and its value can be adjusted by the rise delay time of the eighth inverter (INV8).

The working principle of the preferred embodiment of the present invention shown in FIG. 6 is as follows:

(I) write mode

Before the start of the write operation, the standby mode control signal (S) and the write control signal (WC) are at a logic low level, so that the third PMOS transistor (P21) is turned on and makes the tenth NMOS The transistor (M27) is turned off, so the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at the logic high level will turn on the ninth NMOS transistor (M26), and makes the first low voltage node (VL1) assume a ground voltage.

During the write operation period, the write control signal (WC) is at a logic high level, so that the third PMOS transistor (P21) is turned off, the tenth NMOS transistor (M27) is turned on, and the third PMOS is turned on The drain of the transistor (P21) is at a logic low level. The drain of the third PMOS transistor (P21) at the logic low level turns off the ninth NMOS transistor (M26) and makes the first low voltage The node (VL1) is equal to the gate-source voltage V _{GS (M26} ) of the sixth NMOS transistor (M23 ₎ , thereby effectively preventing the difficulty of writing logic 1. FIG. 7 is a simplified circuit diagram of the preferred embodiment of the present invention of FIG. 6 during the writing period.

Next, according to four writing states, it is explained how the preferred embodiment of the present invention shown in FIG. 7 completes the writing operation.

(1) Node A originally stored logic 0, but now wants to write logic 0:

Before the write operation occurs (the write word line control signal WWLC is the ground voltage), the first NMOS transistor (M11) is turned ON. Since the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line (WWL) changes from Low (ground voltage) to High (power supply voltage V _DD ). When the voltage of the write word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, access transistor), the third NMOS transistor (M13) is turned off ) Changes to ON. At this time, because the write bit line (WBL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle.

(2) Node A originally stored logic 0, but now wants to write logic 1:

Before the write operation occurs (the write word line control signal WWLC is the ground voltage), the first NMOS transistor (M11) is turned ON. It is worth noting here that because the first NMOS transistor (M11) is ON, when the write operation starts, the write word line control signal (WWLC) changes from Low (ground voltage) to High, the The voltage of the node A will slightly increase following the voltage of the write word line control signal (WWLC) due to the parasitic capacitance coupling effect. When the voltage of the write word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON At this time, because the write bit line (WBL) is the voltage level of the power supply voltage (V _DDH ), and because the first NMOS transistor (M11) is still ON and the node B is still in the voltage position Is the initial state close to the voltage level of the power supply voltage (V _DD ), so the first PMOS transistor (P11) is still OFF, and the initial instantaneous voltage of the node A (V _AWI ) is written ) Meet equation (3): V _AWI = V _DD × (R _M11 + R _M23 )/(R _M13 + R _M11 + R _M23 )

And V _AWI >V _TM12 (3)

Where, V _AWI represents the initial instantaneous voltage of node A, R _M13 represents the on-resistance of the third NMOS transistor (M13), R _M11 represents the on-resistance of the first NMOS transistor (M11), and R _M23 represents the The on-resistance of the sixth NMOS transistor (M23), and V _DD and V _TM12 represent the threshold voltage of the power supply voltage (V _DD ) and the second NMOS transistor (M12), respectively. Since a voltage level equal to the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23) is provided at the first low voltage node (VL1), the voltage level of node A can be easily adjusted The level is set to be much higher than the voltage level of the node A of the conventional 5T static random access memory cell of FIG. 4. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), so that node B is discharged to a lower voltage level, and the lower voltage level of node B will cause the The on-resistance equivalent (R _M11 ) of the first NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A The higher voltage level of the node A will pass through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B presents a lower voltage level , The lower voltage level of the node B will pass through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, Following this cycle, the node A can be charged to the power supply voltage (V _DD ), and the logic 1 write operation is completed.

Wherein, the first low voltage node (VL1) originally stores logic 0 at node A, and during the writing of logic 1, it has a gate-source voltage V _{GS (M23)} equal to the sixth NMOS transistor _(M23) After writing logic 1, it will be the level of the ground voltage due to the discharge through the ninth NMOS transistor (M26).

It is worth noting here that the present invention uses a two-stage write word line control circuit (6) to effectively solve the problem that the write time cannot meet the specification when the SRAM operating voltage below 10 nanometers drops below 0.9V Problem, the write word line control circuit (6) sets the write word line control signal (WWLC) to be higher than the write word line (WWL) enable in the first stage The second highest power supply voltage (V _DDH2 ) _whose power supply voltage (V _DD ) is still higher, because the logic 0 was originally stored at the node A and at the beginning of the writing of the logic 1, the third NMOS transistor (M13) works at The saturation zone, the current in the saturation zone is proportional to the square of the gate-source voltage V _{GS (M13)} after deducting its critical voltage V _TM13 , so the write word line control signal (WWLC) During the first stage of the second highest power supply voltage (V _DDH2 ) set higher than the power supply voltage (V _DD ), the speed of writing logic 1 can be effectively accelerated; in addition, in order to slow down the writing period The interference phenomenon of the semi-selected cell, during the second stage after the first stage, the write word line control signal (WWLC) is pulled back to the voltage level of the power supply voltage (V _DD ), The time period between the second phase and the first phase of the write word line control circuit (6) is equal to the output of the fifth inverter (INV5) enough to turn on the eighth PMOS transistor ( P61), and the time until the output of the sixth inverter (INV6) is enough to turn off the ninth PMOS transistor (P62), its value can be increased by the sixth inverter (INV6) Delay time to adjust.

(3) Node A originally stored logic 1, but now wants to write logic 1:

Before the write operation occurs (the write word line control signal WWLC is the ground voltage), the first PMOS transistor (P11) is turned on. When the write word line control signal (WWLC) changes from Low (ground voltage) to High, because the node A is the voltage level of the power supply voltage (V _DD ), and the write bit line (WBL) ) Is the voltage level of the power supply voltage (V _DD ), so when the second highest power supply voltage (V _DDH2 ) is set to be higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) And the sum of V _TM13 of the critical voltage of the third NMOS transistor (M13), that is, V _DD <V _DDH2 <V _DD +V _TM13 (4) will cause the third NMOS transistor (M13) to continue to remain off (OFF) state; at this time, because the first PMOS transistor (P11) is still ON, the voltage of the node A will be maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stored logic 1, but now wants to write logic 0:

Before the write operation occurs (the write word line control signal WWLC is the ground voltage), the first PMOS transistor (P11) is turned on. When the write word line control signal (WWLC) changes from Low (ground voltage) to High, and the voltage of the write word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13) At this time, the third NMOS transistor (M13) changes from off to on. At this time, because the write bit line (WBL) is Low (ground voltage), the node A and the The first low voltage node (VL1) is discharged to complete the logic 0 write operation until the end of the write cycle.

It is worth noting here that when node A writes logic 1 from logic 0 and logic 1 writes logic 0, the third NMOS transistor (M13) works in the saturation region, and the current in the saturation region is its gate-source The voltage level of the polar voltage V _{GS (M13)} is proportional to the square of the threshold voltage after deducting its critical voltage. Therefore, the writing word line control circuit (6) is applied to the writing word line ( WWL) The first stage of enabling, setting the write word line control signal (WWLC) to the second highest power supply voltage (V _DDH2 ) which is higher than the power supply voltage (V _DD ), can be effective Accelerate the writing speed of node A from logic 0 to logic 1 and logic 1 to logic 0.

(II) Read mode

Before the start of the read operation, the read control signal (RC), the write control signal (WC) and the standby mode control signal (S) are all at a logic low level, so that the third PMOS transistor (P21) is turned on And the tenth NMOS transistor (M27) is turned off, so the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at a logic high level will be turned on The ninth NMOS transistor (M26), and makes the first low voltage node (VL1) assume a ground voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned on (ON).

It is worth noting here that during the precharge period before the start of the read operation, the precharge signal (P) is a logic low level, thereby precharging the corresponding read bit line (RBL) to The level of the power supply voltage (V _DD ), but because the operating voltage of process technology such as below 10 nanometers will be reduced to below 0.9 volts, the reading speed will be reduced and the specification cannot be met. Therefore, the present invention proposes two The stage of reading control can improve the reading speed and meet the specifications, while avoiding unnecessary power consumption.

The preferred embodiment of the present invention shown in FIG. 6 uses two-stage reading control to increase reading speed while avoiding unnecessary power consumption. In the first stage of reading operation, the reading control The signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the second low voltage node (VL2) is approximately grounded The accelerated reading voltage (RGND) whose voltage is low, and the accelerated reading voltage (RGND) whose voltage is lower than the ground voltage can effectively improve the reading speed.

In the second phase of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but due to the eighth NMOS transistor ( M25) is turned off, so that the second low voltage node (VL2) will assume a ground voltage through the turned-on fourth NMOS transistor (M21) (because the inverted standby mode control signal (/S) is logic during the read operation High level), which can effectively reduce unnecessary power consumption. It is worth noting here that the time between the second phase and the first phase of the read operation is equal to the read control signal (RC) changing from a logic low level to a logic high level, and to the first The gate voltage of the eight NMOS transistors (M25) is sufficient to turn off the eighth NMOS transistor (M25). The value can be determined by the falling delay time of the third inverter (INV3) and the first delay circuit (D1) Adjust the delay time provided. Furthermore, regardless of whether the first stage or the second stage of the read operation, the fourth NMOS transistor (M21) is turned on (because the inverted standby mode control signal (/S) is logic during the read operation High level). Figure 8 is a simplified circuit diagram of the preferred embodiment of the present invention shown in Figure 6 during reading.

Next, according to two reading states, how the preferred embodiment of the present invention shown in FIG. 8 is controlled by the control circuit (2), the high voltage level control circuit (5), and the read word line control circuit (7) ) In order to improve the reading speed, it also avoids unnecessary power consumption.

(1) Read logic 1 (node A stores logic 1):

Before the read operation occurs, the first NMOS transistor (M11) is turned off (OFF) and the second NMOS transistor (M12) is turned on (ON), the node A and the node B are respectively the power supply voltage (V _DD ) and the ground voltage, and the read bit line (RBL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading period, since the node B is the ground voltage, the second reading transistor (M15) is turned off, thereby effectively maintaining the reading bit line (RBL) to the power supply voltage ( V _DD ) until the end of the read cycle and successfully complete the operation of reading logic 1. It is worth noting here that in the first stage of the read operation, the initial instantaneous voltage (V _RVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy equation (5): V _RVL2I =RGND×R _M21 /(R _M21 +R _M24 +R _M25 )

And V _RVL2I >-V _TM12 (5)

In order to effectively prevent the half-selected cell interference during reading, V _RVL2I represents the initial instantaneous voltage of the second low voltage node (VL2) when reading logic 1, RGND represents the accelerated reading voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), R _M24 represents the on-resistance of the seventh NMOS transistor (M24), R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM12 Represents the threshold voltage of the second NMOS transistor (M12); and in the second stage of the read operation, the voltage (V _RVL2 ) of the second low voltage node (VL2) can be expressed by equation (6) V _RVL2 = The ground voltage (6) can effectively reduce unnecessary power consumption. In addition, in order to effectively reduce the interference of the semi-selected cell during reading and effectively reduce the leakage current, the accelerated reading voltage (RGND) lower than the ground voltage must be set to make the second low voltage node (VL2) The voltage level is lower than the threshold voltage (V _TM12 ) of the second NMOS transistor (M12), and the absolute value of the accelerated read voltage (RGND) lower than the ground voltage can be more rigorously set | RGND| The threshold voltage (V _TM12 ) of the second NMOS transistor (M12), namely |RGND|<V _TM12 (7), where |RGND| and V _TM12 represent the absolute value of the accelerated reading voltage and the first The critical voltage of two NMOS transistors (M12).

(2) Read logic 0 (node A stores logic 0):

Before the reading operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF), the node A and the node B are the ground voltage and the node The power supply voltage (V _DD ), and the read bit line (RBL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading period, since node B is the first high power supply voltage (V _DDH1 ) and the second low voltage node (VL2) is lower than the ground voltage, the present invention _uses the first high power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the absolute value of the second PMOS transistor (P12) threshold voltage | V _TP12 | That is, V _DD <V _DDH1 <V _DD +|V _TP12 | (8)

Where |V _TP12 | represents the absolute value of the critical voltage of the second PMOS transistor (P12), therefore, the read logic 0 can be increased by increasing the conduction degree of the second read transistor (M15) At the same time, the second low voltage node (VL2), which is lower than the ground voltage, is used to further increase the reading speed.

Furthermore, during the reading period, the read word line control circuit (7) controls the read word line in the first stage enabled by the read word line (RWL) The signal (RWLC) is set to the second highest power supply voltage (V _DDH2 ) that is higher than the power supply voltage (V _DD ) to further reduce the resistance of the read path and accelerate the read bit line (RWL) ) Discharge of the charge on the) to further increase the reading speed, and in the second stage after the first stage, the read word line control signal (RWLC) is pulled back to the power supply voltage (V _DD ) to alleviate read interference. It is worth noting here that the second highest power supply voltage (V _DDH2 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the first reading transistor (M14) The sum of V _TM14 of the critical voltage, that is, V _DD <V _DDH2 <V _DD +V _TM14 (9) Comparing equation (4) and equation (9), it can be seen that the second highest power supply voltage (V _DDH2 ) must satisfy the power supply voltage (V _DD) and the first reading electric crystal (M14) V _TM14 total sum of the threshold voltage (V _DD + V _TM14) and the power supply voltage (V _DD) and the third The _smaller of the sum of V _TM13 (V _DD +V _TM13 ) of the critical voltage of the NMOS transistor (M13).

(III) Standby mode

First, explain how the standby start circuit (4) of Figure 6 prompts the dual-port SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: first, before entering the standby mode, the inverted standby mode control signal (/S) Logic High, the inverted standby mode control signal (/S) of the logic High makes the fifth PMOS transistor (P41) off (OFF), and makes the eleventh NMOS transistor (M41) on (ON); Then, after entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low makes the fifth PMOS transistor (P41) conductive (ON) , But within the initial period of the standby mode (the initial period is equal to the reverse standby mode control signal (/S) from logic High to logic Low, from the gate voltage of the eleventh NMOS transistor (M41) Enough time to turn off the eleventh NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2)), the eleventh NMOS transistor (M41) is still on (ON), the first low voltage node (VL1) can be quickly charged to the voltage level of the critical voltage (V _TM23 ) of the sixth NMOS transistor (M23), that is, the 7T dual-port SRAM can quickly enter standby mode. It is worth noting here that after the initial period of standby mode, the eleventh NMOS transistor (M41) turns off and stops supplying current.

Please refer to FIG. 6, in the standby mode, the standby mode control signal (S) is at a logic high level, and the inverted standby mode control signal (/S) is at a logic low level, and the inverted standby of the logic low level The mode control signal (/S) makes the fourth NMOS transistor (M21) in the control circuit (2) OFF, and the standby mode control signal (S) of the logic high level makes the fifth The NMOS transistor (M22) is turned on. At this time, the fifth NMOS transistor (M22) is used as an equalizer. Therefore, the fifth NMOS transistor (M22) in the on state can be used. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels will be equal to the sixth NMOS transistor (M23) The voltage level of the critical voltage (V _TM23 ). FIG. 9 is a simplified circuit diagram of the preferred embodiment of the present invention shown in FIG. 6 during standby.

Next, how to reduce the leakage current in the standby mode of the present invention is described. Please refer to FIG. 9, which describes the leakage currents I ₁ generated by the embodiment of the present invention when in the standby mode. , I ₂ , I ₃ , I ₄ , where it is assumed that the output of the first inverter in the SRAM cell (ie, node A) is logic Low (it is worth noting here that the first low voltage is in standby mode The voltage levels of the node (VL1) and the second low voltage node (VL2) are maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so the node A is a logic low voltage The level is also maintained at the voltage level of the V _TM23 ), and the output of the second inverter (ie, node B) is logic High (power supply voltage V _DD ). Please refer to the conventional 8T dual-port SRAM in FIG. 5 and the embodiment of the present invention in FIG. 9 to illustrate the leakage current of the dual-port static random access memory proposed in the present invention and the conventional 8T dual-port SRAM in FIG. 5 For comparison, first, regarding the leakage current I ₁ flowing through the third NMOS transistor (M13), due to the

Invented in the standby mode, the voltage level of the node A is maintained at the voltage level of the V _TM23 , and it is assumed that the write word line (WWL) is set to the ground voltage in the standby mode, and the write bit The line (WBL) is set to the power supply voltage (V _DD ) in the standby mode, so the gate-source voltage (V _GS ) of the third NMOS transistor (M13) of the present invention is a negative value, in contrast to the standby mode The gate-source voltage (V _GS ) of the NMOS transistor (M3) of the traditional 8T dual-port SRAM in Figure 5 is equal to 0, according to the gate-induced drain leakage (GIDL) effect or 2005 3 The results of Figures 3(A) and 3(B) of US Patent No. US6865119 dated May 8 show that for NMOS transistors, the sub-critical current at the gate-source voltage of -0.1 volts is approximately the gate-source voltage of 1% of the sub-critical current at 0 volts, so the leakage current I ₁ caused by the GIDL effect flowing through the third NMOS transistor (M13) of the present invention is much smaller than that of the conventional 8T dual-port SRAM of FIG. 5 NMOS transistor (M3); furthermore, the drain source voltage (V _DS ) of the third NMOS transistor (M13) of the present invention is the power supply voltage (V _DD ) _minus the voltage level of the V _TM23 , In contrast, the drain source voltage (V _DS ) of the NMOS transistor (M3) of the traditional 8T dual-port SRAM in Figure 5 is equal to the power supply voltage (V _DD ), and the energy barrier drops according to the drain (Drain-Induced Barrier Lowering (abbreviated as DIBL) effect, due to the DIBL effect, the leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention is also smaller than that of the conventional 8T dual-port SRAM NMOS transistor (M3) of FIG. 5 As a result, the leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention is much smaller than the NMOS transistor (M3) of the conventional 8T dual-port SRAM of FIG. 5.

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), since the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) in the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V _TM23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V _DD ) The voltage level of the V _TM23 is deducted. In contrast, the source-drain voltage (V _SD ) of the PMOS transistor (P1) of the traditional 8T dual-port SRAM in Figure 5 is equal to the power supply voltage (V _DD ), according to Due to the DIBL effect, the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the PMOS transistor (P1) of the prior art shown in FIG. 1b.

Then, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) in the standby mode is maintained at the voltage level of the V _TM23 , node A The voltage level of the V _TM23 is also maintained, and the voltage level of the node B is equal to the power supply voltage (V _DD ) and the base of the second NMOS transistor (M12) is the ground voltage. The base-source voltage (V _BS ) of the second NMOS transistor (M12) invented is a negative value, and the drain-source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V _DD ) deduct the voltage level of the V _TM23 , in contrast to the base-source voltage (V _BS ) of the NMOS transistor (M2) of the conventional 8T dual-port SRAM in Figure 5 is equal to 0, and the NMOS transistor (M2) The drain source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and the DIBL effect, the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than Figure 5 is the NMOS transistor (M2) of the traditional 8T dual-port SRAM.

Finally, regarding the leakage current I ₄ flowing through the first reading transistor (M14), since the present invention is different from the reading method of the conventional 8T dual-port SRAM of FIG. 5, and the reading in the standby mode of the present invention The bit line (RBL) can be set to ground voltage, and in order to prevent the voltage level of node B from decreasing in the conventional 8T dual-port SRAM of Figure 5, the bit line pair (RBL, RBLB) for reading in standby mode It is set to the power supply voltage, so there is no comparison of the leakage current I ₄ flowing through the first reading transistor (M14). Based on the above analysis, it can be seen that the dual-port static random access memory proposed by the present invention has a lower leakage current than the conventional 8T dual-port SRAM of FIG. 5.

(IV) Retention mode

In the hold mode, since the first low-voltage node (VL1) and the second low-voltage node (VL2) are set to the ground voltage, the working principle is the same as the traditional dual-port SRAM cell with a single bit line. No more tired.

【Invention Effect】

The 7T dual-port static random access memory with high read/write speed proposed by the present invention has the following effects:

(1) High writing speed: when writing logic 1 from logic 0 and logic 0 from logic 1, the access transistor (ie, the third NMOS transistor M13) works in the saturation region, and the current in the saturation region is It is proportional to the square of its gate-source voltage V _GS(M13) after deducting its critical voltage, so it is used for writing by the two-stage writing word line control circuit (6) In the first phase of enabling the word line (WWL), the write word line control signal (WWLC) is set to the second highest power supply voltage (V _DDH2 ) that is higher than the power supply voltage (V _DD ) ), can effectively speed up the writing speed from logic 0 to logic 1 and from logic 1 to logic 0;

(2) High reading speed and avoid unnecessary power consumption: by the plural control circuits (2), the plural high voltage level control circuits (5) and the plural reading word line control circuits ( 7) An innovative combination to improve reading speed while avoiding unnecessary power consumption; wherein, the plurality of control circuits (2) at the first stage of reading logic 0, the second low voltage node (VL2 ) Is set to a voltage lower than the ground voltage, the plurality of high-voltage level control circuits (5), when reading logic 0, sets the node B to the first higher than the power supply voltage (V _DD ) A high power supply voltage (V _DDH1 ), and the read word line control circuit (7) sets the read word line control signal (RWLC) to be higher than the The power supply voltage (V _DD ) is still the second highest power supply voltage (V _DDH2 ).

(3) Quickly enter the standby mode: The 7T static random access memory proposed by the present invention is provided with a standby start circuit (4) to prompt the SRAM to quickly enter the standby mode, and thereby to improve the standby performance of the 7T dual-port SRAM ;

(4) Increase the speed of writing logic 1 and avoid the problem of writing logic 1 difficult: the present invention can use the plural control circuits (2) and the plural writing word lines during writing operation The control circuit (6) effectively prevents the difficulty of writing logic 1 and also increases the speed of writing logic 1;

(5) Low standby current: Since the 7T static random access memory proposed by the present invention is in the standby mode, the fifth NMOS transistor (M22) in the on state can be used to make the first low voltage node The voltage level of (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the level of the critical voltage of the sixth NMOS transistor (M23). The dual-port static random access memory proposed by the invention also has the effect of low standby current;

(6) Effectively reduce the interference of the semi-selected cell: The 7T static random access memory proposed in the present invention uses a separate read/write path, and the read path is designed to use the first and second reads Transistors (M14 and M15) are connected in series between the read bit line (RBL) and the second low voltage node (VL2), and connect the inverted storage node (B) to the second read The gate of the transistor (M15) is used, so it can effectively reduce half-selected cell disturbance, where the half-selected cell means that it is selected by the read word line (RWL) but not This memory cell is selected by the bit line (RBL).

(7) Low number of transistors: For an SRAM array with 1024 columns and 1024 rows, the traditional 8T dual-port SRAM array in FIG. 5 requires a total of 1024×1024×8=8,388,608 transistors, and the dual The port static random access memory only needs 1024×1024×7+1024×36+6=7,376,902 transistors, which reduces the number of transistors by 12.1%.

(8) Effectively prevent erroneous writing due to unintended factors in standby mode: In standby mode, if the write control signal (WC) is at a logic high level due to unintended factors, due to the multiple control The voltage level of the node (C) in the circuit (2) is the voltage level of the standby mode control signal (S), so it will turn on the ninth NMOS transistor (M26) and make the first low voltage The node (VL1) is the ground voltage, so it can effectively prevent erroneous writing.

Although the present invention specifically discloses and describes selected preferred embodiments, those skilled in the art may understand that any possible changes in form or detail do not depart from the spirit and scope of the present invention. Therefore, all changes within the relevant technical category are included in the patent application scope of the present invention.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧ Standby start circuit

5‧‧‧High voltage level control circuit

6‧‧‧ Writing word line control circuit

7‧‧‧Character line control circuit for reading

WC‧‧‧Write control signal

P11‧‧‧The first PMOS transistor

P12‧‧‧ Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧storage node

B‧‧‧Inverted storage node

C‧‧‧Node

M14‧‧‧ First reading transistor

M15‧‧‧ Second reading transistor

WBL‧‧‧Bit line for writing

WWL‧‧‧Character line for writing

RBL‧‧‧bit line for reading

RWL‧‧‧Character line for reading

WWLC‧‧‧Character line control signal for writing

RWLC‧‧‧Character line control signal for reading

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

VL1‧‧‧The first low voltage node

VL2‧‧‧second low voltage node

M21‧‧‧ Fourth NMOS transistor

M22‧‧‧Fifth NMOS transistor

M23‧‧‧Sixth NMOS transistor

M24‧‧‧NMOS transistor

M25‧‧‧Eighth NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧Tenth NMOS transistor

P21‧‧‧The third PMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

INV3‧‧‧third inverter

D1‧‧‧ First delay circuit

P31‧‧‧The fourth PMOS transistor

P‧‧‧Precharge signal

M41‧‧‧Eleventh NMOS transistor

P41‧‧‧ fifth PMOS transistor

D2‧‧‧second delay circuit

V _DD ‧‧‧ Power supply voltage

V _{DDH1 ‧‧‧The} highest power supply voltage

V _{DDH2 ‧‧‧The} second highest power supply voltage

P51‧‧‧Sixth PMOS transistor

P52‧‧‧The seventh PMOS transistor

INV4‧‧‧ fourth inverter

VH‧‧‧High voltage node

P61‧‧‧Eighth PMOS transistor

P62‧‧‧Ninth PMOS transistor

P63‧‧‧Tenth PMOS transistor

M61‧‧‧Twelfth NMOS transistor

INV5‧‧‧fifth inverter

INV6‧‧‧ sixth inverter

P71‧‧‧Eleventh PMOS transistor

P72‧‧‧12th PMOS transistor

P73‧‧‧Thirteenth PMOS transistor

M71‧‧‧Thirteenth NMOS transistor

INV7‧‧‧ seventh inverter

INV8‧‧‧ Eighth inverter

Claims (10)

A 7T dual-port static random access memory with high read/write speed includes: a memory array, which is composed of a plurality of rows of memory cells and a plurality of rows of memory cells, each A row of memory cells and each row of memory cells include a plurality of memory cells (1); a plurality of control circuits (2), each row of memory cells is provided with a control circuit (2); a plurality of pre-cells Charging circuit (3), each row of memory cells is provided with a pre-charging circuit (3); a standby start circuit (4), the standby start circuit (4) is to facilitate the rapid entry of the 7T dual-port static random access memory Standby mode to effectively improve the standby performance of the 7T dual-port static random access memory; and a plurality of writing word line control circuits (6), each row of memory cells is provided with a writing word line control Circuit (6) to effectively increase the writing speed of logic 0 to logic 1 and logic 1 to logic 0 in the write mode; each memory cell (1) further includes: a first counter The phase inverter is composed of a first PMOS transistor (P11) and a first NMOS transistor (M11). The first inverter is connected to a power supply voltage (V _DD ) and a first low voltage Between the nodes (VL1); a second inverter is composed of a second PMOS transistor (P12) and a second NMOS transistor (M12), the second inverter is connected to a high voltage Between a node (VH) and a second low voltage node (VL2); a storage node (A) is formed by the output of the first inverter; an inverting storage node (B) is formed by the The output of the second inverter is formed; a third NMOS transistor (M13) is connected between the storage node (A) and a write bit line (WBL), and the gate is connected to a Write word line control signal (WWLC); a first reading transistor (M14), the source, gate and drain of the first reading transistor (M14) are connected to a first The drain of two read transistors (M15), a read word line control signal (RWLC) and a read bit line (RBL); and the second read transistor (M15), The source, gate and drain of the second read transistor (M15) are connected to the second low voltage node (VL2), the inverting storage node (B) and the first read power respectively The source of the crystal (M14); wherein, the first inverter and the second inverter are connected in an interactive coupling, that is, the output terminal of the first inverter (ie, the storage node A) is connected to The input terminal of the second inverter, and the output terminal of the second inverter (that is, the inverted storage node B) is connected to the input terminal of the first inverter; and each control circuit (2) It also includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor ( M25), a ninth NMOS Transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV3), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a standby mode control signal (S), and an inverted standby mode control signal (/S); wherein, the fourth NMOS power The source, gate and drain of the crystal (M21) are connected to a ground voltage, the reverse standby mode control signal (/S) and the second low voltage node (VL2); the fifth NMOS transistor ( M22) the source, gate and drain are connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); the sixth NMOS transistor The source of (M23) is connected to the ground voltage, and the gate and the drain are connected together and connected to the first low voltage node (VL1); the source and gate of the seventh NMOS transistor (M24) And the drain are connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); the source of the eighth NMOS transistor (M25) The gate, the gate and the drain are connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first delay circuit ( D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV3) is for receiving the read Control signal (RC), and the output is connected to the input of the first delay circuit (D1); the source, gate, and drain of the ninth NMOS transistor (M26) are connected to the ground voltage, the first The drain of the ten NMOS transistor (M27) and the first low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27) are respectively connected to the standby mode control signal (S ), the write control signal (WC) and the gate of the ninth NMOS transistor (M26); the source, gate and drain of the third PMOS transistor (P21) are respectively connected to the inverting standby Mode control signal (/S), the write control signal (WC) and the drain of the tenth NMOS transistor (M27); wherein, the drain of the third PMOS transistor (P21) and the tenth NMOS transistor The drain of the crystal (M27) and the gate of the ninth NMOS transistor (M26) are connected together and form a node (C). When the write control signal (WC) is at a logic low level, the node (C ) Is the logic level of the inverse standby mode control signal (/S), and when the write control signal (WC) is a logic high level, the voltage level of the node (C) is the The logic level of the standby mode control signal (S), thereby effectively preventing Erroneous writing due to unintended factors in standby mode; where the read control signal (RC) during non-read mode is set to the level of the accelerated read voltage (RGND) to prevent the first The leakage current of seven NMOS transistors (M24) during the non-read mode; furthermore, the standby start circuit (4) is designed to respond to the first low voltage node (VL1) during an initial period of entering standby mode The parasitic capacitance at the site is quickly charged to the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23); finally, each write word line control circuit (6) is powered by an eighth PMOS Crystal (P61), a ninth PMOS transistor (P62), a tenth PMOS transistor (P63), a twelfth NMOS transistor (M61), a fifth inverter (INV5), a sixth inverter Phase device (INV6), a second highest power supply voltage (V _DDH2 ), a write word line (WWL) and the write word line control signal (WWLC); wherein the seventh PMOS power The source, gate and drain of the crystal (P61) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (INV5) and the eighth PMOS transistor (P62) Source; the source, gate and drain of the ninth PMOS transistor (P62) are connected to the drain of the eighth PMOS transistor (P61) and the output of the sixth inverter (INV6), respectively And the write word line control signal (WWLC); the source, gate and drain of the tenth PMOS transistor (P63) are connected to the power supply voltage (V _DD ) and the fifth inversion, respectively The output of the INV5 and the write word line control signal (WWLC); the source, gate and drain of the twelfth NMOS transistor (M61) are connected to the ground voltage and the fifth The output of the inverter (INV5) and the write word line control signal (WWLC); the input of the fifth inverter (INV5) is for receiving the write word line (WWL), and the first The input of the six inverter (INV6) is connected to the output of the fifth inverter (INV5). 7T dual-port static random access memory with high read/write speed as described in item 1 of the patent scope, which also includes a plurality of high voltage level control circuits (5), each row of memory crystals The cell is provided with a high voltage level control circuit (5) to increase the reading speed when reading logic 0. Each high voltage level control circuit (5) further includes: a sixth PMOS transistor (P51), a A seventh PMOS transistor (P52) and a fourth inverter (INV4); wherein the source, gate and drain of the sixth PMOS transistor (P51) are connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH); the source, gate and drain of the seventh PMOS transistor (P52) are respectively connected to a first high power supply voltage (V _DDH1 ), the output of the fourth inverter (INV4) and the high voltage node (VH); the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is Connect to the gate of the seventh PMOS transistor (P52). 7T dual-port static random access memory with high read/write speed as described in item 2 of the patent scope, which also includes a plurality of read word line control circuits (7), each row of memory The body cell is provided with a read word line control circuit (7) to further reduce the resistance of the read path when reading logic 0 and accelerate the discharge of the charge on the read bit line (RWL) To further improve the reading speed, each read word line control circuit (7) further includes: an eleventh PMOS transistor (P71), a twelfth PMOS transistor (P72), a thirteenth PMOS Transistor (P73), a thirteenth NMOS transistor (M71), a seventh inverter (INV7), an eighth inverter (INV8), the second highest power supply voltage (V _DDH2 ), a Read word line (RWL) and read word line control signal (RWLC); wherein the source, gate and drain of the eleventh PMOS transistor (P71) are connected to the first The second high power supply voltage (V _DDH2 ), the output of the seventh inverter (INV7) and the source of the twelfth PMOS transistor (P72); the source of the twelfth PMOS transistor (P72), The gate and the drain are connected to the drain of the eleventh PMOS transistor (P71), the output of the eighth inverter (INV8) and the read word line control signal (RWLC); the first The source, gate and drain of the thirteen PMOS transistor (P73) are connected to the power supply voltage (V _DD ), the output of the seventh inverter (INV7) and the read word line control respectively Signal (RWLC); the source, gate and drain of the thirteenth NMOS transistor (M71) are connected to the ground voltage, the output of the seventh inverter (INV7) and the read character, respectively Line control signal (RWLC); the input of the seventh inverter (INV7) is for receiving the read word line (RWL), and the input of the eighth inverter (INV8) is inverse to the seventh The output connection of the phase device (INV7). 7T dual-port static random access memory with high read/write speed as described in item 3 of the patent scope, wherein each precharge circuit (3) is composed of a third PMOS transistor (P31) And a precharge signal (P); wherein, the source, gate and drain of the third PMOS transistor (P31) are connected to the power supply voltage (V _DD ) and the precharge signal (P ) And the read bit line (RBL), so that during a pre-charge period, the pre-charge signal (P) of the logic low level is used to pre-charge the read bit line (RBL) to the The level of the power supply voltage (V _DD ); the standby start circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2) and The inverse standby mode control signal (/S) is composed of; wherein the source, gate and drain of the fifth PMOS transistor (P41) are connected to the power supply voltage (V _DD ) and the inversion respectively The standby mode control signal (/S) and the drain of the eleventh NMOS transistor (M41); the source, gate and drain of the eleventh NMOS transistor (M41) are respectively connected to the first low The voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) is connected to the gate of the eleventh NMOS transistor (M41). 7T dual-port static random access memory with high read/write speed as described in item 4 of the patent scope, where the storage node (A) originally stores logic 0, and writes logic 1 Write the initial instantaneous voltage (V _AWI ) to satisfy the following equation: V _AWI =V _DD ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 ) and V _AWI >V _TM12 where V _AWI represents the storage Node (A) stores the logic 0 and writes the initial instantaneous voltage of logic 1, R _M11 , R _M13 and R _M23 represent the first NMOS transistor (M11) and the third NMOS transistor (M13) respectively And the on-resistance of the sixth NMOS transistor (M23), and V _DD and V _TM12 represent the threshold voltage of the power supply voltage (V _DD ) and the second NMOS transistor (M12), respectively. For the 7T dual-port static random access memory with high read/write speed as described in item 5 of the patent scope, the second highest power supply voltage (V _DDH2 ) is set to meet the power supply voltage (V _DD ) and the sum of the threshold voltage (V _TM14 ) of the first reading transistor (M14) (ie V _DD +V _TM14 ) and the power supply voltage (V _DD ) and the third NMOS transistor (M13) The _smaller of the sum of the threshold voltage (V _TM13 ) (ie V _DD +V _TM13 ). 7T dual-port static random access memory with high read/write speed as described in item 6 of the patent scope, wherein the word line control circuit (6) for each write can be enabled when enabled It is further subdivided into two stages. In a first stage enabled by the write word line (WWL), the write word line control signal (WWLC) is set to be higher than the power supply voltage (V _DD ) The second highest power supply voltage (V _DDH2 ) is also increased to effectively increase the writing speed, and in a second stage after the first stage, the write word line control signal (WWLC) is used Pull back to the power supply voltage (V _DD ) to slow down write interference; wherein, the time between the second stage and the first stage of each write word line control circuit (6) is equal to The output of the fifth inverter (INV5) is sufficient to turn on the eighth PMOS transistor (P61), and the output to the sixth inverter (INV6) is sufficient to turn off the ninth PMOS transistor (P62) The time up to its value can be dynamically adjusted by the rising delay time of the sixth inverter (INV6). 7T dual-port static random access memory with high read/write speed as described in item 7 of the patent scope, where the read operation can be subdivided into two stages, one of the read operations The first stage is to effectively increase the reading speed by setting the second low voltage node (VL2) to a voltage lower than the ground voltage, and the second stage of the reading operation is The second low-voltage node (VL2) is set back to the ground voltage in order to reduce unnecessary power consumption; in the first stage of the read operation, the second low-voltage node (VL2) is initially read when reading logic 1 The instantaneous voltage (V _RVL2I ) must satisfy the following equation: V _RVL2I =RGND×R _M21 /(R _M21 +R _M24 +R _M25 ) and V _RVL2I >-V _TM12 to effectively prevent the interference of the semi-selected cell during reading, Where, V _RVL2I represents the initial instantaneous voltage of the second low voltage node (VL2) when reading logic 1, RGND represents the accelerated reading voltage, and R _M21 represents the conduction of the fourth NMOS transistor (M21) Resistance, R _M24 represents the on-resistance of the seventh NMOS transistor (M24), R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM12 represents the critical voltage of the second NMOS transistor (M12) . 7T dual-port static random access memory with high read/write speed as described in item 1 of the patent scope, wherein the first high power supply voltage (V _DDH1 ) is set higher than the power supply Voltage (V _DD ) but lower than the absolute value of the power supply voltage (V _DD ) and the critical voltage of the second PMOS transistor (P12) |V _TP12 |, that is, V _DD <V _DDH1 <V _DD +| V _TP12 |. 7T dual-port static random access memory with high read/write speed as described in item 1 of the patent scope, wherein the accelerated read voltage (RGND) in each control circuit (2) The absolute value |RGND| is set lower than the threshold voltage (V _TM12 ) of the second NMOS transistor (M12) in each memory cell (1), that is, |RGND|<V _TM12 .

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