TWI673712B - Seven-transistor dual port static random access memory with improved access speed - Google Patents

Abstract

The invention proposes a 7T dual-port static random access memory with high access speed, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby A start circuit (4), a plurality of high voltage level control circuits (5), a plurality of writing word line control circuits (6), and a plurality of reading word line control circuits (7). Thereby, in the writing mode, the combination of the plurality of control circuits (2) and the plurality of writing word line control circuits (6) can be used to prevent writing logic 1 from being difficult, and also effectively improve Write speed, and in the read mode, the plurality of control circuits (2), the plurality of high voltage level control circuits (5), and the plurality of read word line control circuits (7) The combination is used to increase the reading speed while avoiding unnecessary power consumption.

Description

7T dual-port static random access memory with high access speed

The invention relates to a 7T dual port static random access memory (SRAM) with high access speed, particularly to a 7T SRAM which can effectively improve the standby performance of the 7T SRAM and can effectively improve the read performance. SRAM with fast access speed and write speed, which can effectively reduce leakage current, reduce half-selected cell interference during reading, and avoid unnecessary power loss.

As shown in Figure 1a, the conventional static random access memory (SRAM) in the port includes a memory array. The memory array is composed of a plurality of memory blocks (MB _1). , MB ₂ etc.), each memory block is further composed of a plurality of rows of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word lines, WL ₁ , WL _2, etc.), each character line corresponds to a plurality of rows of memory One column in the unit cell; and multiple bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _m, etc.), each bit line pair corresponds to the multiple row memory cell One row, and each bit line pair is composed of a bit line (BL ₁ ... BL _m ) and a complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b is a schematic circuit diagram of a 6T port static random access memory (SRAM) cell. Among them, the PMOS transistors (P1) and (P2) are called load transistors and NMOS transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL BLB and BLB are bit line and complementary bit line, respectively. Since this port SRAM cell requires 6 transistors, and to read the logic 0, in order to avoid the initial instant of the read operation (initial instant) Another driving transistor is turned on, and the initial instantaneous voltage (V _AR ) read by node A must satisfy equation (1): V _AR = V _DD × (R _M1 ) / (R _M1 + R _M3 ) <V _TM2 (1) to prevent half-selected cell disturbance during reading, where V _AR represents the initial instantaneous voltage of node A and R _M1 and R _M3 respectively represent the NMOS transistor (M1 ) And the on-resistance of the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply voltage and the threshold voltage of the NMOS transistor (M2), which leads to driving the transistor The current drive capability ratio (ie, the cell ratio) between the body and the access transistor is usually set between 2.2 and 3.5 (please refer to US Patent No. US76060B2 of October 20, 1998, column 2 columns 8-10 Row).

Figure 1b shows the simulation results of HSPICE transient analysis during the write operation of the 6T-port static random access memory cell. As shown in Figure 2, it is simulated using TSMC 90nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a circuit diagram of a 5T SRAM cell with a single bit line. Compared with the 6T SRAM cell in Figure 1b, this 5T static The RAM cell has one transistor and one bit line less than the 6T SRAM cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2. And in the case of the channel width-to-length ratio of the NMOS transistors M1, M2, and M3, there is a problem that it is quite difficult to write a logic 1. Consider the case where node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transferred from the bit line (BL), the logic 0 previously written in node A is overwritten by the logic 1 The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 ) / (R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of node A, R _M1 and R _M3 represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3), respectively. Comparing equation (1) and equation (2), it can be seen that the initial instantaneous voltage (V _AW ) is less than the NMOS transistor (M2) ) Threshold voltage (V _TM2 ), so the operation of writing logic 1 cannot be completed. The simulation results of HSPICE transient analysis during the write operation of the 5T SRAM cell shown in Figure 3, as shown in Figure 4, are simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that the 5T SRAM cell with a single bit line has the problem of writing logic 1 quite difficult.

Next, we discuss the SRAM and dual-port architecture. The 6T SRAM cell in Figure 1b is the SRAM static-access memory (SRAM) crystal. For example, it uses two bit lines BL and BLB for reading and writing, that is, reading and writing are achieved through the same pair of bit lines, so that only reading or writing can be performed at the same time. Write operation, therefore, when you want to design dual-port static random access memory with simultaneous read and write capabilities, you need to add two more access transistors and another pair of bit lines (refer to Figure 5) Circuit, where WBL and WBLB are bit line pairs for writing, RBL and RBLB are bit line pairs for reading, WWL is a word line for writing, and RWL is a word line for reading), which makes the memory The area of the cell is greatly increased. If we can simplify the structure of the memory cell, so that one bit line is responsible for reading and the other bit line is responsible for writing. When taking the memory, the memory cell does not need to add two more transistors and a pair of bit lines, so the area of the memory cell will be much reduced. The traditional dual-port static random access memory cell The reason why this method is not adopted is that it is quite difficult to write a logic 1 as described above.

So far, many technologies for dual-port static random access memory cells with a single read bit line have been proposed, such as "Dual write wordline memory cell" (No. US9336863B2, May 105, proposed in Patent Document 1). Granted to Qualcomm Corporation on the 10th). It uses a two-stage write operation to avoid the problem of writing logic 1 due to the use of a single write bit line. The logic 1 is written in advance in the first stage of the write operation. In the second stage of the writing operation, it is decided whether to discharge the previously written logic 1 to logic 0 depending on the actual data written; the "Method of writing to and reading data from a three" "-dimensional two port register file" (No. 9275724B2, awarded to TSMC Corporation on March 1, 105), which uses two dedicated read NMOS transistors to achieve the read of the SRAM cell of a single read bit line Fetch operation, and the use of two access transistors and the need for complementary write bit lines during the write operation resulted in the lack of a large number of SRAM cell transistors; the “two-port static random” proposed in Patent Document 3 "Retrieving Memory" (No. TW I605551B, awarded to Xiuping University of Science and Technology on November 11, 106), which is designed by the combination of a control circuit and a high-voltage level control circuit. In the first stage of the read operation, the control circuit Reduce the potential of the original ground voltage node to less than the ground voltage, and cooperate with the high voltage level control circuit to reduce the resistance of the read path, and accelerate the discharge of the charge of a single read bit line to improve the read speed of the SRAM While In the second stage of the reading operation, the voltage lower than the ground voltage is changed back to the ground voltage to avoid unnecessary power consumption. Although these patents can effectively solve the problem of writing logic 1 caused by the use of a single write bit line, none of these patents take into account that the SRAM operating voltage will drop below 0.9 volts. As the temperature (PVT) changes, the write operation may not be completed within the specified time, so there is still room for improvement.

In view of this, the main object of the present invention is to propose a 7T dual-port static random access memory with high access speed, which can effectively solve the problem by a two-stage writing word line control circuit (6). When the operating voltage of the SRAM below nanometer drops below 0.9V, the problem that the writing time cannot meet the specifications is easily caused. The writing word line control circuit (6) is equivalent to the corresponding writing word line (WWL) enabled. In one stage, the corresponding writing word line control signal (WWLC) is set to the second highest power supply voltage (V _DDH2 ) which is higher than the power supply voltage (V _DD ) to effectively improve the writing speed. In the second stage after the first stage, the corresponding writing word line control signal (WWLC) is pulled back to the power supply voltage (V _DD ) to slow down write interference.

A secondary object of the present invention is to provide a 7T dual-port static random access memory with high access speed, which can be read by the read word line control circuit (7) to correspond to the read word line ( In the first stage of enabling, the corresponding read word line control signal (RWLC) is set to the second highest power supply voltage (V _DDH2 ) which is higher than the power supply voltage (V _DD ) to further Reduce the resistance of the read path and accelerate the discharge of the charge on the read bit line (RWL) to effectively improve the read speed. In the second phase after the first phase, the corresponding read The word line control signal (RWLC) is pulled back to the power supply voltage (V _DD ) to mitigate read interference.

The invention proposes a 7T dual-port static random access memory with high access speed. Body, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start circuit (4), a plurality of high voltage level control circuits (5), A plurality of writing word line control circuits (6) and a plurality of reading word line control circuits (7). Thereby, in the writing mode, the combination of the plurality of control circuits (2) and the plurality of writing word line control circuits (6) can be used to prevent writing logic 1 from being difficult, and also effectively improve Write speed, and in the read mode, the plurality of control circuits (2), the plurality of high voltage level control circuits (5), and the plurality of read word line control circuits (7) The combination is used to increase the reading speed while avoiding unnecessary power consumption.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧ pre-charge circuit

4‧‧‧ Standby start circuit

5‧‧‧high voltage level control circuit

6‧‧‧writing word line control circuit

7‧‧‧reading character line control circuit

/ WC‧‧‧ Inverted write control signal

WC‧‧‧ write control signal

P11‧‧‧The first PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧The first NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧Third NMOS transistor

A‧‧‧Storage Node

B‧‧‧ Inverted Storage Node

C‧‧‧node

M14‧‧‧First reading transistor

M15‧‧‧Second reading transistor

WBL‧‧‧Bit line for writing

WWL‧‧‧writing character line

RBL‧‧‧Bit line for reading

RWL‧‧‧Read Character Line

WWLC‧‧‧writing word line control signal

RWL‧‧‧Read Character Line Control Signal

S‧‧‧Standby mode control signal

/ S‧‧‧ Inverted standby mode control signal

VL1‧‧‧The first low voltage node

VL2‧‧‧Second Low Voltage Node

M21‧‧‧Fourth NMOS transistor

M22‧‧‧Fifth NMOS transistor

M23‧‧‧sixth NMOS transistor

M24‧‧‧Seventh NMOS transistor

M25‧‧‧eighth NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧Tenth NMOS Transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

INV3‧‧‧Third Inverter

D1‧‧‧first delay circuit

P31‧‧‧Third PMOS transistor

P‧‧‧Pre-charge signal

M41‧‧‧Twelfth NMOS transistor

P41‧‧‧Fourth PMOS transistor

D2‧‧‧Second Delay Circuit

V _DD ‧‧‧ Power supply voltage

V _DDH1 ‧‧‧ Highest power supply voltage

V _DDH2 ‧‧‧ the second highest power supply voltage

P51‧‧‧Fifth PMOS transistor

P52‧‧‧Sixth PMOS transistor

INV4‧‧‧Fourth Inverter

VH‧‧‧High Voltage Node

P61‧‧‧Seventh PMOS transistor

P62‧‧‧eighth PMOS transistor

P63‧‧‧9th PMOS transistor

M61‧‧‧Thirteenth NMOS Transistor

INV5‧‧‧Fifth Inverter

INV6‧‧‧Sixth Inverter

P71‧‧‧Tenth PMOS transistor

P72‧‧‧11th PMOS transistor

P73‧‧‧The twelfth PMOS transistor

M71‧‧‧fourteenth NMOS transistor

INV7‧‧‧Seventh Inverter

INV8‧‧‧ Eighth Inverter

BLB‧‧‧ Complementary Bit Line

BLB ₁ … BLB _m ‧‧‧ complementary bit line

MB ₁ … MB _k ‧‧‧Memory block

WL ₁ … WL _n ‧‧‧Character line

BL ₁ … BL _m ‧‧‧bit line

M1… M4‧‧‧NMOS transistor

P1… P2‧‧‧PMOS transistor

I ₁ , I ₂ , I ₃ , I ₄ ‧‧‧ Leakage current

Figure 1a shows a conventional static random access memory cell; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; Figure 2 shows a conventional 6T static random access memory cell Figure 3 is a timing diagram of a conventional 5T SRAM cell; Figure 4 is a timing diagram of a conventional 5T SRAM cell; FIG. 5 is a circuit diagram showing a conventional 8T dual-port static random access memory cell; FIG. 6 is a circuit diagram showing a circuit proposed by a preferred embodiment of the present invention; FIG. 7 is a diagram showing the present invention of FIG. 6 Simplified circuit diagram of the preferred embodiment during writing; FIG. 8 shows a simplified circuit diagram of the preferred embodiment of the present invention during reading in FIG. 6; FIG. 9 shows a preferred embodiment of the present invention in FIG. 6 Simplified circuit diagram during standby.

According to the above main object, the present invention proposes a 7T dual-port static random access memory with high access speed, which mainly includes a memory array. The memory array is composed of a plurality of memory cells and a plurality of rows. The unit cell is composed of a plurality of memory cell units (1) and a plurality of control circuits (2). Each control unit is provided with a control circuit. (2); a plurality of pre-charging circuits (3), each row of memory cells is provided with a pre-charging circuit (3); a standby start-up circuit (4), the standby start-up circuit (4) promotes the fast entry of dual-port SRAM Standby mode to effectively improve the standby performance of dual-port SRAM; a plurality of high-voltage level control circuits (5), each column of memory cells is provided with a high-voltage level control circuit (5) to read logic 0 Reduce the resistance of the read path to improve the read speed; a plurality of writing word line control circuits (6), each column of the memory cell is provided with a writing word line control circuit (6) to When logic 0 is written to or written from logic 1, In the first stage of enabling the corresponding writing word line (WWL), the corresponding writing word line control signal (WWLC) is set to the second highest power supply voltage higher than the power supply voltage (V _DD ). (V _DDH2 ) to effectively improve the writing speed; and a plurality of read word line control circuits (7), each column of memory cells is provided with a read word line control circuit (7) to read When logic 0 is taken, in the first stage where the corresponding read word line (RWL) is enabled, the corresponding read word line control signal (RWLC) is set to be higher than the power supply voltage (V _DD ). The second high power supply voltage (V _DDH2 ) to further reduce the resistance of the read path and accelerate the discharge of the charge on the read bit line (RWL), thereby effectively improving the read speed.

For ease of explanation, the 7T dual-port static random access memory with high access speed shown in Figure 6 consists of only one memory cell (1), one writing word line (WWL), one Write bit line (WBL), read word line (RWL), read bit line (RBL), a control circuit (2), a precharge circuit (3), a standby start Circuit (4), A high voltage level control circuit (5), a writing word line control circuit (6), and a reading word line control circuit (7) are described as examples. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor) Crystal P12 and a second NMOS transistor M12), a third NMOS transistor (M13), a first reading transistor (M14), and a second reading transistor (M15), among which, The first inverter and the second inverter are connected by mutual coupling, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the second inverter The output of the phase inverter (node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the second inverter The output (node B) is used to store the inverted data of the SRAM cell.

The first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11) of the memory cell (1) is connected to a power supply voltage (V _DD ) and a first Between the low voltage node (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected between a high voltage node (VH) and a second low Between the voltage node (VL2), the source, gate and drain of the first reading transistor (M14) are connected to the drain and reading of the second reading transistor (M15), respectively. A word line (RWL) and the read bit line (RBL) are used, and a source, a gate, and a drain of the second read transistor (M15) are respectively connected to the second low-voltage node (VL2), the output of the second inverter (ie, node B) and the source of the first reading transistor (M14).

Please refer to FIG. 6 again. The control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS Transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control signal (RC), a third inverter (INV3), a first delay Circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), an inverted write control signal (/ WC), a standby mode control signal (S), and an inverted standby mode control Signal (/ S). The source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverting standby mode control signal (/ S) and the second low voltage node (VL2); the fifth The source, gate, and drain of the NMOS transistor (M22) are connected to the first low-voltage node (VL1), the standby mode control signal (S), and the second low-voltage node (VL2); the first The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) The gate, and drain are connected to the drain, the read control signal (RC), and the second low voltage node (VL2) of the eighth NMOS transistor (M25); the eighth NMOS transistor (M25) The source, gate, and drain are connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1), and the source of the seventh NMOS transistor (M24); the first The delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV3) is for receiving The read control (RC), and the output is connected to the input of the first delay circuit (D1); the source, gate and drain of the ninth NMOS transistor (M26) are respectively connected to the ground voltage and the tenth NMOS The drain of the transistor (M27) and the first low voltage node (VL1); the source, gate, and drain of the tenth NMOS transistor (M27) are connected to the ground voltage and the write control signal, respectively. (WC) and the gate of the ninth NMOS transistor (M26); and the source, gate and drain of the eleventh NMOS transistor (M28) are connected to the inverting standby mode control signal, respectively (/ S), the inverted write control signal (/ WC) and the drain of the tenth NMOS transistor (M27). It is worth noting here that the inverted standby mode control signal (/ S) is obtained by the standby mode control signal (S) via an inverter, and the inverted write control signal (/ WC) is obtained by A write control signal (WC) is obtained via another inverter.

Among them, the drain of the eleventh NMOS transistor (M28), the drain of the tenth NMOS transistor (M27), and the gate of the ninth NMOS transistor (M26) are connected together to form a node ( C), when the write control signal (WC) is a logic low level, the voltage level of the node (C) is the logic level of the inverted standby mode control signal (/ S), and when the write control signal When the signal (WC) is a logic high level, the voltage level of the node (C) is the ground voltage, thereby effectively preventing the write control signal (WC) from being a logic high level due to unexpected factors during standby operation. Alignment leads to the problem of erroneous writing. Furthermore, since the voltage level of the node (C) during the writing operation is constant to the ground voltage, it has a highly stable writing operation. In addition, due to the hold mode, the The voltage level of node (C) is the voltage level of the power supply voltage (V _DD ) _minus the threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28), so it enters the write mode in the following ( At this time, WC is a logic high level), because the charge stored in the node (C) must be discharged enough to close the node (C). The gate of the ninth NMOS transistor (M26), hence making both the writing operation is completed more quickly.

The control circuit (2) is designed to control the voltage levels of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes. In the write mode, the unit cell is selected. The source voltage (that is, the first low-voltage node VL1) of the driving transistor (that is, the first NMOS transistor M11) that is closer to the bit line (WBL) for writing is set to be one higher than the ground voltage The predetermined voltage (i.e., the gate-source voltage V _{GS (M23) of} the sixth NMOS transistor (M23)) and the source voltage of another driving transistor (i.e., the second NMOS transistor M12) in the selected cell ( That is, the second low voltage node VL2) is set to a ground voltage in order to prevent the problem of writing logic 1 from being difficult.

In the first stage of the read mode, the source voltage (that is, the second lowest value) of the driving transistor (that is, the second NMOS transistor M12) that is closer to the read bit line (RBL) in the selected cell is selected. The voltage node VL2) is set to a voltage lower than the ground voltage, and the second low voltage node (VL2), which is lower than the ground voltage, can effectively improve the reading speed, and in the second stage of the reading mode, The source voltage of the driving transistor (ie, the second NMOS transistor M12) in the selected unit cell that is closer to the read bit line (RBL) is set back to the ground voltage in order to reduce unnecessary power consumption. The read mode is The time interval between the second stage and the first stage is equal to that when the read control signal (RC) changes from a logic low level to a logic high level, and reaches the gate voltage of the eighth NMOS transistor (M25). The time sufficient to turn off the eighth NMOS transistor (M25) can be adjusted by the falling delay time of the third inverter (INV3) and the delay time provided by the first delay circuit (D1).

In the standby mode, the source voltages of the driving transistors in all memory cells are set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current; while in the hold mode, the voltages in the memory cells are set to The source voltage of the driving transistor is set to the ground voltage in order to maintain the original holding characteristics. The first low voltage node (VL1) and the second low voltage node VL2 are in a write mode, a read mode, a standby mode, and a hold mode. The detailed operating voltage levels are shown in Table 1 below.

The inverted write control signal (/ WC) in Table 1 is an inverted signal of a write control signal (WC), and the write control signal (WC) is a write enable signal (Write Enable (Referred to as WE) and the corresponding AND gate result of the writing word line (WWL) signal, at this time only the writing enable signal (WE) and the corresponding writing word line When the (WWL) signal is a logic high level, the write control signal (WC) is a logic high level; the read control signal (RC) is a read enable signal (RE) and the corresponding read Take the result of the AND operation of the word line (RWL) signal. It is worth noting here that, for non-selected word lines and non-selected positioning element lines, the floating state is set, and the read control signal (RC) during the non-read mode is set to the acceleration. The level of the voltage (RGND) is read to prevent the leakage current of the seventh NMOS transistor (M24).

Please refer to Fig. 6. The precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P). The source and gate of the third PMOS transistor (P31) And the drain are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit line (RBL), in order to facilitate the precharge period, The precharge signal (P) is used to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V _DD ).

Please refer to FIG. 6 again, the standby start circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2), and the inverting standby Mode control signal (/ S). The source, gate, and drain of the fourth PMOS transistor (P41) are connected to the power supply voltage (V _DD ), the inverting standby mode control signal (/ S), and the twelfth NMOS transistor. The drain of (M41); the source, gate and drain of the twelfth NMOS transistor (M41) are connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) respectively And the drain of the fourth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/ S), and the output of the second delay circuit (D2) is Connected to the gate of the twelfth NMOS transistor (M41).

Please refer to FIG. 6 again. The high voltage level control circuit (5) is composed of a fifth PMOS transistor (P51), a sixth PMOS transistor (P52), and a fourth inverter (INV4). , Wherein the source, gate and drain of the fifth PMOS transistor (P51) are connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH), respectively, The source, gate and drain of the sixth PMOS transistor (P52) are connected to a first high power supply voltage (V _DDH1 ), the output of the fourth inverter (INV4) and the high voltage node, respectively. (VH), and the input of the fourth inverter (INV4) is for receiving the read control signal (RC), and the output is connected to the drain of the sixth PMOS transistor (P52). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage Between the node (VH) and the second low voltage node (VL2).

Please refer to FIG. 6 again. The writing word line control circuit (6) is composed of a seventh PMOS transistor (P61), an eighth PMOS transistor (P62), and a ninth PMOS transistor (P63). , A thirteenth NMOS transistor (M61), a fifth inverter (INV5), a sixth inverter (INV6), a second highest power supply voltage (V _DDH2 ), a character for writing A line (WWL) and a writing word line control signal (WWLC). The source, gate and drain of the seventh PMOS transistor (P61) are connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (INV5) and the eighth PMOS, respectively. The source of the transistor (P62); the source, gate, and drain of the eighth PMOS transistor (P62) are connected to the drain of the seventh PMOS transistor (P61) and the sixth inverter, respectively. The output of (INV6) and the writing word line control signal (WWLC); the source, gate, and drain of the ninth PMOS transistor (P63) are connected to the power supply voltage (V _DD ), The output of the fifth inverter (INV5) and the writing word line control signal (WWLC); the source, gate, and drain of the thirteenth NMOS transistor (M61) are connected to the write respectively The input word line control signal (WWLC), the output of the fifth inverter (INV5) and the ground voltage; the input of the fifth inverter (INV5) is for receiving the write word line (WWL ), And the input of the sixth inverter (INV6) is connected to the output of the fifth inverter (INV5).

The writing word line control circuit (6) uses a two-stage operation when it is enabled to effectively solve the problem that the writing time cannot meet the specifications when the operating voltage drop of the SRAM below 10 nm is below 0.9. In the first stage of the enabled word line (WWL), the writing word line control signal (WWLC) is set to the second highest power supply voltage (V _DD ) which is higher than the power supply voltage (V _DD ). V _DDH2 ) to effectively increase the writing speed, and in the second stage after the first stage, the writing word line control signal (WWLC) is pulled back to the power supply voltage (V _DD ), In order to reduce write interference, the time interval between the second phase and the first phase of the write word line control circuit (6) is equal to the output of the fifth inverter (INV5) enough to turn on the The time from the seventh PMOS transistor (P61) counts until the output of the sixth inverter (INV6) is sufficient to turn off the eighth PMOS transistor (P62), and its value can be determined by the sixth inverter (INV6) to adjust the rise delay time.

Please refer to FIG. 6 again. The read word line control circuit (7) is composed of a tenth PMOS transistor (P71), an eleventh PMOS transistor (P72), and a twelfth PMOS transistor ( P73), a fourteenth NMOS transistor (M71), a seventh inverter (INV7), an eighth inverter (INV8), the second high power supply voltage (V _DDH2 ), a read A word line (RWL) and a read word line control signal (RWLC). The source, gate and drain of the tenth PMOS transistor (P71) are connected to the second high power supply voltage (V _DDH2 ), the output of the seventh inverter (INV7) and the eleventh The source of the PMOS transistor (P72); the source, gate, and drain of the eleventh PMOS transistor (P72) are connected to the drain and eighth of the tenth PMOS transistor (P71), respectively. The output of the inverter (INV8) and the read word line control signal (RWLC); the source, gate and drain of the twelfth PMOS transistor (P73) are connected to the power supply voltage (V _DD ), the output of the seventh inverter (INV7) and the read word line control signal (RWLC); the source, gate and drain of the fourteenth NMOS transistor (M71) are connected respectively To the read word line control signal (RWLC), the output of the seventh inverter (INV7) and the ground voltage; the input of the seventh inverter (INV7) is for receiving the read character Line (RWL), and the input of the eighth inverter (INV8) is connected to the output of the seventh inverter (INV7).

The read word line control circuit (7) uses a two-stage operation when it is enabled, and in the first stage of the read word line (RWL) enable, the read word line control signal (RWLC) is set to the second highest power supply voltage (V _DDH2 ) which is higher than the power supply voltage (V _DD ) to effectively improve the reading speed, and in the second phase after the first phase, then Pull the read word line control signal (RWLC) back to the power supply voltage (V _DD ) to slow down read disturbance; wherein, the second word line control circuit (7) of the read The period between the phase and the first phase is calculated from the time when the output of the seventh inverter (INV7) is sufficient to turn on the tenth PMOS transistor (P71), and reaches the time of the eighth inverter (INV8). The output is long enough to turn off the eleventh PMOS transistor (P72), and its value can be adjusted by the rising delay time of the eighth inverter (INV8).

The working principle of the preferred embodiment of the present invention shown in FIG. 6 is as follows:

(I) write mode

Before the write operation starts, the write control signal (WC) is at a logic low level, so that the eleventh NMOS transistor (M28) is turned on, and the tenth NMOS transistor (M27) is turned off (OFF) ), Since the inverted standby mode control signal (/ S) is at a logic high level, the drain of the eleventh NMOS transistor (M28) is at a logic high level, and the logic high level is at the eleventh NMOS The drain of the transistor (M28) will turn on the ninth NMOS transistor (M26) and make the low voltage node (VL1) a ground voltage.

During the write operation period, the write control signal (WC) is at a logic high level, so that the tenth NMOS transistor (M27) is turned on and the eleventh NMOS transistor (M28) is drained. The electrode is grounded. The grounding voltage causes the ninth NMOS transistor (M26) to turn off, and makes the low voltage node (VL1) equal to the gate-source voltage V _{GS (M26) of} the sixth NMOS transistor (M23 ₎ . This can effectively prevent the problem of writing logic 1 from being difficult. FIG. 7 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during a writing period.

The following describes how the writing operation of the preferred embodiment of the present invention shown in FIG. 7 is completed according to four writing states.

(1) Node A originally stored logic 0, but now wants to write logic 0:

Before the writing operation occurs (the writing word line control signal WWLC is a ground voltage), the first NMOS transistor (M11) is turned on. Since the first NMOS transistor (M11) is ON, when the writing operation is started, the writing word line (WWL) changes from Low (ground voltage) to High (power supply voltage V _DD ). When the voltage of the word line control signal (WWLC) for writing is greater than the threshold voltage of the third NMOS transistor (M13) (that is, the access transistor), the third NMOS transistor (M13) is turned off (OFF). ) Is turned on (ON). At this time, because the bit line for writing (WBL) is a ground voltage, the node A will be discharged, and a logic 0 writing operation is completed until the writing cycle ends.

(2) Node A originally stored logic 0, but now wants to write logic 1:

Before the writing operation occurs (the writing word line control signal WWLC is a ground voltage), the first NMOS transistor (M11) is turned on. It is worth noting here that because the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line control signal (WWLC) changes from Low (ground voltage) to High. The voltage at the node A will slightly increase due to the parasitic capacitance coupling effect following the writing word line control signal (WWLC). When the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON At this time, because the writing bit line (WBL) is the voltage level of the power supply voltage (V _DDH ), and because the first NMOS transistor (M11) is still ON and the node B is still at the voltage level The initial state of the voltage level of the power supply voltage (V _DD ) must be near, so the first PMOS transistor (P11) is still OFF, and the initial instantaneous voltage (V _AWI ) written by the node A ) Satisfies equation (3): V _AWI = V _DD × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 )> V _TM12 (3) where V _AWI represents the initial instantaneous voltage of node A R _M13 represents the on-resistance of the third NMOS transistor (M13), R _M11 represents the on-resistance of the first NMOS transistor (M11), R _M23 represents the on-resistance of the sixth NMOS transistor (M23), and V _DD and V _TM12 represent the power supply voltage (V _DD ) and the threshold voltage of the second NMOS transistor (M12), respectively. Since a voltage level equal to the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23) is provided at the first low voltage node (VL1), the voltage level of node A can be easily set. The quasi-setting is much higher than the voltage level of the node A of the conventional 5T SRAM cell in FIG. 4. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), so that the node B is discharged to a lower voltage level. The lower voltage level of the node B will make the The on-resistance (R _M11 ) of the first NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A Standard, the higher voltage level of the node A will pass through the second inverter (consisting of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B presents a lower voltage level , The lower voltage level of the node B will pass through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, According to this cycle, the node A can be charged to the power supply voltage (V _DD ), and the writing operation of the logic 1 is completed.

Wherein, the first low voltage node (VL1) originally stores logic 0 at node A, and during the writing of logic 1, it has a gate-source voltage V _{GS (M23)} equal to the sixth NMOS transistor (M23). Voltage level, and after the logic 1 is written, it will be at the ground voltage level due to discharge through the ninth NMOS transistor (M26).

It is worth noting here that the present invention uses a two-stage writing word line control circuit (6) to effectively solve the SRAM operation voltage drop below 0.9nm to below 0.9V, which easily causes the write time to fail to meet the specifications. In the first stage of enabling the writing word line (WWL), the writing word line control circuit (6) sets the writing word line control signal (WWLC) more than the The power supply voltage (V _DD ) is still higher than the second highest power supply voltage (V _DDH2 ). Since the logic 0 was originally stored in node A and the logic 1 was initially written, the third NMOS transistor (M13) works at Saturation area, the current in the saturation area is proportional to the square of the gate-source voltage V _{GS (M13)} after deducting its threshold voltage V _TM13 , so the word line control signal (WWLC) During the first stage, which is set to be higher than the power supply voltage (V _DD ) and the second high power supply voltage (V _DDH2 ), the speed of writing logic 1 can be effectively accelerated; in addition, in order to slow down the write period, The interference phenomenon of the semi-selected unit cell, during the second stage after the first stage, the writing word The element line control signal (WWLC) pulls back the voltage level of the power supply voltage (V _DD ), wherein the time interval between the second stage and the first stage of the word line control circuit (6) for writing is separated Is equal to the time when the output of the fifth inverter (INV5) is sufficient to turn on the seventh PMOS transistor (P61), and the output of the sixth inverter (INV6) is sufficient to turn off the eighth PMOS transistor. The time until (P62) can be adjusted by the rising delay time of the sixth inverter (INV6).

(3) Node A originally stored logic 1, but now wants to write logic 1:

Before the writing operation occurs (the writing word line control signal WWLC is a ground voltage), the first PMOS transistor (P11) is turned on. When the writing word line control signal (WWLC) changes from Low (ground voltage) to High, the node A is the voltage level of the power supply voltage (V _DD ), and the writing bit line (WBL) ) Is the voltage level of the power supply voltage (V _DD ), so when the second high power supply voltage (V _DDH2 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD) ) And the sum of the threshold voltage V _TM13 of the third NMOS transistor (M13), that is, V _DD <V _DDH2 <V _DD + V _TM13 (4) will cause the third NMOS transistor (M13) to remain off. (OFF) state; at this time, because the first PMOS transistor (P11) is still ON, the voltage of the node A is maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stored logic 1, but now wants to write logic 0:

Before the writing operation occurs (the writing word line control signal WWLC is a ground voltage), the first PMOS transistor (P11) is turned on. When the writing word line control signal (WWLC) changes from Low (ground voltage) to High, and the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13) At this time, the third NMOS transistor (M13) changes from OFF to ON. At this time, because the write bit line (WBL) is Low (ground voltage), the node A and the The first low voltage node (VL1) discharges and completes the logic 0 writing operation until the end of the writing cycle.

It is worth noting here that when node A is written to logic 1 by logic 0 and logic 0 is written to logic 1, the third NMOS transistor (M13) operates in the saturation region, and the current in the saturation region is related to its gate-source. The voltage level of the pole voltage V _{GS (M13)} is proportional to the square of the threshold voltage after deducting the threshold voltage. Therefore, the writing word line control circuit (6) is applied to the writing word line ( In the first stage of enabling (WWL), the writing word line control signal (WWLC) is set to the second highest power supply voltage (V _DDH2 ) which is higher than the power supply voltage (V _DD ), which is effective. Accelerate the writing speed of node A from logic 0 to logic 1 and from logic 1 to logic 0.

(II) read mode

Before the read operation starts, the read control signal (RC) and the write control signal (WC) are at logic low levels, and the inverted standby mode control signal (/ S) and the inverted write control signal (/ WC) are logic high levels, making the eleventh NMOS transistor (M28) on, and turning off the tenth NMOS transistor (M27), so the drain of the eleventh NMOS transistor (M28) At the logic high level, the drain of the eleventh NMOS transistor (M28) at the logic high level will turn on the ninth NMOS transistor (M26) and make the first low voltage node (VL1) a ground voltage. On the other hand, because the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off, and the eighth NMOS transistor (M25) is turned on.

It is worth noting here that during the pre-charging period before the read operation starts, the pre-charging signal (P) is at a logic low level, thereby pre-charging the corresponding read bit line (RBL) to The level of the power supply voltage (V _DD ), but because, for example, the operating voltage of a process technology below 10 nanometers will drop below 0.9 volts will cause a reduction in the reading speed and fail to meet the specifications. Therefore, the present invention proposes two Phased read control is used to increase read speed and meet specifications while avoiding unnecessary power loss.

The preferred embodiment of the present invention shown in FIG. 6 uses a two-stage read control to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the read operation, the read control The signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the second low voltage node (VL2) is approximately grounded. The accelerated read voltage (RGND) whose voltage is low, and the accelerated read voltage (RGND) which is lower than the ground voltage can effectively improve the reading speed.

In the second phase of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still on, but at this time the eighth NMOS transistor ( M25) is turned off, so the second low voltage node (VL2) will be grounded via the fourth NMOS transistor (M21) that is turned on (because the inverting standby mode control signal (/ S) is logic during read operation) High level), which can effectively reduce unnecessary power consumption. It is worth noting here that the time interval between the second phase and the first phase of the read operation is equal to the transition of the read control signal (RC) from a logic low level to a logic high level, and reaches the first The gate voltage of the eight NMOS transistor (M25) is enough time to turn off the eighth NMOS transistor (M25), and its value can be determined by the falling delay time of the third inverter (INV3) and the first delay circuit. (D1) Adjust the delay time provided. Furthermore, the fourth NMOS transistor (M21) is in a conducting state regardless of whether it is the first stage or the second stage of the read operation (because the inverted standby mode control signal (/ S) is logic during the read operation High level). FIG. 8 is a simplified circuit diagram of the preferred embodiment of the present invention shown in FIG. 6 during reading.

Next, the preferred embodiment of the present invention shown in FIG. 8 will be described according to two read states. Why use the control circuit (2), the high voltage level control circuit (5), and the read word line control circuit (7) to improve the reading speed and avoid unnecessary power loss.

(1) Read logic 1 (node A stores logic 1):

Before the read operation occurs, the first NMOS transistor (M11) is OFF and the second NMOS transistor (M12) is ON. The node A and the node B are the power supply voltages, respectively. (V _DD ) and ground voltage, and the read bit line (RBL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading period, since the node B is at the ground voltage, the second reading transistor (M15) is turned off, thereby effectively maintaining the reading bit line (RBL) as the power supply voltage ( V _DD ) until the end of the read cycle, the read logic 1 operation is successfully completed. It is worth noting here that in the first stage of the read operation, the initial instantaneous voltage (V _RVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy equation (5): V _RVL2I = RGND × R _M21 / (R _M21 + R _M24 + R _M25 )>-V _TM12 (5) to effectively prevent half-selected cell interference during reading, where V _RVL2I represents the second low voltage node ( VL2) read the initial instantaneous voltage when reading logic 1, RGND represents the accelerated read voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), and R _M24 represents the seventh NMOS transistor (M24) ), R _M25 represents the on resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12); and in the second stage of the read operation, The voltage (V _RVL2 ) of the second low voltage node (VL2) can be represented by equation (6). V _RVL2 = ground voltage (6). This can effectively reduce unnecessary power consumption. Furthermore, in order to effectively reduce the half-selected cell interference and effectively reduce the leakage current during reading, the accelerated reading voltage (RGND), which is lower than the ground voltage, must be set to the value of the second low voltage node (VL2). The voltage level is lower than the threshold voltage (V _TM12 ) of the second NMOS transistor (M12), and the absolute value of the accelerated read voltage (RGND), which is lower than the ground voltage, can be set more strictly | RGND | The threshold voltage (V _TM12 ) of the second NMOS transistor (M12), that is, | RGND | <V _TM12 (7), where | RGND | and V _TM12 represent the absolute value of the accelerated read voltage and the first The threshold voltage of two NMOS transistors (M12).

(2) Read logic 0 (node A stores logic 0):

Before the read operation occurs, the first NMOS transistor (M11) is ON and the second NMOS transistor (M12) is OFF. The node A and the node B are ground voltage and the The power supply voltage (V _DD ), and the read bit line (RBL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3). During the reading period, since the node B is the first high power supply voltage (V _DDH1 ), and the second low voltage node (VL2) is a voltage lower than the ground voltage, the present invention _applies the first high power supply voltage (V _DDH1 ) is set to be higher than the absolute value of the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the threshold voltage of the second PMOS transistor (P12) | V _TP12 | That is, V _DD <V _DDH1 <V _DD + | V _TP12 | (8)

Among them, | V _TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12). Therefore, by increasing the conduction degree of the second reading transistor (M15), the reading logic 0 can be improved. Speed, and the second low voltage node (VL2), which is lower than the ground voltage, is used to further improve the reading speed.

Furthermore, during the reading period, the reading word line control circuit (7) is used to control the reading word line in the first stage of enabling the reading word line (RWL). The signal (RWLC) is set to the second highest power supply voltage (V _DDH2 ) which is higher than the power supply voltage (V _DD ) to further reduce the resistance of the read path and accelerate the read bit line (RWL Discharge of the charge on) to further increase the reading speed, and in the second stage after the first stage, the read word line control signal (RWLC) is pulled back to the power supply voltage (V _DD ) to reduce read interference. It is worth noting here that the second high power supply voltage (V _DDH2 ) is set to be higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the first reading transistor (M14) The sum of V _TM14 of the critical voltage, that is, V _DD <V _DDH2 <V _DD + V _TM14 (9) Comparing equation (4) and equation (9), it can be seen that the second highest power supply voltage (V _DDH2 ) Must satisfy the sum of the power supply voltage (V _DD ) and the threshold voltage V _TM14 of the first reading transistor (M14) (V _DD + V _TM14 ) and the power supply voltage (V _DD ) and the third The _smaller of the sum of the V _TM13 threshold voltage (V _DD + V _TM13 ) of the NMOS transistor (M13).

(III) Standby mode

First, explain how the standby startup circuit (4) in Figure 6 promotes the dual-port SRAM to enter the standby mode quickly, so as to effectively improve the standby performance of the SRAM: first, before entering the standby mode, the inverted standby mode control signal (/ S) It is logic High. The inverted standby mode control signal (/ S) of the logic High turns off the fourth PMOS transistor (P41) and turns on the twelfth NMOS transistor (M41). After entering the standby mode, the inverting standby mode control signal (/ S) is logic Low, and the inverting standby mode control signal (/ S) of logic low causes the fourth PMOS transistor (P41) to be turned on (ON) , But in the initial period of the standby mode (the initial period is equal to the inversion of the standby mode control signal (/ S) from logic High to logic Low counting from the gate voltage to the twelfth NMOS transistor (M41) The time until the twelfth NMOS transistor (M41) is turned off, which can be adjusted by a delay time provided by the second delay circuit (D2)), the twelfth NMOS transistor (M41) is still on (ON), so that the first low-voltage node (VL1) can be quickly charged to the sixth NMOS transistor The voltage level of the threshold voltage (V _TM23 ) of the body (M23), that is, the dual-port SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (M41) is turned off and stops supplying current.

Please refer to FIG. 6. In the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/ S) is a logic low level. The logic low level is the inverted standby The mode control signal (/ S) can turn off the fourth NMOS transistor (M21) in the control circuit (2), and the standby mode control signal (S) at the logic high level makes the fifth The NMOS transistor (M22) is turned on. At this time, the fifth NMOS transistor (M22) is used as an equalizer. Therefore, the fifth NMOS transistor (M22) can be turned on. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are all equal to the voltage levels of the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V _TM23 ). FIG. 9 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during the standby period.

Next, how to reduce the leakage current in the standby mode of the present invention will be described. Please refer to FIG. 9. FIG. 9 describes the respective leakage currents I ₁ generated when the embodiment of the present invention is in the standby mode. , I ₂ , I ₃ , I ₄ , where it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is logic Low (It is worth noting here that due to the first low voltage in standby mode The voltage levels of the node (VL1) and the second low voltage node (VL2) are maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so node A is a logic low voltage The level is also maintained at the voltage level of the V _TM23 ), and the output of the second inverter (ie, node B) is logic High (power supply voltage V _DD ). Please refer to the conventional 8T dual-port SRAM in FIG. 5 and the embodiment of the present invention in FIG. 9 to explain the leakage current of the dual-port static random access memory proposed in the present invention and the conventional 8T dual-port SRAM in FIG. 5. For comparison, first, regarding the leakage current I ₁ flowing through the third NMOS transistor (M13), since the voltage level of the node A is maintained at the voltage level of the V _TM23 in the standby mode of the present invention, and it is assumed that the write The input word line (WWL) is set to the ground voltage in the standby mode, and the write bit line (WBL) is set to the power supply voltage (V _DD ) in the standby mode. The gate-source voltage (V _GS ) of the three NMOS transistor (M13) is negative. In contrast, in the standby mode, the gate-source voltage (V _GS ) of the NMOS transistor (M3) of the traditional 8T dual-port SRAM shown in Figure 5 It is equal to 0. According to the Gate Induced Drain Leakage (GIDL) effect or the results of Figure 3 (A) and 3 (B) of US6865119 patent case on March 8, 2005, it can be known that for NMOS power For the crystal, the sub-critical current when the gate-source voltage is -0.1 volts is about 1% of the sub-critical current when the gate-source voltage is 0 volts. Therefore, the leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention caused by the GIDL effect is much smaller than the NMOS transistor (M3) of the conventional 8T dual-port SRAM in FIG. 5; furthermore, According to the present invention, the drain-source voltage (V _DS ) of the third NMOS transistor (M13) is the power supply voltage (V _DD ) _minus the voltage level of the V _TM23 , in contrast to the traditional 8T dual-port SRAM in FIG. 5. The drain-source voltage (V _DS ) of the NMOS transistor (M3) is equal to the power supply voltage (V _DD ). According to the Drain-Induced Barrier Lowering (DIBL) effect caused by the drain, due to the DIBL effect, The induced leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention is also smaller than that of the conventional 8T dual-port SRAM NMOS transistor (M3) of FIG. 5; as a result, the third NMOS transistor of the present invention flows The leakage current I _{1 of the} transistor (M13) is much smaller than the NMOS transistor (M3) of the conventional 8T dual-port SRAM in FIG. 5.

Then regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), since the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) in the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V _TM23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V _DD ) The voltage level of the V _TM23 is deducted. In contrast, the source-drain voltage (V _SD ) of the PMOS transistor (P1) of the traditional 8T dual-port SRAM in Figure 5 is equal to the power supply voltage (V _DD ). DIBL effect, so the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the PMOS transistor (P1) of the prior art in FIG. 1b.

Then, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V _TM23 in the standby mode, the node A The voltage level of V _TM23 is also maintained, and the voltage level of node B is equal to the power supply voltage (V _DD ) and the substrate of the second NMOS transistor (M12) is ground voltage. The base-source voltage (V _BS ) of the second NMOS transistor (M12) is negative, and the drain-source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V _DD ) The V _TM23 voltage level is deducted. In contrast, the base-source voltage (V _BS ) of the NMOS transistor (M2) of the traditional 8T dual-port SRAM in FIG. 5 is equal to 0, and the NMOS transistor (M2) The drain-source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and the DIBL effect, it can be known that the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than Figure 5 shows the NMOS transistor (M2) of a conventional 8T dual-port SRAM.

Finally, regarding the leakage current I ₄ flowing through the first reading transistor (M14), the present invention is different from the conventional 8T dual-port SRAM in FIG. 5 in the reading method, and the reading in the standby mode of the present invention The bit line (RBL) can be set to ground voltage. In order to prevent the voltage level of node B from dropping, the conventional 8T dual-port SRAM in Figure 5 uses read bit line pairs (RBL, RBLB) in standby mode. Since the power supply voltage is set, the leakage current I ₄ flowing through the first reading transistor (M14) cannot be compared. Based on the above analysis, it can be seen that the dual-port static random access memory proposed by the present invention has a lower leakage current than the conventional 8T dual-port SRAM of FIG. 5.

(IV) Retention mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to the ground voltage, the working principle is the same as that of a conventional dual-port SRAM cell with a single bit line. No more repetition.

[Effect of Invention]

The 7T dual-port static random access memory with high access speed provided by the present invention has the following effects:

(1) High write speed: Because the logic 0 is written by logic 0 and the logic 0 is written by logic 1, the access transistor (ie, the third NMOS transistor M13) works in the saturation region, and the current in the saturation region is It is proportional to the square of its gate-source voltage V _{GS (M13)} after deducting its threshold voltage. Therefore, the writing word line control circuit (6) is used for writing. In the first stage of enabling the word line (WWL), the writing word line control signal (WWLC) is set to the second highest power supply voltage (V _DDH2 ) which is higher than the power supply voltage (V _DD ). ), Which can effectively accelerate the writing speed from logic 0 to logic 1 and from logic 1 to logic 0;

(2) High read speed and avoid unnecessary power consumption: by the plurality of control circuits (2), the plurality of high voltage level control circuits (5), and the plurality of word line control circuits for reading ( 7) an innovative combination to improve the reading speed while avoiding unnecessary power consumption; among the plurality of control circuits (2), in the first stage of reading logic 0, the second low voltage node (VL2 ) Is set to a voltage lower than the ground voltage. When the plurality of high voltage level control circuits (5) read logic 0, the node B is set to the first higher than the power supply voltage (V _DD ). A high power supply voltage (V _DDH1 ), and the read word line control circuit (7) sets the read word line control signal (RWLC) to be higher than the The power supply voltage (V _DD ) is also higher than the second highest power supply voltage (V _DDH2 ).

(3) Quickly enter standby mode: Because the 7T dual-port static random access memory with high access speed proposed by the present invention is provided with a standby startup circuit (4) to prompt the SRAM to enter the standby mode quickly, and thereby seek Improve the standby performance of 7T dual-port SRAM;

(4) Improve the speed of writing logic 1 and avoid the problem of writing logic 1. The present invention can use the plurality of control circuits (2) and the plurality of word lines for writing during the writing operation. The control circuit (6) effectively prevents the difficulty of writing the logic 1 and also increases the speed of writing the logic 1;

(5) Low standby current: As the 7T dual-port static random access memory with high access speed proposed in the present invention is in the standby mode, the fifth NMOS transistor (M22) which is in an on state can be used, So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the voltage levels of the sixth NMOS transistor (M23) The threshold voltage level, so the dual-port static random access memory proposed by the present invention also has the effect of low standby current;

(6) Effectively reduce half-selected cell interference: The 7T dual-port static random access memory with high access speed proposed by the present invention uses a separate read / write path, and the read path is designed to change the First and second reading transistors (M14 and M15) are connected in series between the reading bit line (RBL) and the second low voltage node (VL2), and the inverting storage node (B ) Is connected to the gate of the second reading transistor (M15), so the semi-selected crystal can be effectively reduced Half-selected cell disturbance, where the semi-selected cell is a memory cell selected by the read word line (RWL) but not selected by the read bit line (RBL).

(7) Low transistor count: For a SRAM array with 1024 columns and 1024 rows, the traditional 8T dual-port SRAM array shown in Figure 5 requires a total of 1024 × 1024 × 8 = 8,388,608 transistors, and the 7T proposed by the present invention The dual-port static random access memory only needs 1024 × 1024 × 7 + 1024 × 36 + 6 = 7,376,902 transistors, which reduces the number of transistors by 12.1%.

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or detail may be changed without departing from the spirit and scope of the present invention. Therefore, all changes in the related technical scope are included in the scope of patent application of the present invention.

Claims (10)

A 7T dual-port static random access memory with high access speed includes: a memory array composed of a plurality of rows of memory cell units and a plurality of rows of memory unit cells, each row of memory The unit cell and each row of memory unit cells each include a plurality of memory unit cells (1); a plurality of control circuits (2); each column of memory unit cells is provided with a control circuit (2); a plurality of precharge circuits ( 3), each row of memory cell is provided with a precharge circuit (3); a standby start circuit (4), the standby start circuit (4) prompts the 7T dual-port static random access memory to quickly enter the standby mode, In order to effectively improve the standby performance of the 7T dual-port static random access memory; and a plurality of writing word line control circuits (6), each column of memory cell is provided with a writing word line control circuit (6 ), So that the writing mode effectively improves the writing speed from logic 0 to logic 1 and logic 1 to logic 0; wherein each memory cell (1) further includes: a first inverter Is composed of a first PMOS transistor (P11) and a first NMOS transistor (M11) The first inverter is connected between a power supply voltage (V _DD ) and a first low voltage node (VL1); a second inverter is connected by a second PMOS transistor (P12) And a second NMOS transistor (M12), the second inverter is connected between a high voltage node (VH) and a second low voltage node (VL2); a storage node (A), Formed by the output terminal of the first inverter; an inverting storage node (B) formed by the output terminal of the second inverter; a third NMOS transistor (M13) connected to the Between the storage node (A) and a write bit line (WBL), and the gate is connected to a write word line control signal (WWLC); a first read transistor (M14), the The source, gate and drain of the first read transistor (M14) are connected to the drain of a second read transistor (M15) and a read word line control signal (RWLC). And a read bit line (RBL); and the second read transistor (M15), the source, gate and drain of the second read transistor (M15) are respectively connected to the The second low voltage node (VL2), the inverting storage node (B) and The source of the first reading transistor (M14); wherein the first inverter and the second inverter are connected in an interactive coupling, that is, the output terminal of the first inverter (that is, the The storage node A) is connected to the input of the second inverter, and the output of the second inverter (that is, the inverting storage node B) is connected to the input of the first inverter; and Each control circuit (2) further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor (M24) , An eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control signal (RC) , A third inverter (INV3), a first delay circuit (D1), an accelerated read voltage (RGND), an inverted write control signal (/ WC), a write control signal (WC), A standby mode control signal (S) and an inverted standby mode control signal (/ S); wherein the source, gate, and drain of the fourth NMOS transistor (M21) are connected to a ground voltage, the Inverted standby mode control signal (/ S) and The second low voltage node (VL2); the source, gate and drain of the fifth NMOS transistor (M22) are connected to the first low voltage node (VL1) and the standby mode control signal (S), respectively. And the second low voltage node (VL2); the source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1) ); The source, gate and drain of the seventh NMOS transistor (M24) are connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low Voltage node (VL2); the source, gate, and drain of the eighth NMOS transistor (M25) are connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1), and the first The source of the seven NMOS transistors (M24); the first delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25); The input of the third inverter (INV3) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the source of the ninth NMOS transistor (M26) Pole, gate and drain Are connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27) are Respectively connected to the ground voltage, the write control signal (WC) and the gate of the ninth NMOS transistor (M26); the source, gate and drain of the eleventh NMOS transistor (M28) are respectively Connected to the gate of the inversion standby mode control signal (/ S), the inversion write control signal (/ WC) and the ninth NMOS transistor (M26); wherein the eleventh NMOS transistor (M28) ), The drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C). When the write control signal (WC ) Is the logic low level, the voltage level of the node (C) is the logic level of the inverted standby mode control signal (/ S), and when the write control signal (WC) is the logic high level, the node The voltage level of (C) is the ground voltage, so as to effectively prevent the write control signal (WC) from being a logic high level due to unexpected factors during standby operation and thus cause a erroneous write. Problem; furthermore, since the voltage level of the node (C) during the write operation is constant to the ground voltage, it has a highly stable write operation; in addition, because of the voltage level of the node (C) during the hold mode The voltage level of the power supply voltage (V _DD ) _minus the threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28), so it enters the write mode later (the write control signal WC at this time) (The logic high level), because the charge stored in the node (C) must be discharged enough to turn off the ninth NMOS transistor (M26) with the node (C) as the gate, it also has a faster speed The writing operation is completed; wherein the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent the seventh NMOS transistor (M24) from Leakage current during read mode; further, the standby start circuit (4) is designed to quickly charge the parasitic capacitance at the first low voltage node (VL1) to the six NMOS transistor (M23) of the threshold voltage (V _TM23) voltage level; Finally, each of the write The word line control circuit (6) consists of a seventh PMOS transistor (P61), an eighth PMOS transistor (P62), a ninth PMOS transistor (P63), and a thirteenth NMOS transistor (M61) A fifth inverter (INV5), a sixth inverter (INV6), a second high power supply voltage (V _DDH2 ), a writing word line (WWL), and the writing word Line control signal (WWLC); the source, gate and sink of the seventh PMOS transistor (P61) are connected to the second high power supply voltage (V _DDH2 ) and the fifth inverter The output of (INV5) and the source of the eighth PMOS transistor (P62); the source, gate, and drain of the eighth PMOS transistor (P62) are connected to the seventh PMOS transistor (P61) respectively The drain, the output of the sixth inverter (INV6) and the writing word line control signal (WWLC); the source, gate, and drain of the ninth PMOS transistor (P63) are connected respectively To the power supply voltage (V _DD ), the output of the fifth inverter (INV5) and the writing word line control signal (WWLC); the source and gate of the thirteenth NMOS transistor (M61) A pole and a drain are respectively connected to the writing word line control. The signal (WWLC), the output of the fifth inverter (INV5), and the ground voltage; the input of the fifth inverter (INV5) is for receiving the writing word line (WWL), and the sixth The input of the inverter (INV6) is connected to the output of the fifth inverter (INV5). The 7T dual-port static random access memory with high access speed as described in item 1 of the scope of patent application, which further includes a plurality of high-voltage level control circuits (5), one for each row of memory cells. High voltage level control circuit (5) to increase the reading speed when reading logic 0. Each high voltage level control circuit (5) further includes: a fifth PMOS transistor (P51), a sixth The PMOS transistor (P52) and a fourth inverter (INV4); wherein the source, gate, and drain of the fifth PMOS transistor (P51) are connected to the power supply voltage (V _DD ), The read control signal (RC) and the high voltage node (VH); the source, gate and drain of the sixth PMOS transistor (P52) are connected to a first high power supply voltage (V _DDH1 ), respectively. The output of the fourth inverter (INV4) and the high voltage node (VH); the input of the fourth inverter (INV4) is for receiving the read control signal (RC), and the output is connected to The gate of the sixth PMOS transistor (P52). The 7T dual-port static random access memory with high access speed as described in item 2 of the scope of patent application, which further includes a plurality of read word line control circuits (7), and each row of memory cell A read word line control circuit (7) is provided to further reduce the resistance of the read path when reading logic 0 and accelerate the discharge of the charge on the read bit line (RWL) to further improve Reading speed, the word line control circuit (7) for each reading further includes: a tenth PMOS transistor (P71), an eleventh PMOS transistor (P72), and a twelfth PMOS transistor ( P73), a fourteenth NMOS transistor (M71), a seventh inverter (INV7), an eighth inverter (INV8), the second high power supply voltage (V _DDH2 ), the reading The word line (RWL) and the read word line control signal (RWLC); wherein the source, gate and drain of the tenth PMOS transistor (P71) are respectively connected to the second high power supply Voltage (V _DDH2 ), output of the seventh inverter (INV7) and source of the eleventh PMOS transistor (P72); source, gate and sink of the eleventh PMOS transistor (P72) pole Connected to the drain of the tenth PMOS transistor (P71), the output of the eighth inverter (INV8), and the word line control signal (RWLC) for reading; the twelfth PMOS transistor (P73) The source, gate, and drain are connected to the power supply voltage (V _DD ), the output of the seventh inverter (INV7), and the read word line control signal (RWLC); the tenth The source, gate, and drain of the four NMOS transistors (M71) are connected to the ground voltage, the output of the seventh inverter (INV7), and the read word line control signal (RWLC); the The input of the seventh inverter (INV7) is for receiving the read word line (RWL), and the input of the eighth inverter (INV8) is connected to the output of the seventh inverter (INV7) . The 7T dual-port static random access memory with high access speed as described in item 3 of the patent application scope, wherein each of the precharge circuits (3) is composed of a third PMOS transistor (P31) and a It consists of a pre-charge signal (P); wherein the source, gate and drain of the third PMOS transistor (P31) are connected to the power supply voltage (V _DD ), the pre-charge signal (P) and The read bit line (RBL) is used to precharge the read bit line (RBL) to the power supply by a precharge signal (P) at a logic low level during a precharge period. Voltage (V _DD ) level; the standby start circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2), and the inverse Composed of a phase standby mode control signal (/ S); wherein the source, gate and drain of the fourth PMOS transistor (P41) are respectively connected to the power supply voltage (V _DD ) and the inverting standby mode The control signal (/ S) and the drain of the twelfth NMOS transistor (M41); the source, gate and drain of the twelfth NMOS transistor (M41) are connected to the first low voltage node, respectively (VL 1) The output of the second delay circuit (D2) and the drain of the fourth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/ S ), And the output of the second delay circuit (D2) is connected to the gate of the twelfth NMOS transistor (M41). The 7T dual-port static random access memory with high access speed as described in item 4 of the scope of the patent application, wherein the storage node (A) originally stores logic 0, and is initially written in logic 1 The instantaneous voltage (V _AWI ) satisfies the following equation: V _AWI = V _DD × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 ) and V _AWI > V _TM12 where V _AWI represents the storage node (A ) The write initial instantaneous voltage written to logic 1 by storing logic 0, R _M11 , R _M13 and R _M23 respectively represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the first The on-resistance of the six NMOS transistors (M23), and V _DD and V _TM12 represent the power supply voltage (V _DD ) and the threshold voltage of the second NMOS transistor (M12), respectively. According to the 7T dual-port static random access memory with high access speed described in item 5 of the scope of patent application, the second high power supply voltage (V _DDH2 ) is set to satisfy the power supply voltage (V _DD ) and The sum of the threshold voltage (V _TM14 ) of the first reading transistor (M14) (ie, V _DD + V _TM14 ), and the threshold voltage of the power supply voltage (V _DD ) and the third NMOS transistor (M13) The _smaller of the sum of (V _TM13 ) (ie V _DD + V _TM13 ). The 7T dual-port static random access memory with high access speed as described in item 6 of the scope of patent application, wherein the word line control circuit (6) for each write can be further subdivided into Two stages, in a first stage where the writing word line (WWL) is enabled, the writing word line control signal (WWLC) is set to be higher than the power supply voltage (V _DD ) The second high power supply voltage (V _DDH2 ) is used to effectively improve the writing speed, and in a second stage after the first stage, the writing word line control signal (WWLC) is pulled back down The power supply voltage (V _DD ) is used to reduce write interference; wherein the time interval between the second stage and the first stage of each write word line control circuit (6) is equal to the fifth stage. The time when the output of the inverter (INV5) is sufficient to turn on the seventh PMOS transistor (P61) and the time until the output of the sixth inverter (INV6) is sufficient to turn off the eighth PMOS transistor (P62) Its value can be dynamically adjusted by the rising delay time of the sixth inverter (INV6). The 7T dual-port static random access memory with high access speed as described in item 7 of the scope of the patent application, wherein the read operation can be further subdivided into two phases, in the first phase of one of the read operations The second low voltage node (VL2) is set to a voltage lower than the ground voltage to effectively improve the reading speed, and in a second stage of the reading operation, the second low voltage is The node (VL2) is set back to the ground voltage in order to reduce unnecessary power consumption. In the first stage of the read operation, the second low-voltage node (VL2) reads the initial instantaneous voltage when reading logic 1 ( V _RVL2I ) must satisfy the following equation: V _RVL2I = RGND × R _M21 / (R _M21 + R _M24 + R _M25 ) and V _RVL2I > -V _TM12 to effectively prevent half-selected cell interference during reading, where V _RVL2I represents the initial instant voltage of the second low voltage node (VL2) when reading logic 1, RGND represents the accelerated read voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), R _M24 represents the on-resistance of the seventh NMOS transistor (M24), and R _M25 represents the eighth NMOS transistor (M25) And V _TM12 represents the threshold voltage of the second NMOS transistor (M12). The 7T dual-port static random access memory with high access speed as described in item 1 of the scope of patent application, wherein the first high power supply voltage (V _DDH1 ) is set higher than the power supply voltage (V _DD ) but lower than the sum of the absolute value of the power supply voltage (V _DD ) and the threshold voltage of the second PMOS transistor (P12) | V _TP12 |, that is, V _DD <V _DDH1 <V _DD + | V _TP12 | . The 7T dual-port static random access memory with high access speed as described in item 1 of the scope of patent application, wherein the absolute value of the accelerated read voltage (RGND) in each control circuit (2) | RGND | is set to be lower than the threshold voltage (V _TM12 ) of the second NMOS transistor (M12) in each memory cell (1), that is, | RGND | <V _TM12 .