TWI760176B - Memory device - Google Patents
Memory device Download PDFInfo
- Publication number
- TWI760176B TWI760176B TW110112794A TW110112794A TWI760176B TW I760176 B TWI760176 B TW I760176B TW 110112794 A TW110112794 A TW 110112794A TW 110112794 A TW110112794 A TW 110112794A TW I760176 B TWI760176 B TW I760176B
- Authority
- TW
- Taiwan
- Prior art keywords
- nmos transistor
- voltage
- logic
- read
- inverter
- Prior art date
Links
Images
Landscapes
- Static Random-Access Memory (AREA)
Abstract
本發明提出一種記憶裝置,其主要包括一記憶體陣列(1)、複數個控制電路(2)、複數個預充電電路(3)、一待機啟動電路(4)、複數個高電壓位準控制電路(5)、複數個寫入用字元線控制電路(6)、複數個讀取用字元線控制電路(7)、以及一個寫入驅動電路(8)。藉此,於寫入模式時,可藉由該複數個控制電路(2)、該複數個寫入用字元線控制電路(6)以及該複數個寫入驅動電路(8)的組合以防止寫入邏輯1困難之同時,亦有效提高寫入速度,而於讀取模式時,則藉由該複數個控制電路(2)、該複數個高電壓位準控制電路(5)以及該複數個讀取用字元線控制電路(7)的組合以於提高讀取速度的同時,亦避免無謂的功率耗損。再者,本發明SRAM晶胞中設置有一耦合元件(CE)連接於反相儲存節點(B)與讀取用字元線控制信號(RWLC)之間,該耦合元件(CE)因應該SRAM晶胞工作於保持(retention)模式與讀取模式以及該反相儲存節點之儲存邏輯狀態而提供不同的耦合電容,其中當該SRAM晶胞處於保持模式且該反相儲存節點(B)為邏輯1時提供最大的耦合電容,亦即當該SRAM晶胞處於保持模式且該反相儲 存節點(B)為邏輯1時所具有之耦合電容大於該反相儲存節點(B)為邏輯0時之耦合電容,且大於該SRAM晶胞處於讀取模式時之耦合電容,藉此,可於讀取邏輯0初期提高該反相儲存節點(B)之電壓位準,從而有效減小讀取路徑之等效電阻,因此可更進一步提高讀取速度。 The present invention provides a memory device, which mainly comprises a memory array (1), a plurality of control circuits (2), a plurality of pre-charging circuits (3), a standby start-up circuit (4), and a plurality of high-voltage level controls A circuit (5), a plurality of write word line control circuits (6), a plurality of read word line control circuits (7), and a write drive circuit (8). Therefore, in the write mode, the plurality of control circuits (2), the plurality of word line control circuits (6) for writing and the plurality of write drive circuits (8) can be used to prevent the While it is difficult to write logic 1, the writing speed is also effectively improved. In the read mode, the plurality of control circuits (2), the plurality of high-voltage level control circuits (5) and the plurality of The combination of the word line control circuit (7) for reading can improve the reading speed and avoid unnecessary power consumption. Furthermore, a coupling element (CE) is set in the SRAM cell of the present invention to be connected between the inverted storage node (B) and the read word line control signal (RWLC), and the coupling element (CE) corresponds to the SRAM cell. The cell works in retention mode and read mode and the storage logic state of the inverting storage node provides different coupling capacitances, wherein when the SRAM cell is in retention mode and the inverting storage node (B) is logic 1 provides the largest coupling capacitance when the SRAM cell is in hold mode and the inverting storage When the storage node (B) is logic 1, the coupling capacitance is greater than the coupling capacitance when the inverting storage node (B) is logic 0, and is larger than the coupling capacitance when the SRAM cell is in the read mode. In the initial stage of reading logic 0, the voltage level of the inverting storage node (B) is increased, thereby effectively reducing the equivalent resistance of the reading path, thus further improving the reading speed.
Description
本發明係有關於一種具7T(seven transistor)雙埠(dual port)靜態隨機存取記憶體(Static Random Access Memory,簡稱SRAM)之記憶裝置,尤指一種有效提高7T SRAM待機效能,並能有效提高讀取速度與寫入速度,且能有效降低漏電流(leakage current)、降低讀取時之半選定晶胞干擾以及避免無謂的功率耗損之SRAM。 The present invention relates to a memory device with a 7T (seven transistor) dual port static random access memory (Static Random Access Memory, SRAM for short), and more particularly to a memory device that effectively improves the standby performance of the 7T SRAM and can effectively An SRAM that improves read speed and write speed, effectively reduces leakage current, reduces half-selected cell interference when reading, and avoids unnecessary power consumption.
習知之單埠靜態隨機存取記憶體(SRAM)如第1a圖所示,其主要包括一記憶體陣列(memory array),該記憶體陣列係由複數個記憶體區塊(memory block,MB1、MB2等)所組成,每一記憶體區塊更由複數列記憶體晶胞(a plurality of rows of memory cells)與複數行記憶體晶胞(a plurality of columns of memory cells)所組成,每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞;複數條字元線(word line,WL1、WL2等),每一字元線對應至複數列記憶體晶胞中之一列;以及複數位元線對(bit line pairs,BL1、BLB1...BLm、BLBm等),每一位元線對係對應至複數行記憶體晶胞中之一行,且每一位元線對係由一位元線(BL1...BLm)及一互補位元線(BLB1...BLBm)所組成。 As shown in Figure 1a, a conventional SRAM (Static Random Access Memory) mainly includes a memory array, which is composed of a plurality of memory blocks (MB 1) . , MB 2 , etc.), each memory block is further composed of a plurality of rows of memory cells and a plurality of columns of memory cells, Each column of memory cells and each row of memory cells respectively include a plurality of memory cells; a plurality of word lines (word lines, WL 1 , WL 2 , etc.), each word line corresponds to a plurality of column memory A row in the body cell; and a plurality of bit line pairs (BL1, BLB1 ... BLm , BLBm , etc.), each bit line pair corresponds to a plurality of rows in the memory cell One row, and each bit line pair consists of one bit line (BL 1 . . . BL m ) and a complementary bit line (BLB 1 . . . BLB m ).
第1b圖所示即是6T單埠靜態隨機存取記憶體(SRAM)晶胞
之電路示意圖,其中,PMOS電晶體(P1)和(P2)稱為負載電晶體(load transistor),NMOS電晶體(M1)和(M2)稱為驅動電晶體(driving transistor),NMOS電晶體(M3)和(M4)稱為存取電晶體(access transistor),WL為字元線(word line),而BL及BLB分別為位元線(bit line)及互補位元線(complementary bit line),由於該單埠SRAM晶胞需要6個電晶體,且於讀取邏輯0時,為了避免讀取操作初始瞬間(initial instant)另一驅動電晶體導通,節點A之讀取初始瞬間電壓(VAR)必須滿足方程式(1):VAR=VDD×(RM1)/(RM1+RM3)<VTM2 (1)以防止讀取時之半選定晶胞干擾(half-selected cell disturbance),其中,VAR表示節點A之讀取初始瞬間電壓,RM1與RM3分別表示該NMOS電晶體(M1)與該NMOS電晶體(M3)之導通電阻,而VDD與VTM2分別表示電源供應電壓與該NMOS電晶體(M2)之臨界電壓,此導致驅動電晶體與存取電晶體之間的電流驅動能力比(即單元比率,cell ratio)通常設定在2.2至3.5之間(請參考98年10月20日第US7606060B2號專利說明書第2欄第8-10行)。
Figure 1b shows the circuit diagram of a 6T SRAM cell, in which the PMOS transistors (P1) and (P2) are called load transistors, and the NMOS transistors are called load transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is the word line, and BL and BLB are the bit line and the complementary bit line respectively, because the port SRAM cell requires 6 transistors, and when
第1b圖所示6T單埠靜態隨機存取記憶體晶胞於寫入操作時之HSPICE暫態分析模擬結果,如第2圖所示,其係使用TSMC 90奈米CMOS製程參數加以模擬。 Figure 1b shows the HSPICE transient analysis simulation results of a 6T port SRAM cell during a write operation, as shown in Figure 2, which is simulated using TSMC 90nm CMOS process parameters.
用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5T單埠靜態隨機存取記憶體晶胞之電路示意圖,與第1b圖之6T單埠靜態隨機存取記憶體晶胞相比,此種5T靜態隨機存取記憶體晶胞比6T靜態隨機存取記憶體晶胞少一個電晶體及少一條位元線,惟該5T單埠靜態隨機存取記憶體晶胞
在不變更PMOS電晶體P1和P2以及NMOS電晶體M1、M2和M3的通道寬長比的情況下存在寫入邏輯1相當困難之問題。茲考慮記憶體晶胞左側節點A原本儲存邏輯0的情況,由於節點A之電荷僅單獨自位元線(BL)傳送,因此在將節點A中先前寫入的邏輯0蓋寫成邏輯1之寫入初始瞬間電壓(VAW)等於方程式(2):
One way to reduce the transistor count of a 6T static random access memory (SRAM) cell is disclosed in FIG. 3 . Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line. Compared with the 6T SRAM cell in Figure 1b, this 5T SRAM cell The random access memory unit cell has one less transistor and one less bit line than the 6T SRAM unit cell, but the 5T port SRAM unit cell does not change the PMOS transistors P1 and P2. And in the case of the channel width to length ratio of the NMOS transistors M1, M2 and M3, there is a problem that it is quite difficult to write a
VAW=VDD×(RM1)/(RM1+RM3) (2)其中,VAW表示節點A之寫入初始瞬間電壓,RM1與RM3分別表示NMOS電晶體(M1)與NMOS電晶體(M3)之導通電阻,比較方程式(1)與方程式(2)可知,寫入初始瞬間電壓(VAW)小於NMOS電晶體(M2)之臨界電壓(VTM2),因而無法完成寫入邏輯1之操作。第3圖所示5T靜態隨機存取記憶體晶胞,於寫入操作時之HSPICE暫態分析模擬結果,如第4圖所示,其係使用TSMC 90奈米CMOS製程參數加以模擬,由該模擬結果可証實,具單一位元線之5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。
V AW =V DD ×(R M1 )/(R M1 +R M3 ) (2) Among them, V AW represents the initial instantaneous voltage of node A writing, and R M1 and R M3 represent the NMOS transistor (M1) and the NMOS transistor respectively Comparing equation (1) and equation (2), the on-resistance of transistor (M3) shows that the initial instantaneous voltage (V AW ) of writing is less than the threshold voltage (V TM2 ) of the NMOS transistor (M2), so the writing cannot be completed. Operation of
接下來討論靜態隨機存取記憶體(SRAM)之單埠及雙埠架構,第1b圖之6T靜態隨機存取記憶體(SRAM)晶胞即是單埠靜態隨機存取記憶體(SRAM)晶胞之一例,其係使用兩條位元線BL及BLB做讀寫的動作,也就是讀與寫均是經由同樣的一對位元線來達成,是以在同一時間內只能進行讀或寫的動作,因此,當欲設計具有同時讀寫能力之雙埠靜態隨機存取記憶體時,便需要多加入兩顆存取電晶體以及另一對位元線,這使得記憶體晶胞的面積大大地增加,如果我們能夠簡化記憶體晶胞的架構,使得一條位元線負責讀取的動作,而另一條位元線負責寫入的動作,則雙埠靜態隨機存取記憶體晶胞的面積便會減小許多,傳統的雙埠靜態隨機存取記
憶體晶胞之所以不採用這種方法,是因為如前所述存在寫入邏輯1相當困難之問題。
Next, we will discuss the port and dual-port architecture of static random access memory (SRAM). The 6T SRAM cell in Figure 1b is the port SRAM cell. An example of a cell uses two bit lines BL and BLB for read and write operations, that is, read and write are achieved through the same pair of bit lines, so only read or write operations can be performed at the same time. Therefore, when designing a dual-port SRAM with simultaneous reading and writing capability, it is necessary to add two more access transistors and another pair of bit lines, which makes the memory cell’s The area is greatly increased. If we can simplify the structure of the memory cell so that one bit line is responsible for the read action and the other bit line is responsible for the write action, the dual-port static random access memory cell The area will be greatly reduced, the traditional dual-port static random access memory
The reason why the memory cell does not use this method is that it is very difficult to write a
迄今,有許多具單一讀取位元線之雙埠靜態隨機存取記憶體晶胞之技術被提出,例如專利文獻所提出之「雙埠靜態隨機存取記憶體」(TW 1660348B,108年5月21日授予修平科技大學),其指定代表圖如第5圖所示,惟該專利文獻於讀取操作時仍有下列缺失:(一)對於高電壓位準控制電路(5),若第一高電源供應電壓(VDDH1)因非預期的時序因素而早於電源供應電壓(VDD)被提供,則第六PMOS電晶體(P51)易因寄生PNP電晶體的閂鎖(latch-up)效應而提早損毀、(二)對於控制電路(2),若加速讀取電壓(RGND)因非預期的時序因素而早於接地電壓(GND)被提供,則第四NMOS電晶體(M21)易因寄生NPN電晶體的閂鎖效應而提早損毀及(三)對於SRAM晶胞,第二讀取用電晶體(M15)於讀取操作時的等效電阻稍嫌過大,因此仍有改進空間。 So far, many technologies of dual-port SRAM cell with a single read bit line have been proposed, such as the "Dual-port SRAM" proposed in the patent document (TW 1660348B, May 108) Awarded to Xiuping University of Science and Technology on May 21), its designated representative diagram is shown in Figure 5, but the patent document still has the following defects during the reading operation: (1) For the high-voltage level control circuit (5), if the first A high power supply voltage (V DDH1 ) is provided earlier than the power supply voltage (V DD ) due to unexpected timing factors, and the sixth PMOS transistor ( P51 ) is prone to latch-up of the parasitic PNP transistor (2) for the control circuit (2), if the accelerated read voltage (RGND) is supplied earlier than the ground voltage (GND) due to unexpected timing factors, the fourth NMOS transistor (M21) It is easy to be damaged early due to the latch-up effect of the parasitic NPN transistor and (3) For the SRAM cell, the equivalent resistance of the second read transistor (M15) during the read operation is slightly too large, so there is still room for improvement .
有鑑於此,本發明之主要目的係提出一種具雙埠靜態隨機存取記憶體之記憶裝置,其能藉由於SRAM晶胞中設置一耦合元件(CE)連接於反相儲存節點(B)與讀取用字元線控制信號(RWLC)之間,該耦合元件(CE)因應該SRAM晶胞工作於保持(retention)模式與讀取模式以及該反相儲存節點之儲存邏輯狀態而提供不同的耦合電容,其中當該SRAM晶胞處於保持模式且該反相儲存節點(B)為邏輯1時提供最大的耦合電容,亦即當該SRAM晶胞處於保持模式且該反相儲存節點(B)為邏輯1時所具有之耦合電容大於該反相儲存節點(B)為邏輯0時之耦合電容,且大於該SRAM晶胞處於讀取模式時之耦合電容,藉此,可於讀取邏輯0初期提高該反相儲存節點(B)之電壓位
準,從而有效減小第二讀取用電晶體(M15)之等效電阻,因此可更進一步提高讀取速度。
In view of this, the main purpose of the present invention is to provide a memory device with dual-port SRAM, which can be connected to the inverting storage node (B) and the inverting storage node (B) by arranging a coupling element (CE) in the SRAM cell. Between the read word line control signal (RWLC), the coupling element (CE) provides different logic states due to the SRAM cell working in the retention mode and the read mode and the storage logic state of the inverted storage node. Coupling capacitance, wherein the maximum coupling capacitance is provided when the SRAM cell is in hold mode and the inverting storage node (B) is a
本發明之次要目的係提出一種具雙埠靜態隨機存取記憶體之記憶裝置,其能藉由將高電壓位準控制電路(5)中之第六PMOS電晶體(P51)及第七PMOS電晶體(P52)之的基極(bulk;B)連接至第一高電源供應電壓(VDDH1)以防止該第六PMOS電晶體(P51)因發生閂鎖而提早損毀。 A secondary object of the present invention is to provide a memory device with dual-port SRAM, which can control the sixth PMOS transistor (P51) and the seventh PMOS transistor in the high-voltage level control circuit (5) by controlling the high voltage level. The base (bulk; B) of the transistor (P52) is connected to the first high power supply voltage (V DDH1 ) to prevent the sixth PMOS transistor (P51 ) from being damaged early due to latch-up.
本發明之再一目的係提出一種具雙埠靜態隨機存取記憶體之記憶裝置,其能藉由將控制電路(2)中之第四NMOS電晶體(M21)、第七NMOS電晶體(M24)及第八NMOS電晶體(M25)之基極連接至加速讀取電壓(RGND)以防止該第四NMOS電晶體(M21)因發生閂鎖而提早損毀。 Another object of the present invention is to provide a memory device with dual-port SRAM, which can be achieved by connecting the fourth NMOS transistor (M21) and the seventh NMOS transistor (M24) in the control circuit (2). ) and the base of the eighth NMOS transistor (M25) are connected to the accelerated read voltage (RGND) to prevent the fourth NMOS transistor (M21) from being damaged early due to latch-up.
本發明提出一種記憶裝置,其主要包括一記憶體陣列(1)、複數個控制電路(2)、複數個預充電電路(3)、一待機啟動電路(4)、複數個高電壓位準控制電路(5)、複數個寫入用字元線控制電路(6)、複數個讀取用字元線控制電路(7)、以及一個寫入驅動電路(8)。藉此,於寫入模式時,可藉由該複數個控制電路(2)、該複數個寫入用字元線控制電路(6)以及該複數個寫入驅動電路(8)的組合以防止寫入邏輯1困難之同時,亦有效提高寫入速度,而於讀取模式時,則藉由該複數個控制電路(2)、該複數個高電壓位準控制電路(5)以及該複數個讀取用字元線控制電路(7)的組合以於提高讀取速度的同時,亦避免無謂的功率耗損。再者,本發明SRAM晶胞中設置有一耦合元件(CE)連接於反相儲存節點(B)與讀取用字元線控制信號(RWLC)之間,該耦合元件(CE)因應該SRAM晶胞
工作於保持(retention)模式與讀取模式以及該反相儲存節點之儲存邏輯狀態而提供不同的耦合電容,其中當該SRAM晶胞處於保持模式且該反相儲存節點(B)為邏輯1時提供最大的耦合電容,亦即當該SRAM晶胞處於保持模式且該反相儲存節點(B)為邏輯1時所具有之耦合電容大於該反相儲存節點(B)為邏輯0時之耦合電容,且大於該SRAM晶胞處於讀取模式時之耦合電容,藉此,可於讀取邏輯0初期提高該反相儲存節點(B)之電壓位準,從而有效減小讀取路徑之等效電阻,因此可更進一步提高讀取速度。
The present invention provides a memory device, which mainly comprises a memory array (1), a plurality of control circuits (2), a plurality of pre-charging circuits (3), a standby start-up circuit (4), and a plurality of high-voltage level controls A circuit (5), a plurality of write word line control circuits (6), a plurality of read word line control circuits (7), and a write drive circuit (8). Therefore, in the write mode, the plurality of control circuits (2), the plurality of word line control circuits (6) for writing and the plurality of write drive circuits (8) can be used to prevent the While it is difficult to write
1:SRAM晶胞 1: SRAM cell
2:控制電路 2: Control circuit
3:預充電電路 3: Precharge circuit
4:待機啟動電路 4: Standby start circuit
5:高電壓位準控制電路 5: High voltage level control circuit
6:寫入用字元線控制電路 6: Word line control circuit for writing
7:讀取用字元線控制電路 7: Word line control circuit for reading
8:寫入驅動電路 8: Write drive circuit
P11:第一PMOS電晶體 P11: The first PMOS transistor
P12:第二PMOS電晶體 P12: Second PMOS transistor
M11:第一NMOS電晶體 M11: The first NMOS transistor
M12:第二NMOS電晶體 M12: Second NMOS transistor
M13:第三NMOS電晶體 M13: The third NMOS transistor
A:儲存節點 A: Storage node
B:反相儲存節點 B: Inverted storage node
C:節點 C:node
M14:第一讀取用電晶體 M14: The first read transistor
M15:第二讀取用電晶體 M15: Second read transistor
WBL:寫入用位元線 WBL: Write bit line
WWL:寫入用字元線 WWL: word line for writing
RBL讀取用位元線 RBL read bit lines
RWL:讀取用字元線 RWL: read word line
WWLC:寫入用字元線控制信號 WWLC: Write word line control signal
RWLC:讀取用字元線控制信號 RWLC: word line control signal for reading
S:待機模式控制信號 S: Standby mode control signal
/S:反相待機模式控制信號 /S: Inverted standby mode control signal
VL1:第一低電壓節點 VL1: first low voltage node
VL2:第二低電壓節點 VL2: Second Low Voltage Node
M21:第四NMOS電晶體 M21: Fourth NMOS transistor
M22:第五NMOS電晶體 M22: Fifth NMOS transistor
M23:第六NMOS電晶體 M23: sixth NMOS transistor
M24:第七NMOS電晶體 M24: seventh NMOS transistor
M25:第八NMOS電晶體 M25: Eighth NMOS transistor
M26:第九NMOS電晶體 M26: Ninth NMOS transistor
M27:第十NMOS電晶體 M27: Tenth NMOS transistor
P21:第三PMOS電晶體 P21: The third PMOS transistor
RC:讀取控制信號 RC: read control signal
RGND:加速讀取電壓 RGND: Speed up reading voltage
INV3:第三反相器 INV3: Third Inverter
D1:第一延遲電路 D1: first delay circuit
WC:寫入控制信號 WC: write control signal
CE:耦合元件 CE: Coupling Element
P31:第四PMOS電晶體 P31: Fourth PMOS transistor
P:預充電信號 P: Precharge signal
M41:第十一NMOS電晶體 M41: Eleventh NMOS transistor
P41:第五PMOS電晶體 P41: Fifth PMOS transistor
D2:第二延遲電路 D2: Second delay circuit
VDD:電源供應電壓 V DD : Power supply voltage
VDDH1:第一高電源供應電壓 V DDH1 : The first high power supply voltage
VDDH2:第二高電源供應電壓 V DDH2 : The second highest power supply voltage
P51:第六PMOS電晶體 P51: sixth PMOS transistor
P52:第七PMOS電晶體 P52: seventh PMOS transistor
INV4:第四反相器 INV4: Fourth inverter
VH:高電壓節點 VH: High Voltage Node
P61:第八PMOS電晶體 P61: Eighth PMOS transistor
P62:第九PMOS電晶體 P62: Ninth PMOS transistor
P63:第十PMOS電晶體 P63: Tenth PMOS transistor
M61:第十二NMOS電晶體 M61: Twelfth NMOS transistor
INV5:第五反相器 INV5: Fifth inverter
INV6:第六反相器 INV6: sixth inverter
P71:第十一PMOS電晶體 P71: Eleventh PMOS transistor
P72:第十二PMOS電晶體 P72: Twelfth PMOS transistor
P73:第十三PMOS電晶體 P73: Thirteenth PMOS transistor
M71:第十三NMOS電晶體 M71: Thirteenth NMOS transistor
INV7:第七反相器 INV7: seventh inverter
INV8:第八反相器 INV8: Eighth Inverter
P81:第十四PMOS電晶體 P81: Fourteenth PMOS transistor
M81:第十四NMOS電晶體 M81: Fourteenth NMOS transistor
M82:第十五NMOS電晶體 M82: The fifteenth NMOS transistor
M83:第十六NMOS電晶體 M83: Sixteenth NMOS transistor
INV9:第九反相器 INV9: ninth inverter
INV10:第十反相器 INV10: Tenth Inverter
D3:第三延遲電路 D3: Third delay circuit
D4:第四延遲電路 D4: Fourth delay circuit
VDDH3:第三高電源供應電壓 V DDH3 : The third highest power supply voltage
Y:行解碼器輸出信號 Y: line decoder output signal
Cap:電容器 Cap: capacitor
Din:輸入資料 Din: input data
BLB:互補位元線 BLB: Complementary Bit Line
BLB1…BLBm:互補位元線 BLB 1 …BLB m : Complementary bit line
MB1…MBk:記憶體區塊 MB 1 …MB k : memory block
WL1…WLn:字元線 WL 1 …WL n : word line
BL1…BLm:位元線 BL 1 …BL m : bit line
M1…M4:NMOS電晶體 M1…M4: NMOS transistors
P1…P2:PMOS電晶體 P1…P2: PMOS transistors
第1a圖 係顯示習知之靜態隨機存取記憶體; Figure 1a shows a conventional SRAM;
第1b圖 係顯示習知6T靜態隨機存取記憶體晶胞之電路示意圖; Fig. 1b is a circuit schematic diagram showing a conventional 6T SRAM cell;
第2圖 係顯示習知6T靜態隨機存取記憶體晶胞之寫入動作時序圖; FIG. 2 is a timing diagram of a write operation of a conventional 6T SRAM cell;
第3圖 係顯示習知5T靜態隨機存取記憶體晶胞之電路示意圖; FIG. 3 is a schematic circuit diagram of a conventional 5T SRAM cell;
第4圖 係顯示習知5T靜態隨機存取記憶體晶胞之寫入動作時序圖; FIG. 4 is a timing diagram of a write operation of a conventional 5T SRAM cell;
第5圖 係顯示習知TW I660348B之指定代表圖; Figure 5 shows the designated representative diagram of the conventional TW I660348B;
第6圖 係顯示本發明較佳實施例所提出之電路示意圖; FIG. 6 is a schematic diagram of a circuit proposed by a preferred embodiment of the present invention;
第7a圖 係顯示第6圖於寫入邏輯0期間之簡化電路圖;
Fig. 7a shows the simplified circuit diagram of Fig. 6 during the writing of
第7b圖 係顯示第6圖於寫入邏輯1期間之簡化電路圖;
Fig. 7b shows the simplified circuit diagram of Fig. 6 during the writing of
第8圖 係顯示第6圖於讀取期間之簡化電路圖。 Figure 8 shows a simplified circuit diagram of Figure 6 during reading.
根據上述之主要目的,本發明提出一種記憶裝置,其主要包括一記憶體陣列,該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶 胞所組成,每一列記憶體晶胞與每一行記憶體晶胞均包括有複數個記憶體晶胞(1);複數個控制電路(2),每一列記憶體晶胞設置一個控制電路(2);複數個預充電電路(3),每一行記憶體晶胞設置一個預充電電路(3);一待機啟動電路(4),該待機啟動電路(4)係促使雙埠SRAM快速進入待機模式,以有效提高雙埠SRAM之待機效能;複數個高電壓位準控制電路(5),每一列記憶體晶胞設置一個高電壓位準控制電路(5),以在讀取邏輯0時減少讀取路徑之電阻從而提高讀取速度;複數個寫入用字元線控制電路(6),每一列記憶體晶胞設置一個寫入用字元線控制電路(6),以在由邏輯0寫入邏輯1或由邏輯1寫入邏輯0時,於對應寫入用字元線(WWL)致能的第一階段,將對應寫入用字元線控制信號(WWLC)設定成較電源供應電壓(VDD)還高之第二高電源供應電壓(VDDH2),以有效提高寫入速度;複數個讀取用字元線控制電路(7),每一列記憶體晶胞設置一個讀取用字元線控制電路(7),以在讀取邏輯0時,於對應讀取用用字元線(RWL)致能的第一階段,將對應讀取用字元線控制信號(RWLC)設定成較電源供應電壓(VDD)還高之第二高電源供應電壓(VDDH2),以進一步減少讀取路徑之電阻,並加速讀取用位元線(RWL)上之電荷的放電,從而有效提高讀取速度;以及複數個寫入驅動電路(8),每一行記憶體晶胞設置一個寫入驅動電路(8),以在寫入邏輯0之第一階段將低於接地電壓之電壓位準施加至寫入用位元線(WBL),以加速寫入邏輯0之速度,而於寫入邏輯1時則將高於電源供應電壓(VDD)之第三高電源供應電壓(VDDH3)的位準加至該寫入用位元線(WBL),以加速寫入邏輯1之速度。 According to the above-mentioned main purpose, the present invention provides a memory device, which mainly includes a memory array, the memory array is composed of a plurality of rows of memory cells and a plurality of rows of memory cells, each row of memory cells and Each row of memory unit cells includes a plurality of memory unit cells (1); a plurality of control circuits (2), each row of memory unit cells is provided with a control circuit (2); a plurality of precharge circuits (3), Each row of memory cells is provided with a precharge circuit (3); a standby startup circuit (4), the standby startup circuit (4) prompts the dual-port SRAM to quickly enter the standby mode, so as to effectively improve the standby performance of the dual-port SRAM; a plurality of high-voltage level control circuits (5), each row of memory cells is provided with a high-voltage level control circuit (5), so as to reduce the resistance of the read path and improve the read speed when reading logic 0; There are two write word line control circuits (6), and one write word line control circuit (6) is provided for each column of memory cells, so as to write a logic 1 from a logic 0 or write a logic 0 from a logic 1 When the corresponding write word line (WWL) is enabled in the first stage, the corresponding write word line control signal (WWLC) is set to the second highest power supply higher than the power supply voltage (V DD ) supply voltage (V DDH2 ) to effectively improve the writing speed; a plurality of reading word line control circuits (7), each row of memory cells is provided with a reading word line control circuit (7) to When reading logic 0, in the first stage of enabling the corresponding read word line (RWL), set the corresponding read word line control signal (RWLC) to be higher than the power supply voltage (V DD ) The second highest power supply voltage (V DDH2 ) to further reduce the resistance of the read path and accelerate the discharge of the charge on the read bit line (RWL), thereby effectively increasing the read speed; and a plurality of write A drive circuit (8), each row of memory cells is provided with a write drive circuit (8) to apply a voltage level lower than the ground voltage to the write bit line ( WBL), in order to speed up the writing speed of logic 0, and when writing logic 1, a level of the third highest power supply voltage (V DDH3 ) higher than the power supply voltage (V DD ) is applied to the write-in Bit line (WBL) to speed up the writing of logic 1s.
為了便於說明起見,第6圖所示之雙埠靜態隨機存取記憶體 僅以一個記憶體晶胞(1)、一條寫入用字元線(WWL)、一條寫入用位元線(WBL)、一條讀取用字元線(RWL)、一條讀取用位元線(RBL)、一控制電路(2)、一預充電電路(3)、一待機啟動電路(4)、一高電壓位準控制電路(5)、一寫入用字元線控制電路(6)、一讀取用字元線控制電路(7)以及一寫入驅動電路(8)做為實施例來說明。該記憶體晶胞(1)係包括一第一反相器(由一第一PMOS電晶體P11與一第一NMOS電晶體M11所組成)、一第二反相器(由一第二PMOS電晶體P12與一第二NMOS電晶體M12所組成)、一第三NMOS電晶體(M13)、一第一讀取用電晶體(M14)、一第二讀取用電晶體(M15)以及一耦合元件(CE),其中,該第一反相器及該第二反相器係呈交互耦合連接,亦即該第一反相器之輸出(即節點A)係連接該第二反相器之輸入,而該第二反相器之輸出(即節點B)則連接該第一反相器之輸入,並且該第一反相器之輸出(節點A)係用於儲存SRAM晶胞之資料,而該第二反相器之輸出(節點B)則用於儲存SRAM晶胞之反相資料。 For the sake of illustration, the dual-port SRAM shown in Figure 6 Only one memory cell (1), one write word line (WWL), one write bit line (WBL), one read word line (RWL), and one read bit line line (RBL), a control circuit (2), a precharge circuit (3), a standby start circuit (4), a high voltage level control circuit (5), a word line control circuit for writing (6) ), a read word line control circuit (7) and a write drive circuit (8) are described as embodiments. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11 ), a second inverter (composed of a second PMOS transistor M11 ) The crystal P12 is composed of a second NMOS transistor M12), a third NMOS transistor (M13), a first read transistor (M14), a second read transistor (M15), and a coupling Element (CE), wherein the first inverter and the second inverter are connected in a cross-coupling manner, that is, the output of the first inverter (ie, node A) is connected to the second inverter. input, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, The output of the second inverter (node B) is used to store the inverted data of the SRAM cell.
該記憶體晶胞(1)之該第一反相器(由該第一PMOS電晶體P11與該第一NMOS電晶體M11所組成)係連接在一電源供應電壓(VDD)與一第一低電壓節點(VL1)之間,該第二反相器(由該第二PMOS電晶體P12與該第二NMOS電晶體M12所組成)係連接在一高電壓節點(VH)與一第二低電壓節點(VL2)之間,該第一讀取用電晶體(M14)之源極、閘極與汲極係分別連接至該第二讀取用電晶體(M15)之汲極、該讀取用字元線(RWL)與該讀取用位元線(RBL),而該第二讀取用電晶體(M15)之源極、閘極與汲極則分別連接至該第二低電壓節點(VL2)、該第二反相器 之輸出(即節點B)與該第一讀取用電晶體(M14)之源極。再者,該耦合元件(CE)係由一PMOS電晶體所組成,該PMOS電晶體之閘極連接對應讀取用字元線控制電路(7)所輸出之一讀取用字元線控制信號(RWLC),該PMOS電晶體之源極與汲極連接在一起並連接至該節點(B)。 The first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11 ) of the memory cell (1) is connected to a power supply voltage (V DD ) and a first Between the low voltage node (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected to a high voltage node (VH) and a second low voltage Between the voltage nodes (VL2), the source, gate and drain of the first read transistor (M14) are respectively connected to the drain of the second read transistor (M15). A word line (RWL) and the read bit line (RBL) are used, and the source, gate and drain of the second read transistor (M15) are respectively connected to the second low voltage node (VL2), the output of the second inverter (ie node B) and the source of the first read transistor (M14). Furthermore, the coupling element (CE) is composed of a PMOS transistor, and the gate of the PMOS transistor is connected to a read word line control signal outputted by the corresponding read word line control circuit (7). (RWLC), the source and drain of the PMOS transistor are connected together and to the node (B).
請再參考第6圖,該控制電路(2)係由一第四NMOS電晶體(M21)、一第五NMOS電晶體(M22)、一第六NMOS電晶體(M23)、一第七NMOS電晶體(M24)、一第八NMOS電晶體(M25)、一第九NMOS電晶體(M26)、一第十NMOS電晶體(M27)、一第三PMOS電晶體(P21)、一讀取控制信號(RC)、一第三反相器(INV3)、一第一延遲電路(D1)、一加速讀取電壓(RGND)、一寫入控制信號(WC)、一待機模式控制信號(S)以及一反相待機模式控制信號(/S)所組成。該第四NMOS電晶體(M21)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與該第二低電壓節點(VL2);該第五NMOS電晶體(M22)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該待機模式控制信號(S)與該第二低電壓節點(VL2);該第六NMOS電晶體(M23)之源極係連接至接地電壓,而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1);該第七NMOS電晶體(M24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M25)之汲極、該讀取控制信號(RC)與該第二低電壓節點(VL2);該第八NMOS電晶體(M25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、該第一延遲電路(D1)之輸出與該第七NMOS電晶體(M24)之源極;該第一延遲電路(D1)係連接在該第三反相器(INV3)之輸出與該第八NMOS電晶體(M25)之該閘極之 間;該第三反相器(INV3)之輸入係供接收該讀取控制信號(RC),而輸出則連接至該第一延遲電路(D1)之輸入;該第九NMOS電晶體(M26)之源極、閘極與汲極係分別連接至接地電壓、該第十NMOS電晶體(M27)之汲極與該第一低電壓節點(VL1);該第十NMOS電晶體(M27)之源極、閘極與汲極係分別連接至該接地電壓、該寫入控制信號(WC)與該第九NMOS電晶體(M26)之閘極;而該第三PMOS電晶體(P21)之源極、閘極與汲極係分別連接至該第九NMOS電晶體(M26)之閘極、該寫入控制信號(WC)與該反相待機模式控制信號(/S)。其中,該第四NMOS電晶體(M21)、該第七NMOS電晶體(M24)及該第八NMOS電晶體(M25)之基極連接至該加速讀取電壓(RGND)以防止該第四NMOS電晶體(M21)因發生閂鎖而提早損毀,該反相待機模式控制信號(/S)係由該待機模式控制信號(S)經一反相器而獲得。 Please refer to FIG. 6 again, the control circuit (2) consists of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV3), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a standby mode control signal (S) and It consists of an inverted standby mode control signal (/S). The source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverting standby mode control signal (/S) and the second low voltage node (VL2); the fifth The source, gate and drain of the NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); the first low voltage node (VL1) The source of the six NMOS transistors (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) , the gate and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); the eighth NMOS transistor (M25) ) source, gate and drain are respectively connected to the acceleration read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first A delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25) between; the input of the third inverter (INV3) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the ninth NMOS transistor (M26) The source, gate and drain are respectively connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the source of the tenth NMOS transistor (M27) The pole, gate and drain are respectively connected to the ground voltage, the write control signal (WC) and the gate of the ninth NMOS transistor (M26); and the source of the third PMOS transistor (P21) , the gate electrode and the drain electrode are respectively connected to the gate electrode of the ninth NMOS transistor (M26), the write control signal (WC) and the inverting standby mode control signal (/S). Wherein, the bases of the fourth NMOS transistor (M21), the seventh NMOS transistor (M24) and the eighth NMOS transistor (M25) are connected to the accelerated reading voltage (RGND) to prevent the fourth NMOS The transistor (M21) is damaged early due to latch-up, and the inverting standby mode control signal (/S) is obtained from the standby mode control signal (S) through an inverter.
其中,該第三PMOS電晶體(P21)之汲極、該第十NMOS電晶體(M27)之汲極及該第九NMOS電晶體(M26)之閘極係連接在一起並形成一節點(C),當該寫入控制信號(WC)為邏輯低位準時,該節點(C)之電壓位準係為該反相待機模式控制信號(/S)之邏輯電壓位準,而當該寫入控制信號(WC)為邏輯高位準時,該節點(C)之電壓位準係為該接地電壓,藉此以穩定地完成寫入操作(由於寫入操作期間該節點C之電壓位準恆為該接地電壓)。 Wherein, the drain of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C ), when the write control signal (WC) is a logic low level, the voltage level of the node (C) is the logic voltage level of the inverting standby mode control signal (/S), and when the write control signal (/S) When the signal (WC) is a logic high level, the voltage level of the node (C) is the ground voltage, thereby completing the writing operation stably (because the voltage level of the node C is always the grounding voltage during the writing operation Voltage).
該控制電路(2)係設計成可因應不同操作模式而控制該第一低電壓節點(VL1)與該第二低電壓節點(VL2)之電壓位準,於寫入模式時,將選定晶胞中較接近該寫入用位元線(WBL)之驅動電晶體(即該 第一NMOS電晶體M11)的源極電壓(即該第一低電壓節點VL1)設定成較接地電壓為高之一預定電壓(即該第六NMOS電晶體(M23)之閘源極電壓VGS(M23))且將選定晶胞中另一驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成接地電壓,以便防止寫入邏輯1困難之問題。 The control circuit (2) is designed to control the voltage levels of the first low-voltage node (VL1) and the second low-voltage node (VL2) according to different operation modes, and selects the cell in the write mode. The source voltage (ie, the first low voltage node VL1 ) of the drive transistor (ie, the first NMOS transistor M11 ) that is closer to the write bit line (WBL) is set to one higher than the ground voltage The predetermined voltage (ie the gate-source voltage V GS (M23) of the sixth NMOS transistor (M23) ) and the source voltage ( That is, the second low voltage node VL2) is set to the ground voltage in order to prevent the problem of difficulty in writing logic 1s.
於讀取模式之第一階段時,將選定晶胞中較接近讀取用位元線(RBL)之驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成呈較接地電壓為低之電壓,該較接地電壓為低之該第二低電壓節點(VL2)可有效提高讀取速度,而於讀取模式之第二階段時,將選定晶胞中較接近讀取用位元線(RBL)之驅動電晶體(即該第二NMOS電晶體M12)的源極電壓設定回接地電壓,以便減少無謂的功率消耗,其中該讀取模式之該第二階段與該第一階段相隔之時間,係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算,並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間,其值可藉由該第三反相器(INV3)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。 In the first stage of the read mode, the source voltage of the drive transistor (ie, the second NMOS transistor M12 ) that is closer to the read bit line (RBL) in the unit cell (ie, the second lowest voltage) is selected. The voltage node VL2) is set to a lower voltage than the ground voltage. The second low voltage node (VL2), which is lower than the ground voltage, can effectively improve the read speed. In the second stage of the read mode, the The source voltage of the drive transistor (ie, the second NMOS transistor M12 ) in the selected cell that is closer to the read bit line (RBL) is set back to ground to reduce wasteful power consumption, wherein the read mode The time interval between the second stage and the first stage is equal to the time from the read control signal (RC) from the logic low level to the logic high level, and to the gate voltage of the eighth NMOS transistor (M25) The time sufficient to turn off the eighth NMOS transistor (M25) can be adjusted by the falling delay time of the third inverter (INV3) and the delay time provided by the first delay circuit (D1).
於待機模式時,將所有記憶體晶胞中之驅動電晶體的源極電壓設定成較接地電壓為高之該預定電壓,以便降低漏電流;而於保持模式時則將記憶體晶胞中之驅動電晶體的源極電壓設定成接地電壓,以便維持原來之保持特性,該第一低電壓節點(VL1)及該第二低電壓節點VL2於寫入模式、讀取模式、待機模式與保持模式之詳細工作電壓位準如下述表1所示。 In the standby mode, the source voltages of the drive transistors in all the memory cells are set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current; in the hold mode, the source voltages of the memory cells are set to be higher than the ground voltage. The source voltage of the driving transistor is set to the ground voltage in order to maintain the original hold characteristics. The first low voltage node (VL1) and the second low voltage node VL2 are in write mode, read mode, standby mode and hold mode The detailed operating voltage levels are shown in Table 1 below.
表1中之該寫入控制信號(WC)則為一寫入致能信號(Write Enable,簡稱WE)與對應之寫入用字元線(WWL)信號的及閘(AND gate)運算結果,此時僅於該寫入致能信號(WE)與該對應之寫入用字元線(WWL)信號均為邏輯高位準時,該寫入控制信號(WC)方為邏輯高位準;該讀取控制信號(RC)為一讀取致能信號(Read Enable,簡稱RE)與對應之讀取用字元線(RWL)信號的及閘運算結果。在此值得注意的是,對於非選定字元線及非選定位元線係設定為浮接(floating)狀態,而對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準,以防止該第七NMOS電晶體(M24)之漏電流。 The write control signal (WC) in Table 1 is the AND gate operation result of a write enable signal (Write Enable, WE for short) and the corresponding write word line (WWL) signal, At this time, only when the write enable signal (WE) and the corresponding write word line (WWL) signal are both at logic high level, the write control signal (WC) is at logic high level; the read The control signal (RC) is a sum gate operation result of a read enable signal (Read Enable, RE for short) and a corresponding read word line (RWL) signal. It is worth noting here that the unselected word lines and unselected bit lines are set to the floating state, and the read control signal (RC) during the non-read mode is set to the acceleration Read the level of the voltage (RGND) to prevent the leakage current of the seventh NMOS transistor (M24).
請參考第6圖,該預充電電路(3)係由一第四PMOS電晶體(P31)以及一預充電信號(P)所組成,該第四PMOS電晶體(P31)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該預充電信號(P)與相對應之讀取用位元線(RBL),以便於預充電期間,藉由邏輯低位準之該預充電信號(P),以將相對應之讀取用位元線(RBL)預充電至該電源供應 電壓(VDD)之位準。 Please refer to FIG. 6, the precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P). The source and gate of the fourth PMOS transistor (P31) and the drain are respectively connected to the power supply voltage (V DD ), the precharge signal (P) and the corresponding read bit line (RBL), so that during precharge, the logic low level of the The precharge signal (P) is used to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V DD ).
請再參考第6圖,該待機啟動電路(4)係由一第五PMOS電晶體(P41)、一第十一NMOS電晶體(M41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成。該第五PMOS電晶體(P41)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該反相待機模式控制信號(/S)與該第十一NMOS電晶體(M41)之汲極;該第十一NMOS電晶體(M41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第五PMOS電晶體(P41)之汲極;該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S),而該第二延遲電路(D2)之輸出則連接至該第十一NMOS電晶體(M41)之閘極。 Please refer to FIG. 6 again, the standby startup circuit (4) consists of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2) and the inverting standby Mode control signal (/S). The source, gate and drain of the fifth PMOS transistor (P41) are respectively connected to the power supply voltage (V DD ), the inverting standby mode control signal (/S) and the eleventh NMOS transistor The drain of (M41); the source, gate and drain of the eleventh NMOS transistor (M41) are respectively connected to the first low voltage node (VL1) and the output of the second delay circuit (D2) and the drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverting standby mode control signal (/S), and the output of the second delay circuit (D2) is Connected to the gate of the eleventh NMOS transistor (M41).
請再參考第6圖,該高電壓位準控制電路(5)係由一第六PMOS電晶體(P51)、一第七PMOS電晶體(P52)以及一第四反相器(INV4)所組成,其中該第六PMOS電晶體(P51)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該讀取控制信號(RC)與該高電壓節點(VH),該第七PMOS電晶體(P52)之源極、閘極與汲極係分別連接至一第一高電源供應電壓(VDDH1)、該第四反相器(INV4)之輸出與該高電壓節點(VH),而該第四反相器(INV4)之輸入係供接收該讀取控制信號(RC),而輸出則連接至該第七PMOS電晶體(P52)之汲極。在此值得注意的是,該第六PMOS電晶體(P51)及該第七PMOS電晶體(P52)之的基極連接至該第一高電源供應電壓(VDDH1)以防止該第六PMOS電晶體(P51)因發生閂鎖而提早損毀,且該第一反相器係連接在該電源供應電壓(VDD)與該第一低電壓節點(VL1)之間,而該第二反相器則連接在該高電壓節點(VH)與該第二低 電壓節點(VL2)之間。 Please refer to FIG. 6 again, the high voltage level control circuit (5) is composed of a sixth PMOS transistor (P51), a seventh PMOS transistor (P52) and a fourth inverter (INV4). , wherein the source, gate and drain of the sixth PMOS transistor (P51) are respectively connected to the power supply voltage (V DD ), the read control signal (RC) and the high voltage node (VH), The source, gate and drain of the seventh PMOS transistor (P52) are respectively connected to a first high power supply voltage (V DDH1 ), the output of the fourth inverter (INV4) and the high voltage node (VH), and the input of the fourth inverter (INV4) is used to receive the read control signal (RC), and the output is connected to the drain of the seventh PMOS transistor (P52). It is worth noting here that the bases of the sixth PMOS transistor (P51) and the seventh PMOS transistor (P52) are connected to the first high power supply voltage (V DDH1 ) to prevent the sixth PMOS transistor The crystal (P51) is damaged early due to latch-up, and the first inverter is connected between the power supply voltage (V DD ) and the first low-voltage node ( VL1 ), and the second inverter is Then it is connected between the high voltage node (VH) and the second low voltage node (VL2).
請再參考第6圖,該寫入用字元線控制電路(6)係由一第八PMOS電晶體(P61)、一第九PMOS電晶體(P62)、一第十PMOS電晶體(P63)、一第十二NMOS電晶體(M61)、一第五反相器(INV5)、一第六反相器(INV6)、一第二高電源供應電壓(VDDH2)、一寫入用字元線(WWL)以及一寫入用字元線控制信號(WWLC)所組成。該第八PMOS電晶體(P61)之源極、閘極與汲極係分別連接至該第二高電源供應電壓(VDDH2)、該第五反相器(INV5)之輸出與該第九PMOS電晶體(P62)之源極;該第九PMOS電晶體(P62)之源極、閘極與汲極係分別連接至該第八PMOS電晶體(P61)之汲極、該第六反相器(INV6)之輸出與該寫入用字元線控制信號(WWLC);該第十PMOS電晶體(P63)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該第五反相器(INV5)之輸出與該寫入用字元線控制信號(WWLC);該第十二NMOS電晶體(M61)之源極、閘極與汲極係分別連接至該接地電壓、該第五反相器(INV5)之輸出與該寫入用字元線控制信號(WWLC);該第五反相器(INV5)之輸入係供接收該寫入用字元線(WWL),而該第六反相器(INV6)之輸入則與該第五反相器(INV5)之輸出連接。 Please refer to FIG. 6 again, the writing word line control circuit (6) consists of an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), and a tenth PMOS transistor (P63) , a twelfth NMOS transistor (M61), a fifth inverter (INV5), a sixth inverter (INV6), a second high power supply voltage (V DDH2 ), a writing character line (WWL) and a write word line control signal (WWLC). The source, gate and drain of the eighth PMOS transistor (P61) are respectively connected to the second high power supply voltage (V DDH2 ), the output of the fifth inverter (INV5) and the ninth PMOS The source of the transistor (P62); the source, gate and drain of the ninth PMOS transistor (P62) are respectively connected to the drain of the eighth PMOS transistor (P61) and the sixth inverter The output of (INV6) and the writing word line control signal (WWLC); the source, gate and drain of the tenth PMOS transistor (P63) are respectively connected to the power supply voltage (V DD ), The output of the fifth inverter (INV5) and the writing word line control signal (WWLC); the source, gate and drain of the twelfth NMOS transistor (M61) are respectively connected to the ground voltage, the output of the fifth inverter (INV5) and the write word line control signal (WWLC); the input of the fifth inverter (INV5) is for receiving the write word line (WWL) ), and the input of the sixth inverter (INV6) is connected to the output of the fifth inverter (INV5).
該寫入用字元線控制電路(6)於致能時係採用二階段操作以有效解決10奈米以下SRAM操作電壓降為0.9以下時易造成寫入時間無法滿足規範之問題,於該寫入用字元線(WWL)致能的第一階段,將該寫入用字元線控制信號(WWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2),以有效提高寫入速度,而於該第一階段後之 第二階段時,則將該寫入用字元線控制信號(WWLC)拉低回該電源供應電壓(VDD),以減緩寫干擾入;其中,該寫入用字元線控制電路(6)之該第二階段與該第一階段相隔之時間,係等於該第五反相器(INV5)之輸出足以導通該第八PMOS電晶體(P61)之時間起算,並至該第六反相器(INV6)之輸出足以關閉該第九PMOS電晶體(P62)為止之時間,其值可藉由該第六反相器(INV6)之上升延遲時間來調整。 When the writing word line control circuit (6) is enabled, it adopts two-stage operation to effectively solve the problem that the writing time cannot meet the specification when the operating voltage of the SRAM below 10 nm falls below 0.9. In the first stage of enabling the input word line (WWL), the write word line control signal (WWLC) is set to the second highest power supply voltage (V DD ) higher than the power supply voltage (V DD ). V DDH2 ) to effectively improve the writing speed, and in the second stage after the first stage, the writing word line control signal (WWLC) is pulled back to the power supply voltage (V DD ), In order to slow down the write disturbance; wherein, the time interval between the second stage and the first stage of the writing word line control circuit (6) is equal to the output of the fifth inverter (INV5) enough to turn on the From the time of the eighth PMOS transistor (P61) to the time until the output of the sixth inverter (INV6) is sufficient to turn off the ninth PMOS transistor (P62), its value can be determined by the sixth inverter (INV6) Adjust the rise delay time of the device (INV6).
請再參考第6圖,該讀取用字元線控制電路(7)係由一第十一PMOS電晶體(P71)、一第十二PMOS電晶體(P72)、一第十三PMOS電晶體(P73)、一第十三NMOS電晶體(M71)、一第七反相器(INV7)、一第八反相器(INV8)、該第二高電源供應電壓(VDDH2)、一讀取用字元線(RWL)以及一讀取用字元線控制信號(RWLC)所組成。該第十一PMOS電晶體(P71)之源極、閘極與汲極係分別連接至該第二高電源供應電壓(VDDH2)、該第七反相器(INV7)之輸出與該第十二PMOS電晶體(P72)之源極;該第十二PMOS電晶體(P72)之源極、閘極與汲極係分別連接至該該第十一PMOS電晶體(P71)之汲極、該第八反相器(INV8)之輸出與該讀取用字元線控制信號(RWLC);第十三PMOS電晶體(P73)之源極、閘極與汲極係分別連接至該電源供應電壓(VDD)、該第七反相器(INV7)之輸出與該讀取用字元線控制信號(RWLC);該第十三NMOS電晶體(M71)之源極、閘極與汲極係分別連接至該接地電壓、該第七反相器(INV7)之輸出與該讀取用字元線控制信號(RWLC);該第七反相器(INV7)之輸入係供接收該讀取用字元線(RWL),而該第八反相器(INV8)之輸入則與該第七反相器(INV7)之輸出連接。 Please refer to FIG. 6 again, the read word line control circuit (7) consists of an eleventh PMOS transistor (P71), a twelfth PMOS transistor (P72), and a thirteenth PMOS transistor (P73), a thirteenth NMOS transistor (M71), a seventh inverter (INV7), an eighth inverter (INV8), the second high power supply voltage (V DDH2 ), a read It consists of a word line (RWL) and a read word line control signal (RWLC). The source, gate and drain of the eleventh PMOS transistor (P71) are respectively connected to the second high power supply voltage (V DDH2 ), the output of the seventh inverter (INV7) and the tenth Sources of two PMOS transistors (P72); the source, gate and drain of the twelfth PMOS transistor (P72) are respectively connected to the drain of the eleventh PMOS transistor (P71), the The output of the eighth inverter (INV8) and the read word line control signal (RWLC); the source, gate and drain of the thirteenth PMOS transistor (P73) are respectively connected to the power supply voltage (V DD ), the output of the seventh inverter (INV7) and the read word line control signal (RWLC); the source, gate and drain of the thirteenth NMOS transistor (M71) are connected are respectively connected to the ground voltage, the output of the seventh inverter (INV7) and the read word line control signal (RWLC); the input of the seventh inverter (INV7) is used for receiving the read word line (RWL), and the input of the eighth inverter (INV8) is connected to the output of the seventh inverter (INV7).
該讀取用字元線控制電路(7)於致能時係採用二階段操作,於該讀取用字元線(RWL)致能的第一階段,將該讀取用字元線控制信號(RWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2),以有效提高讀取速度,而於該第一階段後之第二階段時,則將該讀取用字元線控制信號(RWLC)拉低回該電源供應電壓(VDD),以減緩讀取擾入;其中,該讀取用字元線控制電路(7)之該第二階段與該第一階段相隔之時間,係等於該第七反相器(INV7)之輸出足以導通該第十一PMOS電晶體(P71)之時間起算,並至該第八反相器(INV8)之輸出足以關閉該第十二PMOS電晶體(P72)為止之時間,其值可藉由該第八反相器(INV8)之上升延遲時間來調整。 The read word line control circuit (7) adopts a two-stage operation when it is enabled. In the first stage of the read word line (RWL) enabling, the read word line control signal (RWLC) is set to the second high power supply voltage (V DDH2 ) higher than the power supply voltage (V DD ) to effectively improve the reading speed, and in the second stage after the first stage, the Pull down the read word line control signal (RWLC) back to the power supply voltage (V DD ) to slow down read disturbance; wherein, the second read word line control circuit (7) The time interval between the phase and the first phase is equal to the time when the output of the seventh inverter (INV7) is sufficient to turn on the eleventh PMOS transistor (P71), and ends at the eighth inverter (INV8) The time until the output is sufficient to turn off the twelfth PMOS transistor (P72) can be adjusted by the rise delay time of the eighth inverter (INV8).
請再參考第6圖,該寫入驅動電路(8)係由一第十四PMOS電晶體(P81)、一第十四NMOS電晶體(M81)、一第十五NMOS電晶體(M82)、一第十六NMOS電晶體(M83)、一第九反相器(INV9)、一第十反相器(INV10)、一電容器(Cap)、一輸入資料(Din)、一行解碼器輸出信號(Y)、一第三延遲電路(D3)、一第四延遲電路(D4)以及一第三高電源供應電壓(VDDH3)所組成,其中該第十四PMOS電晶體(P81)之源極、閘極與汲極係分別連接至該第三高電源供應電壓(VDDH3)、該第九反相器(INV9)之輸出與該第十四NMOS電晶體(M81)之汲極,該第十四NMOS電晶體(M81)之源極、閘極與汲極係分別連接至該第十六NMOS電晶體(M83)之汲極、該第九反相器(INV9)之輸出與該第十四PMOS電晶體(P81)之汲極,該第十五NMOS電晶體(M82)之源極、閘極與汲極係分別連接至該接地電壓、該第三延遲電路(D3)之輸出與該第十四 PMOS電晶體(P81)之汲極,該第十六NMOS電晶體(M83)之源極、閘極與汲極係分別連接至該接地電壓、該第十反相器(INV10)之輸出與該第十四NMOS電晶體(M81)之源極,該第九反相器(INV9)之輸入係供接收該輸入資料(Din),而輸出則連接至該第十四PMOS電晶體(P81)之閘極、該第十四NMOS電晶體(M81)之閘極以及該第三延遲電路(D3)之輸入,該第十反相器(INV10)之輸入係供接收該行解碼器輸出信號(Y),而輸出則連接至該第四延遲電路(D4)之輸入以及該第十六NMOS電晶體(M83)之閘極,該電容器(Cap)之一端係連接至該第四延遲電路(D4)之輸出,而該電容器(Cap)之另一端則連接至該第十四NMOS電晶體(M81)之源極以及該第十六NMOS電晶體(M83)之汲極,其中,該第十四PMOS電晶體(P81)之汲極、該第十四NMOS電晶體(M81)之汲極與該第十五NMOS電晶體(M82)之汲極係共同連接至該寫入用位元線(WBL),該寫入用位元線(WBL)於寫入邏輯0之第一階段係設計成低於於該接地電壓之電壓位準,以加速寫入邏輯0之速度,而於寫入邏輯1時則設計成高於該電源供應電壓(VDD)之該第三高電源供應電壓(VDDH3)的位準,以加速寫入邏輯1之速度。 Please refer to FIG. 6 again, the writing driving circuit (8) consists of a fourteenth PMOS transistor (P81), a fourteenth NMOS transistor (M81), a fifteenth NMOS transistor (M82), A sixteenth NMOS transistor (M83), a ninth inverter (INV9), a tenth inverter (INV10), a capacitor (Cap), an input data (Din), a line of decoder output signals ( Y), a third delay circuit (D3), a fourth delay circuit (D4) and a third high power supply voltage (V DDH3 ), wherein the source of the fourteenth PMOS transistor (P81), The gate and the drain are respectively connected to the third high power supply voltage (V DDH3 ), the output of the ninth inverter (INV9) and the drain of the fourteenth NMOS transistor (M81). The source, gate and drain of the four NMOS transistors (M81) are connected to the drain of the sixteenth NMOS transistor (M83), the output of the ninth inverter (INV9) and the fourteenth NMOS transistor (M83), respectively. The drain of the PMOS transistor (P81), the source, gate and drain of the fifteenth NMOS transistor (M82) are respectively connected to the ground voltage, the output of the third delay circuit (D3) and the first The drain of the fourteenth PMOS transistor (P81), the source, gate and drain of the sixteenth NMOS transistor (M83) are respectively connected to the ground voltage and the output of the tenth inverter (INV10) With the source of the fourteenth NMOS transistor (M81), the input of the ninth inverter (INV9) is for receiving the input data (Din), and the output is connected to the fourteenth PMOS transistor (P81) ), the gate of the fourteenth NMOS transistor (M81) and the input of the third delay circuit (D3), the input of the tenth inverter (INV10) is for receiving the output signal of the row decoder (Y), and the output is connected to the input of the fourth delay circuit (D4) and the gate of the sixteenth NMOS transistor (M83), and one end of the capacitor (Cap) is connected to the fourth delay circuit ( D4) output, and the other end of the capacitor (Cap) is connected to the source of the fourteenth NMOS transistor (M81) and the drain of the sixteenth NMOS transistor (M83), wherein the tenth The drains of the four PMOS transistors (P81), the drains of the fourteenth NMOS transistor (M81) and the drains of the fifteenth NMOS transistor (M82) are jointly connected to the write bit line ( WBL), the write bit line (WBL) is designed to be lower than the voltage level of the ground voltage in the first stage of writing logic 0 to accelerate the speed of writing logic 0. 1 is designed to be a level higher than the third highest power supply voltage (V DDH3 ) of the power supply voltage (V DD ) to speed up the speed of writing logic 1s.
該寫入驅動電路(8)致能與否係由該行解碼器輸出信號(Y)之邏輯位準決定,當該行解碼器輸出信號(Y)為邏輯低位準時,該寫入驅動電路(8)為非致能狀態,而當該行解碼器輸出信號(Y)為邏輯高位準時,該寫入驅動電路(8)處於致能狀態。當該行解碼器輸出信號(Y)為邏輯低位準時,該第十反相器(INV10)之輸出為邏輯高位準,一方面導通該第十六NMOS電晶體(M83),另一方面經過該第四延遲電路(D4)所 提供之延遲時間後對該電容器(Cap)之一端充電,由於導通的該第十六NMOS電晶體(M83),使得該電容器(Cap)之另一端為該接地電壓,而該電容器(Cap)之一端則會因電容器(Cap)的充電而保持該電源供應電壓(VDD)之電壓位準。 Whether the write driving circuit (8) is enabled is determined by the logic level of the output signal (Y) of the row decoder. When the output signal (Y) of the row decoder is at a logic low level, the writing driving circuit ( 8) is a non-enable state, and when the row decoder output signal (Y) is at a logic high level, the write-in driver circuit (8) is in an enabled state. When the line decoder output signal (Y) is at a logic low level, the output of the tenth inverter (INV10) is at a logic high level, which turns on the sixteenth NMOS transistor (M83) on the one hand, and passes through the After the delay time provided by the fourth delay circuit (D4), one end of the capacitor (Cap) is charged. Due to the conduction of the sixteenth NMOS transistor (M83), the other end of the capacitor (Cap) is the ground voltage , and one end of the capacitor (Cap) will maintain the voltage level of the power supply voltage (V DD ) due to the charging of the capacitor (Cap).
該寫入驅動電路(8)於寫入邏輯0之致能狀態時係採用二階段操作,於該寫入驅動電路(8)致能的第一階段,邏輯高位準之該行解碼器輸出信號(Y),使得該第十反相器(INV10)之輸出為邏輯低位準,一方面使該第十六NMOS電晶體(M83)為截止(OFF)狀態,另一方面經過該第四延遲電路(D4)所提供之延遲時間後對該電容器(Cap)之一端快速放電至該接地電壓,由於此時該輸入資料(Din)為邏輯低位準,使得該第九反相器(INV9)之輸出為邏輯高位準,於是導通該第十四NMOS電晶體(M81),並使該第十四PMOS電晶體(P81)為截止(OFF)狀態,因此該寫入用位元線(WBL)之電壓位準於該寫入驅動電路(8)寫入邏輯0之第一階段時滿足方程式(3):
The write-in driver circuit (8) adopts a two-stage operation when the write-in
VWBL1=-VDD×Cap/(Cap+CWBL) (3) V WBL1 =-V DD ×Cap/(Cap+C WBL ) (3)
其中,VWBL1表示該寫入用位元線(WBL)於寫入邏輯0之第一階段的電壓位準,VWBL1的絕對值設計為小於該第三NMOS電晶體(M13)之臨界電壓,例如可設計為-100mV、-150mV或-200mV,VDD為該電源供應電壓(VDD)之電壓位準,而Cap與CWBL分別表示該該電容器(Cap)之電容值與該寫入用位元線(WBL)之寄生電容值。
Wherein, V WBL1 represents the voltage level of the write bit line (WBL) in the first stage of writing
當邏輯低位準之該輸入資料(Din)經過該該第九反相器(INV9)以及該第三延遲電路(D3)所提供之延遲時間後,該寫入驅動電
路(8)進入致能的第二階段,此時由於該第十五NMOS電晶體(M82)為導通狀態,使得該寫入用位元線(WBL)之電壓位準於該寫入驅動電路(8)寫入邏輯0之第二階段時滿足方程式(4):
When the input data (Din) at a logic low level passes through the delay time provided by the ninth inverter (INV9) and the third delay circuit (D3), the write drive circuit
The circuit (8) enters the second stage of enabling. At this time, since the fifteenth NMOS transistor (M82) is in an on state, the voltage level of the write bit line (WBL) is at the level of the write drive circuit. (8) Equation (4) is satisfied when the second stage of
VWBL2=0 (4) V WBL2 = 0 (4)
茲說明第6圖之本發明較佳實施例的工作原理如下: The working principle of the preferred embodiment of the present invention shown in Fig. 6 is described as follows:
(I)寫入模式(write mode) (I) write mode (write mode)
於寫入操作開始前,該待機模式控制信號(S)與該寫入控制信號(WC)為邏輯低位準,使得該第三PMOS電晶體(P21)導通(ON),並使得該第十NMOS電晶體(M27)截止(OFF),於是該第三PMOS電晶體(P21)之汲極呈邏輯高位準,該邏輯高位準之該第三PMOS電晶體(P21)之汲極會導通該第九NMOS電晶體(M26),並使得該第一低電壓節點(VL1)呈接地電壓。 Before the writing operation starts, the standby mode control signal (S) and the writing control signal (WC) are at a logic low level, so that the third PMOS transistor (P21) is turned on (ON), and the tenth NMOS transistor is turned on. The transistor (M27) is turned off (OFF), so the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at the logic high level will turn on the ninth The NMOS transistor (M26) makes the first low voltage node (VL1) be at the ground voltage.
而於寫入操作期間內,該寫入控制信號(WC)為邏輯高位準,使得該第三PMOS電晶體(P21)截止,該第十NMOS電晶體(M27)導通,並使得該第三PMOS電晶體(P21)之汲極呈邏輯低位準,該邏輯低位準之該第三PMOS電晶體(P21)之汲極會使得該第九NMOS電晶體(M26)截止,並使得該第一低電壓節點(VL1)等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M26),藉此得以有效防止寫入邏輯1困難之問題。第7a圖所示為第6圖之本發明較佳實施例於寫入邏輯0期間之簡化電路圖,而第7b圖所示則為寫入邏輯1期間之簡化電路圖。
During the write operation period, the write control signal (WC) is at a logic high level, so that the third PMOS transistor (P21) is turned off, the tenth NMOS transistor (M27) is turned on, and the third PMOS transistor (M27) is turned on. The drain of the transistor (P21) is at a logic low level, and the drain of the third PMOS transistor (P21) at the logic low level will turn off the ninth NMOS transistor (M26) and make the first low voltage The node ( VL1 ) is equal to the gate-source voltage V GS ( M26 ) of the sixth NMOS transistor ( M23 ), thereby effectively preventing the problem of difficulty in writing logic 1s. FIG. 7a shows a simplified circuit diagram of the preferred embodiment of the present invention of FIG. 6 during writing of a
接下來依4種寫入狀態來說明第7a圖與第7b圖之本發明較佳實施例如何完成寫入邏輯0與寫入邏輯1動作。
Next, according to four write states, how the preferred embodiment of the present invention shown in FIGS. 7a and 7b completes the operations of writing
(一)節點A原本儲存邏輯0,而現在欲寫入邏輯0:
(1) Node A originally stored
在寫入動作發生前(該寫入用字元線控制信號WWLC為接地電壓),該第一NMOS電晶體(M11)為導通(ON)。因為該第一NMOS電晶體(M11)為ON,所以當寫入動作開始時,該寫入用字元線(WWL)由Low(接地電壓)轉High(電源供應電壓VDD)。當該寫入用字元線控制信號(WWLC)的電壓大於該第三NMOS電晶體(M13)(即存取電晶體)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為該寫入用位元線(WBL)於寫入邏輯0之第一階段係設計成低於於該接地電壓之電壓位準,而於寫入邏輯0之第二階段則拉回至該接地電壓,所以會將該節點A放電,而完成邏輯0的寫入動作,直到寫入週期結束。
Before the writing operation occurs (the writing word line control signal WWLC is at the ground voltage), the first NMOS transistor (M11) is turned on (ON). Since the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line (WWL) changes from Low (ground voltage) to High (power supply voltage V DD ). When the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned off (OFF). ) turns on (ON), at this time, because the write bit line (WBL) is designed to be lower than the ground voltage in the first stage of writing
(二)節點A原本儲存邏輯0,而現在欲寫入邏輯1:
(2) Node A originally stored
在寫入動作發生前(該寫入用字元線控制信號WWLC為接地電壓),該第一NMOS電晶體(M11)為導通(ON)。在此值得注意的是,因為該第一NMOS電晶體(M11)為ON,所以當寫入動作開始時,該寫入用字元線控制信號(WWLC)由Low(接地電壓)轉High,該節點A的電壓會由於寄生電容耦合效應而跟隨該寫入用字元線控制信號(WWLC)的電壓呈現些微上升。當該寫入用字元線控制信號(WWLC)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為該寫入用位元線(WBL)為該 第三高電源供應電壓(VDDH3)之電壓位準,並且因為該第一NMOS電晶體(M11)仍為ON且該節點B仍處於電壓位準為接近於該電源供應電壓(VDD)之電壓位準的初始狀態,所以該第一PMOS電晶體(P11)仍為截止(OFF),而該節點A之寫入初始瞬間電壓(VAWI)滿足方程式(5): Before the writing operation occurs (the writing word line control signal WWLC is at the ground voltage), the first NMOS transistor (M11) is turned on (ON). It is worth noting here that because the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line control signal (WWLC) changes from Low (ground voltage) to High, and the The voltage of the node A will rise slightly following the voltage of the write word line control signal (WWLC) due to the parasitic capacitive coupling effect. When the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF (OFF) to ON (ON) , because the write bit line (WBL) is the voltage level of the third high power supply voltage (V DDH3 ), and because the first NMOS transistor (M11) is still ON and the node B is still In the initial state where the voltage level is close to the voltage level of the power supply voltage (V DD ), the first PMOS transistor (P11) is still turned off (OFF), and the initial instantaneous voltage of the node A is written (V AWI ) satisfies equation (5):
VAWI1==VDDH3×(RM11+RM23)/(RM13+RM11+RM23)>VTM12 (5)其中,VAWI1表示節點A寫入邏輯1之寫入初始瞬間電壓,RM13表示該第三NMOS電晶體(M13)之導通電阻,RM11表示該第一NMOS電晶體(M11)之導通電阻,RM23表示該第六NMOS電晶體(M23)之導通電阻,而VDDH3與VTM12分別表示該第三高電源供應電壓之電壓位準與該第二NMOS電晶體(M12)之臨界電壓。由於在該第一低電壓節點(VL1)處提供一等於該第六NMOS電晶體(M23)之閘-源極電壓VGS(M23)之電壓位準,因此可輕易地將節點A之電壓位準設定成比第4圖之習知5T靜態隨機存取記憶體晶胞之該節點A之電壓位準還要高許多。該還要高許多之分壓電壓位準係足以使該第二NMOS電晶體(M12)導通,於是使得節點B放電至一較低電壓位準,該節點B之較低電壓位準會使得該第一NMOS電晶體(M11)之導通等效電阻(RM11)呈現較高的電阻值,該第一NMOS電晶體(M11)之該較高的電阻值會於該節點A獲得較高電壓位準,該節點A之較高電壓位準又會經由該第二反相器(由第二PMOS電晶體P12與第二NMOS電晶體M12所組成),而使得該節點B呈現更低電壓位準,該節點B之更低電壓位準又會經由該第一反相器(由第一PMOS電晶體P11與第一NMOS電晶體M11所組成),而使得該節點A獲得更高電壓位準,依此循環,即可將該節點A充電至該電源供應電壓(VDD),而完成邏輯1的寫入動作。
V AWI1 ==V DDH3 ×(R M11 +R M23 )/(R M13 +R M11 +R M23 )>V TM12 (5) Among them, V AWI1 represents the initial instantaneous voltage of writing
其中,該第一低電壓節點(VL1)於節點A原本儲存邏輯0,而在寫入邏輯1之期間,係具有等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M23)的電壓位準,而於寫入邏輯1後,又會因經由該第九NMOS電晶體(M26)放電而為接地電壓之位準。
Wherein, the first low voltage node (VL1) originally stores
在此值得注意的是,本發明係藉由二階段的寫入用字元線控制電路(6)以有效解決10奈米以下SRAM操作電壓降為0.9V以下時易造成寫入時間無法滿足規範之問題,該寫入用字元線控制電路(6)於該寫入用字元線(WWL)致能的第一階段,將該寫入用字元線控制信號(WWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2),由於在節點A原本儲存邏輯0而在寫入邏輯1初期,該第三NMOS電晶體(M13)係工作於飽和區,飽和區之電流係與閘-源極電壓VGS(M13)之電壓位準扣減其臨界電壓VTM13後之平方成正比例,因此將該寫入用字元線控制信號(WWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2)的該第一階段期間,可有效加速寫入邏輯1之速度;此外,為了減緩寫入期間對於半選定晶胞的干擾現象,於該第一階段後之第二階段期間,則將該寫入用字元線控制信號(WWLC)拉低回該電源供應電壓(VDD)之電壓位準,其中,該寫入用字元線控制電路(6)之該第二階段與該第一階段相隔之時間,係等於該第五反相器(INV5)之輸出足以導通該第八PMOS電晶體(P61)之時間起算,並至該第六反相器(INV6)之輸出足以關閉該第九PMOS電晶體(P62)為止之時間,其值可藉由該第六反相器(INV6)之上升延遲時間來調整。
It is worth noting here that the present invention uses a two-stage writing word line control circuit (6) to effectively solve the problem that the writing time cannot meet the specification when the operating voltage of the SRAM below 10 nm is below 0.9V. In the first stage of enabling the writing word line (WWL), the writing word line control circuit (6) sets the writing word line control signal (WWLC) to a higher value than the writing word line control signal (WWLC). The power supply voltage (V DD ) is still higher than the second high power supply voltage (V DDH2 ), since the
(三)節點A原本儲存邏輯1,而現在欲寫入邏輯1:
(3) Node A originally stored
在寫入動作發生前(該寫入用字元線控制信號WWLC為接地電壓),該第一PMOS電晶體(P11)為導通(ON)。當該寫入用字元線控制信號(WWLC)由Low(接地電壓)轉High,由於該節點A為該電源供應電壓(VDD)之電壓位準,且該寫入用位元線(WBL)為該第三高電源供應電壓(VDDH3)之電壓位準,因此當該第二高電源供應電壓(VDDH2)設定為高於該電源供應電壓(VDD)但低於該電源供應電壓(VDD)與該第三NMOS電晶體(M13)臨界電壓之VTM13的總和時,亦即 Before the write operation occurs (the write word line control signal WWLC is at the ground voltage), the first PMOS transistor ( P11 ) is turned on (ON). When the write word line control signal (WWLC) changes from Low (ground voltage) to High, since the node A is the voltage level of the power supply voltage (V DD ), and the write bit line (WBL) ) is the voltage level of the third high power supply voltage (V DDH3 ), so when the second high power supply voltage (V DDH2 ) is set higher than the power supply voltage (V DD ) but lower than the power supply voltage (V DD ) and the sum of the threshold voltage of the third NMOS transistor (M13) V TM13 , namely
VDD<VDDH2<VDD+VTM13 (6)會使該第三NMOS電晶體(M13)繼續保持截止(OFF)狀態;此時因為該第一PMOS電晶體(P11)仍為ON,所以該節點A的電壓會維持於該電源供應電壓(VDD)之電壓位準,直到寫入週期結束。 V DD <V DDH2 <V DD +V TM13 (6) will keep the third NMOS transistor (M13) in an OFF state; at this time, because the first PMOS transistor (P11) is still ON, so The voltage of the node A is maintained at the voltage level of the power supply voltage (V DD ) until the end of the write cycle.
(四)節點A原本儲存邏輯1,而現在欲寫入邏輯0:
(4) Node A originally stored
在寫入動作發生前(該寫入用字元線控制信號WWLC為接地電壓),該第一PMOS電晶體(P11)為導通(ON)。當該寫入用字元線控制信號(WWLC)由Low(接地電壓)轉High,且該寫入用字元線控制信號(WWLC)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為該寫入用位元線(WBL)為滿足方程式(3)的電壓位準(VWBL1),其小於0V,並且因為該第一PMOS電晶體(P11)仍為ON且該節點B處於電壓位準為接近於該接地電壓之電壓位準的初始狀態,所以該第一NMOS電晶體(M11)仍為截止, 而該節點A之寫入初始瞬間電壓(VAWI0)滿足方程式(7): Before the write operation occurs (the write word line control signal WWLC is at the ground voltage), the first PMOS transistor ( P11 ) is turned on (ON). When the writing word line control signal (WWLC) turns from Low (ground voltage) to High, and the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13) At this time, the third NMOS transistor (M13) is turned from OFF (OFF) to ON (ON). At this time, because the write bit line (WBL) is a voltage level (V WBL1 ) that satisfies equation (3) , which is less than 0V, and because the first PMOS transistor (P11) is still ON and the node B is in an initial state where the voltage level is close to the voltage level of the ground voltage, the first NMOS transistor (M11 ) is still off, and the initial write-in instantaneous voltage (V AWI0 ) of the node A satisfies equation (7):
VAWI0=VWBL1×RP11/(RM13+RP11)+VDD×RM13/(RM13+RP11) (7) V AWI0 =V WBL1 ×R P11 /(R M13 +R P11 )+V DD ×R M13 /(R M13 +R P11 ) (7)
VAWI0表示節點A由邏輯1寫入邏輯0之寫入初始瞬間電壓,RM13與RP11分別表示該第三NMOS電晶體(M13)與該第一PMOS電晶體(P11)之導通電阻,而VWBL1與VDD分別表示該寫入用位元線(WBL)於寫入邏輯0之第一階段的電壓位準與該電源供應電壓(VDD)之電壓位準,由於由邏輯1寫入邏輯0時,該第三NMOS電晶體(M13)係工作於飽和區,飽和區之電流係與其閘-源極電壓VGS(M13)之電壓位準扣減其臨界電壓後之平方成正比例,因此藉由該寫入用位元線(WBL)於寫入邏輯0之第一階段的電壓位準(VWBL1)小於0V以及藉由將該寫入用字元線控制信號(WWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2)的設計方式,可有效加速由邏輯1寫入邏輯0之速度。
V AWI0 represents the initial write voltage at node A from
在此值得注意的是,節點A由邏輯0寫入邏輯1以及由邏輯1寫入邏輯0時,該第三NMOS電晶體(M13)係工作於飽和區,飽和區之電流係與其閘-源極電壓VGS(M13)之電壓位準扣減其臨界電壓後之平方成正比例,因此藉由二階段的該寫入用字元線控制電路(6)而於該寫入用字元線(WWL)致能的第一階段,將該寫入用字元線控制信號(WWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2),可有效加速節點A由邏輯0寫入邏輯1以及由邏輯1寫入邏輯0之寫入速度;再者,於節點A由邏輯1寫入邏輯0時,可藉由前述方程式(3)於由邏輯1寫入邏輯0之初期提供低於該接地電壓之電壓位準(VWBL1)給該寫入用位元線(WBL),其中,VWBL1的絕對值限定為小於該第三NMOS電晶體(M13)之臨界電壓,
例如可設計為-100mV、-150mV或-200mV,藉此可藉由進一步加大工作於飽和區之該第三NMOS電晶體(M13)的閘-源極電壓VGS(M13),以有效地提高節點A由邏輯1寫入邏輯0之寫入速度。
It is worth noting here that when node A is written from
(II)讀取模式(read mode) (II) read mode (read mode)
於讀取操作開始前,該讀取控制信號(RC)、該寫入控制信號(WC)及該待機模式控制信號(S)均為邏輯低位準,使得該第三PMOS電晶體(P21)導通,並使得該第十NMOS電晶體(M27)截止,於是該第三PMOS電晶體(P21)之汲極呈邏輯高位準,邏輯高位準之該第三PMOS電晶體(P21)之汲極會導通第九NMOS電晶體(M26),並使得該第一低電壓節點(VL1)呈接地電壓。另一方面,由於該讀取控制信號(RC)為邏輯低位準,使得該第七NMOS電晶體(M24)截止(OFF),並使得該第八NMOS電晶體(M25)導通(ON)。 Before the read operation starts, the read control signal (RC), the write control signal (WC) and the standby mode control signal (S) are all logic low levels, so that the third PMOS transistor (P21) is turned on , and the tenth NMOS transistor (M27) is turned off, so the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at the logic high level is turned on The ninth NMOS transistor (M26) makes the first low voltage node (VL1) be at the ground voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned on (ON).
在此值得注意的是,於讀取操作開始前之預充電期間,該預充電信號(P)係為邏輯低位準,藉此以將相對應之讀取用位元線(RBL)預充電至該電源供應電壓(VDD)之位準,惟由於例如10奈米以下製程技術之操作電壓將降為0.9伏特以下時將造成讀取速度降低而無法滿足規範之問題,因此,本發明提出二階段的讀取控制以於提高讀取速度並滿足規範的同時,亦避免無謂的功率耗損。 It should be noted here that during the precharge period before the start of the read operation, the precharge signal (P) is at a logic low level, thereby precharging the corresponding read bit line (RBL) to The level of the power supply voltage (V DD ) cannot meet the standard problem because the operating voltage of the process technology below 10 nm will be reduced to less than 0.9 volt, which will cause the reading speed to decrease and cannot meet the specification. Therefore, the present invention proposes two Staged read control to improve read speed and meet specifications while avoiding unnecessary power consumption.
第6圖所示之本發明較佳實施例係藉由二階段的讀取控制以於提高讀取速度的同時,亦避免無謂的功率耗損,於讀取操作之第一階段,該讀取控制信號(RC)為邏輯高位準,使得該第七NMOS電晶體(M24)導通,由於此時該第八NMOS電晶體(M25)仍導通,於是該第二低電壓節點(VL2) 大約呈較接地電壓為低之該加速讀取電壓(RGND),該較接地電壓為低之該加速讀取電壓(RGND)可有效提高讀取速度。 The preferred embodiment of the present invention shown in FIG. 6 uses two-stage read control to improve the read speed while avoiding unnecessary power consumption. In the first stage of the read operation, the read control The signal (RC) is a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the second low voltage node (VL2) About the accelerated read voltage (RGND) lower than the ground voltage, the accelerated read voltage (RGND) lower than the ground voltage can effectively improve the read speed.
而於讀取操作之第二階段,雖然該讀取控制信號(RC)仍為邏輯高位準,使得該第七NMOS電晶體(M24)仍為導通,惟由於此時該第八NMOS電晶體(M25)截止,於是該第二低電壓節點(VL2)會經由導通的該第四NMOS電晶體(M21)而呈接地電壓(由於讀取操作期間該反相待機模式控制信號(/S)為邏輯高位準),藉此可有效減少無謂的功率消耗。在此值得注意的是,該讀取操作之該第二階段與該第一階段相隔之時間,係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算,並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間,其值可藉由該第三反相器(INV3)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。再者,無論於讀取操作之第一階段抑是第二階段,該第四NMOS電晶體(M21)均呈導通狀態(由於讀取操作期間該反相待機模式控制信號(/S)為邏輯高位準)。第8圖所示為第6圖之本發明較佳實施例於讀取期間之簡化電路圖。 In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, so that the seventh NMOS transistor (M24) is still turned on, because the eighth NMOS transistor ( M25) is turned off, so the second low voltage node (VL2) will be at ground voltage through the turned on fourth NMOS transistor (M21) (due to the inverting standby mode control signal (/S) during the read operation is logic high level), thereby effectively reducing unnecessary power consumption. It should be noted here that the time interval between the second phase of the read operation and the first phase is equal to the time from when the read control signal (RC) changes from a logic low level to a logic high level, and ends at the first The time until the gate voltage of the eight NMOS transistors (M25) is sufficient to turn off the eighth NMOS transistor (M25) can be determined by the falling delay time of the third inverter (INV3) and the first delay circuit (D1) to adjust the delay time provided. Furthermore, the fourth NMOS transistor (M21) is in an on state whether in the first stage or the second stage of the read operation (because the inverting standby mode control signal (/S) is logic during the read operation). high level). FIG. 8 is a simplified circuit diagram of the preferred embodiment of the present invention of FIG. 6 during reading.
接下來依2種讀取狀態來說明第8圖之本發明較佳實施例如何藉由該耦合元件(CE)、該控制電路(2)、該高電壓位準控制電路(5)以及讀取用字元線控制電路(7)以於提高讀取速度的同時,亦避免無謂的功率耗損。 Next, how the preferred embodiment of the present invention shown in FIG. 8 uses the coupling element (CE), the control circuit (2), the high-voltage level control circuit (5) and the readout according to two readout states will be described. The word line control circuit (7) is used to improve the reading speed while avoiding unnecessary power consumption.
(一)讀取邏輯1(節點A儲存邏輯1): (1) Read logic 1 (node A stores logic 1):
在讀取動作發生前,該第一NMOS電晶體(M11)為截止(OFF)且該第二NMOS電晶體(M12)為導通(ON),該節點A與該節點B分別為該電
源供應電壓(VDD)與接地電壓,且該耦合元件(CE)為截止(OFF),而該讀取用位元線(RBL)則因該預充電電路(3)而等於該電源供應電壓(VDD)。於讀取期間,由於節點B為接地電壓,且該耦合元件(CE)為截止(OFF),因此該第二讀取用電晶體(M15)截止(OFF),藉此可有效保持該讀取用位元線(RBL)為該電源供應電壓(VDD)直到讀取週期結束而順利完成讀取邏輯1之操作。在此值得注意的是,於讀取操作之該第一階段,該第二低電壓節點(VL2)於讀取邏輯1時之讀取初始瞬間電壓(VRVL2I)必須滿足方程式(8):
Before the read operation occurs, the first NMOS transistor (M11) is turned off (OFF) and the second NMOS transistor (M12) is turned on (ON), the node A and the node B are respectively the power supply voltage (V DD ) and ground voltage, and the coupling element (CE) is turned off (OFF), and the read bit line (RBL) is equal to the power supply voltage (V DD ) due to the precharge circuit (3) ). During the reading period, since the node B is at the ground voltage and the coupling element (CE) is turned off (OFF), the second read transistor (M15) is turned off (OFF), thereby effectively maintaining the reading The power supply voltage (V DD ) is supplied by the bit line (RBL) until the end of the read cycle and the operation of reading
VRVL2I=RGND×RM21/(RM21+RM24+RM25)>-VTM12 (8)以有效地防止讀取時之半選定晶胞干擾,其中,VRVL2I表示該第二低電壓節點(VL2)於讀取邏輯1時之讀取初始瞬間電壓,RGND表示該加速讀取電壓,RM21表示該第四NMOS電晶體(M21)之導通電阻,RM24表示該第七NMOS電晶體(M24)之導通電阻,RM25表示該第八NMOS電晶體(M25)之導通電阻,而VTM12表示該第二NMOS電晶體(M12)之臨界電壓;而於該讀取操作之該第二階段,該第二低電壓節點(VL2)之電壓(VRVL2)可由方程式(9)表示
V RVL2I =RGND×R M21 /(R M21 +R M24 +R M25 )>-V TM12 (8) to effectively prevent half-selected cell interference during reading, where V RVL2I represents the second low voltage node (VL2) The reading initial instantaneous voltage when reading
VRVL2=接地電壓 (9)藉此,可有效地減少無謂的功率消耗。再者,為了有效降低讀取時之半選定晶胞干擾與有效降低漏電流,必須將較接地電壓為低之該加速讀取電壓(RGND)設定為使該第二低電壓節點(VL2)之電壓位準小於該第二NMOS電晶體(M12)之臨界電壓(VTM12),同時可更嚴謹地將較接地電壓為低之該加速讀取電壓(RGND)之絕對值|RGND|設定為低於該第二NMOS電 晶體(M12)之臨界電壓(VTM12),亦即 VRVL2 = ground voltage (9) Thereby, unnecessary power consumption can be effectively reduced. Furthermore, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, the accelerated reading voltage (RGND), which is lower than the ground voltage, must be set to make the second low voltage node (VL2) The voltage level is lower than the threshold voltage (V TM12 ) of the second NMOS transistor ( M12 ), and the absolute value |RGND| of the accelerated read voltage (RGND), which is lower than the ground voltage, can be set to be low more precisely The threshold voltage (V TM12 ) of the second NMOS transistor ( M12 ) is
|RGND|<VTM12 (10)其中,|RGND|與VTM12分別表示該加速讀取電壓之絕對值與該第二NMOS電晶體(M12)之臨界電壓。 |RGND|<V TM12 (10) Wherein, |RGND| and V TM12 represent the absolute value of the accelerated read voltage and the threshold voltage of the second NMOS transistor ( M12 ), respectively.
(二)讀取邏輯0(節點A儲存邏輯0): (2) Read logic 0 (node A stores logic 0):
在讀取動作發生前,該第一NMOS電晶體(M11)為導通(ON)且該第二NMOS電晶體(M12)為截止(OFF),該節點A與該節點B分別為接地電壓與該電源供應電壓(VDD),且該耦合元件(CE)因導通(ON)而提供高耦合電容,而該讀取用位元線(RBL)則因該預充電電路(3)而等於該電源供應電壓(VDD)。於讀取期間,由於節點B為該第一高電源供應電壓(VDDH1),該耦合元件(CE)因截止(OFF)而提供低耦合電容,且該第二低電壓節點(VL2)呈較接地電壓為低之電壓,本發明將該第一高電源供應電壓(VDDH1)設定為高於該電源供應電壓(VDD)但低於該電源供應電壓(VDD)與該第二PMOS電晶體(P12)臨界電壓之絕對值|VTP12|的總和,亦即 Before the read operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF), and the node A and the node B are respectively the ground voltage and the The power supply voltage (V DD ), and the coupling element (CE) provides high coupling capacitance due to the conduction (ON), and the read bit line (RBL) is equal to the power supply due to the precharge circuit (3) Supply Voltage (V DD ). During reading, since node B is the first high power supply voltage (V DDH1 ), the coupling element (CE) is turned off (OFF) to provide low coupling capacitance, and the second low voltage node (VL2) is relatively low. The ground voltage is a low voltage, the present invention sets the first high power supply voltage (V DDH1 ) to be higher than the power supply voltage (V DD ) but lower than the power supply voltage (V DD ) and the second PMOS power The sum of the absolute value of the threshold voltage of the crystal (P12) |V TP12 |, namely
VDD<VDDH1<VDD+|VTP12| (11) V DD <V DDH1 <V DD +|V TP12 | (11)
其中,|VTP12|表示該第二PMOS電晶體(P12)臨界電壓之絕對值,因此,可藉由增加該第二讀取用電晶體(M15)之導通程度,以提高讀取邏輯0之速度,同時配合較接地電壓為低之該第二低電壓節點(VL2)以進一步提高讀取速度。
Wherein, |V TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12), therefore, the conduction level of the second read transistor (M15) can be increased to improve the read
再者,於讀取期間,藉由該讀取用字元線控制電路(7)以於該讀取用字元線(RWL)致能的第一階段,將該讀取用字元線控制信號 (RWLC)設定成較該電源供應電壓(VDD)還高之該第二高電源供應電壓(VDDH2),以進一步減少讀取路徑之電阻,並加速該讀取用位元線(RWL)上之電荷的放電從而再進一步提高讀取速度,而於該第一階段後之第二階段時,則將該讀取用字元線控制信號(RWLC)拉低回該電源供應電壓(VDD),以減緩讀取干擾。在此值得注意的是,該第二高電源供應電壓(VDDH2)設定為高於該電源供應電壓(VDD)但低於該電源供應電壓(VDD)與該第一讀取用電晶體(M14)臨界電壓之VTM14的總和時,亦即 Furthermore, during the read period, the read word line is controlled by the read word line control circuit (7) in the first stage of enabling the read word line (RWL) Signal (RWLC) is set to the second high power supply voltage (V DDH2 ) higher than the power supply voltage (V DD ) to further reduce the resistance of the read path and speed up the read bit line (RWL) ) to discharge the charge on the ) to further increase the read speed, and in the second stage after the first stage, the read word line control signal (RWLC) is pulled down back to the power supply voltage (V DD ) to mitigate read disturb. It should be noted here that the second high power supply voltage (V DDH2 ) is set higher than the power supply voltage (V DD ) but lower than the power supply voltage (V DD ) and the first read transistor (M14) the sum of the threshold voltage V TM14 , that is
VDD<VDDH2<VDD+VTM14 (12) V DD <V DDH2 <V DD +V TM14 (12)
比較方程式(6)與方程式(12)可知,該第二高電源供應電壓(VDDH2)必須滿足該電源供應電壓(VDD)與該第一讀取用電晶體(M14)臨界電壓之VTM14的總和(VDD+VTM14)以及該電源供應電壓(VDD)與該第三NMOS電晶體(M13)臨界電壓之VTM13的總和(VDD+VTM13)兩者中之較小者。 Comparing equation (6) with equation (12), it can be known that the second high power supply voltage (V DDH2 ) must satisfy V TM14 between the power supply voltage (V DD ) and the threshold voltage of the first read transistor (M14) The sum of (V DD +V TM14 ) and the smaller of the power supply voltage (V DD ) and the sum of the threshold voltages of the third NMOS transistor (M13) V TM13 (V DD +V TM13 ).
再者,為了簡化電路設計,可將該第一高電源供應電壓(VDDH1)、該第二高電源供應電壓(VDDH2)與該第三高電源供應電壓(VDDH3)設計成相同,其值為大於該電源供應電壓(VDD)但小於等於滿足該電源供應電壓(VDD)與該第一讀取用電晶體(M14)臨界電壓之VTM14的總和(VDD+VTM14)、該電源供應電壓(VDD)與該第三NMOS電晶體(M13)臨界電壓之VTM13的總和(VDD+VTM13)以及該電源供應電壓(VDD)與該第二PMOS電晶體(P12)臨界電壓之絕對值|VTP12|總和(VDD+|VTP12|)三者中之較小者(該值可由方程式(6)、方程式(11)與方程式(12)推知)。 Furthermore, in order to simplify the circuit design, the first high power supply voltage (V DDH1 ), the second high power supply voltage (V DDH2 ) and the third high power supply voltage (V DDH3 ) can be designed to be the same. The value is greater than the power supply voltage (V DD ) but less than or equal to the sum of V TM14 that satisfies the power supply voltage (V DD ) and the threshold voltage of the first read transistor (M14) (V DD +V TM14 ), The sum of the power supply voltage (V DD ) and the threshold voltage of the third NMOS transistor (M13) V TM13 (V DD +V TM13 ) and the power supply voltage (V DD ) and the second PMOS transistor ( P12 ) ) of the absolute value of the threshold voltage |V TP12 | sum (V DD + |V TP12 |), whichever is the smaller (this value can be inferred from Equation (6), Equation (11) and Equation (12)).
最後,該耦合元件(CE)設計成因應該SRAM晶胞工作於保持模式與讀取模式以及該反相儲存節點之儲存邏輯狀態而提供不同的耦合電
容,其中當該SRAM晶胞處於保持模式且該反相儲存節點(B)為邏輯1時提供最大的耦合電容,亦即當該SRAM晶胞處於保持模式且該反相儲存節點(B)為邏輯1時所具有之耦合電容大於該反相儲存節點(B)為邏輯0時之耦合電容,且大於該SRAM晶胞處於讀取模式時之耦合電容,藉此,可於讀取邏輯0初期提高該反相儲存節點(B)之電壓位準,從而有效減小該第二讀取用電晶體(M15)之等效電阻,因此可更進一步提高讀取速度,併予指明。
Finally, the coupling element (CE) is designed to provide different coupling voltages due to the operation of the SRAM cell in hold mode and read mode and the storage logic state of the inverting storage node.
Capacitance, wherein the maximum coupling capacitance is provided when the SRAM cell is in hold mode and the inverting storage node (B) is
1:SRAM晶胞 1: SRAM cell
2:控制電路 2: Control circuit
3:預充電電路 3: Precharge circuit
4:待機啟動電路 4: Standby start circuit
5:高電壓位準控制電路 5: High voltage level control circuit
6:寫入用字元線控制電路 6: Word line control circuit for writing
7:讀取用字元線控制電路 7: Word line control circuit for reading
8:寫入驅動電路 8: Write drive circuit
P11:第一PMOS電晶體 P11: The first PMOS transistor
P12:第二PMOS電晶體 P12: Second PMOS transistor
M11:第一NMOS電晶體 M11: The first NMOS transistor
M12:第二NMOS電晶體 M12: Second NMOS transistor
M13:第三NMOS電晶體 M13: The third NMOS transistor
A:儲存節點 A: Storage node
B:反相儲存節點 B: Inverted storage node
C:節點 C:node
M14:第一讀取用電晶體 M14: The first read transistor
M15:第二讀取用電晶體 M15: Second read transistor
WBL:寫入用位元線 WBL: Write bit line
WWL:寫入用字元線 WWL: word line for writing
RBL:讀取用位元線 RBL: read bit line
RWL:讀取用字元線 RWL: read word line
WWLC:寫入用字元線控制信號 WWLC: Write word line control signal
RWLC:讀取用字元線控制信號 RWLC: word line control signal for reading
S:待機模式控制信號 S: Standby mode control signal
/S:反相待機模式控制信號 /S: Inverted standby mode control signal
VL1:第一低電壓節點 VL1: first low voltage node
VL2:第二低電壓節點 VL2: Second Low Voltage Node
M21:第四NMOS電晶體 M21: Fourth NMOS transistor
M22:第五NMOS電晶體 M22: Fifth NMOS transistor
M23:第六NMOS電晶體 M23: sixth NMOS transistor
M24:第七NMOS電晶體 M24: seventh NMOS transistor
M25:第八NMOS電晶體 M25: Eighth NMOS transistor
M26:第九NMOS電晶體 M26: Ninth NMOS transistor
M27:第十NMOS電晶體 M27: Tenth NMOS transistor
P21:第三PMOS電晶體 P21: The third PMOS transistor
RC:讀取控制信號 RC: read control signal
RGND:加速讀取電壓 RGND: Speed up reading voltage
INV3:第三反相器 INV3: Third Inverter
D1:第一延遲電路 D1: first delay circuit
WC:寫入控制信號 WC: write control signal
CE:耦合元件 CE: Coupling Element
P31:第四PMOS電晶體 P31: Fourth PMOS transistor
P:預充電信號 P: Precharge signal
M41:第十一NMOS電晶體 M41: Eleventh NMOS transistor
P41:第五PMOS電晶體 P41: Fifth PMOS transistor
D2:第二延遲電路 D2: Second delay circuit
VDD:電源供應電壓 V DD : Power supply voltage
VDDH1:第一高電源供應電壓 V DDH1 : The first high power supply voltage
VDDH2:第二高電源供應電壓 V DDH2 : The second highest power supply voltage
P51:第六PMOS電晶體 P51: sixth PMOS transistor
P52:第七PMOS電晶體 P52: seventh PMOS transistor
INV4:第四反相器 INV4: Fourth inverter
VH:高電壓節點 VH: High Voltage Node
P61:第八PMOS電晶體 P61: Eighth PMOS transistor
P62:第九PMOS電晶體 P62: Ninth PMOS transistor
P63:第十PMOS電晶體 P63: Tenth PMOS transistor
M61:第十二NMOS電晶體 M61: Twelfth NMOS transistor
INV5:第五反相器 INV5: Fifth inverter
INV6:第六反相器 INV6: sixth inverter
P71:第十一PMOS電晶體 P71: Eleventh PMOS transistor
P72:第十二PMOS電晶體 P72: Twelfth PMOS transistor
P73:第十三PMOS電晶體 P73: Thirteenth PMOS transistor
M71:第十三NMOS電晶體 M71: Thirteenth NMOS transistor
INV7:第七反相器 INV7: seventh inverter
INV8:第八反相器 INV8: Eighth Inverter
P81:第十四PMOS電晶體 P81: Fourteenth PMOS transistor
M81:第十四NMOS電晶體 M81: Fourteenth NMOS transistor
M82:第十五NMOS電晶體 M82: The fifteenth NMOS transistor
M83:第十六NMOS電晶體 M83: Sixteenth NMOS transistor
INV9:第九反相器 INV9: ninth inverter
INV10:第十反相器 INV10: Tenth Inverter
D3:第三延遲電路 D3: Third delay circuit
D4:第四延遲電路 D4: Fourth delay circuit
VDDH3:第三高電源供應電壓 V DDH3 : The third highest power supply voltage
Y:行解碼器輸出信號 Y: line decoder output signal
Cap:電容器 Cap: capacitor
Din:輸入資料 Din: input data
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW110112794A TWI760176B (en) | 2021-04-08 | 2021-04-08 | Memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW110112794A TWI760176B (en) | 2021-04-08 | 2021-04-08 | Memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI760176B true TWI760176B (en) | 2022-04-01 |
TW202240791A TW202240791A (en) | 2022-10-16 |
Family
ID=82199090
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW110112794A TWI760176B (en) | 2021-04-08 | 2021-04-08 | Memory device |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI760176B (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080158938A1 (en) * | 2006-12-27 | 2008-07-03 | James David Burnett | Memory cells with lower power consumption during a write operation |
TW201919052A (en) * | 2017-11-10 | 2019-05-16 | 修平學校財團法人修平科技大學 | Seven-transistor dual port static random access memory with fast writing speed capable of effectively increasing the performance of seven-transistor SRAM and increasing reading and writing speed and reducing leakage current |
TW202004761A (en) * | 2018-05-24 | 2020-01-16 | 修平學校財團法人修平科技大學 | Seven-transistor dual port static random access memory with fast read/write speed |
TW202006727A (en) * | 2018-07-18 | 2020-02-01 | 修平學校財團法人修平科技大學 | Dual port static random access memory |
TWI716162B (en) * | 2019-10-24 | 2021-01-11 | 修平學校財團法人修平科技大學 | Dual port static random access memory |
-
2021
- 2021-04-08 TW TW110112794A patent/TWI760176B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080158938A1 (en) * | 2006-12-27 | 2008-07-03 | James David Burnett | Memory cells with lower power consumption during a write operation |
TW201919052A (en) * | 2017-11-10 | 2019-05-16 | 修平學校財團法人修平科技大學 | Seven-transistor dual port static random access memory with fast writing speed capable of effectively increasing the performance of seven-transistor SRAM and increasing reading and writing speed and reducing leakage current |
TW202004761A (en) * | 2018-05-24 | 2020-01-16 | 修平學校財團法人修平科技大學 | Seven-transistor dual port static random access memory with fast read/write speed |
TW202006727A (en) * | 2018-07-18 | 2020-02-01 | 修平學校財團法人修平科技大學 | Dual port static random access memory |
TWI716162B (en) * | 2019-10-24 | 2021-01-11 | 修平學校財團法人修平科技大學 | Dual port static random access memory |
Also Published As
Publication number | Publication date |
---|---|
TW202240791A (en) | 2022-10-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW202006727A (en) | Dual port static random access memory | |
TW202004761A (en) | Seven-transistor dual port static random access memory with fast read/write speed | |
TWI742992B (en) | Semiconductor device | |
TWI716162B (en) | Dual port static random access memory | |
TWI726823B (en) | Dual port static random access memory | |
TWI727909B (en) | Semiconductor memory device | |
TWI727901B (en) | Static random access memory | |
TWI704575B (en) | Seven-transistor static random access memory with improved access speed | |
TWI760176B (en) | Memory device | |
TWI766739B (en) | Memory device | |
TWI760153B (en) | Memory device | |
TWI733624B (en) | Semiconductor memory device | |
TWI717876B (en) | Semiconductor memory device | |
TWI713027B (en) | Dual port static random access memory with fast read/write speed | |
TWI781854B (en) | Memory device | |
TWI713026B (en) | Seven-transistor dual port static random access memory | |
TWI781836B (en) | Semiconductor memory device | |
TWI717877B (en) | Seven-transistor static random access memory with fast read/write speed | |
TWI713028B (en) | Dual port static random access memory with improved access speed | |
TWI709962B (en) | Seven-transistor dual port static random access memory with improved access speed | |
TWI681403B (en) | Seven-transistor dual port static random access memory | |
TWM639382U (en) | Dual port static random access memory | |
TW202415220A (en) | Semiconductor memory device | |
TWM627680U (en) | Semiconductor memory device | |
TWM633601U (en) | Memory device |