TWI742992B - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), a standby startup circuit (4), and a plurality of high voltage level controls A circuit (5), a plurality of word line control circuits for writing (6), a plurality of word line control circuits for reading (7), and a write drive circuit (8). Therefore, in the writing mode, the combination of the plurality of control circuits (2), the plurality of writing word line control circuits (6), and the plurality of write drive circuits (8) can prevent While writing logic 1 is difficult, it also effectively improves the writing speed. In the read mode, the plurality of control circuits (2), the plurality of high voltage level control circuits (5) and the plurality of The combination of the word line control circuit (7) for reading can improve the reading speed while avoiding unnecessary power consumption. Furthermore, the SRAM cell of the present invention is provided with a coupling element (CE) connected between the inverted storage node (B) and the word line control signal (RWLC) for reading. The coupling element (CE) corresponds to the SRAM crystal The cell works in retention mode and read mode and the storage logic state of the inverted storage node to provide different coupling capacitances, wherein when the SRAM cell is in the retention mode and the inverted storage node (B) is logic 1 Provide the largest coupling capacitance when the SRAM cell is in the hold mode and the inverted storage The coupling capacitance when the storage node (B) is logic 1 is greater than the coupling capacitance when the inverted storage node (B) is logic 0, and is greater than the coupling capacitance when the SRAM cell is in the read mode, so that Increase the voltage level of the inverted storage node (B) at the initial stage of reading logic 0, thereby effectively reducing the equivalent resistance of the reading path, and thus further increasing the reading speed.

Description

Semiconductor device

The present invention relates to a semiconductor device with 7T (seven transistor) dual port static random access memory (Static Random Access Memory, referred to as SRAM), in particular to a semiconductor device with 7T (seven transistor) dual port static random access memory (SRAM). Improve read speed and write speed, and can effectively reduce leakage current (leakage current), reduce half-selected cell interference during read, and avoid unnecessary power consumption of SRAM.

The conventional single-port static random access memory (SRAM) is shown in Figure 1a. It mainly includes a memory array. The memory array is composed of a plurality of memory blocks (MB _1). , MB _2, etc.), each memory block is further composed of a plurality of rows of memory cells and a plurality of columns of memory cells. Each row of memory cell and each row of memory cell includes a plurality of memory cells; a plurality of word lines (word lines, WL ₁ , WL _2, etc.), each word line corresponds to a plurality of rows of memory A column in the body cell; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _m, etc.), each bit line pair corresponds to the plural row memory cell One row, and each bit line pair is composed of a bit line (BL ₁ ... BL _m ) and a complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b shows the circuit diagram of the 6T single-port static random access memory (SRAM) unit cell. Among them, PMOS transistors (P1) and (P2) are called load transistors and NMOS transistors (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL And BLB are bit lines and complementary bit lines respectively. Because the single-port SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) Another driving transistor is turned on, and the read initial instant voltage (V _AR ) of node A must satisfy equation (1):

V _AR =V _DD ×(R _M1 )/(R _M1 +R _M3 )<V _TM2 (1) to prevent half-selected cell disturbance during reading, where V _AR represents node A Read the initial instantaneous voltage, R _M1 and R _M3 respectively represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply voltage and the NMOS transistor ( M2) the threshold voltage, which results in the current drive capability ratio between the drive transistor and the access transistor (that is, the cell ratio) is usually set between 2.2 and 3.5 (please refer to US76060B2 dated October 20, 1998). Patent No. 2, column 2, lines 8-10).

Figure 1b shows the HSPICE transient analysis simulation results of the 6T single-port static random access memory cell during the write operation. As shown in Figure 2, it is simulated using TSMC 90nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a schematic circuit diagram of a 5T single-port static random access memory cell with only a single bit line. Compared with the 6T single-port static random access memory cell in Figure 1b, this 5T static The random access memory cell is one less transistor and one bit line less than the 6T static random access memory cell, but the 5T single-port static random access memory cell does not change the PMOS transistors P1 and P2 And in the case of the channel width-to-length ratio of NMOS transistors M1, M2, and M3, there is a problem that writing logic 1 is quite difficult. Consider the situation where node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transferred from the bit line (BL), the logic 0 written in node A is overwritten with logic 1 Enter the initial instantaneous voltage (V _AW ) equal to equation (2):

V _AW =V _DD ×(R _M1 )/(R _M1 +R _M3 ) (2) Among them, V _AW represents the initial instantaneous voltage of node A, and R _M1 and R _M3 represent NMOS transistor (M1) and NMOS respectively The on-resistance of the transistor (M3), comparing equation (1) with equation (2) shows that the initial instant voltage (V _AW ) of writing is less than the threshold voltage (V _TM2 ) of the NMOS transistor (M2), so writing cannot be completed Operation of logic 1. Figure 3 shows the HSPICE transient analysis simulation result of the 5T static random access memory cell during the write operation. As shown in Figure 4, it is simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that the 5T static random access memory cell with a single bit line has the problem that it is quite difficult to write logic 1.

Next, discuss the single-port and dual-port architectures of static random access memory (SRAM). The 6T static random access memory (SRAM) cell in Figure 1b is the single-port static random access memory (SRAM) crystal. An example of a cell is that it uses two bit lines BL and BLB to do read and write actions, that is, read and write are achieved through the same pair of bit lines, so only read or Therefore, when you want to design a dual-port static random access memory with simultaneous read and write capabilities, you need to add two more access transistors and another pair of bit lines, which makes the memory cell The area is greatly increased. If we can simplify the structure of the memory cell so that one bit line is responsible for reading and the other bit line is responsible for writing, then the dual-port static random access memory cell The area will be reduced a lot, the traditional dual-port static random access memory The reason why this method is not used in the memory cell is because, as mentioned above, there is a problem that writing logic 1 is quite difficult.

So far, many technologies for dual-port static random access memory cells with a single read bit line have been proposed, such as the "7T static random access memory with high read/write speed" proposed in the patent literature. "(TW I655629B, granted to Shuping University of Science and Technology on April 1, 108). The designated representative diagram is shown in Figure 5. However, the patent document still has the following defects during the read operation: (1) For high voltage levels In the control circuit (5), if the first high power supply voltage (V _DDH1 ) is provided earlier than the power supply voltage (V _DD ) due to unexpected timing factors, the sixth PMOS transistor (P51) is prone to parasitic PNP power The crystal’s latch-up effect causes premature damage. (2) For the control circuit (2), if the accelerated reading voltage (RGND) is provided earlier than the ground voltage (GND) due to unexpected timing factors, then The fourth NMOS transistor (M21) is prone to premature damage due to the latch-up effect of the parasitic NPN transistor and (3) For the SRAM cell, the second read transistor (M15) has a slightly equivalent resistance during the read operation. Too big, so there is still room for improvement.

In view of this, the main purpose of the present invention is to provide a semiconductor device with dual-port static random access memory, which can be connected to the inverting storage node (B) and the inverting storage node (B) by providing a coupling element (CE) in the SRAM cell Between the word line control signals (RWLC) for reading, the coupling element (CE) provides a difference due to the SRAM cell operating in the retention mode and the read mode and the storage logic state of the inverted storage node Coupling capacitor, where the maximum coupling capacitance is provided when the SRAM cell is in the holding mode and the inverting storage node (B) is logic 1, that is, when the SRAM cell is in the holding mode and the inverting storage node (B) The coupling capacitance when it is logic 1 is greater than the coupling capacitance when the inverted storage node (B) is logic 0, and is greater than the coupling capacitance when the SRAM cell is in the read mode, so that logic 0 can be read Initially increase the voltage level of the inverted storage node (B) Therefore, the equivalent resistance of the second reading transistor (M15) can be effectively reduced, and the reading speed can be further improved.

The secondary objective of the present invention is to provide a semiconductor device with dual-port static random access memory, which can be achieved by combining the sixth PMOS transistor (P51) and the seventh PMOS in the high voltage level control circuit (5) The base (bulk; B) of the transistor (P52) is connected to the first high power supply voltage (V _DDH1 ) to prevent the sixth PMOS transistor (P51) from premature damage due to latch-up.

Another object of the present invention is to provide a semiconductor device with dual-port static random access memory, which can be used to control the fourth NMOS transistor (M21) and the seventh NMOS transistor (M24) in the control circuit (2). ) And the base of the eighth NMOS transistor (M25) are connected to the accelerated read voltage (RGND) to prevent the fourth NMOS transistor (M21) from premature damage due to latch-up.

The present invention provides a semiconductor device, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), a standby startup circuit (4), and a plurality of high voltage level controls A circuit (5), a plurality of word line control circuits for writing (6), a plurality of word line control circuits for reading (7), and a write drive circuit (8). Therefore, in the writing mode, the combination of the plurality of control circuits (2), the plurality of writing word line control circuits (6), and the plurality of write drive circuits (8) can prevent While writing logic 1 is difficult, it also effectively improves the writing speed. In the read mode, the plurality of control circuits (2), the plurality of high voltage level control circuits (5) and the plurality of The combination of the word line control circuit (7) for reading can improve the reading speed while avoiding unnecessary power consumption. Furthermore, the SRAM cell of the present invention is provided with a coupling element (CE) connected between the inverted storage node (B) and the word line control signal (RWLC) for reading. The coupling element (CE) corresponds to the SRAM crystal Cell Working in retention mode and read mode and the storage logic state of the inverted storage node to provide different coupling capacitors, wherein when the SRAM cell is in the retention mode and the inverted storage node (B) is logic 1 Provides the largest coupling capacitance, that is, when the SRAM cell is in the hold mode and the inverting storage node (B) has a logic 1, the coupling capacitance is greater than when the inverting storage node (B) is logic 0 , And greater than the coupling capacitance when the SRAM cell is in the read mode, so that the voltage level of the inverted storage node (B) can be increased at the initial stage of reading logic 0, thereby effectively reducing the equivalent of the read path Resistance, so the reading speed can be further improved.

1: SRAM cell

2: Control circuit

3: Pre-charge circuit

4: Standby start circuit

5: High voltage level control circuit

6: Word line control circuit for writing

7: Character line control circuit for reading

8: Write drive circuit

P11: The first PMOS transistor

P12: second PMOS transistor

M11: The first NMOS transistor

M12: second NMOS transistor

M13: The third NMOS transistor

A: Storage node

B: Inverted storage node

C: Node

M14: First reading transistor

M15: second reading transistor

WBL: bit line for writing

WWL: Character line for writing

RBL: bit line for reading

RWL: Character line for reading

WWLC: Word line control signal for writing

RWLC: Character line control signal for reading

S: Standby mode control signal

/S: Inverted standby mode control signal

VL1: the first low voltage node

VL2: second low voltage node

M21: Fourth NMOS transistor

M22: Fifth NMOS transistor

M23: The sixth NMOS transistor

M24: seventh NMOS transistor

M25: Eighth NMOS transistor

M26: Ninth NMOS Transistor

M27: Tenth NMOS Transistor

P21: The third PMOS transistor

RC: Read control signal

RGND: Accelerated reading voltage

INV3: third inverter

D1: The first delay circuit

/WC: Inverted write control signal

CE: Coupling element

P31: Fourth PMOS transistor

P: Precharge signal

M41: The eleventh NMOS transistor

P41: Fifth PMOS transistor

D2: The second delay circuit

V _DD : Power supply voltage

V _DDH1 : The first high power supply voltage

V _DDH2 : The second highest power supply voltage

P51: The sixth PMOS transistor

P52: seventh PMOS transistor

INV4: Fourth inverter

VH: high voltage node

P61: Eighth PMOS transistor

P62: Ninth PMOS Transistor

P63: Tenth PMOS Transistor

M61: Twelfth NMOS Transistor

INV5: Fifth inverter

INV6: sixth inverter

P71: The eleventh PMOS transistor

P72: The twelfth PMOS transistor

P73: The thirteenth PMOS transistor

M71: The thirteenth NMOS transistor

INV7: seventh inverter

INV8: Eighth inverter

P81: Fourteenth PMOS Transistor

M81: Fourteenth NMOS Transistor

M82: fifteenth NMOS transistor

M83: Sixteenth NMOS Transistor

INV9: Ninth inverter

INV10: Tenth inverter

D3: The third delay circuit

D4: The fourth delay circuit

V _DDH3 : The third highest power supply voltage

Y: Line decoder output signal

Cap: Capacitor

Din: input data

BLB: Complementary bit line

BLB ₁ …BLB _m : complementary bit line

MB ₁ …MB _k : memory block

WL ₁ …WL _n : character line

BL ₁ …BL _m : bit line

M1...M4: NMOS transistor

P1...P2: PMOS transistor

Figure 1a shows the conventional static random access memory;

Figure 1b is a schematic diagram showing the circuit of a conventional 6T static random access memory cell;

Figure 2 is a timing diagram showing the write operation of the conventional 6T static random access memory cell;

Figure 3 is a schematic diagram showing the circuit of a conventional 5T static random access memory cell;

Figure 4 is a timing diagram showing the write operation of a conventional 5T static random access memory cell;

Figure 5 shows the designated representative figure of the conventional TW I655629B;

Figure 6 is a schematic diagram showing the circuit proposed by the preferred embodiment of the present invention;

Figure 7a shows the simplified circuit diagram of Figure 6 during the logic 0 writing period;

Figure 7b shows the simplified circuit diagram of Figure 6 during the writing of logic 1;

Figure 8 shows the simplified circuit diagram of Figure 6 during reading.

According to the above-mentioned main objective, the present invention provides a semiconductor device, which mainly includes a memory array, the memory array is composed of a plurality of rows of memory cell and a plurality of rows of memory cell, each row of memory cell and Each row of memory cell includes a plurality of memory cell (1); a plurality of control circuits (2), each column of memory cell is provided with a control circuit (2); a plurality of precharge circuits (3), Each row of memory cell is equipped with a pre-charge circuit (3); a standby startup circuit (4), the standby startup circuit (4) prompts the dual-port SRAM to quickly enter the standby mode to effectively improve the standby performance of the dual-port SRAM; A plurality of high-voltage level control circuits (5), each column of memory cell is equipped with a high-voltage level control circuit (5) to reduce the resistance of the read path when reading logic 0 to increase the reading speed; A word line control circuit (6) for writing. Each column of memory cell is equipped with a word line control circuit (6) for writing, so that when logic 0 is written to logic 1 or logic 1 is written to logic 0 When the corresponding writing word line (WWL) is enabled in the first stage, the corresponding writing word line control signal (WWLC) is set to the second highest power source that is higher _{than the power supply voltage (V DD)} Supply voltage (V _DDH2 ) to effectively increase the writing speed; multiple read word line control circuits (7), each column of memory cell is equipped with a read word line control circuit (7), in order to When reading logic 0, set the corresponding read word line control signal (RWLC) to be higher than the power supply voltage (V _DD ) in the first phase of enabling the corresponding read word line (RWL) The second highest power supply voltage (V _DDH2 ) to further reduce the resistance of the read path and accelerate the discharge of the charge on the read bit line (RWL), thereby effectively increasing the read speed; and multiple writes Drive circuit (8), each row of memory cell is provided with a write drive circuit (8) to apply a voltage level lower than the ground voltage to the write bit line ( WBL), to accelerate the speed of writing logic 0, and when writing logic 1, add the third highest power supply voltage (V _{DDH3 ) level higher than the power supply voltage (V DD} ) to the writing Bit line (WBL) to accelerate the speed of writing logic 1.

For ease of explanation, the dual-port static random access memory shown in Figure 6 Only one memory cell (1), one writing word line (WWL), one writing bit line (WBL), one reading word line (RWL), one reading bit line Line (RBL), a control circuit (2), a precharge circuit (3), a standby startup circuit (4), a high voltage level control circuit (5), a word line control circuit for writing (6) ), a read word line control circuit (7) and a write drive circuit (8) as examples for illustration. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor) (P12 and a second NMOS transistor M12), a third NMOS transistor (M13), a first reading transistor (M14), a second reading transistor (M15) and a coupling Element (CE), wherein the first inverter and the second inverter are in an alternate coupling connection, that is, the output of the first inverter (ie node A) is connected to the second inverter Input, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, The output of the second inverter (node B) is used to store the inverted data of the SRAM cell.

The first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11) of the memory cell (1) is connected to a power supply voltage (V _DD ) and a first Between the low voltage node (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected to a high voltage node (VH) and a second low voltage node (VH). Between the voltage node (VL2), the source, gate, and drain of the first read transistor (M14) are connected to the drain and drain of the second read transistor (M15), respectively. The word line (RWL) and the read bit line (RBL) are used, and the source, gate, and drain of the second read transistor (M15) are respectively connected to the second low voltage node (VL2), the output of the second inverter (ie node B) and the source of the first read transistor (M14). Furthermore, the coupling element (CE) is composed of a PMOS transistor, and the gate connection of the PMOS transistor corresponds to a reading word line control signal output by the reading word line control circuit (7) (RWLC), the source and drain of the PMOS transistor are connected together and connected to the node (B).

Please refer to Figure 6 again. The control circuit (2) consists of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV3), a first delay circuit (D1), an acceleration read voltage (RGND), an inverted write control signal (/WC), a standby mode control signal ( S) and an inverted standby mode control signal (/S). The source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverted standby mode control signal (/S) and the second low voltage node (VL2); the fifth The source, gate and drain of the NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); The source of the six NMOS transistors (M23) is connected to the ground voltage, while the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) , The gate and drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); the eighth NMOS transistor (M25) The source, gate and drain of) are respectively connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first The delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25) The input of the third inverter (INV3) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the ninth NMOS transistor (M26) The source, gate and drain are respectively connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the source of the tenth NMOS transistor (M27) The pole, gate and drain are respectively connected to the ground voltage, the standby mode control signal (S) and the gate of the ninth NMOS transistor (M26); and the source of the third PMOS transistor (P21) , The gate and the drain are respectively connected to the inverted write control signal (/WC), the standby mode control signal (S) and the drain of the tenth NMOS transistor (M27). Wherein, the bases of the fourth NMOS transistor (M21), the seventh NMOS transistor (M24) and the eighth NMOS transistor (M25) are connected to the accelerated read voltage (RGND) to prevent the fourth NMOS The transistor (M21) is prematurely damaged due to latch-up. The inverted standby mode control signal (/S) is obtained from the standby mode control signal (S) through an inverter, and the inverted write control signal (/WC) is obtained from a write control signal (WC) through another inverter.

Wherein, the drain of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27), and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C ), when the standby mode control signal (S) is at a logic low level, the voltage level of the node (C) is the voltage level of the inverted write control signal (/WC), and when the standby mode control signal When (S) is the logic high level, the voltage level of the node (C) is the ground voltage, thereby effectively preventing the standby mode control signal (S) from becoming logic due to unexpected factors when writing logic 1 High level and thus lead to the problem of not being able to write.

The control circuit (2) is designed to control the voltage levels of the first low voltage node (VL1) and the second low voltage node (VL2) in response to different operating modes. In the write mode, the unit cell is selected The source voltage (that is, the first low voltage node VL1) of the drive transistor (that is, the first NMOS transistor M11) closer to the write bit line (WBL) is set to be one higher than the ground voltage A predetermined voltage (i.e., the gate-source voltage V _{GS(M23) of} the sixth NMOS transistor (M23)) and the source voltage (i.e., the second NMOS transistor M12) of another driving transistor in the unit cell ( That is, the second low voltage node VL2) is set to a ground voltage to prevent the problem of difficulty in writing logic 1s.

In the first stage of the read mode, select the source voltage of the driving transistor (ie the second NMOS transistor M12) that is closer to the read bit line (RBL) in the selected unit cell (ie, the second lowest The voltage node VL2) is set to have a voltage lower than the ground voltage. The second low voltage node (VL2), which is lower than the ground voltage, can effectively increase the reading speed. In the second stage of the reading mode, the The source voltage of the driving transistor (that is, the second NMOS transistor M12) closer to the read bit line (RBL) in the selected unit cell is set back to the ground voltage to reduce unnecessary power consumption. The read mode The time between the second stage and the first stage is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level and reaches the gate voltage of the eighth NMOS transistor (M25) The time sufficient to turn off the eighth NMOS transistor (M25) can be adjusted by the falling delay time of the third inverter (INV3) and the delay time provided by the first delay circuit (D1).

In the standby mode, the source voltage of the driving transistors in all the memory cells is set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current; while in the hold mode, the source voltage of the driving transistors in the memory cell The source voltage of the driving transistor is set to the ground voltage to maintain the original retention characteristics. The first low voltage node (VL1) and the second low voltage node VL2 are in write mode, read mode, standby mode, and hold mode The detailed working voltage level is as shown in Table 1 below Show.

The inverted write control signal (/WC) in Table 1 is the inverted signal of a write control signal (WC), and the write control signal (WC) is a write enable signal (Write Enable , WE for short When the (WWL) signal is at a logic high level, the write control signal (WC) is at a logic high level; the read control signal (RC) is a read enable signal (Read Enable, referred to as RE) and the corresponding read Take the word line (RWL) signal and gate operation result. It is worth noting here that the non-selected character line and the non-selected positioning element line are set to a floating state, and the read control signal (RC) during the non-read mode is set to the acceleration Read the level of the voltage (RGND) to prevent the leakage current of the seventh NMOS transistor (M24).

Please refer to Figure 6, the precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P). The source and gate of the fourth PMOS transistor (P31) And the drain are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit line (RBL), so that during the precharge period, the logic low level of the The precharge signal (P) is used to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V _DD ).

Please refer to Figure 6 again, the standby startup circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2) and the inverting standby circuit The mode control signal (/S) is composed. The source, gate and drain of the fifth PMOS transistor (P41) are respectively connected to the power supply voltage (V _DD ), the inverted standby mode control signal (/S) and the eleventh NMOS transistor The drain of (M41); the source, gate and drain of the eleventh NMOS transistor (M41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) And the drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) is Connect to the gate of the eleventh NMOS transistor (M41).

Please refer to Figure 6 again, the high voltage level control circuit (5) is composed of a sixth PMOS transistor (P51), a seventh PMOS transistor (P52) and a fourth inverter (INV4) , Wherein the source, gate and drain of the sixth PMOS transistor (P51) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH), The source, gate and drain of the seventh PMOS transistor (P52) are respectively connected to a first high power supply voltage (V _DDH1 ), the output of the fourth inverter (INV4) and the high voltage node (VH), and the input of the fourth inverter (INV4) is for receiving the read control signal (RC), and the output is connected to the drain of the seventh PMOS transistor (P52). It is worth noting here that the bases of the sixth PMOS transistor (P51) and the seventh PMOS transistor (P52) are connected to the first high power supply voltage (V _DDH1 ) to prevent the sixth PMOS transistor The crystal (P51) is damaged prematurely due to latch-up, and the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter It is connected between the high voltage node (VH) and the second low voltage node (VL2).

Please refer to Figure 6 again, the word line control circuit for writing (6) consists of an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), and a tenth PMOS transistor (P63) , A twelfth NMOS transistor (M61), a fifth inverter (INV5), a sixth inverter (INV6), a second high power supply voltage (V _DDH2 ), a writing character Line (WWL) and a word line control signal (WWLC) for writing. The source, gate and drain of the eighth PMOS transistor (P61) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (INV5) and the ninth PMOS The source of the transistor (P62); the source, gate and drain of the ninth PMOS transistor (P62) are respectively connected to the drain of the eighth PMOS transistor (P61) and the sixth inverter The output of (INV6) and the word line control signal (WWLC) for writing; the source, gate and drain of the tenth PMOS transistor (P63) are respectively connected to the power supply voltage (V _DD ), The output of the fifth inverter (INV5) and the word line control signal (WWLC) for writing; the source, gate and drain of the twelfth NMOS transistor (M61) are respectively connected to the ground Voltage, the output of the fifth inverter (INV5) and the word line control signal (WWLC) for writing; the input of the fifth inverter (INV5) is for receiving the word line for writing (WWL) ), and the input of the sixth inverter (INV6) is connected to the output of the fifth inverter (INV5).

The word line control circuit (6) for writing uses a two-stage operation when it is enabled to effectively solve the problem that the writing time cannot meet the specification when the operating voltage of SRAM below 10 nm drops below 0.9. In the first stage of enabling the word line (WWL) for writing, the word line control signal for writing (WWLC) is set to the second high power supply voltage ( _{V DD) higher than the power supply voltage (V DD)} V _DDH2 ) to effectively increase the writing speed, and in the second stage after the first stage, the word line control signal (WWLC) for writing is pulled down back to the power supply voltage (V _DD ), In order to slow down the write interference; wherein, the time between the second stage and the first stage of the word line control circuit (6) for writing is equal to that the output of the fifth inverter (INV5) is sufficient to turn on the Calculated from the time of the eighth PMOS transistor (P61) and until the output of the sixth inverter (INV6) is sufficient to turn off the ninth PMOS transistor (P62), its value can be determined by the sixth inverter The rise delay time of the inverter (INV6) is adjusted.

Please refer to Figure 6 again, the read word line control circuit (7) is composed of an eleventh PMOS transistor (P71), a twelfth PMOS transistor (P72), and a thirteenth PMOS transistor (P73), a thirteenth NMOS transistor (M71), a seventh inverter (INV7), an eighth inverter (INV8), the second high power supply voltage (V _DDH2 ), a read It is composed of a word line (RWL) and a read word line control signal (RWLC). The source, gate, and drain of the eleventh PMOS transistor (P71) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the seventh inverter (INV7) and the tenth The source of two PMOS transistors (P72); the source, gate and drain of the twelfth PMOS transistor (P72) are connected to the drain, the drain of the eleventh PMOS transistor (P71), respectively The output of the eighth inverter (INV8) and the read word line control signal (RWLC); the source, gate and drain of the thirteenth PMOS transistor (P73) are respectively connected to the power supply voltage (V _DD ), the output of the seventh inverter (INV7) and the word line control signal (RWLC) for reading; the source, gate and drain system of the thirteenth NMOS transistor (M71) Are respectively connected to the ground voltage, the output of the seventh inverter (INV7) and the word line control signal (RWLC) for reading; the input of the seventh inverter (INV7) is for receiving the reading Word line (RWL), and the input of the eighth inverter (INV8) is connected to the output of the seventh inverter (INV7).

The read word line control circuit (7) adopts a two-stage operation when it is enabled. In the first stage when the read word line (RWL) is enabled, the read word line control signal (RWLC) is set to the second high power supply voltage (V _DDH2 ) higher than the power supply voltage (V _DD ) to effectively increase the reading speed, and in the second stage after the first stage, then Pull down the read word line control signal (RWLC) back to the power supply voltage (V _DD ) to slow the read disturbance; wherein, the second read word line control circuit (7) The time between the phase and the first phase is equal to the time required for the output of the seventh inverter (INV7) to turn on the eleventh PMOS transistor (P71), and to the eighth inverter (INV8) The time until the output is sufficient to turn off the twelfth PMOS transistor (P72), its value can be adjusted by the rise delay time of the eighth inverter (INV8).

Please refer to Figure 6 again. The write drive circuit (8) consists of a fourteenth PMOS transistor (P81), a fourteenth NMOS transistor (M81), a fifteenth NMOS transistor (M82), A sixteenth NMOS transistor (M83), a ninth inverter (INV9), a tenth inverter (INV10), a capacitor (Cap), an input data (Din), a row of decoder output signals ( Y), a third delay circuit (D3), a fourth delay circuit (D4), and a third high power supply voltage (V _DDH3 ), wherein the source of the fourteenth PMOS transistor (P81), The gate and drain are respectively connected to the third high power supply voltage (V _DDH3 ), the output of the ninth inverter (INV9) and the drain of the fourteenth NMOS transistor (M81), the tenth The source, gate and drain of the four NMOS transistors (M81) are respectively connected to the drain of the sixteenth NMOS transistor (M83), the output of the ninth inverter (INV9) and the fourteenth The drain of the PMOS transistor (P81), the source, gate, and drain of the fifteenth NMOS transistor (M82) are connected to the ground voltage, the output of the third delay circuit (D3) and the first The drain of the fourteenth PMOS transistor (P81), the source, gate, and drain of the sixteenth NMOS transistor (M83) are connected to the ground voltage and the output of the tenth inverter (INV10), respectively With the source of the fourteenth NMOS transistor (M81), the input of the ninth inverter (INV9) is for receiving the input data (Din), and the output is connected to the fourteenth PMOS transistor (P81) ), the gate of the fourteenth NMOS transistor (M81) and the input of the third delay circuit (D3). The input of the tenth inverter (INV10) is for receiving the output signal of the row decoder (Y), and the output is connected to the input of the fourth delay circuit (D4) and the gate of the sixteenth NMOS transistor (M83). One end of the capacitor (Cap) is connected to the fourth delay circuit ( D4) output, and the other end of the capacitor (Cap) is connected to the source of the fourteenth NMOS transistor (M81) and the drain of the sixteenth NMOS transistor (M83), where the tenth The drain of the four PMOS transistors (P81), the drain of the fourteenth NMOS transistor (M81), and the drain of the fifteenth NMOS transistor (M82) are connected to the write bit line ( WBL), the writing bit line (WBL) in the first stage of writing logic 0 is designed to be lower than the voltage level of the ground voltage to accelerate the speed of writing logic 0, and when writing logic 0 When it is 1, it is designed to be higher than the third highest power supply voltage (V _{DDH3 ) of the power supply voltage (V DD} ) to accelerate the writing speed of logic 1.

Whether the write drive circuit (8) is enabled or not is determined by the logic level of the row decoder output signal (Y). When the row decoder output signal (Y) is at a logic low level, the write drive circuit ( 8) is in the disabled state, and when the row decoder output signal (Y) is at a logic high level, the write drive circuit (8) is in the enabled state. When the row decoder output signal (Y) is at a logic low level, the output of the tenth inverter (INV10) is at a logic high level. On the one hand, the sixteenth NMOS transistor (M83) is turned on, and on the other hand, the After the delay time provided by the fourth delay circuit (D4), one end of the capacitor (Cap) is charged. Because the 16th NMOS transistor (M83) is turned on, the other end of the capacitor (Cap) is the ground voltage , And one end of the capacitor (Cap) will maintain the voltage level of the power supply voltage (V _DD ) due to the charging of the capacitor (Cap).

The write drive circuit (8) adopts a two-stage operation when writing to the enable state of logic 0. In the first stage of the write drive circuit (8) being enabled, the row decoder output signal at a logic high level (Y) to make the output of the tenth inverter (INV10) a logic low level. On the one hand, the sixteenth NMOS transistor (M83) is turned off (OFF), and on the other hand, it passes through the fourth delay circuit After the delay time provided by (D4), one end of the capacitor (Cap) is quickly discharged to the ground voltage. Because the input data (Din) is at a logic low level at this time, the output of the ninth inverter (INV9) Is a logic high level, so the fourteenth NMOS transistor (M81) is turned on, and the fourteenth PMOS transistor (P81) is turned off (OFF), so the voltage of the write bit line (WBL) The level satisfies equation (3) when the write drive circuit (8) writes logic 0 in the first stage:

V _WBL1 =-V _DD ×Cap/(Cap+C _WBL ) (3)

Wherein, V _WBL1 represents the voltage level of the writing bit line (WBL) in the first stage of writing logic 0, and _{the absolute value of V WBL1} is designed to be smaller than the threshold voltage of the third NMOS transistor (M13), For example, it can be designed to be -100mV, -150mV or -200mV, V _{DD is} the voltage level of the power supply voltage (V _DD ), and Cap and C _WBL represent the capacitance value of the capacitor (Cap) and the write-in value, respectively. The parasitic capacitance value of the bit line (WBL).

When the input data (Din) at the logic low level has passed the delay time provided by the ninth inverter (INV9) and the third delay circuit (D3), the write drive circuit (8) enters the enabling In the second stage, at this time, since the fifteenth NMOS transistor (M82) is turned on, the voltage level of the write bit line (WBL) is equal to that of the write logic 0 of the write drive circuit (8). In the second stage, equation (4) is satisfied:

V _WBL2 =0 (4)

Here is an explanation of the working principle of the preferred embodiment of the present invention shown in Fig. 6 as follows:

(I) write mode

Before the write operation starts, the standby mode control signal (S) is at a logic low level, and the inverted write control signal (/WC) is at a logic high level, so that the third PMOS transistor (P21) is turned on (ON) ), and the tenth NMOS transistor (M27) is turned off (OFF), so the drain of the third PMOS transistor (P21) is at a logic high level, and the third PMOS transistor (P21) of the logic high level The drain will turn on the ninth NMOS transistor (M26) and make the first low voltage node (VL1) a ground voltage.

During the write operation period, the standby mode control signal (S) and the inverted write control signal (/WC) are at logic low levels, so that the third PMOS transistor (P21) is turned on, and the tenth NMOS transistor The crystal (M27) is turned off and the drain of the third PMOS transistor (P21) is at a logic low level (because the inverted write control signal (/WC) is at a logic low level at this time), the logic low level is The drain of the third PMOS transistor (P21) turns off the ninth NMOS transistor (M26), and makes the first low voltage node (VL1) equal to the gate source of the sixth NMOS transistor (M23) The voltage V _{GS (M26)} can effectively prevent the problem of difficulty in writing logic 1. FIG. 7a shows the simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during the logic 0 writing period, and FIG. 7b shows the simplified circuit diagram during the logic 1 writing period.

Next, according to the four write states, how to complete the write logic 0 and write logic 1 actions of the preferred embodiment of the present invention shown in FIG. 7a and FIG. 7b will be explained.

(1) Node A originally stored logic 0, but now it wants to write logic 0:

Before the writing operation occurs (the word line control signal WWLC for writing is the ground voltage), the first NMOS transistor (M11) is turned on (ON). Because the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line (WWL) changes from Low (ground voltage) to High (power supply voltage V _DD ). When the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned off (OFF) ) Turns on (ON). At this time, because the writing bit line (WBL) is designed to be lower than the ground voltage in the first stage of writing logic 0, it is written to logic 0 In the second stage, it is pulled back to the ground voltage, so the node A will be discharged to complete the logic 0 write operation until the end of the write cycle.

(2) Node A originally stored logic 0, but now it wants to write logic 1:

Before the writing operation occurs (the word line control signal WWLC for writing is the ground voltage), the first NMOS transistor (M11) is turned on (ON). It is worth noting here that because the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line control signal (WWLC) turns from Low (ground voltage) to High. The voltage of node A will rise slightly following the voltage of the word line control signal (WWLC) for writing due to the parasitic capacitive coupling effect. When the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON At this time, because the write bit line (WBL) is the voltage level of the third high power supply voltage (V _DDH3 ), and because the first NMOS transistor (M11) is still ON and the node B is still In the initial state where the voltage level is close to the voltage level of the power supply voltage (V _DD ), the first PMOS transistor (P11) is still OFF, and the node A writes the initial instantaneous voltage (V _AWI ) satisfies equation (5):

V _AWI1 =V _DDH3 ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 )>V _TM12 (5) Where, V _AWI1 represents the initial instantaneous voltage of writing logic 1 to node A, R _M13 Represents the on-resistance of the third NMOS transistor (M13), R _M11 represents the on-resistance of the first NMOS transistor (M11), R _M23 represents the on-resistance of the sixth NMOS transistor (M23), and V _DDH3 and V _TM12 respectively represents the voltage level of the third high power supply voltage and the threshold voltage of the second NMOS transistor (M12). _{Since a voltage level equal to the gate-source voltage V GS (M23)} of the sixth NMOS transistor (M23) is provided at the first low voltage node (VL1), the voltage level of node A can be easily changed The standard is set to be much higher than the voltage level of the node A of the conventional 5T static random access memory cell in Fig. 4. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), so that node B is discharged to a lower voltage level, and the lower voltage level of node B will cause the The on-resistance (R _M11 ) of the first NMOS transistor (M11) presents a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A Therefore, the higher voltage level of the node A will pass through the second inverter (consisting of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B presents a lower voltage level , The lower voltage level of the node B will pass through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, According to this cycle, the node A can be charged to the power supply voltage (V _DD ) to complete the logic 1 write operation.

Wherein, the first low voltage node (VL1) originally stores logic 0 at node A, and during the writing of logic 1, it has the gate-source voltage V _{GS (M23) of the sixth NMOS transistor (M23)} After the logic 1 is written, the ninth NMOS transistor (M26) discharges and becomes the ground voltage level.

It is worth noting here that the present invention uses a two-stage writing word line control circuit (6) to effectively solve the problem that when the operating voltage of SRAM below 10nm drops below 0.9V, the writing time may not meet the specification. The problem is that the writing word line control circuit (6) sets the writing word line control signal (WWLC) to be lower than the writing word line (WWL) in the first stage of enabling the writing word line (WWL) The power supply voltage (V _DD ) is still higher than the second highest power supply voltage (V _DDH2 ). Since the node A originally stores logic 0 and in the initial stage of writing logic 1, the third NMOS transistor (M13) works at In the saturation region, the current in the saturation region is _{proportional to the square of the gate-source voltage V GS (M13) minus} its threshold voltage V TM13, so the word line control signal (WWLC) for writing The first stage period of the second high power supply voltage (V _DDH2 ) set to be higher than the power supply voltage (V _DD ) can effectively accelerate the speed of writing logic 1; in addition, in order to slow down the writing period for For the interference phenomenon of the half-selected cell, during the second stage after the first stage, the writing word line control signal (WWLC) is pulled down back to the voltage level of the power supply voltage (V _DD ), Wherein, the time between the second stage and the first stage of the writing word line control circuit (6) is equal to that the output of the fifth inverter (INV5) is sufficient to turn on the eighth PMOS transistor ( Calculated from the time of P61) and until the output of the sixth inverter (INV6) is enough to turn off the ninth PMOS transistor (P62), its value can be determined by the rise of the sixth inverter (INV6) Delay time to adjust.

(3) Node A originally stored logic 1, but now wants to write logic 1:

Before the writing operation occurs (the word line control signal WWLC for writing is the ground voltage), the first PMOS transistor (P11) is turned on (ON). When the writing word line control signal (WWLC) turns from Low (ground voltage) to High, the node A is the voltage level of the power supply voltage (V _DD ), and the writing bit line (WBL _{) Is} the voltage level of the third highest power supply voltage (V DDH3 ), so when the second highest power supply voltage (V _DDH2 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the sum of the _{threshold voltage V TM13} of the third NMOS transistor (M13), that is

V _DD <V _DDH2 <V _DD +V _TM13 (6) will make the third NMOS transistor (M13) continue to remain in the OFF state; at this time, because the first PMOS transistor (P11) is still ON, so The voltage of the node A will be maintained at the voltage level of the power supply voltage (V _DD ) until the end of the writing period.

(4) Node A originally stored logic 1, but now wants to write logic 0:

Before the writing operation occurs (the word line control signal WWLC for writing is the ground voltage), the first PMOS transistor (P11) is turned on (ON). When the writing word line control signal (WWLC) changes from Low (ground voltage) to High, and the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13) At this time, the third NMOS transistor (M13) changes from off (OFF) to on (ON), because the write bit line (WBL) is the voltage level (V _WBL1 ) that satisfies the equation (3) , Which is less than 0V, and because the first PMOS transistor (P11) is still ON and the node B is in the initial state where the voltage level is close to the voltage level of the ground voltage, the first NMOS transistor (M11) ) Is still off, and the initial instantaneous voltage (V _AWI0 ) of the node A writes satisfies equation (7):

V _AWI0 =V _WBL1 ×R _P11 /(R _M13 +R _P11 )+V _DD ×R _M13 /(R _M13 +R _P11 ) (7)

V _AWI0 represents the initial instantaneous voltage at which node A is written to logic 0 from logic 1, R _M13 and R _P11 represent the on-resistance of the third NMOS transistor (M13) and the first PMOS transistor (P11), and V _WBL1 and V _DD respectively represent the voltage level of the writing bit line (WBL) in the first stage of writing logic 0 and the voltage level of the power supply voltage (V _DD ), since it is written by logic 1 At logic 0, the third NMOS transistor (M13) works in the saturation region, and the current in the saturation region is proportional to the square _{of its gate-source voltage V GS (M13) minus its threshold voltage. Therefore, the voltage level (V WBL1} ) of the first stage of writing logic 0 by the writing bit line (WBL) is less than 0V and by setting the writing word line control signal (WWLC) to The design of the second highest power supply voltage (V _DDH2 ), which is higher than the power supply voltage (V _DD ), can effectively accelerate the speed of writing logic 0 from logic 1 to logic 0.

It is worth noting here that when node A is written from logic 0 to logic 1 and logic 1 is written to logic 0, the third NMOS transistor (M13) works in the saturation region, and the current in the saturation region is connected to its gate-source The voltage level of the pole voltage V _{GS (M13)} after subtracting its threshold voltage is proportional to the square of the threshold voltage. Therefore, the writing word line ( In the first stage of WWL) enabling, setting the writing word line control signal (WWLC) to the second high power supply voltage (V _{DDH2 ) higher than the power supply voltage (V DD} ) can be effective Accelerate the write speed of node A from logic 0 to logic 1 and from logic 1 to logic 0; furthermore, when node A is from logic 1 to logic 0, the above equation (3) can be used to write logic 1 In the initial stage of writing logic 0, a voltage level (V _WBL1 ) lower than the ground voltage is provided to the writing bit line (WBL), wherein _{the absolute value of V WBL1} is limited to be smaller than the third NMOS transistor (M13 ) Threshold voltage, for example, can be designed to -100mV, -150mV or -200mV, which can further increase the gate-source voltage V _{GS (M13) of the third NMOS transistor (M13) operating in the saturation region )} To effectively increase the write speed of node A from logic 1 to logic 0.

(II) Read mode

Before the read operation starts, the standby mode control signal (S) is at a logic low level, and the inverted write control signal (/WC) is at a logic high level, so that the third PMOS transistor (P21) is turned on and The tenth NMOS transistor (M27) is turned off, so the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at a logic high level is turned on. NMOS transistor (M26), and make the first low voltage node (VL1) a ground voltage. On the other hand, because the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned on (ON).

It is worth noting here that during the precharge period before the start of the read operation, the precharge signal (P) is at a logic low level, so as to precharge the corresponding read bit line (RBL) to The level of the power supply voltage (V _DD ), but because the operating voltage of the process technology below 10 nanometers will drop below 0.9 volts, the reading speed will be reduced and the specification cannot be met. Therefore, the present invention proposes two The read control of the stage can improve the read speed and meet the specifications while avoiding unnecessary power consumption.

The preferred embodiment of the present invention shown in Figure 6 uses two-stage read control to While improving the reading speed, it also avoids unnecessary power consumption. In the first stage of the reading operation, the reading control signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. At this time, the eighth NMOS transistor (M25) is still turned on, so the second low voltage node (VL2) approximately presents the acceleration reading voltage (RGND) lower than the ground voltage, and the acceleration reading voltage (RGND) lower than the ground voltage The reading voltage (RGND) can effectively increase the reading speed.

In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but at this time the eighth NMOS transistor ( M25) is turned off, so the second low voltage node (VL2) will be at the ground voltage via the turned-on fourth NMOS transistor (M21) (because the inverted standby mode control signal (/S) is logic logic during the read operation) High level), which can effectively reduce unnecessary power consumption. It is worth noting here that the time between the second phase and the first phase of the read operation is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level, and reaches the first phase. The time until the gate voltage of the eight NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25) can be determined by the fall delay time of the third inverter (INV3) and the first delay circuit (D1) Adjust the delay time provided. Furthermore, whether in the first stage or the second stage of the read operation, the fourth NMOS transistor (M21) is in a conducting state (because the inverted standby mode control signal (/S) is a logic during the read operation) High level). Fig. 8 is a simplified circuit diagram of the preferred embodiment of the present invention in Fig. 6 during the read period.

Next, according to the two reading states, how the preferred embodiment of the present invention in Figure 8 uses the coupling element (CE), the control circuit (2), the high voltage level control circuit (5), and the reading The word line control circuit (7) is used to improve the reading speed while avoiding unnecessary power loss.

(1) Read logic 1 (node A stores logic 1):

Before the read operation occurs, the first NMOS transistor (M11) is turned off (OFF) and the second NMOS transistor (M12) is turned on (ON), the node A and the node B are respectively the power supply voltage (V _DD ) and the ground voltage, and the coupling element (CE) is OFF, and the read bit line (RBL) is equal to the power supply voltage (V _{DD) due to the precharge circuit (3)} ). During the reading period, since the node B is at the ground voltage and the coupling element (CE) is turned off (OFF), the second reading transistor (M15) is turned off (OFF), thereby effectively maintaining the reading The bit line (RBL) is used to supply the voltage (V _DD ) to the power supply until the end of the read cycle to successfully complete the read logic 1 operation. It is worth noting here that in the first stage of the read operation, the read initial instantaneous voltage (V _RVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy equation (8):

V _RVL2I =RGND×R _M21 /(R _M21 +R _M24 +R _M25 )>-V _TM12 (8) to effectively prevent the half-selected cell interference during reading, where V _RVL2I represents the second low voltage node (VL2) Read the initial instantaneous voltage when reading logic 1, RGND represents the accelerated reading voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), and R _M24 represents the seventh NMOS transistor ( M24) the on-resistance, R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12); and in the second stage of the read operation _{, The voltage (V RVL2} ) of the second low voltage node (VL2) can be expressed by equation (9)

V _RVL2 = ground voltage (9) This can effectively reduce unnecessary power consumption. Furthermore, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, the accelerated reading voltage (RGND), which is lower than the ground voltage, must be set to make the second low voltage node (VL2) The voltage level is smaller than the threshold voltage (V _TM12 ) of the second NMOS transistor (M12), and at the same time, the absolute value of the accelerated reading voltage (RGND), which is lower than the ground voltage, can be set to low |RGND| _{The threshold voltage (V TM12} ) of the second NMOS transistor (M12), which is

|RGND|<V _TM12 (10) where |RGND| and V _TM12 respectively represent the absolute value of the accelerating read voltage and the threshold voltage of the second NMOS transistor (M12).

(2) Read logic 0 (node A stores logic 0):

Before the reading action occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF), the node A and the node B are ground voltage and the The power supply voltage (V _DD ), and the coupling element (CE) provides a high coupling capacitance due to conduction (ON), and the read bit line (RBL) is equal to the power supply due to the precharge circuit (3) Supply voltage (V _DD ). During the reading period, since node B is the first high power supply voltage (V _DDH1 ), the coupling element (CE) is turned off (OFF) to provide a low coupling capacitor, and the second low voltage node (VL2) is relatively low. The ground voltage is a low voltage. The present invention _{sets the first high power supply voltage (V DDH1} ) to be higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the second PMOS voltage The sum of the absolute value of the critical voltage of the crystal (P12) |V _TP12 |, that is

V _DD <V _DDH1 <V _DD +|V _TP12 | (11)

Where |V _TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12). Therefore, the conduction degree of the second read transistor (M15) can be increased to improve the read logic 0 At the same time, the second low voltage node (VL2), which is lower than the ground voltage, can be used to further increase the reading speed.

Furthermore, during the reading period, the reading word line control circuit (7) is used to control the reading word line (RWL) in the first stage when the reading word line (RWL) is enabled The signal (RWLC) is set to the second highest power supply voltage (V _{DDH2 ) higher than the power supply voltage (V DD} ) to further reduce the resistance of the read path and speed up the read bit line (RWL) ) To further increase the reading speed, and in the second stage after the first stage, the word line control signal (RWLC) for reading is pulled down back to the power supply voltage (V _DD ) to slow down read interference. It is worth noting here that the second high power supply voltage (V _DDH2 ) is set to be higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the first reading transistor (M14) When the threshold voltage is _{the sum of V TM14} , that is

V _DD <V _DDH2 <V _DD +V _TM14 (12)

Comparing equation (6) with equation (12), it can be seen that the second high power supply voltage (V _DDH2 ) must meet the threshold voltage of the power supply voltage (V _DD ) and the first reading transistor (M14) V _{TM14 The smaller} of the sum (V _DD +V TM14) and the sum of the power supply voltage (V _DD ) and the threshold voltage of the third NMOS transistor (M13) V _TM13 (V _DD +V _TM13 ).

Furthermore, in order to simplify the circuit design, the first high power supply voltage (V _DDH1 ), the second high power supply voltage (V _DDH2 ) and the third high power supply voltage (V _DDH3 ) can be designed to be the same. The value is greater than the power supply voltage (V _DD ) but less than or equal to the _{sum of V TM14} (V _DD +V _TM14 ) that _{satisfies the power supply voltage (V DD} ) and the threshold voltage of the first read transistor (M14), The sum of the power supply voltage (V _DD ) and the threshold voltage of the third NMOS transistor (M13) V _{TM13 (V DD} +V _TM13 ) and the power supply voltage (V _DD ) and the second PMOS transistor (P12 ) The absolute value of the critical voltage |V _TP12 | (V _DD +|V _{TP12 |) is the smaller of the three (the value can be inferred from} equation (6), equation (11) and equation (12)).

Finally, the coupling element (CE) is designed to provide different coupling capacitances in response to the SRAM cell operating in the hold mode and the read mode and the storage logic state of the inverted storage node. When the SRAM cell is in the hold mode and the The inverting storage node (B) provides the largest coupling capacitance when it is logic 1, that is, when the SRAM cell is in the hold mode and the inverting storage node (B) is logic 1, the coupling capacitance is greater than the inverting storage Node (B) is the coupling capacitance when logic 0 is greater than the coupling capacitance when the SRAM cell is in the read mode, so that the voltage level of the inverting storage node (B) can be increased at the initial stage of reading logic 0 , Thereby effectively reducing the equivalent resistance of the second reading transistor (M15), so the reading speed can be further improved, and it is specified.

1: SRAM cell

2: Control circuit

3: Pre-charge circuit

4: Standby start circuit

5: High voltage level control circuit

6: Word line control circuit for writing

7: Character line control circuit for reading

8: Write drive circuit

P11: The first PMOS transistor

P12: second PMOS transistor

M11: The first NMOS transistor

M12: second NMOS transistor

M13: The third NMOS transistor

A: Storage node

B: Inverted storage node

C: Node

M14: First reading transistor

M15: second reading transistor

WBL: bit line for writing

WWL: Character line for writing

RBL: bit line for reading

RWL: Character line for reading

WWLC: Word line control signal for writing

RWLC: Character line control signal for reading

S: Standby mode control signal

/S: Inverted standby mode control signal

VL1: the first low voltage node

VL2: second low voltage node

M21: Fourth NMOS transistor

M22: Fifth NMOS transistor

M23: The sixth NMOS transistor

M24: seventh NMOS transistor

M25: Eighth NMOS transistor

M26: Ninth NMOS Transistor

M27: Tenth NMOS Transistor

P21: The third PMOS transistor

RC: Read control signal

RGND: Accelerated reading voltage

INV3: third inverter

D1: The first delay circuit

/WC: Inverted write control signal

CE: Coupling element

P31: Fourth PMOS transistor

P: Precharge signal

M41: The eleventh NMOS transistor

P41: Fifth PMOS transistor

D2: The second delay circuit

V _DD : Power supply voltage

V _DDH1 : The first high power supply voltage

V _DDH2 : The second highest power supply voltage

P51: The sixth PMOS transistor

P52: seventh PMOS transistor

INV4: Fourth inverter

VH: high voltage node

P61: Eighth PMOS transistor

P62: Ninth PMOS Transistor

P63: Tenth PMOS Transistor

M61: Twelfth NMOS Transistor

INV5: Fifth inverter

INV6: sixth inverter

P71: The eleventh PMOS transistor

P72: The twelfth PMOS transistor

P73: The thirteenth PMOS transistor

M71: The thirteenth NMOS transistor

INV7: seventh inverter

INV8: Eighth inverter

P81: Fourteenth PMOS Transistor

M81: Fourteenth NMOS Transistor

M82: fifteenth NMOS transistor

M83: Sixteenth NMOS Transistor

INV9: Ninth inverter

INV10: Tenth inverter

D3: The third delay circuit

D4: The fourth delay circuit

V _DDH3 : The third highest power supply voltage

Y: Line decoder output signal

Cap: Capacitor

Din: input data

Claims (9)

A semiconductor device including: A memory array, the memory array is composed of a plurality of rows of memory cell and a plurality of rows of memory cell, each row of memory cell and each row of memory cell includes a plurality of memory cell ( 1); A plurality of control circuits (2), one control circuit (2) is provided for each row of memory cell; A plurality of precharge circuits (3), one precharge circuit (3) is provided for each row of memory cell; A standby activation circuit (4), the standby activation circuit (4) prompts the 7T static random access memory to quickly enter the standby mode, so as to effectively improve the standby performance of the 7T static random access memory; A plurality of word line control circuits for writing (6), each column of memory cell is provided with a word line control circuit (6) for writing, in order to effectively improve the writing mode from logic 0 to logic 1 and from The writing speed of the logic 1 into the logic 0; and A plurality of write drive circuits (8), each row of memory cell is provided with a write drive circuit (8) to effectively increase the writing of the logic 0 to the logic 1 and the logic 1 to write in the writing mode The write speed of the logic 0; Among them, each memory cell (1) further includes: A first inverter is composed of a first PMOS transistor (P11) and a first NMOS transistor (M11). The first inverter is connected to a power supply voltage (V _DD ) and a Between the first low voltage node (VL1); A second inverter is composed of a second PMOS transistor (P12) and a second NMOS transistor (M12). The second inverter is connected to a high voltage node (VH) and a first Between two low voltage nodes (VL2); A storage node (A) is formed by the output terminal of the first inverter; An inverting storage node (B) is formed by the output terminal of the second inverter; A third NMOS transistor (M13) is connected between the storage node (A) and a writing bit line (WBL), and the gate is connected to a writing word line control signal (WWLC) ； A first reading transistor (M14), the source, gate and drain of the first reading transistor (M14) are respectively connected to the drain of a second reading transistor (M15) 1. A word line control signal (RWLC) for reading and a bit line (RBL) for reading; The second reading transistor (M15), the source, gate and drain of the second reading transistor (M15) are respectively connected to the second low voltage node (VL2) and the inverted storage Node (B) and the source of the first read transistor (M14); and A coupling element (CE), the coupling element (CE) is connected between the inverted storage node (B) and the read word line control signal (RWLC), and works in response to the memory cell (1) Different coupling capacitances are provided in a retention mode and a read mode and the storage logic state of the inverted storage node (B), wherein when the memory cell (1) is in the retention mode and the inverted The storage node (B) provides the largest coupling capacitance when it is logic 1, that is, when the memory cell (1) is in the holding mode and the inverted storage node (B) is logic 1, the coupling capacitance is greater than the The coupling capacitance when the inverted storage node (B) is logic 0, and is greater than the coupling capacitance when the memory cell (1) is in the read mode; Wherein, the first inverter and the second inverter are alternately coupled, that is, the output terminal of the first inverter (that is, the storage node A) is connected to the input of the second inverter Terminal, and the output terminal of the second inverter (that is, the inverting storage node B) is connected to the input terminal of the first inverter; Each control circuit (2) further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor (M24) , An eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), A third inverter (INV3), a first delay circuit (D1), an acceleration read voltage (RGND), an inverted write control signal (/WC), a standby mode control signal (S), and a Inverted standby mode control signal (/S); Wherein, the source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and the second low voltage node (VL2); The source, gate and drain of the fifth NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2) ； The source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); The source, gate and drain of the seventh NMOS transistor (M24) are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); The source, gate, and drain of the eighth NMOS transistor (M25) are respectively connected to the accelerated reading voltage (RGND), the output of the first delay circuit (D1), and the seventh NMOS transistor (M24). ) Of the source; The first delay circuit (D1) is connected between the output of the third inverter (INV3) and the gate of the eighth NMOS transistor (M25); The input of the third inverter (INV3) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); The source, gate and drain of the ninth NMOS transistor (M26) are respectively connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); The source, gate and drain of the tenth NMOS transistor (M27) are respectively connected to the ground voltage, the standby mode control signal (S) and the gate of the ninth NMOS transistor (M26); The source, gate and drain of the third PMOS transistor (P21) are respectively connected to the inverted write control signal (/WC), the standby mode control signal (S) and the tenth NMOS transistor ( M27) the drain pole; Wherein, the bases of the fourth NMOS transistor (M21), the seventh NMOS transistor (M24) and the eighth NMOS transistor (M25) are connected to the accelerated read voltage (RGND) to prevent the fourth NMOS Transistor (M21) was damaged prematurely due to latch-up; Wherein, the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent the seventh NMOS transistor (M24) from malfunctioning during the non-read mode Leakage current. The semiconductor device described in claim 1, wherein the coupling element (CE) is composed of a PMOS transistor, and the gate of the PMOS transistor is connected to the read word line control signal (RWLC) , The source and drain of the PMOS transistor are connected together and connected to the inverting storage node (B). The semiconductor device described in the first item of the patent application, wherein each word line control circuit (6) for writing is composed of an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), A tenth PMOS transistor (P63), a twelfth NMOS transistor (M61), a fifth inverter (INV5), a sixth inverter (INV6), a second high power supply voltage (V _DDH2 ), a word line for writing (WWL) and the word line control signal (WWLC) for writing; Wherein, the source, gate and drain of the eighth PMOS transistor (P61) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (INV5) and the first 9. The source of the PMOS transistor (P62); The source, gate, and drain of the ninth PMOS transistor (P62) are respectively connected to the drain of the eighth PMOS transistor (P61), the output of the sixth inverter (INV6), and the write Use word line control signal (WWLC); The source, gate, and drain of the tenth PMOS transistor (P63) are respectively connected to the power supply voltage (V _DD ), the output of the fifth inverter (INV5), and the word line for writing Control signal (WWLC); The source, gate, and drain of the twelfth NMOS transistor (M61) are respectively connected to the ground voltage, the output of the fifth inverter (INV5), and the word line control signal for writing (WWLC) ); The input of the fifth inverter (INV5) is for receiving the word line (WWL) for writing, and the input of the sixth inverter (INV6) is the same as the output of the fifth inverter (INV5) connect; Among them, each write drive circuit (8) further includes: a fourteenth PMOS transistor (P81), a fifteenth NMOS transistor (M81), a fifteenth NMOS transistor (M82), a tenth Six NMOS transistors (M83), a ninth inverter (INV9), a tenth inverter (INV10), a capacitor (Cap), an input data (Din), a row of decoder output signals (Y), A third delay circuit (D3), a fourth delay circuit (D4), and a third high power supply voltage (V _DDH3 ); Wherein, the source, gate and drain of the fourteenth PMOS transistor (P81) are respectively connected to the third high power supply voltage (V _DDH3 ), the output of the ninth inverter (INV9) and the The drain of the fourteenth NMOS transistor (M81); The source, gate and drain of the fourteenth NMOS transistor (M81) are respectively connected to the drain of the sixteenth NMOS transistor (M83), the output of the ninth inverter (INV9) and the The drain of the fourteenth PMOS transistor (P81); The source, gate and drain of the fifteenth NMOS transistor (M82) are respectively connected to the connection Ground voltage, the output of the third delay circuit (D3) and the drain of the fourteenth PMOS transistor (P81); The source, gate, and drain of the sixteenth NMOS transistor (M83) are connected to the ground voltage, the output of the tenth inverter (INV10), and the fourteenth NMOS transistor (M81). Source The input of the ninth inverter (INV9) is for receiving the input data (Din), and the output is connected to the gate of the fourteenth PMOS transistor (P81) and the fourteenth NMOS transistor (M81) The gate and the input of the third delay circuit (D3); The input of the tenth inverter (INV10) is for receiving the row decoder output signal (Y), and the output is connected to the input of the fourth delay circuit (D4) and the sixteenth NMOS transistor (M83) Gate One end of the capacitor (Cap) is connected to the output of the fourth delay circuit (D4), and the other end of the capacitor (Cap) is connected to the source of the fourteenth NMOS transistor (M81) and the tenth Six drain of NMOS transistor (M83); Wherein, the drain of the fourteenth PMOS transistor (P81), the drain of the fourteenth NMOS transistor (M81), and the drain of the fifteenth NMOS transistor (M82) are commonly connected to the write Use a bit line (WBL), the write bit line (WBL) in the first stage of writing the logic 0 is designed to be lower than the voltage level of the ground voltage to accelerate the writing of the logic 0 In the second stage of writing logic 0, it is pulled back to the ground voltage to slow down the interference when writing logic 0; When writing the logic 1, the writing bit line (WBL) is designed to be higher than the power supply voltage (V _DD ) of the third highest power supply voltage (V _DDH3 ) level to speed up writing Enter the speed of logic 1; Wherein, each write drive circuit (8) satisfies the following equation in the first stage of writing the logic 0: V _WBL1 =-V _DD ×Cap/(Cap+C _WBL ) Wherein, V _WBL1 represents the voltage level of the writing bit line (WBL) in the first stage of writing the logic 0, and the _{absolute value of V WBL1} is designed to be smaller than the threshold of the third NMOS transistor (M13) Voltage, V _{DD is} the voltage level of the power supply voltage (V _DD ), and Cap and C _WBL respectively represent the capacitance value of the capacitor (Cap) and the parasitic capacitance value of the write bit line (WBL). The semiconductor device described in item 3 of the scope of patent application, which further includes a plurality of high-voltage level control circuits (5), and each column of memory cell is provided with a high-voltage level control circuit (5) for reading When logic 0 is taken to increase the reading speed, each high voltage level control circuit (5) further includes: a sixth PMOS transistor (P51), a seventh PMOS transistor (P52), and a fourth inverter ( INV4); Wherein, the source, gate and drain of the sixth PMOS transistor (P51) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH); The source, gate and drain of the seventh PMOS transistor (P52) are respectively connected to a first high power supply voltage (V _DDH1 ), the output of the fourth inverter (INV4) and the high voltage node (VH); The input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the gate of the seventh PMOS transistor (P52); Wherein, the bases of the fifth PMOS transistor (P51) and the sixth PMOS transistor (P52) are connected to the first high power supply voltage (V _DDH1 ) to prevent the fifth PMOS transistor (P51) from being caused by Premature damage due to latch-up. The semiconductor device described in item 1 of the scope of patent application, which further includes a plurality of word line control circuits (7) for reading, and each row of memory cell is provided with a word line control circuit (7) for reading , In order to further reduce the resistance of the read path when reading logic 0, and accelerate the discharge of the charge on the read bit line (RWL) to further increase the read speed, each read word line control The circuit (7) further includes: an eleventh PMOS transistor (P71), a twelfth PMOS transistor (P72), a thirteenth PMOS transistor (P73), and a thirteenth NMOS transistor (M71) , A seventh inverter (INV7), an eighth inverter (INV8), the second high power supply voltage (V _DDH2 ), the read word line (RWL), and the read character Line control signal (RWLC); Wherein, the source, gate and drain of the eleventh PMOS transistor (P71) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the seventh inverter (INV7) and the The source of the twelfth PMOS transistor (P72); The source, gate and drain of the twelfth PMOS transistor (P72) are respectively connected to the drain of the eleventh PMOS transistor (P71), the output of the eighth inverter (INV8) and the Character line control signal for reading (RWLC); The source, gate and drain of the thirteenth PMOS transistor (P73) are respectively connected to the power supply voltage (V _DD ), the output of the seventh inverter (INV7) and the word line for reading Control signal (RWLC); The source, gate, and drain of the thirteenth NMOS transistor (M71) are respectively connected to the ground voltage, the output of the seventh inverter (INV7), and the word line control signal for reading (RWLC) ); The input of the seventh inverter (INV7) is for receiving the read word line (RWL), and the input of the eighth inverter (INV8) is the same as the output of the seventh inverter (INV7) connect. The semiconductor device described in claim 1, wherein the storage node (A) originally stores the logic 0, and the initial write instant voltage (V _AWI1 ) for writing the logic 1 satisfies the following equation: V _AWI1 =V _DDH3 ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 )>V _TM12 where, V _AWI1 means that the storage node (A) stores the logic 0 and writes it to the logic 1 The initial instantaneous voltage of writing, R _M11 , R _M13 and R _M23 respectively represent the on-resistance of the first NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor (M23), And V _DDH3 and V _TM12 respectively represent the voltage level of the third high power supply voltage and the threshold voltage of the second NMOS transistor (M12); And the storage node (A) originally stores the logic 1, and the initial instantaneous voltage (V _AWI0 ) for writing the logic 0 satisfies the following equation: V _AWI0 =V _WBL1 ×R _P11 /(R _M13 +R _P11 )+V _DD ×R _M13 /(R _M13 +R _P11 ) Where, V _AWI0 means that node A is written by the logic 1 to the logic 0. The instantaneous voltage, R _M13 and R _P11 respectively represent the on-resistance of the third NMOS transistor (M13) and the first PMOS transistor (P11), and V _WBL1 and V _DD respectively represent the write bit line (WBL ) The voltage level of the first stage of writing the logic 0 and the voltage level of the power supply voltage (V _DD ). For the semiconductor device described in claim 1, wherein the read mode can be subdivided into two stages. In the first stage of one of the read modes, the second low voltage node (VL2 ) Is set to a voltage lower than the ground voltage to effectively increase the reading speed, and in a second stage of the reading mode, the second low voltage node (VL2) is set back to the ground voltage to reduce Useless power consumption; in the first stage of the read mode, the read initial instantaneous voltage (V _RVL2I ) of the second low voltage node (VL2) when logic 1 is read must satisfy the following equation: V _RVL2I =RGND×R _M21 /(R _M21 +R _M24 +R _M25 )>-V _TM12 to effectively prevent the half-selected cell interference during reading, where V _RVL2I represents the second low voltage node (VL2) The initial instantaneous voltage when reading logic 1, RGND represents the accelerated reading voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), and R _M24 represents the seventh NMOS transistor (M24) _{R M25} represents the on resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12). The semiconductor device described in claim 4, wherein the first high power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) And the sum of the absolute value of the threshold voltage of the second PMOS transistor (P12) |V _TP12 |, that is V _DD <V _DDH1 <V _DD +|V _TP12 |. The semiconductor device described in claim 4, wherein the first high power supply voltage (V _DDH1 ), the second high power supply voltage (V _DDH2 ), and the third high power supply voltage (V _DDH3 ) Set to be the same, and its value is greater than the power supply voltage (V _DD ) but less than or equal to the sum of the power supply voltage (V _DD ) and the threshold voltage (V _TM14 ) of _{the first read transistor (M14) (V DD)} +V _TM14 ), the sum (V _DD +V _TM13 ) of the power supply voltage (V _DD ) and the _{threshold voltage (V TM13} ) of the third NMOS transistor (M13), and the power supply voltage (V _DD ) and the third NMOS transistor (M13) The sum (V _DD +|V _{TP12 |) of the absolute value (|V TP12} |) of the threshold voltage of the two PMOS transistors (P12) is the smaller of the three.

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