TWI760153B - Memory device - Google Patents

Abstract

The present invention provides a memory device, which mainly comprises a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start-up circuit (4), a plurality of high voltage levels A control circuit (5), a plurality of write word line control circuits (6), a plurality of read word line control circuits (7), and a write drive circuit (8). Therefore, in the write mode, the plurality of control circuits (2), the plurality of word line control circuits (6) for writing and the plurality of write drive circuits (8) can be used to prevent the While it is difficult to write logic 1, the writing speed is also effectively improved. In the read mode, the plurality of control circuits (2), the plurality of high-voltage level control circuits (5) and the plurality of The combination of the word line control circuit (7) for reading can improve the reading speed and avoid unnecessary power consumption. Furthermore, a coupling element (CE) is set in the SRAM cell of the present invention to be connected between the inverted storage node (B) and the read word line control signal (RWLC), and the coupling element (CE) corresponds to the SRAM cell. The cell works in retention mode and read mode and the storage logic state of the inverting storage node provides different coupling capacitances, wherein when the SRAM cell is in retention mode and the inverting storage node (B) is logic 1 provides the largest coupling capacitance when the SRAM cell is in hold mode and the inverting storage When the storage node (B) is logic 1, the coupling capacitance is greater than the coupling capacitance when the inverting storage node (B) is logic 0, and is larger than the coupling capacitance when the SRAM cell is in the read mode. In the initial stage of reading logic 0, the voltage level of the inverting storage node (B) is increased, thereby effectively reducing the equivalent resistance of the reading path, thus further improving the reading speed.

Description

memory device

The present invention relates to a memory device with a 7T (seven transistor) dual port static random access memory (Static Random Access Memory, referred to as SRAM), in particular to a memory device that effectively improves the standby performance of the 7T SRAM and can It can effectively improve the reading speed and writing speed, and can effectively reduce the leakage current (leakage current), reduce the interference of semi-selected cells during reading, and avoid unnecessary power consumption of SRAM.

As shown in Figure 1a, a conventional SRAM (Static Random Access Memory) mainly includes a memory array, which is composed of a plurality of memory blocks (MB ₁₎ . , MB ₂ , etc.), each memory block is further composed of a plurality of rows of memory cells and a plurality of columns of memory cells, Each column of memory cells and each row of memory cells respectively include a plurality of memory cells; a plurality of word lines (word lines, WL ₁ , WL ₂ , etc.), each word line corresponds to a plurality of column memory A row in the body cell; and a plurality of bit line pairs (BL ₁ , BLB ₁ . . . BL _m , BLB _m , etc.), each bit line pair corresponds to a plurality of rows of memory cells One row, and each bit line pair consists of one bit line (BL ₁ . . . BL _m ) and a complementary bit line (BLB ₁ . . . BLB _m ).

Figure 1b shows the circuit diagram of a 6T SRAM cell, in which the PMOS transistors (P1) and (P2) are called load transistors, and the NMOS transistors are called load transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is the word line, and BL and BLB are the bit line and the complementary bit line respectively, because the port SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) The other driving transistor is turned on, and the read initial instantaneous voltage (V _AR ) of node A must satisfy equation (1):

_VAR =V _DD ×(R _M1 )/(R _M1 +R _M3 )<V _TM2 (1) to prevent half-selected cell disturbance during reading, where _VAR represents node A To read the initial instantaneous voltage, R _M1 and R _M3 respectively represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply voltage and the NMOS transistor ( The threshold voltage of M2), which results in the current drive capability ratio (ie cell ratio) between the drive transistor and the access transistor is usually set between 2.2 and 3.5 (please refer to US76060B2 dated October 20, 1998). No. patent specification, column 2, lines 8-10).

Figure 1b shows the HSPICE transient analysis simulation results of a 6T port SRAM cell during a write operation, as shown in Figure 2, which is simulated using TSMC 90nm CMOS process parameters.

One way to reduce the transistor count of a 6T static random access memory (SRAM) cell is disclosed in FIG. 3 . Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line. Compared with the 6T SRAM cell in Figure 1b, this 5T SRAM cell The random access memory unit cell has one less transistor and one less bit line than the 6T SRAM unit cell, but the 5T port SRAM unit cell does not change the PMOS transistors P1 and P2. And in the case of the channel width to length ratio of the NMOS transistors M1, M2 and M3, there is a problem that it is quite difficult to write a logic 1. Consider the case where the node A on the left side of the memory cell originally stores a logic 0. Since the charge of the node A is only transmitted from the bit line (BL) alone, the logic 0 previously written in the node A is overwritten with a logic 1 write. Enter the initial instantaneous voltage (V _AW ) equal to equation (2):

V _AW =V _DD ×(R _M1 )/(R _M1 +R _M3 ) (2) Among them, V _AW represents the initial instantaneous voltage of node A writing, and R _M1 and R _M3 represent the NMOS transistor (M1) and the NMOS transistor respectively Comparing equation (1) and equation (2), the on-resistance of transistor (M3) shows that the initial instantaneous voltage (V _AW ) of writing is less than the threshold voltage (V _TM2 ) of the NMOS transistor (M2), so the writing cannot be completed. Operation of logic 1. Figure 3 shows the HSPICE transient analysis simulation results of a 5T SRAM cell during write operation, as shown in Figure 4, which is simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that it is very difficult to write logic 1 in the 5T SRAM cell with a single bit line.

Next, we will discuss the port and dual-port architecture of static random access memory (SRAM). The 6T SRAM cell in Figure 1b is the port SRAM cell. An example of a cell uses two bit lines BL and BLB for read and write operations, that is, read and write are achieved through the same pair of bit lines, so only read or write operations can be performed at the same time. Therefore, when designing a dual-port SRAM with simultaneous reading and writing capability, it is necessary to add two more access transistors and another pair of bit lines, which makes the memory cell’s The area is greatly increased. If we can simplify the structure of the memory cell so that one bit line is responsible for the read action and the other bit line is responsible for the write action, the dual-port static random access memory cell The area will be greatly reduced, the traditional dual-port static random access memory The reason why the memory cell does not use this method is that it is very difficult to write a logic 1 as mentioned above.

So far, many technologies of dual-port SRAM cell with a single read bit line have been proposed, such as the "7T SRAM with high access speed" (TW) proposed in the patent literature. I678705B, awarded to Xiuping University of Science and Technology on December 1, 108), its designated representative diagram is shown in Figure 5, but the patent document still has the following defects during the reading operation: (1) For the high-voltage level control circuit ( 5), if the first high power supply voltage (V _DDH1 ) is provided earlier than the power supply voltage (V _DD ) due to an unexpected timing factor, the sixth PMOS transistor (P51 ) is prone to the latching of the parasitic PNP transistor. (2) For the control circuit (2), if the accelerated read voltage (RGND) is provided earlier than the ground voltage (GND) due to unexpected timing factors, the fourth NMOS The transistor (M21) is easily damaged early due to the latch-up effect of the parasitic NPN transistor and (3) for the SRAM cell, the equivalent resistance of the second read transistor (M15) during the read operation is slightly too large, So there is still room for improvement.

In view of this, the main purpose of the present invention is to provide a memory device with dual-port SRAM, which can be connected to the inverting storage node (B) by arranging a coupling element (CE) in the SRAM cell Between the read word line control signal (RWLC) and the read word line control signal (RWLC), the coupling element (CE) provides a difference due to the SRAM cell operating in the retention mode and the read mode and the storage logic state of the inverting storage node. , which provides the largest coupling capacitance when the SRAM cell is in hold mode and the inverting storage node (B) is logic 1, that is, when the SRAM cell is in hold mode and the inverting storage node (B) ) is logic 1, and the coupling capacitance is greater than the coupling capacitance when the inverting storage node (B) is logic 0, and is larger than the coupling capacitance when the SRAM cell is in the read mode. 0 Initially raise the voltage level of the inverting storage node (B) Therefore, the equivalent resistance of the second read transistor (M15) can be effectively reduced, so that the read speed can be further improved.

The secondary objective of the present invention is to provide a memory device with dual-port SRAM, which can control the sixth PMOS transistor (P51) and the seventh PMOS transistor (P51) in the high-voltage level control circuit (5). The base (bulk; B) of the PMOS transistor (P52) is connected to the first high power supply voltage (V _DDH1 ) to prevent the sixth PMOS transistor (P51) from being damaged early due to latch-up.

Another object of the present invention is to provide a memory device with dual-port SRAM, which can be achieved by connecting the fourth NMOS transistor (M21) and the seventh NMOS transistor (M21) in the control circuit (2). The bases of M24) and the eighth NMOS transistor (M25) are connected to the acceleration read voltage (RGND) to prevent the fourth NMOS transistor (M21) from being damaged early due to latch-up.

The present invention provides a memory device, which mainly comprises a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start-up circuit (4), a plurality of high voltage levels A control circuit (5), a plurality of write word line control circuits (6), a plurality of read word line control circuits (7), and a write drive circuit (8). Therefore, in the write mode, the plurality of control circuits (2), the plurality of word line control circuits (6) for writing and the plurality of write drive circuits (8) can be used to prevent the While it is difficult to write logic 1, the writing speed is also effectively improved. In the read mode, the plurality of control circuits (2), the plurality of high-voltage level control circuits (5) and the plurality of The combination of the word line control circuit (7) for reading can improve the reading speed and avoid unnecessary power consumption. Furthermore, a coupling element (CE) is set in the SRAM cell of the present invention to be connected between the inverted storage node (B) and the read word line control signal (RWLC), and the coupling element (CE) corresponds to the SRAM cell. cell Operates in retention mode and read mode and stores the logic state of the inverting storage node to provide different coupling capacitances, wherein when the SRAM cell is in retention mode and the inverting storage node (B) is a logic 1 Provides the largest coupling capacitance, that is, when the SRAM cell is in hold mode and the inverting storage node (B) is logic 1, the coupling capacitance is greater than the coupling capacitance when the inverting storage node (B) is logic 0 , and is larger than the coupling capacitance when the SRAM cell is in the read mode, thereby increasing the voltage level of the inverting storage node (B) at the initial stage of reading logic 0, thereby effectively reducing the equivalent of the read path resistance, so the read speed can be further improved.

1: SRAM cell

2: Control circuit

3: Precharge circuit

4: Standby start circuit

5: High voltage level control circuit

6: Word line control circuit for writing

7: Word line control circuit for reading

8: Write drive circuit

P11: The first PMOS transistor

P12: Second PMOS transistor

M11: The first NMOS transistor

M12: Second NMOS transistor

M13: The third NMOS transistor

A: Storage node

B: Inverted storage node

C:node

M14: The first read transistor

M15: Second read transistor

WBL: Write bit line

WWL: word line for writing

RBL: read bit line

RWL: read word line

WWLC: Write word line control signal

RWLC: word line control signal for reading

S: Standby mode control signal

/S: Inverted standby mode control signal

VL1: first low voltage node

VL2: Second Low Voltage Node

M21: Fourth NMOS transistor

M22: Fifth NMOS transistor

M23: sixth NMOS transistor

M24: seventh NMOS transistor

M25: Eighth NMOS transistor

M26: Ninth NMOS transistor

M27: Tenth NMOS transistor

P21: The third PMOS transistor

RC: read control signal

RGND: Speed up reading voltage

INV3: Third Inverter

D1: first delay circuit

WC: write control signal

/WC: Inverted write control signal

P31: Fourth PMOS transistor

P: Precharge signal

M41: Eleventh NMOS transistor

P41: Fifth PMOS transistor

D2: Second delay circuit

V _DD : Power supply voltage

V _DDH1 : The first high power supply voltage

V _DDH2 : The second highest power supply voltage

P51: sixth PMOS transistor

P52: seventh PMOS transistor

INV4: Fourth inverter

VH: High Voltage Node

P61: Eighth PMOS transistor

P62: Ninth PMOS transistor

P63: Tenth PMOS transistor

M61: Twelfth NMOS transistor

INV5: Fifth inverter

INV6: sixth inverter

P71: Eleventh PMOS transistor

P72: Twelfth PMOS transistor

P73: Thirteenth PMOS transistor

M71: Thirteenth NMOS transistor

INV7: seventh inverter

INV8: Eighth Inverter

P81: Fourteenth PMOS transistor

M81: Fourteenth NMOS transistor

M82: The fifteenth NMOS transistor

M83: Sixteenth NMOS transistor

INV9: ninth inverter

INV10: Tenth Inverter

D3: Third delay circuit

D4: Fourth delay circuit

V _DDH3 : The third highest power supply voltage

Y: line decoder output signal

Cap: capacitor

Din: input data

BLB: Complementary Bit Line

BLB ₁ …BLB _m : Complementary bit line

MB ₁ …MB _k : memory block

WL ₁ …WL _n : word line

BL ₁ …BL _m : bit line

M1…M4: NMOS transistors

P1…P2: PMOS transistors

CE: Coupling Element

Figure 1a shows a conventional SRAM;

Fig. 1b is a circuit schematic diagram showing a conventional 6T SRAM cell;

FIG. 2 is a timing diagram of a write operation of a conventional 6T SRAM cell;

FIG. 3 is a schematic circuit diagram of a conventional 5T SRAM cell;

FIG. 4 is a timing diagram of a write operation of a conventional 5T SRAM cell;

Figure 5 shows the designated representative diagram of the conventional TW I678705B;

FIG. 6 is a schematic diagram of a circuit proposed by a preferred embodiment of the present invention;

Fig. 7a shows the simplified circuit diagram of Fig. 6 during the writing of logic 0;

Fig. 7b shows the simplified circuit diagram of Fig. 6 during the writing of logic 1;

Figure 8 shows a simplified circuit diagram of Figure 6 during reading.

According to the above-mentioned main purpose, the present invention provides a memory device, which mainly includes a memory array, the memory array is composed of a plurality of rows of memory cells and a plurality of rows of memory cells, each row of memory cells Each row of memory unit cells includes a plurality of memory unit cells (1); a plurality of control circuits (2), and each row of memory unit cells is provided with a control circuit (2); a plurality of precharge circuits (3) , each row of memory cells is provided with a precharge circuit (3); a standby start-up circuit (4), the standby start-up circuit (4) prompts the dual-port SRAM to quickly enter the standby mode, so as to effectively improve the standby performance of the dual-port SRAM a plurality of high-voltage level control circuits (5), each row of memory cells is provided with a high-voltage level control circuit (5), so as to reduce the resistance of the reading path when reading logic 0, thereby increasing the reading speed; A plurality of write word line control circuits (6), each row of memory cells is provided with a write word line control circuit (6), to write logic 1 from logic 0 or write logic from logic 1 When it is 0, in the first stage of enabling the corresponding write word line (WWL), set the corresponding write word line control signal (WWLC) to the second highest level higher than the power supply voltage (V _DD ) The power supply voltage (V _DDH2 ) can effectively improve the writing speed; a plurality of reading word line control circuits (7), each row of memory cells is provided with a reading word line control circuit (7) to When the logic 0 is read, in the first stage of enabling the corresponding read word line (RWL), the corresponding read word line control signal (RWLC) is set to be lower than the power supply voltage (V _DD ) A high second-highest power supply voltage (V _DDH2 ) to further reduce the resistance of the read path and accelerate the discharge of the charge on the read bit line (RWL), thereby effectively increasing the read speed; and a plurality of write A write drive circuit (8) is provided for each row of memory cells to apply a voltage level lower than the ground voltage to the write bit line in the first stage of writing logic 0 (WBL), to speed up the writing of logic 0, and when writing logic 1, a level of the third highest power supply voltage (V _DDH3 ) higher than the power supply voltage (V _DD ) is applied to the writing Use bit lines (WBL) to speed up writing logic 1s.

For the sake of illustration, the dual-port SRAM shown in Figure 6 Only one memory cell (1), one write word line (WWL), one write bit line (WBL), one read word line (RWL), and one read bit line line (RBL), a control circuit (2), a precharge circuit (3), a standby start circuit (4), a high voltage level control circuit (5), a word line control circuit for writing (6) ), a read word line control circuit (7) and a write drive circuit (8) are described as embodiments. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11 ), a second inverter (composed of a second PMOS transistor M11 ) The crystal P12 is composed of a second NMOS transistor M12), a third NMOS transistor (M13), a first read transistor (M14), a second read transistor (M15), and a coupling Element (CE), wherein the first inverter and the second inverter are connected in a cross-coupling manner, that is, the output of the first inverter (ie, node A) is connected to the second inverter. input, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, The output of the second inverter (node B) is used to store the inverted data of the SRAM cell.

The first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11 ) of the memory cell (1) is connected to a power supply voltage (V _DD ) and a first Between the low voltage node (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected to a high voltage node (VH) and a second low voltage Between the voltage nodes (VL2), the source, gate and drain of the first read transistor (M14) are respectively connected to the drain of the second read transistor (M15). A word line (RWL) and the read bit line (RBL) are used, and the source, gate and drain of the second read transistor (M15) are respectively connected to the second low voltage node (VL2), the output of the second inverter (ie node B) and the source of the first read transistor (M14). Furthermore, the coupling element (CE) is composed of a PMOS transistor, and the gate of the PMOS transistor is connected to a read word line control signal outputted by the corresponding read word line control circuit (7). (RWLC), the source and drain of the PMOS transistor are connected together and to the node (B).

Please refer to FIG. 6 again, the control circuit (2) consists of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV3), a first delay circuit (D1), an acceleration read voltage (RGND), a write control signal (WC), an inversion write control signal (/ WC), a standby mode control signal (S) and an inverted standby mode control signal (/S). The source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverting standby mode control signal (/S) and the second low voltage node (VL2); the fifth The source, gate and drain of the NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); the first low voltage node (VL1) The source of the six NMOS transistors (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) , the gate and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the second low voltage node (VL2); the eighth NMOS transistor (M25) ) source, gate and drain are respectively connected to the acceleration read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first A delay circuit (D1) is connected between the output of the third inverter (INV3) and the eighth NMOS Between the gates of the transistor (M25); the input of the third inverter (INV3) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1) ; The source, gate and drain of the ninth NMOS transistor (M26) are respectively connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the The source, gate and drain of the tenth NMOS transistor (M27) are respectively connected to the write control signal (WC), the standby mode control signal (S) and the gate of the ninth NMOS transistor (M26) and the source, gate and drain of the third PMOS transistor (P21) are respectively connected to the inverting write control signal (/WC), the standby mode control signal (S) and the tenth NMOS The drain of the transistor (M27). Wherein, the bases of the fourth NMOS transistor (M21), the seventh NMOS transistor (M24) and the eighth NMOS transistor (M25) are connected to the accelerated reading voltage (RGND) to prevent the fourth NMOS The transistor (M21) is damaged early due to latch-up, the inverting standby mode control signal (/S) is obtained from the standby mode control signal (S) through an inverter, and the inverting write control signal (/WC) is obtained from the write control signal (WC) via another inverter.

Wherein, the drain of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C ), when the standby mode control signal (S) is at a logic low level, the voltage level of the node (C) is the voltage level of the inverting write control signal (/WC), and when the standby mode control signal When (S) is a logic high level, the voltage level of the node (C) is the logic level of the write control signal (WC).

The control circuit (2) is designed to control the voltage levels of the first low-voltage node (VL1) and the second low-voltage node (VL2) according to different operation modes, and selects the cell in the write mode. The source voltage (ie, the first low voltage node VL1 ) of the drive transistor (ie, the first NMOS transistor M11 ) that is closer to the write bit line (WBL) is set to one higher than the ground voltage The predetermined voltage (ie the gate-source voltage V _{GS (M23) of the sixth NMOS transistor (M23)} ) and the source voltage ( That is, the second low voltage node VL2) is set to the ground voltage in order to prevent the problem of difficulty in writing logic 1s.

In the first stage of the read mode, the source voltage of the drive transistor (ie, the second NMOS transistor M12 ) that is closer to the read bit line (RBL) in the unit cell (ie, the second lowest voltage) is selected. The voltage node VL2) is set to a lower voltage than the ground voltage. The second low voltage node (VL2), which is lower than the ground voltage, can effectively improve the read speed. In the second stage of the read mode, the The source voltage of the drive transistor (ie, the second NMOS transistor M12 ) in the selected cell that is closer to the read bit line (RBL) is set back to ground to reduce wasteful power consumption, wherein the read mode The time interval between the second stage and the first stage is equal to the time from the read control signal (RC) from the logic low level to the logic high level, and to the gate voltage of the eighth NMOS transistor (M25) The time sufficient to turn off the eighth NMOS transistor (M25) can be adjusted by the falling delay time of the third inverter (INV3) and the delay time provided by the first delay circuit (D1).

In the standby mode, the source voltages of the drive transistors in all the memory cells are set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current; in the hold mode, the source voltages of the memory cells are set to be higher than the ground voltage. The source voltage of the driving transistor is set to the ground voltage in order to maintain the original hold characteristics. The first low voltage node (VL1) and the second low voltage node VL2 are in write mode, read mode, standby mode and hold mode The detailed operating voltage levels are shown in Table 1 below.

The inverted write control signal (/WC) in Table 1 is the inverted signal of a write control signal (WC), and the write control signal (WC) is a write enable signal (Write Enable) , WE for short) and the AND gate operation result of the corresponding write word line (WWL) signal, at this time only the write enable signal (WE) and the corresponding write word line When the (WWL) signals are all logic high levels, the write control signal (WC) is a logic high level; the read control signal (RC) is a read enable signal (Read Enable, RE for short) and the corresponding read Takes the result of the sum gate operation of the word line (RWL) signal. It is worth noting here that the unselected word lines and unselected bit lines are set to the floating state, and the read control signal (RC) during the non-read mode is set to the acceleration Read the level of the voltage (RGND) to prevent the leakage current of the seventh NMOS transistor (M24).

Please refer to FIG. 6, the precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P). The source and gate of the fourth PMOS transistor (P31) and the drain are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit line (RBL), so that during precharge, the logic low level of the The precharge signal (P) is used to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V _DD ).

Please refer to FIG. 6 again, the standby startup circuit (4) consists of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2) and the inverting standby Mode control signal (/S). The source, gate and drain of the fifth PMOS transistor (P41) are respectively connected to the power supply voltage (V _DD ), the inverting standby mode control signal (/S) and the eleventh NMOS transistor The drain of (M41); the source, gate and drain of the eleventh NMOS transistor (M41) are respectively connected to the first low voltage node (VL1) and the output of the second delay circuit (D2) and the drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverting standby mode control signal (/S), and the output of the second delay circuit (D2) is Connected to the gate of the eleventh NMOS transistor (M41).

Please refer to FIG. 6 again, the high voltage level control circuit (5) is composed of a sixth PMOS transistor (P51), a seventh PMOS transistor (P52) and a fourth inverter (INV4). , wherein the source, gate and drain of the sixth PMOS transistor (P51) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH), The source, gate and drain of the seventh PMOS transistor (P52) are respectively connected to a first high power supply voltage (V _DDH1 ), the output of the fourth inverter (INV4) and the high voltage node (VH), and the input of the fourth inverter (INV4) is used to receive the read control signal (RC), and the output is connected to the drain of the seventh PMOS transistor (P52). It is worth noting here that the bases of the sixth PMOS transistor (P51) and the seventh PMOS transistor (P52) are connected to the first high power supply voltage (V _DDH1 ) to prevent the sixth PMOS transistor The crystal (P51) is damaged early due to latch-up, and the first inverter is connected between the power supply voltage (V _DD ) and the first low-voltage node ( VL1 ), and the second inverter is Then it is connected between the high voltage node (VH) and the second low voltage node (VL2).

Please refer to FIG. 6 again, the writing word line control circuit (6) consists of an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), and a tenth PMOS transistor (P63) , a twelfth NMOS transistor (M61), a fifth inverter (INV5), a sixth inverter (INV6), a second high power supply voltage (V _DDH2 ), a writing character line (WWL) and a write word line control signal (WWLC). The source, gate and drain of the eighth PMOS transistor (P61) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (INV5) and the ninth PMOS The source of the transistor (P62); the source, gate and drain of the ninth PMOS transistor (P62) are respectively connected to the drain of the eighth PMOS transistor (P61) and the sixth inverter The output of (INV6) and the writing word line control signal (WWLC); the source, gate and drain of the tenth PMOS transistor (P63) are respectively connected to the power supply voltage (V _DD ), The output of the fifth inverter (INV5) and the writing word line control signal (WWLC); the source, gate and drain of the twelfth NMOS transistor (M61) are respectively connected to the ground voltage, the output of the fifth inverter (INV5) and the write word line control signal (WWLC); the input of the fifth inverter (INV5) is for receiving the write word line (WWL) ), and the input of the sixth inverter (INV6) is connected to the output of the fifth inverter (INV5).

When the writing word line control circuit (6) is enabled, it adopts two-stage operation to effectively solve the problem that the writing time cannot meet the specification when the operating voltage of the SRAM below 10 nm falls below 0.9. In the first stage of enabling the input word line (WWL), the write word line control signal (WWLC) is set to the second highest power supply voltage (V _DD ) higher than the power supply voltage (V DD ). V _DDH2 ) to effectively improve the writing speed, and in the second stage after the first stage, the writing word line control signal (WWLC) is pulled back to the power supply voltage (V _DD ), In order to slow down the write disturbance; wherein, the time interval between the second stage and the first stage of the writing word line control circuit (6) is equal to the output of the fifth inverter (INV5) enough to turn on the From the time of the eighth PMOS transistor (P61) to the time until the output of the sixth inverter (INV6) is sufficient to turn off the ninth PMOS transistor (P62), its value can be determined by the sixth inverter (INV6) Adjust the rise delay time of the device (INV6).

Please refer to FIG. 6 again, the read word line control circuit (7) consists of an eleventh PMOS transistor (P71), a twelfth PMOS transistor (P72), and a thirteenth PMOS transistor (P73), a thirteenth NMOS transistor (M71), a seventh inverter (INV7), an eighth inverter (INV8), the second high power supply voltage (V _DDH2 ), a read It consists of a word line (RWL) and a read word line control signal (RWLC). The source, gate and drain of the eleventh PMOS transistor (P71) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the seventh inverter (INV7) and the tenth Sources of two PMOS transistors (P72); the source, gate and drain of the twelfth PMOS transistor (P72) are respectively connected to the drain of the eleventh PMOS transistor (P71), the The output of the eighth inverter (INV8) and the read word line control signal (RWLC); the source, gate and drain of the thirteenth PMOS transistor (P73) are respectively connected to the power supply voltage (V _DD ), the output of the seventh inverter (INV7) and the read word line control signal (RWLC); the source, gate and drain of the thirteenth NMOS transistor (M71) are connected are respectively connected to the ground voltage, the output of the seventh inverter (INV7) and the read word line control signal (RWLC); the input of the seventh inverter (INV7) is used for receiving the read word line (RWL), and the input of the eighth inverter (INV8) is connected to the output of the seventh inverter (INV7).

The read word line control circuit (7) adopts a two-stage operation when it is enabled. In the first stage of the read word line (RWL) enabling, the read word line control signal (RWLC) is set to the second high power supply voltage (V _DDH2 ) higher than the power supply voltage (V _DD ) to effectively improve the reading speed, and in the second stage after the first stage, the Pull down the read word line control signal (RWLC) back to the power supply voltage (V _DD ) to slow down read disturbance; wherein, the second read word line control circuit (7) The time interval between the phase and the first phase is equal to the time when the output of the seventh inverter (INV7) is sufficient to turn on the eleventh PMOS transistor (P71), and ends at the eighth inverter (INV8) The time until the output is sufficient to turn off the twelfth PMOS transistor (P72) can be adjusted by the rise delay time of the eighth inverter (INV8).

Please refer to FIG. 6 again, the writing driving circuit (8) consists of a fourteenth PMOS transistor (P81), a fourteenth NMOS transistor (M81), a fifteenth NMOS transistor (M82), A sixteenth NMOS transistor (M83), a ninth inverter (INV9), a tenth inverter (INV10), a capacitor (Cap), an input data (Din), a line of decoder output signals ( Y), a third delay circuit (D3), a fourth delay circuit (D4) and a third high power supply voltage (V _DDH3 ), wherein the source of the fourteenth PMOS transistor (P81), The gate and the drain are respectively connected to the third high power supply voltage (V _DDH3 ), the output of the ninth inverter (INV9) and the drain of the fourteenth NMOS transistor (M81). The source, gate and drain of the four NMOS transistors (M81) are connected to the drain of the sixteenth NMOS transistor (M83), the output of the ninth inverter (INV9) and the fourteenth NMOS transistor (M83), respectively. The drain of the PMOS transistor (P81), the source, gate and drain of the fifteenth NMOS transistor (M82) are respectively connected to the ground voltage, the output of the third delay circuit (D3) and the first The drain of the fourteenth PMOS transistor (P81), the source, gate and drain of the sixteenth NMOS transistor (M83) are respectively connected to the ground voltage and the output of the tenth inverter (INV10) With the source of the fourteenth NMOS transistor (M81), the input of the ninth inverter (INV9) is for receiving the input data (Din), and the output is connected to the fourteenth PMOS transistor (P81) ), the gate of the fourteenth NMOS transistor (M81) and the input of the third delay circuit (D3), the input of the tenth inverter (INV10) is for receiving the output signal of the row decoder (Y), and the output is connected to the input of the fourth delay circuit (D4) and the gate of the sixteenth NMOS transistor (M83), and one end of the capacitor (Cap) is connected to the fourth delay circuit ( D4) output, and the other end of the capacitor (Cap) is connected to the source of the fourteenth NMOS transistor (M81) and the drain of the sixteenth NMOS transistor (M83), wherein the tenth The drains of the four PMOS transistors (P81), the drains of the fourteenth NMOS transistor (M81) and the drains of the fifteenth NMOS transistor (M82) are jointly connected to the write bit line ( WBL), the write bit line (WBL) is designed to be lower than the voltage level of the ground voltage in the first stage of writing logic 0 to accelerate the speed of writing logic 0. 1 is designed to be a level higher than the third highest power supply voltage (V _DDH3 ) of the power supply voltage (V _DD ) to speed up the speed of writing logic 1s.

Whether the write driving circuit (8) is enabled is determined by the logic level of the output signal (Y) of the row decoder. When the output signal (Y) of the row decoder is at a logic low level, the writing driving circuit ( 8) is a non-enable state, and when the row decoder output signal (Y) is at a logic high level, the write-in driver circuit (8) is in an enabled state. When the line decoder output signal (Y) is at a logic low level, the output of the tenth inverter (INV10) is at a logic high level, which turns on the sixteenth NMOS transistor (M83) on the one hand, and passes through the After the delay time provided by the fourth delay circuit (D4), one end of the capacitor (Cap) is charged. Due to the conduction of the sixteenth NMOS transistor (M83), the other end of the capacitor (Cap) is the ground voltage , and one end of the capacitor (Cap) will maintain the voltage level of the power supply voltage (V _DD ) due to the charging of the capacitor (Cap).

The write-in driver circuit (8) adopts a two-stage operation when the write-in logic 0 is enabled. In the first stage of the write-in driver circuit (8), the output signal of the row decoder is at a logic high level. (Y), so that the output of the tenth inverter (INV10) is a logic low level, on the one hand, the sixteenth NMOS transistor (M83) is turned off (OFF) state, on the other hand, through the fourth delay circuit After the delay time provided by (D4), one end of the capacitor (Cap) is rapidly discharged to the ground voltage. Since the input data (Din) is at a logic low level at this time, the output of the ninth inverter (INV9) is It is a logic high level, so the fourteenth NMOS transistor (M81) is turned on, and the fourteenth PMOS transistor (P81) is turned off (OFF) state, so the voltage of the write bit line (WBL) The level satisfies equation (3) when the write driver circuit (8) writes a logic 0 in the first stage:

V _WBL1 =-V _DD ×Cap/(Cap+C _WBL ) (3)

Wherein, V _WBL1 represents the voltage level of the write bit line (WBL) in the first stage of writing logic 0, and the absolute value of V _WBL1 is designed to be less than the threshold voltage of the third NMOS transistor (M13), For example, it can be designed to be -100mV, -150mV or -200mV, V _DD is the voltage level of the power supply voltage (V _DD ), and Cap and C _WBL represent the capacitance value of the capacitor (Cap) and the write-in voltage respectively. Parasitic capacitance value of the bit line (WBL).

When the input data (Din) of logic low level passes through the ninth inverter After (INV9) and the delay time provided by the third delay circuit (D3), the write driver circuit (8) enters the second stage of enabling, at this time, since the fifteenth NMOS transistor (M82) is turned on state, so that the voltage level of the write bit line (WBL) satisfies equation (4) when the write driver circuit (8) writes the second stage of logic 0:

V _WBL2 = 0 (4)

The working principle of the preferred embodiment of the present invention shown in Fig. 6 is described as follows:

(I) write mode (write mode)

Before the writing operation starts, the standby mode control signal (S) is at a logic low level, and the inverting write control signal (/WC) is at a logic high level, so that the third PMOS transistor (P21) is turned on (ON). ), and the tenth NMOS transistor (M27) is turned off (OFF), so the drain of the third PMOS transistor (P21) is at a logic high level, and the third PMOS transistor (P21) at the logic high level Its drain will turn on the ninth NMOS transistor (M26), and make the first low voltage node (VL1) be at the ground voltage.

During the write operation period, the standby mode control signal (S) and the inversion write control signal (/WC) are at a logic low level, so that the third PMOS transistor (P21) is turned on, and the tenth NMOS transistor is turned on. The crystal (M27) is turned off, and the drain of the third PMOS transistor (P21) is at a logic low level (because the inverting write control signal (/WC) is at a logic low level at this time), and the logic low level is at a logic low level. The drain of the third PMOS transistor (P21) turns off the ninth NMOS transistor (M26) and makes the first low voltage node (VL1) equal to the gate-source of the sixth NMOS transistor (M23) voltage V _{GS (M26)} , thereby effectively preventing the problem of difficulty in writing logic 1s. FIG. 7a shows a simplified circuit diagram of the preferred embodiment of the present invention of FIG. 6 during writing of a logic 0, and FIG. 7b shows a simplified circuit diagram of a period of writing a logic 1. FIG.

Next, according to four write states, how the preferred embodiment of the present invention shown in FIGS. 7a and 7b completes the operations of writing logic 0 and writing logic 1 will be described.

(1) Node A originally stored logic 0, but now wants to write logic 0:

Before the writing operation occurs (the writing word line control signal WWLC is at the ground voltage), the first NMOS transistor (M11) is turned on (ON). Since the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line (WWL) changes from Low (ground voltage) to High (power supply voltage V _DD ). When the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned off (OFF). ) turns on (ON), at this time, because the write bit line (WBL) is designed to be lower than the ground voltage in the first stage of writing logic 0, and the logic 0 is written at a voltage level lower than the ground voltage In the second stage, it is pulled back to the ground voltage, so the node A is discharged, and the write operation of logic 0 is completed until the end of the write cycle.

(2) Node A originally stored logic 0, but now wants to write logic 1:

Before the writing operation occurs (the writing word line control signal WWLC is at the ground voltage), the first NMOS transistor (M11) is turned on (ON). It is worth noting here that because the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line control signal (WWLC) changes from Low (ground voltage) to High, and the The voltage of the node A will rise slightly following the voltage of the write word line control signal (WWLC) due to the parasitic capacitive coupling effect. When the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF (OFF) to ON (ON) , because the write bit line (WBL) is the voltage level of the third high power supply voltage (V _DDH3 ), and because the first NMOS transistor (M11) is still ON and the node B is still In the initial state where the voltage level is close to the voltage level of the power supply voltage (V _DD ), the first PMOS transistor (P11) is still turned off (OFF), and the initial instantaneous voltage of the node A is written (V _AWI ) satisfies equation (5):

V _AWI1 =V _DDH3 ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 )>V _TM12 (5) Among them, V _AWI1 represents the initial instantaneous voltage of writing logic 1 at node A, and R _M13 represents the on-resistance of the third NMOS transistor (M13), R _M11 represents the on-resistance of the first NMOS transistor (M11), R _M23 represents the on-resistance of the sixth NMOS transistor (M23), and V _DDH3 and V _TM12 respectively represents the voltage level of the third high power supply voltage and the threshold voltage of the second NMOS transistor (M12). Since a voltage level equal to the gate-source voltage V _{GS ( M23 )} of the sixth NMOS transistor ( M23 ) is provided at the first low voltage node ( VL1 ), the voltage level of node A can be easily changed to The standard is set to be much higher than the voltage level of the node A of the conventional 5T SRAM cell in FIG. 4 . The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), thereby discharging node B to a lower voltage level that causes the The ON equivalent resistance (R _M11 ) of the first NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A The higher voltage level of the node A will pass through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B presents a lower voltage level , the lower voltage level of the node B will pass through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11 ), so that the node A obtains a higher voltage level, According to this cycle, the node A can be charged to the power supply voltage (V _DD ), and the writing operation of logic 1 is completed.

Wherein, the first low voltage node (VL1) originally stores logic 0 at node A, and during writing logic 1, it has a gate-source voltage V _{GS (M23) equal to the sixth NMOS transistor (M23)} After the logic 1 is written, it will be the ground voltage level due to the discharge through the ninth NMOS transistor (M26).

It is worth noting here that the present invention uses a two-stage writing word line control circuit (6) to effectively solve the problem that the writing time cannot meet the specification when the operating voltage of the SRAM below 10 nm is below 0.9V. In the first stage of enabling the writing word line (WWL), the writing word line control circuit (6) sets the writing word line control signal (WWLC) to a higher value than the writing word line control signal (WWLC). The power supply voltage (V _DD ) is still higher than the second high power supply voltage (V _DDH2 ), since the logic 0 is originally stored at the node A and the third NMOS transistor ( M13 ) operates at the initial stage of writing the logic 1 In the saturation region, the current in the saturation region is proportional to the voltage level of the gate-source voltage V _{GS (M13)} minus the square of the threshold voltage V _TM13 . Therefore, the word line control signal (WWLC) is used for this writing. During the first phase of the second high power supply voltage (V _DDH2 ), which is set to be higher than the power supply voltage (V _DD ), the speed of writing logic 1 can be effectively accelerated; For the interference phenomenon of the semi-selected cell, during the second stage after the first stage, the writing word line control signal (WWLC) is pulled down back to the voltage level of the power supply voltage (V _DD ), Wherein, the time interval between the second stage and the first stage of the writing word line control circuit (6) is equal to the output of the fifth inverter (INV5) enough to turn on the eighth PMOS transistor ( From the time of P61) to the time until the output of the sixth inverter (INV6) is sufficient to turn off the ninth PMOS transistor (P62), its value can be increased by the sixth inverter (INV6) delay time to adjust.

(3) Node A originally stored logic 1, but now wants to write logic 1:

Before the write operation occurs (the write word line control signal WWLC is at the ground voltage), the first PMOS transistor ( P11 ) is turned on (ON). When the write word line control signal (WWLC) changes from Low (ground voltage) to High, since the node A is the voltage level of the power supply voltage (V _DD ), and the write bit line (WBL) ) is the voltage level of the third high power supply voltage (V _DDH3 ), so when the second high power supply voltage (V _DDH2 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the sum of the threshold voltage of the third NMOS transistor (M13) V _TM13 , namely

V _DD <V _DDH2 <V _DD +V _TM13 (6) will keep the third NMOS transistor (M13) in an OFF state; at this time, because the first PMOS transistor (P11) is still ON, so The voltage of the node A is maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stored logic 1, but now wants to write logic 0:

Before the write operation occurs (the write word line control signal WWLC is at the ground voltage), the first PMOS transistor ( P11 ) is turned on (ON). When the writing word line control signal (WWLC) turns from Low (ground voltage) to High, and the voltage of the writing word line control signal (WWLC) is greater than the threshold voltage of the third NMOS transistor (M13) At this time, the third NMOS transistor (M13) is turned from OFF (OFF) to ON (ON). At this time, because the write bit line (WBL) is a voltage level (V _WBL1 ) that satisfies equation (3) , which is less than 0V, and because the first PMOS transistor (P11) is still ON and the node B is in an initial state where the voltage level is close to the voltage level of the ground voltage, the first NMOS transistor (M11 ) is still turned off, and the initial write-in instantaneous voltage (V _AWI0 ) of the node A satisfies equation (7):

V _AWI0 =V _WBL1 ×R _P11 /(R _M13 +R _P11 )+V _DD ×R _M13 /(R _M13 +R _P11 ) (7)

V _AWI0 represents the initial write voltage at node A from logic 1 to logic 0, R _M13 and R _P11 represent the on-resistances of the third NMOS transistor (M13) and the first PMOS transistor (P11), respectively, and V _WBL1 and V _DD represent the voltage level of the write bit line (WBL) in the first stage of writing logic 0 and the voltage level of the power supply voltage (V _DD ), respectively. When logic 0, the third NMOS transistor (M13) works in the saturation region, and the current in the saturation region is proportional to the square of its gate-source voltage _{VGS (M13)} minus its threshold voltage, Therefore, the voltage level (V _WBL1 ) in the first stage of writing logic 0 by the write bit line (WBL) is less than 0V and by setting the write word line control signal (WWLC) to The design of the second high power supply voltage (V _DDH2 ), which is higher than the power supply voltage (V _DD ), can effectively speed up the speed of writing logic 0s from logic 1s.

It is worth noting here that when node A is written from logic 0 to logic 1 and logic 1 is written to logic 0, the third NMOS transistor (M13) works in the saturation region, and the current in the saturation region is related to its gate-source The voltage level of the pole voltage V _{GS (M13)} is proportional to the square after deducting its threshold voltage. Therefore, through the two-stage writing word line control circuit (6), the writing word line ( In the first stage of enabling WWL, the writing word line control signal (WWLC) is set to the second high power supply voltage (V _DDH2 ) which is higher than the power supply voltage (V _DD ), which is effective Speed up the writing speed of writing logic 1 from logic 0 to node A and writing logic 0 from logic 1; furthermore, when node A writes logic 0 from logic 1, the above equation (3) can be used to write logic 1 from logic 1. In the initial stage of writing logic 0, a voltage level (V _WBL1 ) lower than the ground voltage is provided to the writing bit line (WBL), wherein the absolute value of V _WBL1 is limited to be smaller than the third NMOS transistor (M13 ) of the threshold voltage, for example, can be designed to be -100mV, -150mV or -200mV, thereby further increasing the gate-source voltage _{VGS (} M13) of the third NMOS transistor (M13) operating in the saturation region ₎ to effectively improve the writing speed of node A from logic 1 to logic 0.

(II) read mode (read mode)

Before the read operation starts, the standby mode control signal (S) is at a logic low level, and the inverting write control signal (/WC) is at a logic high level, so that the third PMOS transistor (P21) is turned on, and The tenth NMOS transistor (M27) is turned off, so the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at the logic high level will turn on the ninth The NMOS transistor (M26) makes the first low voltage node (VL1) be at the ground voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned on (ON).

It should be noted here that during the precharge period before the start of the read operation, the precharge signal (P) is at a logic low level, thereby precharging the corresponding read bit line (RBL) to The level of the power supply voltage (V _DD ) cannot meet the standard problem because the operating voltage of the process technology below 10 nm will be reduced to less than 0.9 volt, which will cause the reading speed to decrease and cannot meet the specification. Therefore, the present invention proposes two Staged read control to improve read speed and meet specifications while avoiding unnecessary power consumption.

The preferred embodiment of the present invention shown in FIG. 6 uses two-stage read control to improve the read speed while avoiding unnecessary power consumption. In the first stage of the read operation, The read control signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the second low voltage node (VL2) About the accelerated read voltage (RGND) lower than the ground voltage, the accelerated read voltage (RGND) lower than the ground voltage can effectively improve the read speed.

In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, so that the seventh NMOS transistor (M24) is still turned on, because the eighth NMOS transistor ( M25) is turned off, so the second low voltage node (VL2) will be at ground voltage through the turned on fourth NMOS transistor (M21) (due to the inverting standby mode control signal (/S) during the read operation is logic high level), thereby effectively reducing unnecessary power consumption. It should be noted here that the time interval between the second phase of the read operation and the first phase is equal to the time from when the read control signal (RC) changes from a logic low level to a logic high level, and ends at the first The time until the gate voltage of the eight NMOS transistors (M25) is sufficient to turn off the eighth NMOS transistor (M25) can be determined by the falling delay time of the third inverter (INV3) and the first delay circuit (D1) to adjust the delay time provided. Furthermore, the fourth NMOS transistor (M21) is in an on state whether in the first stage or the second stage of the read operation (because the inverting standby mode control signal (/S) is logic during the read operation). high level). FIG. 8 is a simplified circuit diagram of the preferred embodiment of the present invention of FIG. 6 during reading.

Next, how the preferred embodiment of the present invention shown in FIG. 8 uses the coupling element (CE), the control circuit (2), the high-voltage level control circuit (5) and the readout according to two readout states will be described. The word line control circuit (7) is used to improve the reading speed while avoiding unnecessary power consumption.

(1) Read logic 1 (node A stores logic 1):

Before the read operation occurs, the first NMOS transistor (M11) is turned off (OFF) and the second NMOS transistor (M12) is turned on (ON), the node A and the node B are respectively the power supply voltage (V _DD ) and ground voltage, and the coupling element (CE) is turned off (OFF), and the read bit line (RBL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3) ). During the reading period, since the node B is at the ground voltage and the coupling element (CE) is turned off (OFF), the second read transistor (M15) is turned off (OFF), thereby effectively maintaining the reading The power supply voltage (V _DD ) is supplied by the bit line (RBL) until the end of the read cycle and the operation of reading logic 1 is successfully completed. It is worth noting here that in the first stage of the read operation, the read initial instantaneous voltage ( _VRVL2I ) of the second low voltage node (VL2) at the time of read logic 1 must satisfy Equation (8):

V _RVL2I =RGND×R _M21 /(R _M21 +R _M24 +R _M25 )>-V _TM12 (8) to effectively prevent half-selected cell interference during reading, where V _RVL2I represents the second low voltage node (VL2) The reading initial instantaneous voltage when reading logic 1, RGND represents the accelerated reading voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), and R _M24 represents the seventh NMOS transistor ( M24) on-resistance, R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12); and in the second stage of the read operation , the voltage ( _VRVL2 ) of the second low voltage node (VL2) can be expressed by equation (9)

_VRVL2 = ground voltage (9) Thereby, unnecessary power consumption can be effectively reduced. Furthermore, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, the accelerated reading voltage (RGND), which is lower than the ground voltage, must be set to make the second low voltage node (VL2) The voltage level is lower than the threshold voltage (V _TM12 ) of the second NMOS transistor ( M12 ), and at the same time, the absolute value |RGND| of the accelerated read voltage (RGND), which is lower than the ground voltage, can be set to be low The threshold voltage (V _TM12 ) of the second NMOS transistor ( M12 ) is

|RGND|<V _TM12 (10) Wherein, |RGND| and V _TM12 represent the absolute value of the acceleration read voltage and the threshold voltage of the second NMOS transistor ( M12 ), respectively.

(2) Read logic 0 (node A stores logic 0):

Before the read operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF), and the node A and the node B are respectively the ground voltage and the The power supply voltage (V _DD ), and the coupling element (CE) provides high coupling capacitance due to the conduction (ON), and the read bit line (RBL) is equal to the power supply due to the precharge circuit (3) Supply Voltage (V _DD ). During reading, since node B is the first high power supply voltage (V _DDH1 ), the coupling element (CE) is turned off (OFF) to provide low coupling capacitance, and the second low voltage node (VL2) is relatively low. The ground voltage is a low voltage, the present invention sets the first high power supply voltage (V _DDH1 ) to be higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the second PMOS power The sum of the absolute value of the threshold voltage of the crystal (P12) | V _TP12 |

V _DD <V _DDH1 <V _DD + | V _TP12 | (11)

Wherein, |V _TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12), therefore, the conduction level of the second read transistor (M15) can be increased to improve the read logic 0 speed, and at the same time cooperate with the second low voltage node (VL2) which is lower than the ground voltage to further improve the read speed.

Furthermore, during the read period, the read word line is controlled by the read word line control circuit (7) in the first stage of enabling the read word line (RWL) Signal (RWLC) is set to the second high power supply voltage (V _DDH2 ) higher than the power supply voltage (V _DD ) to further reduce the resistance of the read path and speed up the read bit line (RWL) ) to discharge the charge on the ) to further increase the read speed, and in the second stage after the first stage, the read word line control signal (RWLC) is pulled down back to the power supply voltage (V _DD ) to mitigate read disturb. It should be noted here that the second high power supply voltage (V _DDH2 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the first read transistor (M14) the sum of the threshold voltage V _TM14 , that is

V _DD <V _DDH2 <V _DD +V _TM14 (12)

Comparing equation (6) with equation (12), it can be known that the second high power supply voltage (V _DDH2 ) must satisfy V _TM14 between the power supply voltage (V _DD ) and the threshold voltage of the first read transistor (M14) The sum of (V _DD +V _TM14 ) and the smaller of the power supply voltage (V _DD ) and the sum of the threshold voltages of the third NMOS transistor (M13) V _TM13 (V _DD +V _TM13 ).

Furthermore, in order to simplify the circuit design, the first high power supply voltage (V _DDH1 ), the second high power supply voltage (V _DDH2 ) and the third high power supply voltage (V _DDH3 ) can be designed to be the same. The value is greater than the power supply voltage (V _DD ) but less than or equal to the sum of V _TM14 that satisfies the power supply voltage (V _DD ) and the threshold voltage of the first read transistor (M14) (V _DD +V _TM14 ), The sum of the power supply voltage (V _DD ) and the threshold voltage of the third NMOS transistor (M13) V _TM13 (V _DD +V _TM13 ) and the power supply voltage (V _DD ) and the second PMOS transistor ( P12 ) ) of the absolute value of the threshold voltage | V _TP12 | sum (V _DD + | V _TP12 | ), whichever is the smaller (this value can be inferred from Equation (6), Equation (11) and Equation (12)).

Finally, the coupling element (CE) is designed to provide different coupling capacitances due to the operation of the SRAM cell in hold mode and read mode and the storage logic state of the inverting storage node, wherein when the SRAM cell is in hold mode and the When the inverting storage node (B) is a logic 1, it provides the largest coupling capacitance, that is, when the SRAM cell is in hold mode and the inverting storage node (B) is a logic 1, the coupling capacitance is greater than that of the inverting storage When the node (B) is a logic 0, the coupling capacitance is larger than the coupling capacitance when the SRAM cell is in the read mode, so that the voltage level of the inverted storage node (B) can be increased at the initial stage of reading the logic 0 , thereby effectively reducing the equivalent resistance of the second read transistor (M15), so that the read speed can be further improved, and specified.

1: SRAM cell

2: Control circuit

3: Precharge circuit

4: Standby start circuit

5: High voltage level control circuit

6: Word line control circuit for writing

7: Word line control circuit for reading

8: Write drive circuit

P11: The first PMOS transistor

P12: Second PMOS transistor

M11: The first NMOS transistor

M12: Second NMOS transistor

M13: The third NMOS transistor

A: Storage node

B: Inverted storage node

C:node

M14: The first read transistor

M15: Second read transistor

WBL: Write bit line

WWL: word line for writing

RBL: read bit line

RWL: read word line

WWLC: Write word line control signal

RWLC: word line control signal for reading

S: Standby mode control signal

/S: Inverted standby mode control signal

VL1: first low voltage node

VL2: Second Low Voltage Node

M21: Fourth NMOS transistor

M22: Fifth NMOS transistor

M23: sixth NMOS transistor

M24: seventh NMOS transistor

M25: Eighth NMOS transistor

M26: Ninth NMOS transistor

M27: Tenth NMOS transistor

P21: The third PMOS transistor

RC: read control signal

RGND: Speed up reading voltage

INV3: Third Inverter

D1: first delay circuit

WC: write control signal

/WC: Inverted write control signal

P31: Fourth PMOS transistor

P: Precharge signal

M41: Eleventh NMOS transistor

P41: Fifth PMOS transistor

D2: Second delay circuit

V _DD : Power supply voltage

V _DDH1 : The first high power supply voltage

V _DDH2 : The second highest power supply voltage

P51: sixth PMOS transistor

P52: seventh PMOS transistor

INV4: Fourth inverter

VH: High Voltage Node

P61: Eighth PMOS transistor

P62: Ninth PMOS transistor

P63: Tenth PMOS transistor

M61: Twelfth NMOS transistor

INV5: Fifth inverter

INV6: sixth inverter

P71: Eleventh PMOS transistor

P72: Twelfth PMOS transistor

P73: Thirteenth PMOS transistor

M71: Thirteenth NMOS transistor

INV7: seventh inverter

INV8: Eighth Inverter

P81: Fourteenth PMOS transistor

M81: Fourteenth NMOS transistor

M82: The fifteenth NMOS transistor

M83: Sixteenth NMOS transistor

INV9: ninth inverter

INV10: Tenth Inverter

D3: Third delay circuit

D4: Fourth delay circuit

V _DDH3 : The third highest power supply voltage

Y: line decoder output signal

Cap: capacitor

Din: input data

CE: Coupling Element

Claims (9)

A memory device, comprising: a memory array, the memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each row of memory cells and each row of memory cells include A plurality of memory unit cells (1); a plurality of control circuits (2), each row of memory unit cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory unit cells is provided with a pre-charge circuit a charging circuit (3); a standby start-up circuit (4), the standby start-up circuit (4) prompts the memory device to quickly enter a standby mode, so as to effectively improve the standby performance of the memory device; a plurality of writing characters Line control circuit (6), each row of memory cells is provided with a word line control circuit (6) for writing, so as to effectively improve the writing of logic 1 from logic 0 and the writing of logic 1 from the logic 1 in the writing mode A writing speed of 0; and a plurality of writing driving circuits (8), one writing driving circuit (8) is provided for each row of memory cells, so as to effectively improve the writing of the logic 1 from the logic 0 in the writing mode and the writing speed of writing the logic 0 by the logic 1; wherein, each memory cell (1) further comprises: a first inverter, which is composed of a first PMOS transistor (P11) and a A first NMOS transistor (M11) is formed, the first inverter is connected between a power supply voltage (V _DD ) and a first low voltage node (VL1); a second inverter is composed of A second PMOS transistor (P12) and a second NMOS transistor (M12) are formed. The second inverter is connected between a high voltage node (VH) and a second low voltage node (VL2). ; a storage node (A) is formed by the output of the first inverter; an inverting storage node (B) is formed by the output of the second inverter; a third NMOS power A crystal (M13) is connected between the storage node (A) and a write bit line (WBL), and the gate is connected to a write word line control signal (WWLC); a first read Take the transistor (M14), the source, gate and drain of the first read transistor (M14) are respectively connected to the drain of a second read transistor (M15), a read Use word line control signal (RWLC) and a read bit line (RBL); the second read transistor (M15), the source and gate of the second read transistor (M15) and the drain are respectively connected to the second low voltage node (VL2), the inversion storage node (B) and the source of the first read transistor (M14); and a coupling element (CE), the A coupling element (CE) is connected between the inverted storage node (B) and the read word line control signal (RWLC), and operates in a retention mode due to the memory cell (1) and A read mode and the stored logic state of the inverting storage node (B) provide different coupling capacitances, wherein when the memory cell (1) is in the hold mode and the inverting storage node (B) is a logic 1 Time Provide the largest coupling capacitance, that is, when the memory cell (1) is in the hold mode and the inverting storage node (B) is logic 1, the coupling capacitance is greater than the inverting storage node (B) is logic The coupling capacitance at 0 is greater than the coupling capacitance when the memory cell (1) is in the read mode; wherein, the first inverter and the second inverter are in an alternate coupling connection, that is, the The output terminal of the first inverter (ie the storage node A) is connected to the input terminal of the second inverter, and the output terminal of the second inverter (ie the inverting storage node B) is connected to The input end of the first inverter; and each control circuit (2) further comprises: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), and a sixth NMOS transistor (M23) , a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21) , a read control signal (RC), a third inverter (INV3), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), an inversion Write control signal (/WC), a standby mode control signal (S) and an inverted standby mode control signal (/S); wherein, the source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the inverting standby mode control signal (/S) and the second low voltage node (VL2); the source, gate and drain of the fifth NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); the source of the sixth NMOS transistor (M23) is connected to the ground voltage, The gate and drain are connected together and connected to the first low voltage node (VL1); the source, gate and drain of the seventh NMOS transistor (M24) are respectively connected to the eighth NMOS transistor The drain of (M25), the read control signal (RC) and the second low voltage node (VL2); the source, gate and drain of the eighth NMOS transistor (M25) are respectively connected to the acceleration read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to the third inverter (INV3) ) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV3) is for receiving the read control signal (RC), and the output is connected to the An input of a delay circuit (D1); the source, gate and drain of the ninth NMOS transistor (M26) are respectively connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first A low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27) are are respectively connected to the write control signal (WC), the standby mode control signal (S) and the drain of the ninth NMOS transistor (M26); the source and gate of the third PMOS transistor (P21) and the drain are respectively connected to the reverse write control signal (/WC), the standby mode control signal (S) and the drain of the tenth NMOS transistor (M27); wherein, the fourth NMOS transistor ( The bases of M21), the seventh NMOS transistor (M24) and the eighth NMOS transistor (M25) are connected to the accelerated read voltage (RGND) to prevent the fourth NMOS transistor (M21) from latching up due to and early damage; wherein, the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent the seventh NMOS transistor (M24) from being in the non-read mode. Take the leakage current during the mode. The memory device of claim 1, wherein the coupling element (CE) is composed of a PMOS transistor, and the gate of the PMOS transistor is connected to the read word line control signal (RWLC). ), the source and drain of the PMOS transistor are connected together and connected to the inverting storage node (B). The memory device of claim 1, wherein each writing word line control circuit (6) is composed of an eighth PMOS transistor (P61) and a ninth PMOS transistor (P62) , a tenth PMOS transistor (P63), a twelfth NMOS transistor (M61), a fifth inverter (INV5), a sixth inverter (INV6), a second high power supply voltage ( V _DDH2 ), a writing word line (WWL) and the writing word line control signal (WWLC); wherein, the source, gate and drain of the eighth PMOS transistor (P61) are respectively connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (INV5) and the source of the ninth PMOS transistor (P62); the ninth PMOS transistor (P62) The source, gate and drain are respectively connected to the drain of the eighth PMOS transistor (P61), the output of the sixth inverter (INV6) and the writing word line control signal (WWLC) ; The source, gate and drain of the tenth PMOS transistor (P63) are respectively connected to the power supply voltage (V _DD ), the output of the fifth inverter (INV5) and the writing word Line control signal (WWLC); the source, gate and drain of the twelfth NMOS transistor (M61) are respectively connected to the ground voltage, the output of the fifth inverter (INV5) and the write-in word line control signal (WWLC); the input of the fifth inverter (INV5) is for receiving the write word line (WWL), and the input of the sixth inverter (INV6) is connected to the input of the sixth inverter (INV6) The outputs of the five inverters (INV5) are connected; wherein, each write driving circuit (8) further comprises: a fourteenth PMOS transistor (P81), a fifteenth NMOS transistor (M81), a tenth Five NMOS transistors (M82), a sixteenth NMOS transistor (M83), a ninth inverter (INV9), a tenth inverter (INV10), a capacitor (Cap), an input data (Din ), a row decoder output signal (Y), a third delay circuit (D3), a fourth delay circuit (D4), and a third high power supply voltage (V _DDH3 ); wherein the fourteenth PMOS transistor The source, gate and drain of (P81) are respectively connected to the third high power supply voltage (V _DDH3 ), the output of the ninth inverter (INV9) and the fourteenth NMOS transistor (M81) The drain; the source, gate and drain of the fourteenth NMOS transistor (M81) are respectively connected to the drain of the sixteenth NMOS transistor (M83) and the ninth inverter (INV9) The output and the drain of the fourteenth PMOS transistor (P81); the source, gate and drain of the fifteenth NMOS transistor (M82) are respectively connected to the ground voltage, the third delay circuit ( The output of D3) is the same as the fourteenth P The drain of the MOS transistor (P81); the source, gate and drain of the sixteenth NMOS transistor (M83) are respectively connected to the ground voltage, the output of the tenth inverter (INV10) and the The source of the fourteenth NMOS transistor (M81); the input of the ninth inverter (INV9) is for receiving the input data (Din), and the output is connected to the fourteenth PMOS transistor (P81) The gate, the gate of the fourteenth NMOS transistor (M81) and the input of the third delay circuit (D3); the input of the tenth inverter (INV10) is for receiving the row decoder output signal (Y ), and the output is connected to the input of the fourth delay circuit (D4) and the gate of the sixteenth NMOS transistor (M83); one end of the capacitor (Cap) is connected to the fourth delay circuit (D4) output, and the other end of the capacitor (Cap) is connected to the source of the fourteenth NMOS transistor (M81) and the drain of the sixteenth NMOS transistor (M83); wherein, the fourteenth PMOS The drain of the transistor (P81), the drain of the fourteenth NMOS transistor (M81) and the drain of the fifteenth NMOS transistor (M82) are jointly connected to the write bit line (WBL) , the write bit line (WBL) is designed to be lower than the voltage level of the ground voltage in the first stage of writing the logic 0 to accelerate the speed of writing the logic 0. In the second stage of 0, it is pulled back to the ground voltage to slow down the interference when writing the logic 0; and when writing the logic 1, the write bit line (WBL) is designed to be higher than the power supply the level of the third highest power supply voltage (V _DDH3 ) of the supply voltage (V _DD ) to speed up the writing speed of the logic 1; wherein, each write driving circuit (8) is used for writing the logic 0 The first stage satisfies the following equation: V _WBL1 =-V _DD ×Cap/(Cap+C _WBL ) where V _WBL1 represents the write bit line (WBL) in the first stage of writing the logic 0 The absolute value of V _WBL1 is designed to be less than the threshold voltage of the third NMOS transistor (M13), V _DD is the voltage level of the power supply voltage (V _DD ), and Cap and C _WBL represent the The capacitance value of the capacitor (Cap) and the parasitic capacitance value of the write bit line (WBL). The memory device according to claim 3, further comprising a plurality of high-voltage level control circuits (5), each row of memory cells is provided with one of the high-voltage level control circuits (5), so as to To increase the reading speed when reading logic 0, each high voltage level control circuit (5) further comprises: a sixth PMOS transistor (P51), a seventh PMOS transistor (P52) and a fourth inverting device (INV4); wherein, the source, gate and drain of the sixth PMOS transistor (P51) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage Node (VH); the source, gate and drain of the seventh PMOS transistor (P52) are respectively connected to a first high power supply voltage (V _DDH1 ) and the output of the fourth inverter (INV4) and the high voltage node (VH); the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the gate of the seventh PMOS transistor (P52) ; wherein, the bases of the fifth PMOS transistor (P51) and the sixth PMOS transistor (P52) are connected to the first high power supply voltage (V _DDH1 ) to prevent the fifth PMOS transistor (P51) Premature damage due to latchup. The memory device according to claim 1, further comprising a plurality of read word line control circuits (7), and each row of memory cells is provided with a read word line control circuit (7). ), to further reduce the resistance of the read path when reading logic 0, and accelerate the discharge of the charge on the read bit line (RWL) to further increase the read speed, each read word line The control circuit (7) further comprises: an eleventh PMOS transistor (P71), a twelfth PMOS transistor (P72), a thirteenth PMOS transistor (P73), and a thirteenth NMOS transistor (M71) ), a seventh inverter (INV7), an eighth inverter (INV8), the second high power supply voltage (V _DDH2 ), the read word line (RWL) and the read word element line control signal (RWLC); wherein, the source, gate and drain of the eleventh PMOS transistor (P71) are respectively connected to the second high power supply voltage (V _DDH2 ), the seventh inversion the output of the device (INV7) and the source of the twelfth PMOS transistor (P72); the source, gate and drain of the twelfth PMOS transistor (P72) are respectively connected to the eleventh PMOS transistor The drain of the crystal (P71), the output of the eighth inverter (INV8) and the read word line control signal (RWLC); the source, gate and drain of the thirteenth PMOS transistor (P73) The poles are respectively connected to the power supply voltage (V _DD ), the output of the seventh inverter (INV7) and the read word line control signal (RWLC); the thirteenth NMOS transistor (M71) The source, gate and drain are respectively connected to the ground voltage, the output of the seventh inverter (INV7) and the read word line control signal (RWLC); the seventh inverter (INV7) The input is for receiving the read word line (RWL), and the input of the eighth inverter (INV8) is connected to the output of the seventh inverter (INV7). The memory device of claim 1, wherein the storage node (A) originally stores the logic 0, and the initial write-in voltage (V _AWI1 ) of the logic 1 satisfies the following equation: V _AWI1 =V _DDH3 ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 )>V _TM12 Wherein, V _AWI1 indicates that the storage node (A) writes the logic 1 by storing the logic 0 The writing initial instantaneous voltage, R _M11 , R _M13 and R _M23 respectively represent the on-resistance of the first NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor (M23), And V _DDH3 and V _TM12 respectively represent the voltage level of a third highest power supply voltage and the threshold voltage of the second NMOS transistor (M12 ); and the storage node (A) originally stores the logic 1, while writing The initial write instantaneous voltage (V _AWI0 ) into the logic 0 satisfies the following equation: V _AWI0 =V _WBL1 ×R _P11 /(R _M13 +R _P11 )+V _DD ×R _M13 /(R _M13 +R _P11 ) where, V _AWI0 represents the initial write voltage at node A from the logic 1 to the logic 0, R _M13 and R _P11 represent the on-resistance of the third NMOS transistor (M13) and the first PMOS transistor (P11), respectively , and V _WBL1 and V _DD respectively represent the voltage level of the write bit line (WBL) in the first stage of writing the logic 0 and the voltage level of the power supply voltage (V _DD ). The memory device of claim 1, wherein the read mode can be subdivided into two stages, and in a first stage of the read mode, the second low voltage node ( VL2) is set to a lower voltage than the ground voltage to effectively increase the read speed, and in a second stage of the read mode, the second low voltage node (VL2) is set back to the ground voltage so as to Reduce unnecessary power consumption; in the first stage of the read mode, the read initial instantaneous voltage ( _VRVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy the following equation: _VRVL2I = RGND×R _M21 /(R _M21 +R _M24 +R _M25 )>-V _TM12 to effectively prevent half-selected cell interference during reading, wherein V _RVL2I indicates that the second low voltage node (VL2) is used for reading The read initial instantaneous voltage at logic 1, RGND represents the accelerated read voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), and R _M24 represents the on-resistance of the seventh NMOS transistor (M24). , R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12). The memory device of claim 4, wherein the first high power supply voltage (V _DDH1 ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) ) and the absolute value |V _TP12 | of the threshold voltage of the second PMOS transistor ( P12 ), that is, V _DD <V _DDH1 <V _DD + |V _TP12 | The memory device of claim 4, wherein the first high power supply voltage (V _DDH1 ), the second high power supply voltage (V _DDH2 ) and the third high power supply voltage (V _{DDH3 )} ) is set to be the same, and its value is greater than the power supply voltage (V _DD ) but less than or equal to the sum of the power supply voltage (V _DD ) and the threshold voltage (V _TM14 ) of the first read transistor (M14 ) (V ) _DD +V _TM14 ), the power supply voltage (V _DD ) and the sum of the third NMOS transistor (M13) threshold voltage (V _TM13 ) (V _DD +V _TM13 ), and the power supply voltage (V _DD ) and the The sum of the absolute values (|V _TP12 |) of the threshold voltages of the second PMOS transistor ( P12 ) (V _DD + | V _TP12 | ) is the smaller of the three.

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