TW201919052A - Seven-transistor dual port static random access memory with fast writing speed capable of effectively increasing the performance of seven-transistor SRAM and increasing reading and writing speed and reducing leakage current - Google Patents

Abstract

The present invention provides a seven-transistor dual port static random access memory with fast writing speed, which mainly comprises a memory array (1), a plurality of control circuits (2), a plurality of pre-charging circuits (3), a standby starting circuit (4), a plurality of high voltage level control circuits (5), and a plurality of write-in driving circuit (6). The memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells is provided with a control circuit (2) and a high voltage level control circuit (5), and each row of memory cells is provided with a pre-charging circuit (3) and a write-in driving circuit (6). Therefore, in the writing mode, the plurality of control circuits (2) and the plurality of write-in drive circuits (6) can effectively prevent the write logic 1 from being difficult, and also increase the speed of writing into the logic 1. In the reading mode, the plurality of control circuits (2) and the plurality of high voltage level control circuits (5) can be used to increase the reading speed while avoiding unnecessary power consumption. In the standby mode, the plurality of control circuits (2) can be used to effectively reduce the leakage current, and the standby starting circuit (4) can be designed to effectively cause the static random access memory to quickly enter the standby mode.

Description

   7T dual-port static random access memory with high write speed   

The invention relates to a 7T dual port static random access memory (SRAM) with high write speed, and particularly to a 7T SRAM which can effectively improve the standby performance of the 7T SRAM and can effectively improve the read performance. SRAM with fast access speed and write speed, which can effectively reduce leakage current, reduce half-selected cell interference during reading, and avoid unnecessary power loss.

As shown in Figure 1a, the conventional static random access memory (SRAM) in the port includes a memory array. The memory array is composed of a plurality of memory blocks (MB _1). , MB ₂ etc.), each memory block is further composed of a plurality of rows of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word lines, WL ₁ , WL _2, etc.), each character line corresponds to a plurality of rows of memory One column in the unit cell; and multiple bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _m, etc.), each bit line pair corresponds to the multiple row memory cell One row, and each bit line pair is composed of a bit line (BL ₁ ... BL _m ) and a complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b is a schematic circuit diagram of a 6T port static random access memory (SRAM) cell. Among them, the PMOS transistors (P1) and (P2) are called load transistors and NMOS transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is a word line, and BL BLB and BLB are bit line and complementary bit line, respectively. Since this port SRAM cell requires 6 transistors, and to read the logic 0, in order to avoid the initial instant of the read operation (initial instant) Another driving transistor is turned on, and the initial instantaneous voltage (V _AR ) read by node A must satisfy equation (1): V _AR = V _DD × (R _M1 ) / (R _M1 + R _M3 ) <V _TM2 (1) to prevent half-selected cell disturbance during reading, where V _AR represents the initial instantaneous voltage of node A and R _M1 and R _M3 respectively represent the NMOS transistor (M1 ) And the on-resistance of the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply voltage and the threshold voltage of the NMOS transistor (M2), which leads to driving the transistor The current drive capability ratio (ie, the cell ratio) between the body and the access transistor is usually set between 2.2 and 3.5 (please refer to US Patent No. US76060B2 of October 20, 1998, column 2 columns 8-10 Row).

Figure 1b shows the simulation results of HSPICE transient analysis during the write operation of the 6T-port static random access memory cell. As shown in Figure 2, it is simulated using TSMC 90nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a circuit diagram of a 5T SRAM cell with a single bit line. Compared with the 6T SRAM cell in Figure 1b, this 5T static The RAM cell has one transistor and one bit line less than the 6T SRAM cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2. And in the case of the channel width-to-length ratio of the NMOS transistors M1, M2, and M3, there is a problem that it is quite difficult to write a logic 1. Consider the case where node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transferred from the bit line (BL), the logic 0 previously written in node A is overwritten by the logic 1 The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 ) / (R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of node A, R _M1 and R _M3 represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3), respectively. Comparing equation (1) and equation (2), it can be seen that the initial instantaneous voltage (V _AW ) is less than the NMOS transistor (M2) ) Threshold voltage (V _TM2 ), so the operation of writing logic 1 cannot be completed. The simulation results of HSPICE transient analysis during the write operation of the 5T SRAM cell shown in Figure 3, as shown in Figure 4, are simulated using TSMC 90nm CMOS process parameters. The simulation results can confirm that the 5T SRAM cell with a single bit line has the problem of writing logic 1 quite difficult.

Next, we discuss the SRAM and dual-port architecture. The 6T SRAM cell in Figure 1b is the SRAM static-access memory (SRAM) crystal. For example, it uses two bit lines BL and BLB for reading and writing, that is, reading and writing are achieved through the same pair of bit lines, so that only reading or writing can be performed at the same time. Write operation, therefore, when you want to design dual-port static random access memory with simultaneous read and write capabilities, you need to add two more access transistors and another pair of bit lines (refer to Figure 5) Circuit, where WBL and WBLB are bit line pairs for writing, RBL and RBLB are bit line pairs for reading, WWL is a word line for writing, and RWL is a word line for reading), which makes the memory The area of the cell is greatly increased. If we can simplify the structure of the memory cell, so that one bit line is responsible for reading and the other bit line is responsible for writing. When the memory is taken, the memory cell does not need to add two more transistors and a pair of bit lines. Such memory cell area will be reduced in many conventional dual-port static random-access memory cell is not the reason why this approach is quite difficult because of the problem of writing a logic 1 is present as described above.

To date, many technologies for dual-port static random access memory cells with a single bit line have been proposed, such as the "7T dual-port static random access memory" proposed in Patent Document 1 (TWI541802 on July 11, 105). "Access Memory (1)", "Dual write wordline memory cell" proposed in Patent Document 2 (US9336863B2, May 10, 105), and Patent Document 3 (US 9275724B2, March 1, 105) "Method of writing to and reading data from a three-dimensional two port register file", "Dual-Port Static Random Access Memory" proposed by Patent Document 4 (June 11, 103, TWI441178), Patent Document No. 5 (US8737117B2, May 27, 103), "System and method to read a memory cell with a complementary metal-oxide-semiconductor (CMOS) read transistor", Patent Document 6 (No. 6, May 103, US8717807B2) "Independently-controlled-gate SRAM", Patent Document 7 (April 1, 103, TWI433152), "7T Dual-Port SRAM", Patent Document 8 (February 1, 103 TWI425509) proposed `` dual port with discharge path State random access memory ", Patent Document 9 (TWI423257 of January 11, 103)," Dual-port SRAM with reduced power supply voltage during write operation ", Patent Document 10 (No. 11 of January 103, 103 TWI423258) proposed "Dual-port static random access memory to increase the voltage level of the word line for writing during writing operation". Although these patents can effectively solve the problem of writing logic 1, None of the patents considered the problem of lowering the write speed and read speed caused by the operating voltage of the process below 20 nanometers falling below 1 volt, so there is still room for improvement.

In view of this, the main object of the present invention is to propose a 7T dual-port static random access memory with high writing speed, which can effectively improve the reading speed by the dual mechanism of the control circuit and the high voltage level control circuit. .

A secondary object of the present invention is to provide a 7T dual-port static random access memory with high write speed, which can write the drive circuit to drive the bit line voltage level higher than the power supply voltage to While effectively preventing write logic 1 from being difficult, it can also effectively improve write speed.

Another object of the present invention is to provide a 7T dual-port static random access memory with high write speed, which can improve the read speed by using two-stage read control while avoiding unnecessary power. Attrition.

The invention proposes a 7T dual-port static random access memory with high writing speed, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby A start circuit (4), a plurality of high voltage level control circuits (5), and a plurality of write drive circuits (6), the memory array is composed of a plurality of rows of memory cell units and a plurality of rows of memory unit cells, Each column of memory cells is provided with a control circuit (2) and a high-voltage level control circuit (5), and each row of memory cells is provided with a precharge circuit (3) and a write drive circuit (6). Therefore, in the write mode, the plurality of control circuits (2) and the plurality of write driving circuits (6) can be used to effectively prevent the difficulty of writing the logic 1 while increasing the speed of writing the logic 1 In the reading mode, the plurality of control circuits (2) and the plurality of high-voltage level control circuits (5) can be used to improve the reading speed while avoiding unnecessary power consumption. In the standby mode At this time, the plurality of control circuits (2) can effectively reduce the leakage current, and the design of the standby start circuit (4) can effectively promote the static random access memory to quickly enter the standby mode.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧ pre-charge circuit

4‧‧‧ Standby start circuit

5‧‧‧high voltage level control circuit

6‧‧‧write drive circuit

P11‧‧‧The first PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧The first NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧Third NMOS transistor

A‧‧‧Storage Node

B‧‧‧ Inverted Storage Node

C‧‧‧node

M14‧‧‧First reading transistor

M15‧‧‧Second reading transistor

WBL‧‧‧Bit line for writing

WWL‧‧‧writing character line

RBL‧‧‧Bit line for reading

RWL‧‧‧Read Character Line

S‧‧‧Standby mode control signal

/ S ‧‧‧ Inverted standby mode control signal

VL1‧‧‧The first low voltage node

VL2‧‧‧Second Low Voltage Node

M21‧‧‧Fourth NMOS transistor

M22‧‧‧Fifth NMOS transistor

M23‧‧‧sixth NMOS transistor

M24‧‧‧Seventh NMOS transistor

M25‧‧‧eighth NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧Tenth NMOS Transistor

P21‧‧‧The third PMOS transistor

RC‧‧‧Read control signal

RGND‧‧‧Accelerated reading voltage

INV‧‧‧Third Inverter

D1‧‧‧first delay circuit

P31‧‧‧Fourth PMOS transistor

P‧‧‧Pre-charge signal

M41‧‧‧11th NMOS transistor

P41‧‧‧Fifth PMOS transistor

D2‧‧‧Second Delay Circuit

V _DD ‧‧‧ Power supply voltage

V _DDH1 ‧‧‧ Highest power supply voltage

V _DDH2 ‧‧‧ the second highest power supply voltage

P51‧‧‧Sixth PMOS transistor

P52‧‧‧The seventh PMOS transistor

I53‧‧‧Fourth inverter

VH‧‧‧High Voltage Node

P61‧‧‧eighth PMOS transistor

P62‧‧‧9th PMOS transistor

P63‧‧‧Tenth PMOS transistor

P64‧‧‧11th PMOS transistor

M61‧‧‧Twelfth NMOS Transistor

M62‧‧‧Thirteenth NMOS Transistor

I63‧‧‧Fifth inverter

Din‧‧‧Enter data

WC‧‧‧ write control signal

BLB ₁ ^… BLB _m ‧‧‧ complementary bit line

BLB‧‧‧ Complementary Bit Line

MB ₁ ^… MB _k ‧‧‧Memory block

WL ₁ ^… WL _n ‧‧‧Character line

BL ₁ ^… BL _m ‧‧‧bit line

M1 ^… M4‧‧‧NMOS transistor

P1 ^… P2‧‧‧PMOS transistor

I ₁ , I ₂ , I ₃ , I ₄ ‧‧‧ Leakage current

Figure 1a shows a conventional static random access memory cell; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; Figure 2 shows a conventional 6T static random access memory cell Figure 3 is a timing diagram of a conventional 5T SRAM cell; Figure 4 is a timing diagram of a conventional 5T SRAM cell; FIG. 5 is a circuit diagram showing a conventional 8T dual-port static random access memory cell; FIG. 6 is a circuit diagram showing a circuit proposed by a preferred embodiment of the present invention; FIG. 7 is a diagram showing the present invention of FIG. 6 A simplified circuit diagram of the preferred embodiment during a write logic 1; FIG. 8 is a timing diagram of the write operation of the preferred embodiment of the present invention in FIG. 6; FIG. 9 is a preferred implementation of the present invention in FIG. 6 Example is a simplified circuit diagram during reading; Figure 10 is a simplified circuit diagram of the preferred embodiment of the present invention shown in Figure 6 during standby.

According to the above-mentioned main purpose, the present invention provides a 7T dual-port static random access memory with high write speed, which mainly includes a memory array. The memory array is composed of a plurality of memory cells and a plurality of rows. The unit cell is composed of a plurality of memory cell units (1) and a plurality of control circuits (2). Each control unit is provided with a control circuit. (2); a plurality of pre-charging circuits (3), each row of memory cells is provided with a pre-charging circuit (3); a standby start-up circuit (4), the standby start-up circuit (4) promotes the fast entry of dual-port SRAM Standby mode to effectively improve the standby performance of the dual-port SRAM; multiple high-voltage level control circuits (5), each column of memory cells is provided with a high-voltage level control circuit (5) to read logic 0 The read speed is further improved; and a plurality of write drive circuits (6), one write drive circuit (6) is provided for each row of memory cells.

For ease of explanation, the 7T SRAM shown in Figure 6 consists of only one memory cell (1), one writing word line (WWL), and one writing bit line (WBL). ), A read word line (RWL), a read bit line (RBL), a control circuit (2), a precharge circuit (3), a standby start circuit (4), a high voltage The level control circuit (5) and a write driving circuit (6) are described as embodiments. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor) Crystal P12 and a second NMOS transistor M12), a third NMOS transistor (M13), a first reading transistor (M14), and a second reading transistor (M15), among which, The first inverter and the second inverter are connected by mutual coupling, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the second inverter The output of the phase inverter (node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the second inverter The output (node B) is used to store the inverted data of the SRAM cell.

The first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11) of the memory cell (1) is connected to a power supply voltage (V _DD ) and a first Between the low voltage node (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected between a high voltage node (VH) and a second low Between the voltage node (VL2), the source, gate and drain of the first reading transistor (M14) are connected to the drain and reading of the second reading transistor (M15), respectively. A word line (RWL) and the read bit line (RBL) are used, and a source, a gate, and a drain of the second read transistor (M15) are respectively connected to the second low-voltage node (VL2), the output of the second inverter (ie, node B) and the source of the first reading transistor (M14).

Please refer to FIG. 6 again. The control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a standby mode control signal (S), and An inverting standby mode control signal (/ S). The source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverting standby mode control signal (/ S) and the second low voltage node (VL2); the fifth The source, gate, and drain of the NMOS transistor (M22) are connected to the first low-voltage node (VL1), the standby mode control signal (S), and the second low-voltage node (VL2); the first The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) The gate, and drain are connected to the drain, the read control signal (RC), and the second low voltage node (VL2) of the eighth NMOS transistor (M25); the eighth NMOS transistor (M25) The source, gate, and drain are connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1), and the source of the seventh NMOS transistor (M24); the first The delay circuit (D1) is connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving The read control letter (RC), and the output is connected to the input of the first delay circuit (D1); the source, gate and drain of the ninth NMOS transistor (M26) are respectively connected to the ground voltage and the tenth NMOS The drain of the transistor (M27) and the first low voltage node (VL1); the source, gate, and drain of the tenth NMOS transistor (M27) are connected to the ground voltage and the write control signal, respectively. (WC) and the gate of the ninth NMOS transistor (M26); and the source, gate, and drain of the third PMOS transistor (P21) are connected to the inverting standby mode control signal (/ S ), The write control signal (WC) and the drain of the tenth NMOS transistor (M27). The inverting standby mode control signal (/ S) is obtained by the inverting standby mode control signal (S) through an inverter.

It is worth noting here that the drain of the third PMOS transistor (P21), the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together and A node (C) is formed. When the write control signal (WC) is at a logic low level, the voltage level of the node (C) is the logic voltage level of the inverted standby mode control signal (/ S), and When the write control signal (WC) is at a logic high level, the voltage level of the node (C) is the ground voltage, thereby stably completing the write operation (due to the voltage level of the node C during the write operation) Quasi-constant is the ground voltage).

The control circuit (2) is designed to control the voltage levels of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes. In the write mode, the unit cell is selected. The source voltage (that is, the first low-voltage node VL1) of the driving transistor (that is, the first NMOS transistor M11) that is closer to the bit line (WBL) for writing is set to be one higher than the ground voltage The predetermined voltage (i.e., the gate-source voltage V _{GS (M23) of} the sixth NMOS transistor (M23)) and the source voltage of another driving transistor (i.e., the second NMOS transistor M12) in the selected cell ( That is, the second low voltage node VL2) is set to a ground voltage in order to prevent the problem of writing logic 1 from being difficult.

In the first stage of the read mode, the source voltage (that is, the second lowest value) of the driving transistor (that is, the second NMOS transistor M12) that is closer to the read bit line (RBL) in the selected cell is selected. The voltage node VL2) is set to a voltage lower than the ground voltage. The second low-voltage node VL2, which is lower than the ground voltage, can effectively improve the reading speed. During the second stage of the reading mode, the crystal is selected. The source voltage of the driving transistor (ie, the second NMOS transistor M12) that is closer to the bit line (RBL) for reading in the cell is set back to the ground voltage in order to reduce unnecessary power consumption. The time interval between the second stage and the first stage is equal to that when the read control signal (RC) changes from a logic low level to a logic high level, and the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off. The time up to the eighth NMOS transistor (M25) can be adjusted by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1).

In the standby mode, the source voltages of the driving transistors in all memory cells are set to a predetermined voltage higher than the ground voltage in order to reduce the leakage current; while in the hold mode, the voltages in the memory cells are set to The source voltage of the driving transistor is set to the ground voltage in order to maintain the original holding characteristics. The detailed operating voltage levels are shown in Table 1 below.

The write control signal (WC) in Table 1 is an AND gate operation result of a write signal (W) and the word line (WL) signal. At this time, only the write signal (W ) Signal and the word line (WL) signal are at a logic high level, the write control signal (WC) is a logic high level; the read control signal (RC) is a read enable (Read Enable for short) RE) signal and the corresponding result of the word line (RWL) signal for reading. It is worth noting here that, for non-selected word lines and non-selected positioning element lines, the floating state is set, and the read control signal (RC) during the non-read mode is set to the acceleration. The level of the voltage (RGND) is read to prevent the leakage current of the seventh NMOS transistor (M24).

Please refer to Fig. 6. The precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P). The source and gate of the fourth PMOS transistor (P31) And the drain are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit line (RBL), in order to facilitate the precharge period, The precharge signal (P) is used to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V _DD ).

Please refer to FIG. 6 again, the standby start circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2), and the inverting standby Mode control signal (/ S). The source, gate, and drain of the fifth PMOS transistor (P41) are connected to the power supply voltage (V _DD ), the inverting standby mode control signal (/ S), and the eleventh NMOS transistor. The drain of (M41); the source, gate and drain of the eleventh NMOS transistor (M41) are connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) respectively And the drain of the fifth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/ S), and the output of the second delay circuit (D2) is Connected to the gate of the eleventh NMOS transistor (M41).

Please refer to FIG. 6 again, the high voltage level control circuit (5) is composed of a sixth PMOS transistor (P51), a seventh PMOS transistor (P52), a fourth inverter (I53), the The read control signal (RC) and a first high power supply voltage (V _DDH1 ). The source, gate and drain of the sixth PMOS transistor (P51) are connected to the power supply voltage ( V _DD ), the read control signal (RC) and the high voltage node (VH), the source, gate and drain of the seventh PMOS transistor (P52) are connected to the first high power supply voltage, respectively. (V _DDH1 ), the output of the fourth inverter (I53) and the high voltage node (VH), and the input of the fourth inverter (I53) is for receiving the read control signal (RC), and The output is connected to the gate of the seventh PMOS transistor (P52). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage Between the node (VH) and the second low voltage node (VL2).

Please refer to FIG. 6 again. The write driving circuit (6) is composed of an eighth PMOS transistor (P61), a ninth PMOS transistor (P62), a tenth PMOS transistor (P63), and a tenth A PMOS transistor (P64), a twelfth NMOS transistor (M61), a thirteenth NMOS transistor (M62), a fifth inverter (I63), an input data (Din), and a second It consists of a high power supply voltage (V _DDH2 ), where the source, gate, and drain of the eighth PMOS transistor (P61) are connected to the second high power supply voltage (V _DDH2 ), the input data ( Din) and the drain of the twelfth NMOS transistor (M61), and the source, gate, and drain of the ninth PMOS transistor (P62) are respectively connected to the second high power supply voltage (V _DDH2 ) The drain of the thirteenth NMOS transistor (M62) and the drain of the twelfth NMOS transistor (M61), and the source, gate and drain of the tenth PMOS transistor (P63) are connected respectively To the second highest power supply voltage (V _DDH2 ), the drain of the twelfth NMOS transistor (M61) and the drain of the thirteenth NMOS transistor (M62), and the eleventh PMOS transistor (P64 ) The source, gate and drain are connected separately The second high power supply voltage _(V DDH2), which fifth inverter (I63) and the output of the thirteenth NMOS transistor (the M62) of the drain, the twelfth NMOS transistor (M61) the source of The electrode, gate and drain are connected to the ground voltage, the input data (Din) and the drain of the eighth PMOS transistor (P61), and the source and gate of the thirteenth NMOS transistor (M62). The pole and the drain are respectively connected to the ground voltage, the output of the fifth inverter (I63) and the drain of the eleventh PMOS transistor (P64), and the input of the fifth inverter (I63) Is for receiving the input data (Din), and the output is connected to the gate of the eleventh PMOS transistor (P64) and the gate of the thirteenth NMOS transistor (M62), wherein the tenth PMOS The drain of the transistor (P63), the drain of the eleventh PMOS transistor (P64), and the drain of the thirteenth NMOS transistor (M62) are commonly connected to the write bit line (WBL) The writing bit line (WBL) is the level of the ground voltage when writing logic 0, and the level of the second high power supply voltage (V _DDH2 ) when writing logic 1. It is worth noting here that the voltage level of the second high power supply voltage (V _DDH2 ) is designed to be higher than the voltage level of the power supply voltage (V _DD ) to accelerate the speed of writing to logic one.

The working principle of the preferred embodiment of the present invention shown in FIG. 6 is as follows:

(I) write mode

Before the write operation starts, the write control signal (WC) is at a logic low level, so that the third PMOS transistor (P21) is turned on (ON), and the tenth NMOS transistor (M27) is turned off (OFF) Therefore, the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at the logic high level will turn on the ninth NMOS transistor (M26) and make The first low voltage node (VL1) is at a ground voltage.

During the write operation period, the write control signal (WC) is at a logic high level, so that the third PMOS transistor (P21) is turned off, the tenth NMOS transistor (M27) is turned on, and the third PMOS transistor is turned on. The drain of the transistor (P21) is at a logic low level. The drain of the third PMOS transistor (P21) at the logic low level will cause the ninth NMOS transistor (M26) to turn off and make the first low voltage The node (VL1) is equal to the gate-source voltage V _{GS (M26} ) of the sixth NMOS transistor (M23 ₎ , thereby effectively preventing the problem of writing logic 1 from being difficult. FIG. 7 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during a writing period.

The following describes how the writing operation of the preferred embodiment of the present invention shown in FIG. 7 is completed according to four writing states.

(1) Node A originally stored logic 0, but now wants to write logic 0: before the writing operation occurs (the writing word line WWL is the ground voltage), the first NMOS transistor (M11) is on ( ON). Since the first NMOS transistor (M11) is ON, the writing word line (WWL) changes from Low (ground voltage) to High (power supply voltage V _DD ) when a writing operation is started. When the voltage of the writing word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13) (that is, the access transistor), the third NMOS transistor (M13) transitions from OFF. In order to be turned on, the write bit line (WBL) is grounded at this time, so the node A will be discharged, and a logic 0 write operation is completed until the write cycle ends.

(2) Node A originally stored logic 0, but now wants to write logic 1: before the writing operation occurs (the writing word line WWL is the ground voltage), the first NMOS transistor (M11) is on ( ON). It is worth noting here that because the first NMOS transistor (M11) is ON, when the writing operation starts, the writing word line (WWL) changes from Low (ground voltage) to High (the power supply Voltage V _DD ), the voltage of the node A will follow the writing word line (WWL) voltage slightly due to the parasitic capacitance coupling effect. When the voltage of the word line for writing (WWL) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. Because the write bit line (WBL) is the voltage level of the second high power supply voltage (V _DDH2 ), and because the first NMOS transistor (M11) is still ON and the node B is still at voltage The level is the initial state close to the voltage level of the power supply voltage (V _DD ), so the first PMOS transistor (P11) is still OFF, and the initial instantaneous voltage (V) written by the node A _AWI ) satisfies equation (3): V _AWI = V _DDH2 × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 )> V _TM12 (3) where V _AWI represents the initial moment of node A's writing Voltage, R _M13 represents the on-resistance of the third NMOS transistor (M13), R _M11 represents the on-resistance of the first NMOS transistor (M11), R _M23 represents the on-resistance of the sixth NMOS transistor (M23), V _DDH2 and V _TM12 represent the second high power supply voltage (V _DDH2 ) and the threshold voltage of the second NMOS transistor (M12), respectively. Because the voltage level of the second high power supply voltage (V _DDH2 ) is designed to be higher than the voltage level of the power supply voltage (V _DD ), and a voltage equal to the voltage level at the first low voltage node (VL1) is provided. The voltage level of the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23), so the voltage level of the node A can be easily set to be higher than the conventional 5T static random access memory of FIG. 4 The voltage level of the node A of the bulk cell is much higher. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), so that the node B is discharged to a lower voltage level. The lower voltage level of the node B will make the The on-resistance (R _M11 ) of the first NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) will obtain a higher voltage level at the node A Standard, the higher voltage level of the node A will pass through the second inverter (consisting of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B presents a lower voltage level , The lower voltage level of the node B will pass through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level, According to this cycle, the node A can be charged to the power supply voltage (V _DD ), and the writing operation of the logic 1 is completed.

It is worth noting here that the first low-voltage node VL1 originally stores logic 0 at node A, and during the writing of logic 1, it has a gate-source voltage V _GS equal to the sixth NMOS transistor (M23). _(M23) , and after the logic 1 is written, it will have a ground voltage level due to discharge through the ninth NMOS transistor (M26).

(Three) node A originally stores logic 1, but now wants to write logic 1: before the writing operation occurs (the writing word line WWL is the ground voltage), the first PMOS transistor (P11) is on ( ON). When the writing word line (WWL) changes from Low (ground voltage) to High (the power supply voltage V _DD ), since the node A is the voltage level of the power supply voltage (V _DD ), and the write The bit line (WBL) is used as the voltage level of the second high power supply voltage (V _DDH2 ), so the third NMOS transistor (M13) will remain in the OFF state. The PMOS transistor (P11) is still ON, so the voltage of the node A will be maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stored logic 1, but now wants to write logic 0: before the writing operation occurs (the writing word line WWL is the ground voltage), the first PMOS transistor (P11) is on ( ON). When the writing word line (WWL) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the writing word line (WWL) is greater than the third NMOS transistor (M13) ), The third NMOS transistor (M13) changes from OFF to ON. At this time, because the write bit line (WBL) is Low (ground voltage), The node A and the first low voltage node (VL1) are discharged to complete a logic 0 writing operation until the writing cycle ends.

The HSPICE transient analysis simulation result during the write operation of the preferred embodiment of the invention shown in FIG. 7 is shown in FIG. 8, which is simulated using TSMC 90 nm CMOS process parameters. It can be confirmed that the 7T dual-port static random access memory proposed by the present invention can increase the voltage level of the first low voltage node (VL1) during the writing period and cooperate with the bit line for writing ( The write driving circuit (6) whose WBL) voltage level is raised higher than the power supply voltage (V _DD ) can effectively prevent the writing logic 1 from being difficult, and can also effectively improve the writing speed.

(II) read mode

Before the read operation starts, the read control signal (RC), write control signal (WC), and the standby mode control signal (S) are all logic low levels, so that the third PMOS transistor (P21) is turned on, And the tenth NMOS transistor (M27) is turned off, so the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) at a logic high level will be turned on. Nine NMOS transistors (M26), and the first low voltage node (VL1) is grounded. On the other hand, because the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off, and the eighth NMOS transistor (M25) is turned on.

It is worth noting here that during the pre-charging period before the read operation starts, the pre-charging signal (P) is at a logic low level, thereby pre-charging the corresponding read bit line (RBL) to The level of the power supply voltage (V _DD ), but because the operating voltage of the process technology below 20 nanometers will fall below 1 volt, the reading speed will be reduced and the specification cannot be met. Therefore, the present invention proposes two Phased read control is used to increase read speed and meet specifications while avoiding unnecessary power loss.

The preferred embodiment of the present invention shown in FIG. 6 uses a two-stage read control to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the read operation, the read control The signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the second low voltage node (VL2) is approximately grounded. The accelerated read voltage (RGND) whose voltage is low, and the accelerated read voltage (RGND) which is lower than the ground voltage can effectively improve the reading speed.

In the second phase of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still on, but at this time the eighth NMOS transistor ( M25) is turned off, so the second low voltage node (VL2) will be grounded via the fourth NMOS transistor (M21) that is turned on (because the inverting standby mode control signal (/ S) is logic during read operation) High level), which can effectively reduce unnecessary power consumption. It is worth noting here that the time interval between the second stage and the first stage of the read operation is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level. The gate voltage of the eight NMOS transistor (M25) is enough time to turn off the eighth NMOS transistor (M25), and its value can be determined by the falling delay time of the third inverter (INV) and the first delay circuit. (D1) Adjust the delay time provided. Furthermore, the fourth NMOS transistor (M21) is in a conducting state regardless of whether it is the first stage or the second stage of the read operation (because the inverted standby mode control signal (/ S) is logic during the read operation) High level). FIG. 9 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during reading.

The following describes how the preferred embodiment of the present invention shown in FIG. 9 uses the control circuit (2) and the high-voltage level control circuit (5) to improve the reading speed while avoiding uselessness according to two read states. Power consumption.

(1) Read logic 1 (node A stores logic 1): before the read operation occurs, the first NMOS transistor (M11) is OFF and the second NMOS transistor (M12) is ON ), The node A and the node B are the power supply voltage (V _DD ) and the ground voltage, respectively, and the read bit line (RBL) is equal to the power supply voltage (3) due to the precharge circuit (3) V _DD ). During the reading period, since the node B is at the ground voltage, the second reading transistor (M15) is turned off, thereby effectively maintaining the reading bit line (RBL) as the power supply voltage ( V _DD ) until the end of the read cycle, the read logic 1 operation is successfully completed. It is worth noting here that in the first stage of the read operation, the initial instantaneous voltage (V _RVL2I ) of the second low voltage node (VL2) when reading logic 1 must satisfy equation (4): V _RVL2I = RGND × R _M21 / (R _M21 + R _M24 + R _M25 )>-V _TM12 (4) to effectively prevent half-selected cell interference during reading, where V _RVL2I represents the second low voltage node ( VL2) read the initial instantaneous voltage when reading logic 1, RGND represents the accelerated read voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), and R _M24 represents the seventh NMOS transistor (M24) ), R _M25 represents the on resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12); and in the second stage of the read operation, The voltage (V _RVL2 ) of the second low-voltage node (VL2) can be represented by equation (5). V _RVL2 = ground voltage (5). This can effectively reduce unnecessary power consumption. Furthermore, in order to effectively reduce the half-selected cell interference and effectively reduce the leakage current during reading, the accelerated reading voltage (RGND), which is lower than the ground voltage, must be set to the value of the second low voltage node (VL2). The voltage level is lower than the threshold voltage (V _TM12 ) of the second NMOS transistor (M12), and the accelerated read voltage (RGND), which is lower than the ground voltage, can be set more strictly than the second NMOS transistor. The threshold voltage (V _TN12 ) of the crystal (M12), that is, | RGND | <V _TM12 (6), where | RGND | and V _TM12 respectively represent the absolute value of the accelerated read voltage and the second NMOS transistor (M12 ).

Furthermore, the first high power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the threshold voltage of the second PMOS transistor (P12). The sum of the absolute values | V _TP12 |, that is, V _DD <V _DDH1 <V _DD + | V _TP12 | (7) where | V _TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12).

(2) Read logic 0 (node A stores logic 0): Before the read operation occurs, the first NMOS transistor (M11) is on and the second NMOS transistor (M12) is off (OFF) ), The node A and the node B are the ground voltage and the power supply voltage (V _DD ), and the read bit line (RBL) is equal to the power supply voltage (3) due to the precharge circuit (3). V _DD ). During the reading period, since the node B is the first high power supply voltage (V _DDH1 ), and the second low voltage node (VL2) is a voltage lower than the ground voltage, because the first high power supply voltage (V _DDH1 ) is set to be higher than the power supply voltage (V _DD ). Therefore, the reading speed can be increased by increasing the conduction degree of the second reading transistor (M15). This second low voltage node (VL2) further improves the read speed.

(III) Standby mode

First, explain how the standby startup circuit (4) in Figure 6 promotes the dual-port SRAM to enter the standby mode quickly, so as to effectively improve the standby performance of the SRAM: first, before entering the standby mode, the inverted standby mode control signal (/ S) Is logic High. The inverted standby mode control signal (/ S) of the logic High turns off the fifth PMOS transistor (P41) and turns on the eleventh NMOS transistor (M41). After entering the standby mode, the inverting standby mode control signal (/ S) is logic Low, and the inverting standby mode control signal (/ S) of the logic Low causes the fifth PMOS transistor (P41) to be turned on (ON). , But in the initial period of the standby mode (the initial period is equal to the inversion standby mode control signal (/ S) transition from logic High to logic Low, counting to the gate voltage of the eleventh NMOS transistor (M41) The time sufficient to turn off the eleventh NMOS transistor (M41) can be adjusted by a delay time provided by the second delay circuit (D2)), the eleventh NMOS transistor (M41) is still on (ON), so that the first low-voltage node (VL1) can be quickly charged to the sixth NMOS transistor The voltage level of the threshold voltage (V _TM23 ) of the body (M23), that is, the 7T dual-port SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the eleventh NMOS transistor (M41) is turned off and stops supplying current.

Please refer to FIG. 6. In the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/ S) is a logic low level. The logic low level is the inverted standby The mode control signal (/ S) can turn off the fourth NMOS transistor (M21) in the control circuit (2), and the standby mode control signal (S) at the logic high level makes the fifth The NMOS transistor (M22) is turned on. At this time, the fifth NMOS transistor (M22) is used as an equalizer. Therefore, the fifth NMOS transistor (M22) can be turned on. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are all equal to the voltage levels of the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V _TM23 ). FIG. 10 is a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 6 during the standby period.

Next, how to reduce the leakage current in the standby mode of the present invention will be described. Please refer to FIG. 10, which describes the respective leakage currents (I ₁ ) generated when the embodiment of the present invention is in the standby mode. , I ₂ , I ₃ , I ₄ , where it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is logic Low (It is worth noting here that due to the first low voltage in the standby mode The voltage levels of the node (VL1) and the second low voltage node (VL2) are maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so node A is a logic low voltage The level is also maintained at the voltage level of the V _TM23 ), and the output of the second inverter (ie, node B) is logic High (power supply voltage V _DD ). Please refer to the conventional 8T dual-port SRAM in FIG. 5 and the embodiment of the present invention in FIG. 10 to illustrate the leakage current of the 7T dual-port static random access memory proposed in the present invention and the conventional 8T dual-port SRAM in FIG. 5. In terms of comparison, first, regarding the leakage current I ₁ flowing through the third NMOS transistor (M13), since the voltage level of the node A is maintained at the voltage level of the V _TM23 in the standby mode of the present invention, and it is assumed that The writing word line (WWL) is set to the ground voltage in the standby mode, and the writing bit line (WBL) is set to the power supply voltage (V _DD ) in the standby mode. a third NMOS transistor (M13) the gate-source voltage (V _GS) is negative, on the other hand, when a conventional stand-by mode of FIG. 5 8T two-port SRAM of the NMOS transistor (M3) of the gate-source voltage (V _GS ) Is equal to 0. According to the Gate Induced Drain Leakage (GIDL) effect or the results of Figures 3 (A) and 3 (B) of US6865119 patent case on March 8, 2005, we can know that for NMOS For transistors, the sub-critical current when the gate-source voltage is -0.1 volts is about 1% of the sub-critical current when the gate-source voltage is 0 volts. Therefore, the leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention caused by the GIDL effect is much smaller than the NMOS transistor (M3) of the conventional 8T dual-port SRAM in FIG. 5; In the present invention, the drain-source voltage (V _DS ) of the third NMOS transistor (M13) is the power supply voltage (V _DD ) _minus the voltage level of the V _TM23 , in contrast to the traditional 8T dual port in FIG. 5 The drain-source voltage (V _DS ) of the NMOS transistor (M3) of the SRAM is equal to the power supply voltage (V _DD ). According to the drain-induced barrier lowering (DIBL) effect of the drain, due to the DIBL effect The leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention is also smaller than that of the conventional 8T dual-port SRAM NMOS transistor (M3) of FIG. 5; as a result, the third NMOS transistor (M3) of the present invention flows through the third The leakage current I _{1 of the} NMOS transistor (M13) is much smaller than the NMOS transistor (M3) of the conventional 8T dual-port SRAM in FIG. 5.

Then regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), since the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) in the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V _TM23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V _DD ) The voltage level of the V _TM23 is deducted. In contrast, the source-drain voltage (V _SD ) of the PMOS transistor (P1) of the traditional 8T dual-port SRAM in Figure 5 is equal to the power supply voltage (V _DD ). DIBL effect, so the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the PMOS transistor (P1) of the prior art in FIG. 1b.

Then, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V _TM23 in the standby mode, the node A The voltage level of V _TM23 is also maintained, and the voltage level of node B is equal to the power supply voltage (V _DD ) and the substrate of the second NMOS transistor (M12) is ground voltage. The base-source voltage (V _BS ) of the second NMOS transistor (M12) is negative, and the drain-source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V _DD ) The V _TM23 voltage level is deducted. In contrast, the base-source voltage (V _BS ) of the NMOS transistor (M2) of the traditional 8T dual-port SRAM in FIG. 5 is equal to 0, and the NMOS transistor (M2) The drain-source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and DIBL effect, it can be known that the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than Figure 5 shows the NMOS transistor (M2) of a conventional 8T dual-port SRAM.

Finally, regarding the leakage current I ₄ flowing through the first reading transistor (M14), the present invention is different from the conventional 8T dual-port SRAM in FIG. 5 in the reading method, and the reading in the standby mode of the present invention The bit line (RBL) can be set to ground voltage. In order to prevent the voltage level of node B from dropping, the conventional 8T dual-port SRAM in Figure 5 uses read bit line pairs (RBL, RBLB) in standby mode. Since the power supply voltage is set, the leakage current I ₄ flowing through the first reading transistor (M14) cannot be compared. Based on the above analysis, it can be seen that the 7T dual-port static random access memory proposed by the present invention has a lower leakage current than the conventional 8T dual-port SRAM of FIG. 5.

(IV) Retension mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to the ground voltage, the working principle is the same as that of a conventional dual-port SRAM cell with a single bit line. No more repetition.

    [Effect of Invention]    

The 7T dual-port static random access memory with high write speed provided by the present invention has the following effects:

(1) High read speed and avoid unnecessary power consumption: The 7T static random access memory system with high write speed proposed by the present invention uses a two-stage read operation. Setting the second low voltage node (VL2) to a voltage lower than the ground voltage, and setting the node B to the first high power supply voltage (V _DDH1 ) higher than the power supply voltage (V _DD ), Therefore, a dual mechanism can be used to effectively improve the reading speed, and in the second stage of reading logic 0, the second low voltage node (VL2) is set back to the ground voltage in order to reduce unnecessary power consumption;

(2) Quickly enter standby mode: As the 7T static random access memory with high write speed proposed by the present invention is provided with a standby startup circuit (4) to prompt the SRAM to enter the standby mode quickly, and thereby seek to improve 7T Standby performance of dual-port SRAM;

(3) Improve the speed of writing logic 1 and avoid the problem of writing logic 1. The present invention can use the plurality of control circuits (2) and the plurality of write driving circuits (6) during the writing operation. ) In order to effectively prevent the difficulty of writing logic 1, it also increases the speed of writing logic 1;

(4) Low standby current: As the 7T static random access memory with high writing speed proposed by the present invention is in standby mode, the fifth NMOS transistor (M22) can be turned on to make the The voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the threshold voltage of the sixth NMOS transistor (M23) Therefore, the 7T dual-port static random access memory proposed by the present invention also has the effect of low standby current;

(5) Effectively reduce half-selected cell interference: The 7T static random access memory with high write speed proposed by the present invention uses a separate read / write path, and the read path is designed to change the first And a second reading transistor (M14 and M15) are connected in series between the reading bit line (RBL) and the second low voltage node (VL2), and the inverting storage node (B) is connected To the gate of the second reading transistor (M15), half-selected cell disturbance can be effectively reduced, wherein the half-selected cell refers to the word line ( RWL) memory cell selected but not selected by the read bit line (RBL).

(6) Low transistor count: For a SRAM array with 1024 columns and 1024 rows, the traditional 8T dual-port SRAM array shown in Figure 5 requires a total of 1024 × 1024 × 8 = 8,388,608 transistors. The 7T proposed by the present invention The dual-port static random access memory only requires 1024 × 1024 × 7 + 1024 × 27 + 6 = 7,367,686 transistors, which reduces the number of transistors by 12.2%.

(7) Complete writing operation with high stability: When the writing control signal (WC) is at a logic high level, the voltage level of the node (C) is the ground voltage, thereby completing writing with high stability Input operation (because the voltage level of the node C is constant at the ground voltage during the write operation).

Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or detail may be changed without departing from the spirit and scope of the present invention. Therefore, all changes in the related technical scope are included in the scope of patent application of the present invention.

Claims (10)

A 7T dual-port static random access memory with high write speed includes: a memory array composed of a plurality of rows of memory cell units and a plurality of rows of memory unit cells, each row of memory The unit cell and each row of memory unit cells each include a plurality of memory unit cells (1); a plurality of control circuits (2); each column of memory unit cells is provided with a control circuit (2); a plurality of precharge circuits ( 3), each row of memory cell is provided with a precharge circuit (3); a standby start circuit (4), the standby start circuit (4) prompts the 7T static random access memory to quickly enter the standby mode to effectively Improve the standby performance of the 7T static random access memory; a plurality of high-voltage level control circuits (5), each column of memory cells is provided with a high-voltage level control circuit (5) to read logic 0 Improve the read speed; and a plurality of write drive circuits (6), each row of memory cells is provided with a write drive circuit (6) to increase the write speed when logic 1 is written; wherein each memory The unit cell (1) further includes: a first inverter A first PMOS transistor (P11) and a first NMOS transistor (M11) is composed of the first inverter is connected between a system power supply voltage (V _DD) and a first node of the low voltage (VL1) ; A second inverter is composed of a second PMOS transistor (P12) and a second NMOS transistor (M12), the second inverter is connected to a high voltage node (VH) and a Between the second low voltage node (VL2); a storage node (A) formed by the output terminal of the first inverter; an inverting storage node (B) formed by the second inverter Formed at the output end; a third NMOS transistor (M13) is connected between the storage node (A) and a corresponding write bit line (WBL), and the gate is connected to a corresponding write Word line (WWL); a first reading transistor (M14), the source, gate and drain of the first reading transistor (M14) are connected to a second reading transistor The drain of the transistor (M15), a word line for reading (RWL) and a bit line for reading (RBL); and the second reading transistor (M15), the second reading The source, gate, and drain of the transistor (M15) are connected to the first Two low voltage nodes (VL2), the inverting storage node (B) and the source of the first reading transistor (M14); wherein the first inverter and the second inverter interact with each other; The coupling connection, that is, the output terminal of the first inverter (that is, the storage node A) is connected to the input terminal of the second inverter, and the output terminal of the second inverter (that is, the inverted storage Node B) is connected to the input terminal of the first inverter; and each control circuit (2) further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal ( WC), a standby mode control signal (S), and an inverted standby mode control signal (/ S); wherein the source, gate, and drain of the fourth NMOS transistor (M21) are connected to a ground, respectively. Voltage, this inverting standby mode control (/ S) and the second low voltage node (VL2); the source, gate, and drain of the fifth NMOS transistor (M22) are connected to the first low voltage node (VL1), the standby The mode control signal (S) and the second low-voltage node (VL2); the source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first A low voltage node (VL1); the source, gate and drain of the seventh NMOS transistor (M24) are respectively connected to the drain of the eighth NMOS transistor (M25) and the read control signal (RC ) And the second low voltage node (VL2); the source, gate and drain of the eighth NMOS transistor (M25) are connected to the accelerated read voltage (RGND) and the first delay circuit (D1 ) And the source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected between the output of the third inverter (INV) and the eighth NMOS transistor (M25) Between the gates; the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the ninth NMOS circuit The source and gate of the crystal (M26) The drain is connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27). The pole system is respectively connected to the ground voltage, the write control signal (WC) and the gate of the ninth NMOS transistor (M26); the source, gate and drain of the third PMOS transistor (P21) Respectively connected to the drain of the inverting standby mode control signal (/ S), the write control signal (WC) and the tenth NMOS transistor (M27); wherein the drain of the third PMOS transistor (P21) Electrode, the drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C). When the write control signal (WC) is logic At the low level, the voltage level of the node (C) is the logic voltage level of the inverted standby mode control signal (/ S), and when the write control signal (WC) is at the logic high level, the node (C) The voltage level of) is the ground voltage, thereby completing the writing operation stably (because the voltage level of the node C is constant to the ground voltage during the writing operation); The read control signal (RC) during the fetch mode is set to the level of the accelerated read voltage (RGND) to prevent leakage current of the seventh NMOS transistor (M24) during non-read mode; The standby startup circuit (4) is designed to quickly charge the parasitic capacitance at the first low voltage node (VL1) to the threshold voltage of the sixth NMOS transistor (M23) during an initial period of entering the standby mode. (V _TM23 ) voltage level; finally, each high voltage level control circuit (5) further includes: a sixth PMOS transistor (P51), a seventh PMOS transistor (P52), and a fourth inverter (I53), the read control signal (RC) and a first high power supply voltage (V _DDH1 ), wherein the source, gate and drain of the sixth PMOS transistor (P51) are respectively connected to the The power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH), the source, gate and drain of the seventh PMOS transistor (P52) are connected to the first a high power supply voltage _(V DDH1), the fourth inverter (I53) and the output of the fourth inverter input system (I53) for the reception of the read node to the high voltage (VH), A control signal (RC), and the output is connected to the seventh PMOS transistor (P52) of the gate.     The 7T dual-port static random access memory with high write speed as described in item 1 of the patent application scope, wherein the first NMOS transistor (M11) and the first NMOS transistor (M11) in each memory cell (1) and The second NMOS transistor (M12) has the same channel width-to-length ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also have the same channel width-to-length ratio.     The 7T dual-port static random access memory with high write speed as described in item 2 of the scope of patent application, wherein each precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a pre-charge circuit. The charging signal (P) is composed of the source, gate and drain of the fourth PMOS transistor (P31) connected to the power supply voltage (V _DD ), the precharge signal (P) and the The corresponding read bit line (RBL) is used to precharge the corresponding read bit line (RBL) to a pre-charge signal (P) at a logic low level during a precharge period. The level of the power supply voltage (V _DD ). The 7T dual-port static random access memory with high write speed as described in item 3 of the patent application scope, wherein the standby start circuit (4) is composed of a fifth PMOS transistor (P41), a tenth An NMOS transistor (M41), a second delay circuit (D2), and the inverting standby mode control signal (/ S); wherein the source, gate, and sink of the fifth PMOS transistor (P41) The poles are respectively connected to the power supply voltage (V _DD ), the inverting standby mode control signal (/ S) and the drain of the eleventh NMOS transistor (M41); the eleventh NMOS transistor (M41) The source, gate, and drain are connected to the first low-voltage node (VL1), the output of the second delay circuit (D2), and the drain of the fifth PMOS transistor (P41); the second An input of the delay circuit (D2) is connected to the inverted standby mode control signal (/ S), and an output of the second delay circuit (D2) is connected to the gate of the eleventh NMOS transistor (M41). The 7T dual-port static random access memory with high writing speed as described in item 4 of the scope of patent application, wherein each write driving circuit (6) is composed of an eighth PMOS transistor (P61) , A ninth PMOS transistor (P62), a tenth PMOS transistor (P63), an eleventh PMOS transistor (P64), a twelfth NMOS transistor (M61), a thirteenth NMOS transistor (M62), a fifth inverter (I63), an input data (Din), and a second high power supply voltage (V _DDH2 ), in which the source and gate of the eighth PMOS transistor (P61) The pole and the drain are respectively connected to the second high power supply voltage (V _DDH2 ), the input data (Din) and the drain of the twelfth NMOS transistor (M61), and the ninth PMOS transistor (P62) The source, gate and drain are connected to the second high power supply voltage (V _DDH2 ), the drain of the thirteenth NMOS transistor (M62) and the twelfth NMOS transistor (M61). Drain, the source, gate and drain of the tenth PMOS transistor (P63) are connected to the second high power supply voltage (V _DDH2 ) and the drain of the twelfth NMOS transistor (M61) And the thirteenth NMOS transistor (M62), the source, gate and drain of the eleventh PMOS transistor (P64) are connected to the second high power supply voltage (V _DDH2 ) and the fifth inverter (I63 ) And the drain of the thirteenth NMOS transistor (M62), and the source, gate, and drain of the twelfth NMOS transistor (M61) are connected to the ground voltage, the input data (Din ) And the drain of the eighth PMOS transistor (P61), and the source, gate, and drain of the thirteenth NMOS transistor (M62) are connected to the ground voltage and the fifth inverter (I63 ), The output and the drain of the eleventh PMOS transistor (P64), and the input of the fifth inverter (I63) is for receiving the input data (Din), and the output is connected to the tenth A gate of a PMOS transistor (P64) and a gate of the thirteenth NMOS transistor (M62), wherein the drain of the tenth PMOS transistor (P63), the eleventh PMOS transistor (P64) The drain electrode of the thirteenth NMOS transistor (M62) is connected to the corresponding writing bit line (WBL), and the corresponding writing bit line (WBL) is in the writing logic. 0 is the level of the ground voltage, and at Logic 1 was the second high power supply voltage _(V DDH2) of the level, wherein the second high power supply voltage _(V DDH2) the voltage level of the system designed to be higher than the power supply voltage (V _DD ) Voltage level to speed up the writing of logic 1. The 7T dual-port static random access memory with high write speed as described in item 5 of the scope of the patent application, wherein the storage node (A) originally stores logic 0 and is initially written to logic 1 The instantaneous voltage (V _AWI ) satisfies the following equation: V _AW1 = V _DDH2 × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 )> V _TM12 where V _AWI indicates that the storage node (A) is stored by storage The initial instantaneous voltage for writing logic 0 and writing logic 1, R _M11 , R _M13 and R _M23 represent the first NMOS transistor (M11), the third NMOS transistor (M13) and the sixth NMOS transistor, respectively. (M23), and V _DDH2 and V _TM12 represent the second high power supply voltage (V _DDH2 ) and the threshold voltage of the second NMOS transistor (M12), respectively.     The 7T dual-port static random access memory with high write speed, as described in item 6 of the scope of the patent application, wherein the read operation can be further subdivided into two phases, in the first phase of one of the read operations The second low voltage node (VL2) is set to a voltage lower than the ground voltage to effectively improve the reading speed, and in a second stage of the reading operation, the second low voltage is The node (VL2) is set back to the ground voltage in order to reduce unnecessary power consumption. The time interval between the second phase and the first phase of the read operation is equal to the logic low of the read control signal (RC). The time from the quasi-transition to the logic high level, until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), can be achieved by the third inverter (INV) A falling delay time is dynamically adjusted with a delay time provided by the first delay circuit (D1).     The 7T dual-port static random access memory with high write speed as described in item 7 of the scope of the patent application, wherein in the first stage of the read operation, the second low-voltage node (VL2) is read The initial instant voltage (V _RVL2I ) when reading logic 1 must satisfy the following equation: V _RVL2I = RGND × R _M21 / (R _M21 + R _M24 + R _M25 )>-V _TM12 to effectively prevent half of the reading time Cell interference is selected, where V _RVL2I represents the initial instant voltage of the second low voltage node (VL2) when reading logic 1, RGND represents the accelerated read voltage, and R _M21 represents the fourth NMOS transistor (M21), R _M24 represents the on resistance of the seventh NMOS transistor (M24), R _M25 represents the on resistance of the eighth NMOS transistor (M25), and V _TM12 represents the second NMOS transistor ( M12). The 7T dual-port static random access memory with high write speed as described in item 1 of the scope of patent application, wherein the accelerated read voltage (RGND) in each control circuit (2) is set to low The threshold voltage (V _TM12 ) of the second NMOS transistor (M12) in each memory cell (1), and the first high power supply voltage (V _DDH1 ) is set higher than the power supply Voltage (V _DD ) but lower than the absolute value of the power supply voltage (V _DD ) and the threshold voltage of the second PMOS transistor (P12) | V _TP12 |, which is V _DD <V _DDH1 <V _DD + ｜ V _TP12 |. The 7T dual-port static random access memory with high write speed as described in item 1 of the scope of patent application, wherein the second initial low-voltage node (VL2) reads the initial instantaneous voltage when reading logic 1 ( V _RVL2I ) must satisfy the following equation: V _RVL2I = RGND × R _M21 / (R _M21 + R _M24 + R _M25 )>-V _TM12 to effectively prevent half-selected cell interference when reading logic 1, where, V _RVL2I represents the initial instant voltage of the second low voltage node (VL2) when reading logic 1, RGND represents the accelerated read voltage, R _M21 represents the on-resistance of the fourth NMOS transistor (M21), R _M24 represents the on-resistance of the seventh NMOS transistor (M24), R _M25 represents the on-resistance of the eighth NMOS transistor (M25), and V _TM12 represents the threshold voltage of the second NMOS transistor (M12).