TWI573137B - 7t dual port static random access memory - Google Patents

Description

7T double-click static random access memory

The invention relates to a 7T dual port static random access memory (SRAM), in particular to an effective improvement of the standby performance of the 7T dual-SRAM SRAM, and can effectively improve the reading speed and It effectively reduces the leakage current and can solve the 7T dual-SRAM SRAM which is difficult to write to the logic 1 with a single bit line.

As is shown in FIG. 1a, the static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of memory blocks (memory block, MB _1). , MB _{2 ,} etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL _{2 ,} etc.), each word line corresponding to a plurality of columns of memory One of the body cells; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _{m ,} etc.), each bit line pair corresponding to a plurality of rows of memory cells One row, and each bit line pair is composed of one bit line (BL ₁ ... BL _m ) and one complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b is a schematic diagram of a 6T單埠 SRAM cell, in which PMOS transistors (P1) and (P2) are called load transistors, NMOS transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is word line, and BL And BLB are a bit line and a complementary bit line, respectively, since the 單埠SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) Another driving transistor is turned on, and the initial instantaneous voltage (V _AR ) of the node A must satisfy the equation (1): V _AR = V _DD × (R _M1 ) / (R _M1 + R _M3 ) < V _TM2 (1) to prevent half-selected cell disturbance when reading, wherein V _AR represents the initial instantaneous voltage of the reading of node A, and R _M1 and R _M3 respectively represent the NMOS transistor (M1) And the on-resistance of the NMOS transistor (M3), and V _DD and V _TM2 respectively represent the power supply voltage and the threshold voltage of the NMOS transistor (M2), which results in driving the transistor The current drive capability ratio between the body and the access transistor (ie, the cell ratio) is usually set between 2.2 and 3.5 (refer to US Patent No. US76060B2, No. 2, No. 8-10, October 20, 1998). Row).

The HSPICE transient analysis results of the 6T單埠 SRAM cell shown in Figure 1b during the write operation, as shown in Figure 2, are simulated using the TSMC 90 nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T 單埠 SRAM cell with only a single bit line, compared to the 6T 單埠 SRAM cell of Figure 1b. The random access memory cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T單埠 SRAM cell does not change the PMOS transistors P1 and P2. In the case of the channel width to length ratio of the NMOS transistors M1, M2, and M3, there is a problem that writing logic 1 is quite difficult. Considering that the node A on the left side of the memory cell originally stores a logic 0, since the charge of the node A is transmitted only from the bit line (BL) alone, the logic 0 previously written in the node A is overwritten with a logic 1 write. The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _M1 ) / (R _M1 + R _M3 ) (2) where V _AW represents the initial instantaneous voltage of the write of node A, R _M1 And R _M3 respectively indicate the on-resistances of the NMOS transistor (M1) and the NMOS transistor (M3). Comparing Equation (1) with Equation (2), the initial transient voltage (V _AW ) is smaller than the NMOS transistor (M2). The threshold voltage (V _TM2 ), and thus the operation of writing logic 1 cannot be completed. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is simulated using the TSMC 90 nm CMOS process parameters. The simulation results confirm that it is quite difficult to write logic 1 in a 5T SRAM cell with a single bit line.

Next, we discuss the static random access memory (SRAM) and double-ended architecture. The 6T static random access memory (SRAM) cell in Figure 1b is the static random access memory (SRAM) crystal. One example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, both reading and writing are achieved through the same pair of bit lines, so that only reading or reading can be performed at the same time. The action of writing, therefore, when designing a dual-static SRAM with simultaneous read and write capabilities, it is necessary to add two access transistors and another pair of bit lines (please refer to Figure 5). a circuit in which WBL and WBLB are write bit line pairs, RBL and RBLB are read bit line pairs, WWL is a write word line, and RWL is a read word line), which makes the memory crystal The area of the cell is greatly increased if we can simplify the structure of the memory cell, making a bit The line is responsible for the read action, and the other bit line is responsible for the write operation. When designing the dual-squat static random access memory, the memory cell does not need to add two transistors and a pair of bit lines. Thus, the area of the memory cell is much reduced. The conventional double-squeezing SRAM cell does not use this method because it is quite difficult to write logic 1 as described above.

So far, many techniques have been proposed for a 7T double-squat static random access memory cell with a single bit line, for example, "Double-band static random memory" proposed in Patent Document 1 (TWI441178, June 11, 103) "Responsive memory", Patent Document 2 (TWI441179, June 11, 103), "Double-band SRAM with discharge path", and Patent Document 3 (No. 8717807 B2, May 6, 103) "Independently-controlled-gate SRAM", "7T Double SRAM" proposed in Patent Document 4 (TWI433152, April 1, 103), and Patent Document 5 (TWI425509, February 1, 103) "Double-band SRAM with discharge path", Patent Document 6 (TWI 423257, January 11, 103), "Double-埠 SRAM for reducing power supply voltage during write operation", Patent Document 7 ( "Tweed SRAM", which raises the voltage level of the write word line during the write operation, as proposed in TWI423258, January 11, 103, Patent Document 8 (June 21, 102) "SEVEN TRANSISTOR SRAM CELL" by TWI399748), Patent Document 9 (US20090161410 A1, June 22, 1998) "SRAM cell with independent static noise margin, trip voltage, and read current optimization" and Patent Document 11 (US Pat. No. 6,675, 151, June 5, 1997) "Ultra high-speed DDP-SRAM cache" proposed by B2), although these patents can effectively solve the problem of writing logic 1 difficult, but since these patents do not consider the operating voltage of 45 nm will be reduced to 1.1. At ±30%, the reading speed is reduced, so there is still room for improvement.

In view of this, the main object of the present invention is to provide a 7T double-pin static random access memory capable of effectively improving the reading speed by a dual mechanism of a control circuit and a high voltage level control circuit.

A secondary object of the present invention is to provide a 7T double-pin static random access memory capable of improving read speed while avoiding unnecessary power consumption while maintaining read speed by two stages.

A further object of the present invention is to provide a 7T dual-chirpson static random access memory capable of effectively causing the SRAM to quickly enter the standby mode by the standby enable circuit, thereby effectively improving the standby performance of the SRAM.

Another object of the present invention is to provide a 7T double-pin static random access memory. The control circuit can effectively reduce the leakage current in the standby mode.

The present invention provides a 7T dual-static static random access memory, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start circuit (4), and a plurality of high voltage level control circuits (5), the memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells is provided with a control circuit, and each memory The unit cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11) and a second inverter (by a second PMOS transistor P12 and a second NMOS transistor M12, an access transistor (composed of a third NMOS transistor M13), a first read transistor (M14), and a second read transistor (M15) ). Each control unit (2) is connected to a source of the first NMOS transistor (M11) of each memory cell of the corresponding column memory cell and the second a source of the NMOS transistor (M12) for controlling a source voltage of the first NMOS transistor (M11) and a source voltage of the second NMOS transistor (M12) in response to different operation modes, thereby writing In the mode, it can effectively prevent the problem of writing logic 1. In the read mode, the read speed can be increased while avoiding unnecessary power consumption. In the standby mode, the leakage current can be effectively reduced. In the mode, the original electrical characteristics can be maintained. Furthermore, the standby start circuit (4) is designed to effectively cause the 7T dual-static SRAM to quickly enter the standby mode, thereby effectively improving the standby performance of the 7T dual-static SRAM. In addition, the design of the plurality of high voltage level control circuits (5) is such that when the logic 0 is read, the degree of conduction of the second read transistor (M15) is increased to further increase the read speed.

BLB ₁ ^... BLB _m ‧‧‧complementary bit line

BLB‧‧‧complementary bit line

MB ₁ ^... MB _k ‧‧‧ memory block

WL ₁ ^... WL _n ‧‧‧ character line

BL ₁ ^... BL _m ‧‧‧ bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

V _DD ‧‧‧Power supply voltage

M14‧‧‧First read transistor

M15‧‧‧Second reading transistor

S‧‧‧Standby mode control signal

/S ‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

P21‧‧‧ Third PMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

WC‧‧‧ write control signal

C‧‧‧ node

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧4th PMOS transistor

P‧‧‧Precharge signal

M41‧‧11 eleventh NMOS transistor

P41‧‧‧ Fifth PMOS transistor

WBL‧‧‧Write bit line

WWL‧‧‧write word line

RBL‧‧‧Reading bit line

RWL‧‧‧Read word line

D2‧‧‧second delay circuit

5‧‧‧High voltage level control circuit

V _DD ‧‧‧Power supply voltage

HV _DD ‧‧‧High power supply voltage

P51‧‧‧6th PMOS transistor

P52‧‧‧ seventh PMOS transistor

I53‧‧‧4th inverter

VH‧‧‧ high voltage node

Figure 1a shows a conventional static random access memory; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; and Fig. 2 shows a conventional 6T static random access memory cell. The write operation timing chart; the third figure shows the circuit diagram of the conventional 5T static random access memory unit cell; the fourth figure shows the write operation timing chart of the conventional 5T static random access memory unit cell; 5 is a circuit diagram showing a conventional 8T dual-static static random access memory cell; FIG. 6 is a schematic circuit diagram showing a preferred embodiment of the present invention; and FIG. 7 is a view showing the invention of FIG. The preferred embodiment is a simplified circuit diagram during the writing of logic 1; FIG. 8 is a timing chart showing the writing operation of the preferred embodiment of the present invention in FIG. 6; and FIG. 9 is a preferred embodiment of the present invention showing FIG. A simplified circuit diagram during the reading period; FIG. 10 is a simplified circuit diagram showing the preferred embodiment of the present invention in the sixth embodiment during standby.

According to the above main object, the present invention provides a 7T binary anti-static random access memory, which mainly comprises a memory array, which is composed of a plurality of memory cells and a plurality of memory cells. Each column of memory cells and each row of memory cells includes a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); Charging circuit (3), each row of memory cells is provided with a pre-charging circuit (3); a standby starting circuit (4), the standby starting circuit (4) prompts the 7T dual-SRAM to quickly enter standby mode to effectively improve 7T The standby performance of the dual-SRAM SRAM: and a plurality of high-voltage level control circuits (5), each column of memory cells is provided with a high-voltage level control circuit (5) to further increase the reading speed when logic 0 is read.

For convenience of explanation, the 7T double-chip static random access memory shown in FIG. 6 has only one memory cell (1), one write word line (WWL), and one write bit line. (WBL), a read word line (RWL), a read bit line (RBL), a control circuit (2), a precharge circuit (3), a standby start circuit (4), and a The high voltage level control circuit (5) is explained as an embodiment. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11) and a second inverter (by a second PMOS) a crystal P12 and a second NMOS transistor M12, a third NMOS transistor (M13), a first read transistor (M14), and a second read transistor (M15), wherein The first inverter and the second inverter are connected in an alternating coupling manner, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the second The output of the phase converter (ie, node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the second The output of the phaser (node B) is used to store the inverted data of the SRAM cell.

The first inverter of the memory cell (1) (composed of the first PMOS transistor P11 and the first NMOS transistor M11) is connected to a power supply voltage (V _DD ) and a first Between the low voltage nodes (VL1), the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12) is connected to a high voltage node (VH) and a second low Between the voltage nodes (VL2), the source, the gate and the drain of the first read transistor (M14) are respectively connected to the drain of the second read transistor (M15), the reading A word line (RWL) and the read bit line (RBL) are used, and a source, a gate and a drain of the second read transistor (M15) are respectively connected to the second low voltage node ( VL2), the output of the second inverter (node B) and the source of the first read transistor (M14).

Referring again to FIG. 6, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS device. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), a standby mode control signal (S), and An inverted standby mode control signal (/S) is formed. a source, a gate and a drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the reverse standby mode control signal (/S) and the second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (M22) are respectively connected to the first low voltage node (VL1), the standby mode control signal (S) and the second low voltage node (VL2); The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate is connected to the drain and connected to the first low battery. a voltage node (VL1); a source, a gate and a drain of the seventh NMOS transistor (M24) are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and The second low voltage node (VL2); the source, the gate and the drain of the eighth NMOS transistor (M25) are respectively connected to the accelerated read voltage (RGND) and the first delay circuit (D1) And outputting a source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to an output of the third inverter (INV) and a gate of the eighth NMOS transistor (M25) The input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the ninth NMOS transistor (M26) a source, a gate and a drain are respectively connected to a ground voltage, a drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); and the tenth NMOS transistor (M27) a source, a gate and a drain are respectively connected to the standby mode control signal (S), the write control signal (WC) and a gate of the ninth NMOS transistor (M26); and the third PMOS transistor Source, gate and bungee of (P21) They are respectively connected to the inverted standby mode control signal (/S), the write control signal (WC) and the drain of the tenth NMOS transistor (M27). It is worth noting here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter.

It is worth noting here that the drain of the third PMOS transistor (P3), the drain of the tenth NMOS transistor (M27), and the gate of the ninth NMOS transistor (M26) are connected together. Forming a node (C), when the write control signal (WC) is a logic low level, the voltage level of the node (C) is the voltage level of the inverted standby mode control signal (/S), and When the write control signal (WC) is logic high, the voltage level of the node (C) is the voltage level of the standby mode control signal (S), thereby effectively preventing the standby mode. Incorrect writes that occur due to unexpected factors.

The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage of the driving transistor (ie, the first NMOS transistor M11) closer to the writing bit line (WBL) is set to be higher than the ground voltage. Predetermining a voltage (ie, a gate-source voltage V _{GS (M23) of} the sixth NMOS transistor (M23)) and selecting a source voltage of another driving transistor (ie, the second NMOS transistor M12) in the selected cell ( That is, the second low voltage node VL2) is set to the ground voltage in order to prevent the problem of writing logic 1 difficult.

In the first phase of the read mode, the source voltage of the driving transistor (ie, the second NMOS transistor M12) that is closer to the read bit line (RBL) in the selected cell (ie, the second low) The voltage node VL2) is set to be the accelerated read voltage (RGND) which is lower than the ground voltage, and the accelerated read voltage (RGND) which is lower than the ground voltage can effectively improve the read speed, and in the read mode In the second stage, the source voltage of the driving transistor (ie, the second NMOS transistor M12) in the selected cell closer to the read bit line (RBL) is set back to the ground voltage to reduce unnecessary power consumption. The time between the second phase of the read mode and the first phase is equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the eighth NMOS transistor ( The gate voltage of M25) is sufficient to turn off the eighth NMOS transistor (M25), and the value thereof can be provided by the first delay circuit (D1) by the falling delay time of the third inverter (INV) The delay time is adjusted.

In the standby mode, the source voltage of the driving transistor in all the memory cells is set to the predetermined voltage higher than the ground voltage to reduce the leakage current; and in the hold mode, the driving power in the memory cell is The source voltage of the crystal is set to the ground voltage in order to maintain the original retention characteristics, and the detailed operating voltage level is as shown in Table 1 above.

The write control signal (WC) in Table 1 is an AND gate operation result of a Write Enable (WE) signal and a corresponding write word line (WWL) signal. At this time, when the write enable (WE) signal and the corresponding write word line (WWL) signal are both at a logic high level, the write control signal (WC) is a logic high level; the read The control signal (RC) is the result of the AND operation of a Read Enable (RE) signal and a corresponding Read Word Line (RWL) signal. It is worth noting here that the unselected word line and the unselected positioning element line are set to a floating state, and the read control signal (RC) is set to the acceleration during the non-read mode. The level of the read voltage (RGND) is read to prevent leakage current of the seventh NMOS transistor (M24).

Referring to FIG. 6, the precharge circuit (3) is composed of a fourth PMOS transistor (P31) and a precharge signal (P), and the source and gate of the fourth PMOS transistor (P31). And the drain system are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit line (RBL), so as to be in a logic low level during precharge Precharge signal (P) to precharge the corresponding read bit line (RBL) to the level of the power supply voltage (V _DD ).

Referring again to FIG. 6, the standby starting circuit (4) is composed of a fifth PMOS transistor (P41), an eleventh NMOS transistor (M41), a second delay circuit (D2), and the reverse standby. The mode control signal (/S) is composed of. a source, a gate and a drain of the fifth PMOS transistor (P41) are respectively connected to the power supply voltage (V _DD ), the inverted standby mode control signal (/S) and the eleventh NMOS transistor a drain of (M41); a source, a gate and a drain of the eleventh NMOS transistor (M41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) And a drain of the fifth PMOS transistor (P41); an input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and an output of the second delay circuit (D2) is Connected to the gate of the eleventh NMOS transistor (M41).

Referring again to FIG. 6, the high voltage level control circuit (5) is composed of a sixth PMOS transistor (P51), a seventh PMOS transistor (P52), and a fourth inverter (I53). The source, the gate and the drain of the sixth PMOS transistor (P51) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH), The source, the gate and the drain of the seventh PMOS transistor (P52) are respectively connected to a high power supply voltage (HV _DD ), the output of the fourth inverter (I53) and the high voltage node (VH) And the input of the fourth inverter (I53) is for receiving the read control signal (RC), and the output is connected to the drain of the seventh PMOS transistor (P52). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage. Between the node (VH) and the second low voltage node (VL2).

The working principle of the preferred embodiment of the invention illustrated in Figure 6 is as follows:

(I) write mode

Before the start of the write operation, the write control signal (WC) is at a logic low level, such that the third PMOS transistor (P21) is turned "ON", and the tenth NMOS transistor (M27) is turned off (OFF). Therefore, the drain of the third PMOS transistor (P21) is at a logic high level, and the drain of the third PMOS transistor (P21) of the logic high level turns on the ninth NMOS transistor (M26), and The first low voltage node (VL1) is at a ground voltage.

During the write operation, the write control signal (WC) is at a logic high level, such that the third PMOS transistor (P21) is turned off, the tenth NMOS transistor (M27) is turned on, and the third PMOS is turned on. The drain of the transistor (P21) is at a logic low level, and the logic low level of the drain of the third PMOS transistor (P21) causes the ninth NMOS transistor (M26) to be turned off, and the first low voltage is made The node (VL1) is equal to the gate-source voltage V _{GS (M26} ) of the sixth NMOS transistor (M23 ₎ , whereby the problem of difficulty in writing the logic 1 is effectively prevented. Figure 7 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 6 during writing.

Next, how the write operation of the preferred embodiment of the present invention in FIG. 7 is completed in accordance with four write states.

(1) Node A originally stores a logic 0, and now wants to write a logic 0: before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M11) is turned on ( ON). Since the first NMOS transistor (M11) is ON, the write word line (WWL) is turned from Low (ground voltage) to High (power supply voltage V _DD ) when the write operation starts. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned off (OFF) To be ON, at this time, since the write bit line (WBL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle.

(2) Node A originally stores a logic 0, and now wants to write a logic 1: before the write operation occurs (the write word line WWL is a ground voltage), the first NMOS transistor (M11) is turned on ( ON). It is worth noting here that since the first NMOS transistor (M11) is ON, when the write operation starts, the write word line (WWL) is turned from Low (ground voltage) to High (the power supply) Voltage V _DD ), the voltage of this node A will slightly increase with the voltage following the write word line (WWL) due to the parasitic capacitance coupling effect.

When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON. Because the write bit line (WBL) is High (the power supply voltage V _DD ), and because the first NMOS transistor (M11) is still ON and the node B is still at a voltage level close to the The initial state of the voltage level of the power supply voltage (V _DD ), so the first PMOS transistor (P11) is still OFF (OFF), and the initial transient voltage (V _AW ) of the node A satisfies the equation (3) ): V _AW = V _DD × (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 ) > V _TN12 (3) where V _AW represents the initial instantaneous voltage of the write of the node A, and R _M13 represents the The on-resistance of the third NMOS transistor (M13), R _M11 represents the on-resistance of the first NMOS transistor (M11), R _M23 represents the on-resistance of the sixth NMOS transistor (M23), and V _DD and V _TN12 Representing the power supply voltage and the threshold voltage of the second NMOS transistor (M12), respectively, because the third NMOS transistor (M13) is still operating in the saturation region and the first NMOS transistor (M11) still For the linear region (triode region), while guiding the third NMOS transistor (M13) through the equivalent resistance (R _M13) is considerably greater than the first NMOS transistor (M11) is turned the equivalent resistance (R _M11), However, since the sixth NMOS transistor (M23) is diode-connected, a gate-source voltage V equal to the sixth NMOS transistor (M23) can be provided at the first low voltage node (VL1). The voltage level of _{GS (M23)} , the resulting initial write voltage (V _AW ) of node A will be higher than the voltage level of the node A of the conventional 5T static random access memory cell of FIG. It is much higher. The much higher voltage division level is sufficient to turn on the second NMOS transistor (M12), thereby causing the node B to discharge to a lower voltage level, and the lower voltage level of the node B causes the The on-resistance equivalent (R _M11 ) of the first NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) obtains a higher voltage level at the node A. The higher voltage level of the node A will pass through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level. The lower voltage level of the node B is again caused by the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level. According to this cycle, the node A can be charged to the power supply voltage (V _DD ), and the logic 1 write operation is completed.

It should be noted here that the first low voltage node VL1 originally stores a logic O at the node A, and has a gate-source voltage V _GS equal to the sixth NMOS transistor (M23) during the writing of the logic 1. The voltage level of _(M23) , after writing logic 1, will have the level of the ground voltage due to discharge through the ninth NMOS transistor (M26).

(3) Node A originally stores logic 1, and now wants to write logic 1: Before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor (P11) is turned on ( ON). When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the write word line (WWL) is greater than the third NMOS transistor (M13) When the threshold voltage is applied, the third NMOS transistor (M13) is turned from OFF to ON; at this time, since the write bit line (WBL) is High (the power supply voltage V _DD ) And because the first PMOS transistor (P11) is still ON, the voltage of the node A is maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stores logic 1, and now wants to write logic 0: before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor (P11) is turned on ( ON). When the write word line (WWL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the write word line (WWL) is greater than the third NMOS transistor (M13) When the threshold voltage is applied, the third NMOS transistor (M13) is turned from OFF to ON. At this time, since the write bit line (WBL) is Low (ground voltage), The node A and the first low voltage node (VL1) are discharged to complete the logic 0 write operation until the end of the write cycle.

In the preferred embodiment of the present invention shown in FIG. 7, the HSPICE transient analysis simulation result at the time of the write operation is as shown in FIG. 8, which is simulated using the TSMC 90 nm CMOS process parameters, from which the simulation result is obtained. It can be confirmed that the 7T double-chip static random access memory proposed by the present invention can improve the voltage level of the first low voltage node (VL1) during the writing period, thereby effectively avoiding the conventional single bit line. It is quite difficult to write a logic 1 in a double-埠 static random access memory cell.

(II) Read mode (read mode)

Before the reading operation starts, the read control signal (RC), the write control signal (WC), and the standby mode control signal (S) are both logic low levels, so that the third PMOS transistor (P21) is turned on. And the tenth NMOS transistor (M27) is turned off, so that the drain of the third PMOS transistor (P21) is at a logic high level, and the logic of the third PMOS transistor (P21) is turned on. Nine NMOS transistors (M26) and the first low voltage node (VL1) is grounded. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned "ON".

It is worth noting here that during pre-charging before the start of the read operation, the pre-charge signal (P) is at a logic low level, thereby pre-charging the corresponding read bit line (RBL) to The power supply voltage (V _DD ) is level, but the operating voltage of the process technology such as 45 nm or less will be reduced to 1.1 ± 30% or less, which will cause the reading speed to be lowered to meet the specification problem. The present invention proposes a two-stage read control to improve read speed and meet specifications while avoiding unnecessary power consumption.

The preferred embodiment of the invention illustrated in Figure 6 is controlled by two stages of read control. In order to improve the reading speed, the unnecessary power consumption is also avoided. In the first stage of the reading operation, the read control signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on due to At this time, the eighth NMOS transistor (M25) is still turned on, and then the second low voltage node (VL2) is at an accelerated read voltage (RGND) lower than the ground voltage, and the accelerated read voltage is lower than the ground voltage. Taking the voltage (RGND) can effectively improve the reading speed.

In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but since the eighth NMOS transistor (at this time) M25) is turned off, and then the second low voltage node (VL2) is grounded via the turned-on fourth NMOS transistor (M21) (due to the inverted standby mode control signal (/S) during the read operation is logic High level), which can effectively reduce unnecessary power consumption. It is worth noting here that the second phase of the read operation is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the The gate voltage of the eight NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), and the value thereof can be decreased by the delay time of the third inverter (INV) and the first delay circuit. (D1) The delay time provided is adjusted. Furthermore, the fourth NMOS transistor (M21) is in an on state regardless of the first phase of the read operation or the second phase (due to the inverted standby mode control signal (/S) being logic during the read operation High level). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 6 during reading.

Next, how to set the accelerated read voltage (RGND) and how to increase the read speed in the preferred embodiment of the present invention in FIG. 9 will be described in terms of two read states.

(1) Read logic 1 (node A storage logic 1): before the read operation occurs, the first NMOS transistor (M11) is off (OFF) and the second NMOS transistor (M12) is on (ON) The node A and the node B are respectively the power supply voltage (V _DD ) and the ground voltage, and the read bit line (RBL) is equal to the power supply voltage due to the precharge circuit (3) V _DD ). During the reading, since the node B is a ground voltage, the second read transistor (M15) is turned off (OFF), thereby effectively maintaining the read bit line (RBL) as the power supply voltage ( V _DD ) The operation of reading logic 1 is successfully completed until the end of the read cycle. It is worth noting here that since the second low voltage node (VL2) is the accelerated read voltage (RGND) at this time, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, it is necessary to The accelerated read voltage (RGND) is set lower than the threshold voltage (V _TN12 ) of the second NMOS transistor (M12), that is, |RGND|<V _TN12 (4), where |RGND| and V _TN11 respectively indicate Accelerating the absolute value of the read voltage and the threshold voltage of the second NMOS transistor (M12).

(2) Reading logic 0 (node A stores logic 0): before the read operation occurs, the first NMOS transistor (M11) is turned on (ON) and the second NMOS transistor (M12) is turned off (OFF) The node A and the node B are respectively a ground voltage and the power supply voltage (V _DD ), and the read bit line (RBL) is equal to the power supply voltage due to the precharge circuit (3) V _DD ). During the reading, since the node B is the high power supply voltage (HV _DD ), and the second low voltage node (VL2) is at the accelerated read voltage (RGND) which is lower than the ground voltage, due to the high power supply The voltage (HV _DD ) is set higher than the power supply voltage (V _DD ), so that the read speed of the second read transistor (M15) can be increased to increase the read speed while matching the comparison. The grounding voltage is low for the accelerated read voltage (RGND) to further increase the read speed. It is worth noting here that the high power supply voltage (HV _DD ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the second PMOS transistor (P12) The sum of the absolute value of the threshold voltage |V _TP12 |, that is, V _DD <HV _DD <V _DD +|V _TP12 | (5) where |V _TP12 | represents the absolute value of the threshold voltage of the second PMOS transistor (P12) value.

(III) Standby mode

First, how the standby start circuit (4) of Fig. 6 causes the 單埠SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: First, the reverse standby mode control signal (/S) before entering the standby mode. Is logic High, the logic high inversion standby mode control signal (/S) causes the fifth PMOS transistor (P41) to be turned off (OFF), and the eleventh NMOS transistor (M41) is turned on (ON); Then, after entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fifth PMOS transistor (P41) to be turned on (ON). However, during the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from the logic High to the logic Low, to the gate voltage of the eleventh NMOS transistor (M41) The time until the eleventh NMOS transistor (M41) is turned off, which can be adjusted by a delay time provided by the second delay circuit (D2), and the eleventh NMOS transistor (M41) is still turned on. (ON), then the first low voltage node (VL1) can be quickly charged to reach the sixth NMOS transistor The voltage level of the threshold voltage (V _TM23 ) of the body (M23), that is, the 7T double-turn SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the eleventh NMOS transistor (M41) is turned off and the supply current is stopped.

Please refer to FIG. 6 . In the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (M21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (M22) is turned on (ON), and the fifth NMOS transistor (M22) is used as an equalizer, so that the fifth NMOS transistor (M22) in an on state can be used. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V _TM23 ). Figure 10 is a simplified circuit diagram of the preferred embodiment of the present invention in Figure 6 during standby.

Next, how to reduce leakage current in the standby mode of the present invention is described. Referring to FIG. 10, FIG. 10 depicts a leakage current I ₁ generated when the embodiment of the present invention is in the standby mode. I ₂ , I ₃ , I ₄ , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage is due to the standby mode) The voltage level of the node (VL2) is maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so the voltage level of the node A is the logic Low and the voltage of the V _TM23 is also maintained. The level of the output of the second inverter (ie, node B) is a logic high (power supply voltage V _DD ). Please refer to the conventional 8T dual-SRAM SRAM of FIG. 5 and the embodiment of the present invention of FIG. 10 to illustrate the leakage current of the 7T dual-static static random access memory proposed by the present invention and the conventional 8T dual-turn SRAM of FIG. In comparison, firstly, regarding the leakage current I ₁ flowing through the third NMOS transistor (M13), since the voltage level of the node A in the standby mode is maintained at the voltage level of the V _TM23 , and the The write word line (WWL) is set to the ground voltage in the standby mode, and the write bit line (WBL) is set to the power supply voltage (V _DD ) in the standby mode, so the present invention The gate-source voltage (V _GS ) of the third NMOS transistor (M13) is a negative value, and the gate-source voltage of the NMOS transistor (M3) of the conventional 8T dual-SRAM SRAM of FIG. 5 in the standby mode (V _GS) ) is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect or the results of Figures 3 (A) and 3 (B) of US Pat. No. 6,865,119, March 8, 2005, for NMOS In the case of a transistor, the subcritical current when the gate source voltage is -0.1 volt is about 1% of the subcritical current when the gate source voltage is 0 volts. Therefore, the leakage current I ₁ of the third NMOS transistor (M13) flowing through the present invention caused by the GIDL effect is much smaller than that of the conventional 8T double-SRAM NMOS transistor (M3) of FIG. 5; The 汲 source voltage (V _DS ) of the third NMOS transistor (M13) of the present invention _deducts the voltage level of the V _TM23 from the power supply voltage (V _DD ), and the conventional 8T double 第 in FIG. 5 The 汲 source voltage (V _DS ) of the SRAM NMOS transistor (M3) is equal to the power supply voltage (V _DD ), which is based on the Drain-Induced Barrier Lowering (DIBL) effect due to the DIBL effect. The induced leakage current I ₁ flowing through the third NMOS transistor (M13) of the present invention is also smaller than the NMOS transistor (M3) of the conventional 8T double-turn SRAM of FIG. 5; as a result, the third of the present invention flows through The leakage current I _{1 of the} NMOS transistor (M13) is much smaller than that of the conventional 8T double-SRAM NMOS transistor (M3) of FIG.

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) due to the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the _VTM23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V _{DD ) Deducting} the voltage level of the V _TM23 , the source drain voltage (V _SD ) of the PMOS transistor (P1) of the conventional 8T dual-SRAM SRAM of FIG. 5 is equal to the power supply voltage (V _DD ), according to The DIBL effect, therefore, the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P1) of Figure 1b.

Then, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V _TM23 in the standby mode, the node A The voltage level is also maintained at the voltage level of the V _TM23 , and the voltage level of the node B is equal to the power supply voltage (V _DD ) and the base of the second NMOS transistor (M12) is the ground voltage, so The base-source voltage (V _BS ) of the second NMOS transistor (M12) of the invention is a negative value, and the 汲 source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V) _DD ) deducting the voltage level of the V _TM23 , and the base-source voltage (V _BS ) of the NMOS transistor (M2) of the conventional 8T double-turn SRAM of FIG. 5 is equal to 0, and the NMOS transistor (M2) The source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and the DIBL effect, the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than Figure 5 is a conventional 8T dual-SRAM NMOS transistor (M2).

Finally, regarding the leakage current I ₄ flowing through the first read transistor (M14), since the present invention is different from the conventional 8T dual-turn SRAM of FIG. 5, and the reading is performed in the standby mode of the present invention. The bit line (RBL) can be set to the ground voltage, and the conventional 8T double-turn SRAM of FIG. 5 is used to prevent the voltage level of the node B from falling. The read bit line pair (RBL, RBLB) in the standby mode is Since the power supply voltage is set, it is not possible to compare the leakage current I ₄ flowing through the first read transistor (M14). Based on the above analysis, the 7T dual-static SRAM of the present invention has a lower leakage current than the conventional 8T dual-SRAM SRAM of FIG.

(IV) hold mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to ground voltage, the working principle is the same as that of the conventional double-bit SRAM cell with a single bit line. No longer said.

【Effects of invention】

The 7T double-click static random access memory proposed by the invention has the following effects:

(1) High read speed and avoiding unnecessary power consumption: The 7T dual-station static random access memory system proposed by the present invention employs a two-stage read operation, in the first stage of reading logic 0 by the second The low voltage node (VL2) is set to the accelerated read voltage (RGND) lower than the ground voltage, and the node B is set to be higher than the power supply voltage (V _DD ) of the high power supply voltage (HV _DD ) Therefore, the dual mechanism can be used to effectively increase the reading speed, and in the second phase of the read logic 0, the second low voltage node (VL2) is set back to the ground voltage to reduce unnecessary power consumption;

(2) Quick entry standby mode: Since the 7T dual-static SRAM (s) proposed by the present invention is provided with a standby start circuit (4) to prompt the SRAM to quickly enter the standby mode, and thereby seek to improve the 7T dual-SRAM Standby performance

(3) The problem of avoiding the difficulty of writing logic 1: The 7T dual-static static random access memory proposed by the present invention can improve the voltage level of the first low voltage node (VL1) during the write operation. Effectively avoiding the problem that it is quite difficult to write a logic 1 with a double-bit SRAM with a single bit line;

(4) Low standby current: Since the 7T dual-static SRAM in the standby mode of the present invention is in the standby mode, the fifth NMOS transistor (M22) in an on state can be used to make the first low The voltage level of the voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the level of the threshold voltage of the sixth NMOS transistor (M23). Therefore, the 7T dual-static static random access memory proposed by the present invention also has the effect of low standby current;

(5) Effectively reducing the half-selected cell interference: the 7T double-chip static random access memory proposed by the present invention uses a separate read/write path, and the read path is designed to be the first and second read A transistor (M14 and M15) is connected in series between the read bit line (RBL) and the second low voltage node (VL2), and the inverting storage node (B) is connected to the second Reading the gate of the transistor (M15), thus effectively reducing the half-selected cell disturbance, wherein the half-selected cell means is selected by the read word line (RWL) but not A unit cell selected by the read bit line (RBL).

(6) Low number of transistors: For an SRAM array having 1024 columns and 1024 rows, the 8T dual-SRAM array of the conventional FIG. 5 requires a total of 1024×1024×8=8,388,608 transistors, and the 7T proposed by the present invention The double-埠 static random access memory requires only at least 1024 × 1024 × 7 + 1024 × 20 + 6 = 7,360,518 transistors, which reduces the number of transistors by 12.3%.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

V _DD ‧‧‧Power supply voltage

M14‧‧‧First read transistor

M15‧‧‧Second reading transistor

WBL‧‧‧Write bit line

WWL‧‧‧write word line

RBL‧‧‧Reading bit line

RWL‧‧‧Read word line

S‧‧‧Standby mode control signal

/S ‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

P21‧‧‧ Third PMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

WC‧‧‧ write control signal

C‧‧‧ node

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧4th PMOS transistor

P‧‧‧Precharge signal

M41‧‧11 eleventh NMOS transistor

P41‧‧‧ Fifth PMOS transistor

D2‧‧‧second delay circuit

5‧‧‧High voltage level control circuit

V _DD ‧‧‧Power supply voltage

HV _DD ‧‧‧High power supply voltage

P51‧‧‧6th PMOS transistor

P52‧‧‧ seventh PMOS transistor

153‧‧‧fourth inverter

VH‧‧‧ high voltage node

Claims (10)

A 7T double-click static random access memory, comprising: a memory array, the memory array is composed of a plurality of memory cells and a plurality of memory cells, each column of memory cells and each row of memory The body cells each comprise a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory The unit cell is provided with a pre-charging circuit (3); a standby starting circuit (4), which causes the static random access memory to quickly enter the standby mode to effectively improve the static random random Accessing the standby performance of the memory; and a plurality of high voltage level control circuits (5), each column of memory cells is provided with a high voltage level control circuit (5) to increase the reading speed when reading logic 0; Each memory cell (1) further includes: a first inverter composed of a first PMOS transistor (P11) and a first NMOS transistor (M11), the first inversion The device is connected to a power supply voltage (V _DD ) and a first low voltage node (VL) 1); a second inverter consisting of a second PMOS transistor (P12) and a second NMOS transistor (M12) connected to a high voltage node ( VH) and a second low voltage node (VL2); a storage node (A) formed by the output of the first inverter; and an inverted storage node (B) by the second Forming an output of the inverter; a third NMOS transistor (M13) is connected between the storage node (A) and a corresponding write bit line (WBL), and the gate is connected to the Corresponding write word line (WWL); a first read transistor (M14), the source, gate and drain of the first read transistor (M14) are respectively connected to a first a drain of the read transistor (M15), a read word line (RWL) and a read bit line (RBL); and the second read transistor (M15), the first The source, the gate and the drain of the second read transistor (M15) are respectively connected to the second low voltage node (VL2), the inverting storage node (B) and the first read transistor ( a source of M14), wherein the first inverter and the second inverter are presented a mutual coupling connection, that is, an output end of the first inverter (ie, the storage node A) is connected to an input end of the second inverter, and an output end of the second inverter (ie, the opposite phase The storage node B) is connected to the input end of the first inverter; and each control circuit (2) further comprises: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a first Six NMOS transistors (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a first a three PMOS transistor (P21), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), and a write control signal (WC), a standby mode control signal (S) and an inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fourth NMOS transistor (M21) are respectively connected to one a ground voltage, the inverted standby mode control signal (/S) and the second low voltage node (VL2); the source, the gate and the drain of the fifth NMOS transistor (M22) are respectively connected to the first Low voltage node (VL1), the waiting a mode control signal (S) and the second low voltage node (VL2); a source of the sixth NMOS transistor (M23) is connected to the ground voltage, and a gate is connected to the drain and connected to the first a low voltage node (VL1); a source, a gate and a drain of the seventh NMOS transistor (M24) are respectively connected to the drain of the eighth NMOS transistor (M25), and the read control signal (RC) And a second low voltage node (VL2); a source, a gate and a drain of the eighth NMOS transistor (M25) are respectively connected to the accelerated read voltage (RGND), the first delay circuit (D1) And an output of the seventh NMOS transistor (M24); the first delay circuit (D1) is coupled between the output of the third inverter (INV) and the eighth NMOS transistor (M25) Between the gates; the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the ninth NMOS transistor a source, a gate and a drain of (M26) are respectively connected to the ground voltage, a drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the tenth NMOS transistor ( M27) source, gate And a drain electrode connected to the standby mode control signal (S), the write control signal (WC) and the gate of the ninth NMOS transistor (M26); the source of the third PMOS transistor (P21) The gate and the drain are respectively connected to the inverted standby mode control signal (/S), the write control signal (WC) and the drain of the tenth NMOS transistor (M27); The drain of the third PMOS transistor (P3), the drain of the tenth NMOS transistor (M27), and the gate of the ninth NMOS transistor (M26) are connected together to form a node (C) When the write control signal (WC) is at a logic low level, the voltage level of the node (C) is the voltage level of the inverted standby mode control signal (/S), and when the write control signal ( WC) is logic high timing, the voltage level of the node (C) is the voltage level of the standby mode control signal (S), thereby effectively preventing false writes due to unexpected factors in the standby mode. Wherein, the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent the seventh NMOS transistor (M24) The leakage current during the non-read mode; further, the standby starting circuit (4) is designed to quickly charge the parasitic capacitance at the first low voltage node (VL1) to the initial period of one of the standby modes. The voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23); finally, each high voltage level control circuit (5) further includes: a sixth PMOS transistor (P51), a seventh PMOS a transistor (P52) and a fourth inverter (I53), wherein a source, a gate and a drain of the sixth PMOS transistor (P51) are respectively connected to the power supply voltage (V _DD ), the reading Taking a control signal (RC) and the high voltage node (VH), the source, the gate and the drain of the seventh PMOS transistor (P52) are respectively connected to a high power supply voltage (HV _DD ), the fourth An output of the inverter (I53) and the high voltage node (VH), wherein an input of the fourth inverter (I53) is for receiving the read control signal (RC), and an output is connected to the seventh PMOS battery The gate of the crystal (P52). The 7T binary static random access memory according to claim 1, wherein the first NMOS transistor (M11) and the second NMOS in each memory cell (1) The transistor (M12) has the same channel width to length ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also have the same channel width to length ratio. The write control signal (WC) is a write enable (WE) signal and the corresponding write word, as in the 7T dual-static SRAM described in claim 2 of the patent application. The result of the AND gate operation of the line (WWL) signal, that is, only when the write enable (WE) signal and the corresponding write word line (WWL) signal are both at a logic high level, The write control signal (WC) is at a logic high level. The read control signal (RC) is a read enable (RE) signal and the corresponding read word, as in the 7T dual-static static random access memory according to claim 3 of the patent application. The result of the AND gate operation of the line (RWL) signal, that is, only when the read enable (RE) signal and the corresponding read word line (RWL) signal are both at a logic high level, The read control signal (RC) is at a logic high level. The 7T dual-static SRAM according to claim 4, wherein each pre-charging circuit (3) is composed of a fourth PMOS transistor (P31) and a pre-charging signal (P). The source, the gate and the drain of the fourth PMOS transistor (P31) are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding read bit a line (RBL) for precharging the corresponding read bit line (RBL) to the power supply voltage (V) by a logic low level (P) during a precharge period _{The level of DD} ). The 7T dual-static SRAM according to claim 5, wherein the standby starting circuit (4) is a fifth PMOS transistor (P41) and an eleventh NMOS transistor (M41). a second delay circuit (D2) and the inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fifth PMOS transistor (P41) are respectively connected to the a power supply voltage (V _DD ), a reverse standby mode control signal (/S) and a drain of the eleventh NMOS transistor (M41); a source and a gate of the eleventh NMOS transistor (M41) And the drain line is respectively connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fifth PMOS transistor (P41); the second delay circuit (D2) The input is connected to the inverting standby mode control signal (/S), and the output of the second delay circuit (D2) is connected to the gate of the eleventh NMOS transistor (M41). The 7T dual-static SRAM according to claim 6, wherein the initial period of the standby start circuit (4) entering the standby mode is equal to the inverted standby mode control signal (/S) The logic high level transitions to a logic low level, until the gate voltage of the eleventh NMOS transistor (M41) is sufficient to turn off the eleventh NMOS transistor (M41), which can be used by the second delay circuit (D2) One of the delay times provided to adjust. The 7T dual-static SRAM according to claim 7, wherein the read operation can be subdivided into two stages, and the second stage of the read operation is performed by the second The low voltage node (VL2) is set to the accelerated read voltage (RGND) lower than the ground voltage to effectively increase the read speed, and in the second phase of the read operation, the second low voltage node is (VL2) Set back to this ground voltage to reduce unnecessary power consumption. The 7T dual-static SRAM according to claim 8, wherein the second phase of the read operation is equal to the read control signal (RC). From the logic low level to the logic high level, until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), which can be used by the third inverter One of the (INV) falling delay times is adjusted with a delay time provided by the first delay circuit (D1). The 7T dual-static SRAM according to claim 9, wherein the accelerated read voltage (RGND) in each control circuit (2) is set lower than the each memory. a threshold voltage (V _TN11 ) of the first NMOS transistor (M11) in the cell (1), and the level of the high power supply voltage (HV _DD ) is set higher than the power supply voltage (V _DD ) The level is lower than the sum of the power supply voltage (V _DD ) and the absolute value of the second PMOS transistor (P12) threshold voltage (V _TP12 ) (|V _TP12 |).