TWI559453B - Single port static random access memory (4) - Google Patents

Single port static random access memory (4) Download PDF

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TWI559453B
TWI559453B TW103110998A TW103110998A TWI559453B TW I559453 B TWI559453 B TW I559453B TW 103110998 A TW103110998 A TW 103110998A TW 103110998 A TW103110998 A TW 103110998A TW I559453 B TWI559453 B TW I559453B
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nmos transistor
control signal
voltage
gate
inverter
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TW103110998A
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TW201537686A (en
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蕭明椿
莊佳諭
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修平學校財團法人修平科技大學
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Description

單埠靜態隨機存取記憶體(四) 單埠Static random access memory (4)

本發明係有關於一種單埠(single port)靜態隨機存取記憶體(Static Random Access Memory,簡稱SRAM),尤指一種有效提高單埠SRAM之待機效能,並能有效提高讀取速度與有效降低漏電流(leakage current)且能解決習知具單一位元線之單埠SRAM寫入邏輯1困難之單埠SRAM。 The invention relates to a single port static random access memory (SRAM), in particular to an effective improvement of the standby performance of the 單埠SRAM, and can effectively improve the reading speed and effectively reduce Leakage current and can solve the problem that SRAM is difficult to write logic 1 with a single bit line.

習知之單埠靜態隨機存取記憶體(SRAM)如第1a圖所示,其主要包括一記憶體陣列(memory array),該記憶體陣列係由複數個記憶體區塊(memory block,MB1、MB2等)所組成,每一記憶體區塊更由複數列記憶體晶胞(a plurality of rows of memory cells)與複數行記憶體晶胞(a plurality of columns of memory cells)所組成,每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞;複數條字元線(word line,WL1、WL2等),每一字元線對應至複數列記憶體晶胞中之一列;以及複數位元線對(bit line pairs,BL1、BLB1...BLm、BLBm等),每一位元線對係對應至複數行記憶體晶胞中之一行,且每一位元線對係由一位元線(BL1...BLm)及一互補位元線(BLB1...BLBm)所組成。 As is shown in FIG. 1a, the static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of memory blocks (memory block, MB 1). , MB 2 , etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL 1 , WL 2 , etc.), each word line corresponding to a plurality of columns of memory One of the body cells; and a plurality of bit line pairs (BL 1 , BLB 1 ... BL m , BLB m , etc.), each bit line pair corresponding to a plurality of rows of memory cells One row, and each bit line pair is composed of one bit line (BL 1 ... BL m ) and one complementary bit line (BLB 1 ... BLB m ).

第1b圖所示即是6T單埠靜態隨機存取記憶體(SRAM)晶胞之電路示意圖,其中,PMOS電晶體(P1)和(P2)稱為負載電晶體(load transistor),NMOS電晶體(M1)和(M2)稱為驅動電晶體(driving transistor),NMOS電晶體(M3)和(M4)稱為存取電晶體(access transistor),WL為字元線(word line),而BL及BLB分別為位元線(bit line)及互補位元線(complementary bit line),由於該單埠SRAM晶胞需要6個電晶體,且驅動電晶體與存取電晶體間的電流驅動能力比(即單元比率,cell ratio)通常設定在2.2至3.5之間,而導致存在有高集積化困難及價格高等缺失。 Figure 1b is a schematic diagram of a 6T單埠 SRAM cell, in which PMOS transistors (P1) and (P2) are called load transistors, NMOS transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is word line, and BL And BLB are respectively a bit line and a complementary bit line. Since the 單埠SRAM cell requires six transistors, and the current driving capability between the driving transistor and the access transistor is greater than (ie, the cell ratio) is usually set between 2.2 and 3.5, resulting in the difficulty of high integration and high price.

第1b圖所示6T單埠靜態隨機存取記憶體晶胞於寫入操作時之HSPICE暫態分析模擬結果,如第2圖所示,其係使用TSMC 90奈米CMOS製程參數加以模擬。 The HSPICE transient analysis results of the 6T單埠 SRAM cell shown in Figure 1b during the write operation, as shown in Figure 2, are simulated using the TSMC 90 nm CMOS process parameters.

用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5T單埠靜態隨機存取記憶體晶胞之電路示意圖,與第1b圖之6T單埠靜態隨機存取記憶體晶胞相比,此種5T靜態隨機存取記憶體晶胞比6T靜態隨機存取記憶體晶胞少一個電晶體及少一條位元線,惟該5T單埠靜態隨機存取記憶體晶胞在不變更PMOS電晶體P1和P2以及NMOS電晶體M1、M2和M3的通道寬長比以維持靜態雜訊邊際(Static Noise Margin,SNM)的情況下存在寫入邏輯1相當困難之問題。茲考慮記憶晶胞左側節點A原本儲存邏輯0的情況,由於節點A之電荷僅單獨自位元線(BL)傳送,因此很難將節點A中先前寫入的邏輯0蓋寫成邏輯1。第3圖所示5T靜態隨機存取記憶體晶胞,於寫入操作時之HSPICE暫態分析模擬結果,如第4圖所示,其係使用TSMC 90奈米CMOS 製程參數加以模擬,由該模擬結果可証實,具單一位元線之5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T 單埠 SRAM cell with only a single bit line, compared to the 6T 單埠 SRAM cell of Figure 1b. The random access memory cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T單埠 SRAM cell does not change the PMOS transistors P1 and P2. And the channel width-to-length ratio of the NMOS transistors M1, M2, and M3 is relatively difficult to write logic 1 in the case of maintaining a static noise margin (SNM). Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 3 shows the HSPICE transient analysis simulation results of the 5T SRAM cell during write operation. As shown in Figure 4, it uses TSMC 90 nm CMOS. The process parameters are simulated. From the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.

迄今,有許多具單一位元線之5T靜態隨機存取記憶體晶胞之技術被提出,例如專利文獻1(99年4月27日第US7706203 B2號)所提出之「Memory System」、專利文獻2(102年8月1日第TWI404065號)所提出之「寫入操作時提高字元線電壓位準之單埠靜態隨機存取記憶體」、專利文獻3(100年6月1日第TW201118873A號)所提出之「寫入操作時降低電源電壓之單埠靜態隨機存取記憶體」及專利文獻4(100年5月16日第TW201117210A號)所提出之「具放電路徑之單埠靜態隨機存取記憶體」,該等專利雖可有效解決寫入邏輯1困難之問題,惟由於該等專利均未考慮到降低待機功率及45奈米操作電壓將降為1.1±30%時所造成讀取速度降低等問題,因此仍有改進空間。 In the past, there have been many techniques for a 5T SRAM cell with a single bit line, such as the "Memory System" proposed in Patent Document 1 (US Pat. No. 7,706,062 B2, April 27, 1999), Patent Literature 2 (TWI404065, August 1, 102, TWI404065) "Standard Static Random Access Memory with Improved Word Line Voltage Level in Write Operation", Patent Document 3 (June 1st, TW201118873A) No.) "Standard Static Random Access Memory with Reduced Power Supply Voltage During Write Operation" and Patent Document 4 (No. TW201117210A, May 16, 100) Access to memory, these patents can effectively solve the problem of writing logic 1 difficult, but since these patents do not take into account the reduction of standby power and 45 nm operating voltage will be reduced to 1.1 ± 30% caused by reading There are still problems with speed reduction and so on, so there is still room for improvement.

至今,有許多降低待機電流之技術被提出,例如專利文獻5(99年12月1日第TW M393773號)所提出之「具放電路徑之雙埠靜態隨機存取記憶體」、專利文獻6(98年3月21日第TW I307890號)所提出之「靜態隨機存取記憶體」、專利文獻7(97年6月3日第US7382674 B2號)所提出之「Static random access memory(SRAM)with clamped source potential in standby mode」、專利文獻8(96年8月7日第US7254085 B2號)所提出之「Static random access memory device and method of reducing standby current」、專利文獻9(95年9月19日第US7110317 B2號)所提出之「SRAM employing virtual rail scheme stable against various process-voltage-temperature variations」、非專利文獻10(Tae-Hyoung Kim et al.,”A Voltage Scalable 0.26 V,64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode”,IEEE Journal of Solid-State Circuits.,Vol.64,pp 1785-1795,2009.)所提出之8T SRAM以及非專利文獻11(Ding-Ming Kwai,”Modeling of SRAM Standby Current by Three-Parameter Lognormal Distribution”,Design,and Testing,2009.MTDT '09.IEEE International Workshop on Memory Technology,pp 77-82,Aug.31 2009-Sept.2009.)所提出之SRAM,該等專利文獻或非專利文獻於待機操作時,均是藉由將所有記憶體晶胞中之驅動電晶體(亦即第1b圖之NMOS電晶體M1和M2)之源極電壓由原本之接地電壓提高至較該接地電壓為高之一預定電壓,以謀求降低待機操作之功率消耗,惟由於該預定電壓僅係藉由電晶體之漏電流對寄生電容的充電而產生,而造成靜態隨機存取記憶體進入待機模式之速度極為緩慢,並因而導致降低待機效能之缺失:亦即該等專利文獻或非專利文獻均缺乏待機啟動電路以促使靜態隨機存取記憶體快速進入待機模式。 In the past, there have been many techniques for reducing the standby current, such as the "double-static static random access memory with discharge path" proposed in Patent Document 5 (No. TW M393773, December 1, 1999), Patent Document 6 ( "Static random access memory" proposed by TW I307890, March 21, 1998, "Static random access memory (SRAM)with", Patent Document 7 (US Pat. No. 7,382,674 B2, June 3, 1997) "Static random access memory device and method of reducing standby current", Patent Document 8 (US Pat. No. 7,725,085 B2, August 7, 1996), Patent Document 9 (September 19, 1995) "SRAM employing virtual rail scheme stable against various process-voltage-temperature variations", No. US7110317 B2), Non-Patent Document 10 (Tae-Hyoung Kim et al., "A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode", IEEE Journal of Solid-State Circuits. , Vol . 64, pp 1785-1795, 2009.) 8T SRAM and Non-Patent Document 11 (Ding-Ming Kwai, "Modeling of SRA M Standby Current by Three-Parameter Lognormal Distribution", Design, and Testing, 2009. MTDT '09. IEEE International Workshop on Memory Technology, pp 77-82, Aug. 31 2009-Sept. 2009.) When the patent document or the non-patent document is in standby operation, the source voltage of the driving transistor (ie, the NMOS transistors M1 and M2 of FIG. 1b) in all the memory cells is from the original ground voltage. Raising to a predetermined voltage higher than the ground voltage to reduce the power consumption of the standby operation, but since the predetermined voltage is generated only by charging the parasitic capacitance by the leakage current of the transistor, causing static random access The speed at which the memory enters the standby mode is extremely slow, and as a result, the lack of standby performance is reduced: that is, the patent documents or the non-patent literature lack a standby start circuit to cause the static random access memory to quickly enter the standby mode.

有鑑於此,本發明之主要目的係提出一種單埠靜態隨機存取記憶體,其能藉由待機啟動電路以有效促使SRAM快速進入待機模式,並因而有效提高SRAM之待機效能。 In view of this, the main object of the present invention is to provide a 單埠 static random access memory capable of effectively causing the SRAM to quickly enter the standby mode by the standby start circuit, thereby effectively improving the standby performance of the SRAM.

本發明之次要目的係提出一種單埠靜態隨機存取記憶體,其能藉由控制電路以有效避免習知具單一位元線之單埠SRAM存在寫入邏輯1相當困難之問題。 A secondary object of the present invention is to provide a 單埠 static random access memory that can be used to effectively avoid the problem of writing logic 1 by the control circuit to effectively avoid the existence of a single bit line SRAM.

本發明之再一目的係提出一種單埠靜態隨機存取記憶體,其能藉由控制電路以有效降低待機模式之漏電流。 Still another object of the present invention is to provide a 單埠 static random access memory capable of effectively reducing leakage current in a standby mode by a control circuit.

本發明之又一目的係提出一種單埠靜態隨機存取記憶體,其能 藉由控制電路以有效提高讀取速度。 Another object of the present invention is to provide a 單埠 static random access memory capable of The control circuit is used to effectively increase the reading speed.

本發明之又一目的係提出一種單埠靜態隨機存取記憶體,其能藉由二階段的讀取控制以於提高讀取速度的同時,亦避免無謂的功率耗損。 Another object of the present invention is to provide a 單埠 static random access memory that can be controlled by two stages to improve read speed while avoiding unnecessary power consumption.

本發明提出一種單埠靜態隨機存取記憶體,其主要包括一記憶體陣列、複數個控制電路(2)、複數個預充電電路(3)以及一待機啟動電路(4),該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成,每一列記憶體晶胞設置一個控制電路,且每一記憶體晶胞(1)係包括一第一反相器(由一第一PMOS電晶體P11與一第一NMOS電晶體M11所組成)、一第二反相器(由一第二PMOS電晶體P12與一第二NMOS電晶體M12所組成)及一存取電晶體(由第三NMOS電晶體M13所組成)。每一控制單元(2)係連接至對應列記憶體晶胞中之每一記憶體晶胞的該第一NMOS電晶體(M11)的源極以及該第二NMOS電晶體(M12)的源極,以便因應不同操作模式而控制該第一NMOS電晶體(M11)的源極電壓以及該第二NMOS電晶體(M12)的源極電壓,藉此於寫入模式時,可有效防止寫入邏輯1困難之問題,於讀取模式時,可於提高讀取速度的同時,亦避免無謂的功率耗損,於待機模式時,可有效降低漏電流,而於保持模式時則可維持原有的電氣特性。再者,藉由該待機啟動電路(4)的設計,以有效促使具單埠SRAM快速進入待機模式,並因而有效提高單埠SRAM之待機效能。 The present invention provides a 單埠 static random access memory, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby start circuit (4), the memory array The memory cell consists of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells is provided with a control circuit, and each of the memory cells (1) includes a first inverter (by a a first PMOS transistor P11 and a first NMOS transistor M11, a second inverter (composed of a second PMOS transistor P12 and a second NMOS transistor M12) and an access transistor (consisting of the third NMOS transistor M13). Each control unit (2) is connected to a source of the first NMOS transistor (M11) of each memory cell of the corresponding column memory cell and a source of the second NMOS transistor (M12) In order to control the source voltage of the first NMOS transistor (M11) and the source voltage of the second NMOS transistor (M12) in response to different operation modes, thereby effectively preventing the write logic in the write mode 1 difficult problem, in the read mode, can improve the reading speed, but also avoid unnecessary power consumption, in the standby mode, can effectively reduce the leakage current, while maintaining the original electrical mode characteristic. Moreover, the design of the standby start circuit (4) is effective to prompt the 單埠SRAM to quickly enter the standby mode, and thus effectively improve the standby performance of the 單埠SRAM.

BLB1 BLBm‧‧‧互補位元線 BLB 1 ... BLB m ‧‧‧complementary bit line

BLB‧‧‧互補位元線 BLB‧‧‧complementary bit line

MB1 MBk‧‧‧記憶體區塊 MB 1 ... MB k ‧‧‧ memory block

WL1 WLn‧‧‧字元線 WL 1 ... WL n ‧‧‧ character line

BL1 BLm‧‧‧位元線 BL 1 ... BL m ‧‧‧ bit line

I1、I2、I3‧‧‧漏電流 I 1 , I 2 , I 3 ‧‧‧ leakage current

1‧‧‧SRAM晶胞 1‧‧‧SRAM cell

2‧‧‧控制電路 2‧‧‧Control circuit

3‧‧‧預充電電路 3‧‧‧Precharge circuit

4‧‧‧待機啟動電路 4‧‧‧Standby start circuit

P11‧‧‧第一PMOS電晶體 P11‧‧‧First PMOS transistor

P12‧‧‧第二PMOS電晶體 P12‧‧‧Second PMOS transistor

M11‧‧‧第一NMOS電晶體 M11‧‧‧First NMOS transistor

M12‧‧‧第二NMOS電晶體 M12‧‧‧Second NMOS transistor

M13‧‧‧第三NMOS電晶體 M13‧‧‧ Third NMOS transistor

A‧‧‧儲存節點 A‧‧‧ storage node

B‧‧‧反相儲存節點 B‧‧‧ Inverting storage node

VDD‧‧‧電源供應電壓 V DD ‧‧‧Power supply voltage

BL‧‧‧位元線 BL‧‧‧ bit line

WL‧‧‧字元線 WL‧‧‧ character line

S‧‧‧待機模式控制信號 S‧‧‧Standby mode control signal

/S‧‧‧反相待機模式控制信號 /S ‧‧‧Inverted standby mode control signal

VL1‧‧‧第一低電壓節點 VL1‧‧‧ first low voltage node

VL2‧‧‧第二低電壓節點 VL2‧‧‧ second low voltage node

M21‧‧‧第四NMOS電晶體 M21‧‧‧4th NMOS transistor

M22‧‧‧第五NMOS電晶體 M22‧‧‧ Fifth NMOS transistor

M23‧‧‧第六NMOS電晶體 M23‧‧‧ sixth NMOS transistor

M24‧‧‧第七NMOS電晶體 M24‧‧‧ seventh NMOS transistor

M25‧‧‧第八NMOS電晶體 M25‧‧‧8th NMOS transistor

M26‧‧‧第九NMOS電晶體 M26‧‧‧Ninth NMOS transistor

M27‧‧‧第十NMOS電晶體 M27‧‧‧ tenth NMOS transistor

M28‧‧‧第十一NMOS電晶體 M28‧‧‧11th NMOS transistor

RC‧‧‧讀取控制信號 RC‧‧‧ read control signal

RGND‧‧‧加速讀取電壓 RGND‧‧‧Accelerated reading voltage

WC‧‧‧寫入控制信號 WC‧‧‧ write control signal

/WC‧‧‧反相寫入控制信號 /WC‧‧‧Inverted write control signal

C‧‧‧節點 C‧‧‧ node

D1‧‧‧第一延遲電路 D1‧‧‧First delay circuit

P31‧‧‧第三PMOS電晶體 P31‧‧‧ Third PMOS transistor

P‧‧‧預充電信號 P‧‧‧Precharge signal

M41‧‧‧第十二NMOS電晶體 M41‧‧‧12th NMOS transistor

P41‧‧‧第四PMOS電晶體 P41‧‧‧4th PMOS transistor

D2‧‧‧第二延遲電路 D2‧‧‧second delay circuit

INV‧‧‧第三反相器 INV‧‧‧ third inverter

第1a圖 係顯示習知之靜態隨機存取記憶體; 第1b圖 係顯示習知6T靜態隨機存取記憶體晶胞之電路示意圖;第2圖 係顯示習知6T靜態隨機存取記憶體晶胞之寫入動作時序圖;第3圖 係顯示習知5T靜態隨機存取記憶體晶胞之電路示意圖;第4圖 係顯示習知5T靜態隨機存取記憶體晶胞之寫入動作時序圖;第5圖 係顯示本發明較佳實施例所提出之電路示意圖;第6圖 係顯示第5圖之本發明較佳實施例於寫入期間之簡化電路圖;第7圖 係顯示第5圖之本發明較佳實施例之寫入動作時序圖;第8圖 係顯示第5圖之本發明較佳實施例於讀取期間之簡化電路圖;第9圖 係顯示第5圖之本發明較佳實施例於待機期間之簡化電路圖。 Figure 1a shows a conventional static random access memory; 1b is a schematic circuit diagram showing a conventional 6T static random access memory cell; FIG. 2 is a timing chart showing a write operation of a conventional 6T static random access memory cell; and FIG. 3 is a conventional display Schematic diagram of a 5T static random access memory cell; Fig. 4 shows a write operation timing diagram of a conventional 5T static random access memory cell; Fig. 5 shows a preferred embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6 is a simplified circuit diagram showing a preferred embodiment of the present invention in FIG. 5 during writing; FIG. 7 is a timing chart showing the writing operation of the preferred embodiment of the present invention in FIG. 5; The figure shows a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during reading; and FIG. 9 is a simplified circuit diagram showing the preferred embodiment of the present invention in FIG. 5 during standby.

根據上述之主要目的,本發明提出一種單埠靜態隨機存取記憶體,其主要包括一記憶體陣列,該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成,每一列記憶體晶胞與每一行記憶體晶胞均包括有複數個記憶體晶胞(1);複數個控制電路(2),每一列記憶晶胞設置一個控制電路(2);複數個預充電電路(3),每一行記憶晶胞設置一個預充電電路(3);以及一待機啟動電路(4),該待機啟動電路(4)係促使SRAM快速進入待機模式,以有效提高SRAM之待機效能。 According to the above main object, the present invention provides a 單埠 static random access memory, which mainly includes a memory array composed of a plurality of column memory cells and a plurality of row memory cells, each A column of memory cells and each row of memory cells include a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharges Circuit (3), each row of memory cells is provided with a precharge circuit (3); and a standby start circuit (4), which causes the SRAM to quickly enter standby mode to effectively improve the standby performance of the SRAM. .

為了便於說明起見,第5圖所示之靜態隨機存取記憶體僅以一個記憶體晶胞(1)、一條字元線(WL)、一條位元線(BL)、一控制電路(2)、一預充電電路(3)以及一待機啟動電路(4)做為實施例來說明。該記憶體晶胞(1)係包括一第一反相器(由一第一PMOS電晶體P11與一第一NMOS電晶體M11所組成)、一第二反相器(由一第二PMOS電晶體P12與 一第二NMOS電晶體M12所組成)、一第三NMOS電晶體(M13),其中,該第一反相器及該第二反相器係呈交互耦合連接,亦即該第一反相器之輸出(即節點A)係連接該第二反相器之輸入,而該第二反相器之輸出(即節點B)則連接該第一反相器之輸入,並且該第一反相器之輸出(節點A)係用於儲存SRAM晶胞之資料,而該第二反相器之輸出(節點B)則用於儲存SRAM晶胞之反相資料。 For convenience of explanation, the static random access memory shown in FIG. 5 has only one memory cell (1), one word line (WL), one bit line (BL), and one control circuit (2). A precharge circuit (3) and a standby start circuit (4) are described as embodiments. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11) and a second inverter (by a second PMOS) Crystal P12 and a second NMOS transistor M12), a third NMOS transistor (M13), wherein the first inverter and the second inverter are connected in an alternating coupling, that is, the first inverter The output (ie node A) is connected to the input of the second inverter, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the first inverter The output (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell.

請再參考第5圖,該控制電路(2)係由一第四NMOS電晶體(M21)、一第五NMOS電晶體(M22)、一第六NMOS電晶體(M23)、一第七NMOS電晶體(M24)、一第八NMOS電晶體(M25)、一第九NMOS電晶體(M26)、一第十NMOS電晶體(M27)、一第十一NMOS電晶體(M28)、一讀取控制信號(RC)、一第三反相器(INV)、一第一延遲電路(D1)、一加速讀取電壓(RGND)、一寫入控制信號(WC)、一反相寫入控制信號(/WC)、一待機模式控制信號(S)以及一反相待機模式控制信號(/S)所組成。該第四NMOS電晶體(M21)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與一第二低電壓節點(VL2);該第五NMOS電晶體(M22)之源極、閘極與汲極係分別連接至該第二低電壓節點(VL2)、該待機模式控制信號(S)與一第一低電壓節點(VL1);該第六NMOS電晶體(M23)之源極係連接至接地電壓,而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1);該第七NMOS電晶體(M24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M25)之汲極、該讀取控制信號(RC)與該第一低電壓節點(VL1);該第八NMOS電晶體(M25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、 該第一延遲電路(D1)之輸出與該第七NMOS電晶體(M24)之源極;該第一延遲電路(D1)係連接在該第三反相器(INV)之輸出與該第八NMOS電晶體(M25)之閘極之間;該第三反相器(INV)之輸入係供接收該讀取控制信號(RC),而輸出則連接至該第一延遲電路(D1)之輸入;該第九NMOS電晶體(M26)之源極、閘極與汲極係分別連接至接地電壓、該第十NMOS電晶體(M27)之汲極和該第十一NMOS電晶體(M28)之汲極與該第一低電壓節點(VL1);該第十NMOS電晶體(M27)之源極、閘極與汲極係分別連接至接地電壓、該寫入控制信號(WC)與該第九NMOS電晶體(M26)之閘極與該第十一NMOS電晶體(M28)之汲極;而該第十一NMOS電晶體(M28)之源極、閘極與汲極係分別連接至該反相待機模式控制信號(/S)、該反相寫入控制信號(/WC)與該第十NMOS電晶體(M27)之汲極。在此值得注意的是,該反相待機模式控制信號(/S)係由該待機模式控制信號(S)經一反相器而獲得;該反相寫入控制信號(/WC)係由該寫入控制信號(WC)經一反相器而獲得。 Referring again to FIG. 5, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS device. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control Signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), and an inverted write control signal ( /WC), a standby mode control signal (S) and an inverted standby mode control signal (/S). a source, a gate and a drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the reverse standby mode control signal (/S) and a second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (M22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) The gate and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); and the eighth NMOS transistor (M25) The source, gate and drain are connected to the accelerated read voltage (RGND), An output of the first delay circuit (D1) and a source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to an output of the third inverter (INV) and the eighth Between the gates of the NMOS transistor (M25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1) The source, the gate and the drain of the ninth NMOS transistor (M26) are respectively connected to a ground voltage, a drain of the tenth NMOS transistor (M27), and the eleventh NMOS transistor (M28) a drain and the first low voltage node (VL1); a source, a gate and a drain of the tenth NMOS transistor (M27) are respectively connected to a ground voltage, the write control signal (WC) and the ninth a gate of the NMOS transistor (M26) and a drain of the eleventh NMOS transistor (M28); and a source, a gate and a drain of the eleventh NMOS transistor (M28) are respectively connected to the opposite The phase standby mode control signal (/S), the inverted write control signal (/WC), and the drain of the tenth NMOS transistor (M27). It should be noted here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter; the inverted write control signal (/WC) is The write control signal (WC) is obtained via an inverter.

該控制電路(2)係設計成可因應不同操作模式而控制該第一低電壓節點(VL1)與該第二低電壓節點(VL2)之電壓位準,於寫入模式時,將選定晶胞中較接近位元線(BL)之驅動電晶體(即該第一NMOS電晶體M11)的源極電壓(即該第一低電壓節點VL1)設定成較接地電壓為高之一預定電壓(即該第六NMOS電晶體(M23)之閘源極電壓VGS(M23))且將選定晶胞中另一驅動電晶體(即該第二NMOS電晶體M12)的源極電壓(即該第二低電壓節點VL2)設定成接地電壓,以便防止寫入邏輯1困難之問題。 The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage (ie, the first low voltage node VL1) of the driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) is set to be a predetermined voltage higher than the ground voltage (ie, The gate-source voltage V GS(M23) of the sixth NMOS transistor (M23) and the source voltage of the other driving transistor (ie, the second NMOS transistor M12) in the selected unit cell (ie, the second The low voltage node VL2) is set to the ground voltage to prevent the difficulty of writing logic 1.

於讀取模式之第一階段時,將選定晶胞中較接近位元線(BL) 之驅動電晶體(即該第一NMOS電晶體M11)的源極電壓(即該第一低電壓節點VL1)設定成呈較接地電壓為低之該加速讀取電壓(RGND),該較接地電壓為低之該加速讀取電壓(RGND)可有效提高讀取速度,而於讀取模式之第二階段時,將選定晶胞中較接近位元線(BL)之驅動電晶體(即該第一NMOS電晶體M11)的源極電壓設定回接地電壓,以便減少無謂的功率消耗,其中該讀取模式之該第二階段與該第一階段相隔之時間,係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算,並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間,其值可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。 In the first phase of the read mode, the closer cell line (BL) in the selected cell will be selected. The source voltage of the driving transistor (ie, the first NMOS transistor M11) (ie, the first low voltage node VL1) is set to be the accelerated reading voltage (RGND) lower than the ground voltage, the grounding voltage The accelerated read voltage (RGND) is low to effectively increase the read speed, and in the second phase of the read mode, the drive transistor closer to the bit line (BL) in the selected cell is selected (ie, the first The source voltage of an NMOS transistor M11) is set back to the ground voltage to reduce unnecessary power consumption, wherein the second phase of the read mode is separated from the first phase by the read control signal (RC) The time from the logic low level to the logic high level, and until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), the value can be obtained by the third The falling delay time of the inverter (INV) is adjusted with the delay time provided by the first delay circuit (D1).

於待機模式時,將所有記憶晶胞中之驅動電晶體的源極電壓設定成較接地電壓為高之該預定電壓,以便降低漏電流;而於保持模式時則將記憶晶胞中之驅動電晶體的源極電壓設定成接地電壓,以便維持原來之保持特性,其詳細工作電壓位準如表1所示。 In the standby mode, the source voltage of the driving transistor in all the memory cells is set to the predetermined voltage higher than the ground voltage to reduce the leakage current; and in the hold mode, the driving power in the memory cell is The source voltage of the crystal is set to the ground voltage to maintain the original retention characteristics. The detailed operating voltage levels are shown in Table 1.

表1中之該寫入控制信號(WC)係為一寫入致能(Write Enable,簡稱WE)信號與對應之字元線(WL)信號的及閘(AND gate)運算結果,此時僅於該寫入致能(WE)信號與該對應之字元線(WL)信號均為邏輯高位準時,該寫入控制信號(WC)方為邏輯高位準;該讀取控制信號(RC)為一讀取致能(Read Enable,簡稱RE)信號與對應之字元線(WL)信號的及閘運算結果。在此值得注意的是,對於非選定字元線及非選定位元線係設定為浮接(floating)狀態,而對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準,以防止該第七NMOS電晶體(M24)之漏電流。 The write control signal (WC) in Table 1 is an AND gate operation result of a Write Enable (WE) signal and a corresponding word line (WL) signal. When the write enable (WE) signal and the corresponding word line (WL) signal are both at a logic high level, the write control signal (WC) is a logic high level; the read control signal (RC) is A read enable (RE) signal and a corresponding word line (WL) signal are gated. It is worth noting here that the unselected word line and the unselected positioning element line are set to a floating state, and the read control signal (RC) is set to the acceleration during the non-read mode. The level of the read voltage (RGND) is read to prevent leakage current of the seventh NMOS transistor (M24).

請參考第5圖,該預充電電路(3)係由一第三PMOS電晶體(P31)以及一預充電信號(P)所組成,該第三PMOS電晶體(P31)之源極、閘極與汲極係分別連接至電源供應電壓(VDD)、該預充電信號(P)與相對應之位元線(BL),以便於預充電期間,藉由邏輯低位準之該預充電信號(P),以將相對應之位元線(BL)預充電至該電源供應電壓(VDD)之位準。 Referring to FIG. 5, the precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P), and the source and gate of the third PMOS transistor (P31). Connected to the power supply voltage (V DD ), the pre-charge signal (P) and the corresponding bit line (BL), respectively, to facilitate the pre-charging signal by logic low level during pre-charging ( P), pre-charging the corresponding bit line (BL) to the level of the power supply voltage (V DD ).

請再參考第5圖,該待機啟動電路(4)係由一第四PMOS電晶體(P41)、一第十二NMOS電晶體(M41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成。該第四PMOS電晶體(P41)之源極、閘極與汲極係分別連接至電源供應電壓(VDD)、該反相待機模式控制信號(/S)與該第十二NMOS電晶體(M41)之汲極;該第十二NMOS電 晶體(M41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第四PMOS電晶體(P41)之汲極;該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S),而該延遲電路(D1)之輸出則連接至該第十二NMOS電晶體(M41)之閘極。 Referring to FIG. 5 again, the standby starting circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2), and the reverse standby. The mode control signal (/S) is composed of. The source, the gate and the drain of the fourth PMOS transistor (P41) are respectively connected to a power supply voltage (V DD ), the inverted standby mode control signal (/S) and the twelfth NMOS transistor ( a drain of M41); a source, a gate and a drain of the twelfth NMOS transistor (M41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) a drain of the fourth PMOS transistor (P41); an input of the second delay circuit (D2) is coupled to the inverted standby mode control signal (/S), and an output of the delay circuit (D1) is coupled to the The gate of the twelfth NMOS transistor (M41).

茲依單埠SRAM之工作模式說明第5圖之本發明較佳實施例的工作原理如下: The working principle of the preferred embodiment of the present invention in FIG. 5 is as follows:

(I)寫入模式(write mode) (I) write mode

於寫入操作開始前,該寫入控制信號(WC)為邏輯低位準、該反相寫入控制信號(/WC)為邏輯高位準,使得該第十一NMOS電晶體(M28)導通(ON),並使得該第十NMOS電晶體(M27)截止(OFF),於是該第十一NMOS電晶體(M28)之汲極呈邏輯高位準,該邏輯高位準之該第十一NMOS電晶體(M28)之汲極會導通該第九NMOS電晶體(M26),並使得該低電壓節點(VL1)呈接地電壓。 Before the start of the write operation, the write control signal (WC) is a logic low level, and the inverted write control signal (/WC) is a logic high level, so that the eleventh NMOS transistor (M28) is turned on (ON). And causing the tenth NMOS transistor (M27) to be turned off (OFF), so that the drain of the eleventh NMOS transistor (M28) is at a logic high level, and the logic is at a high level of the eleventh NMOS transistor ( The drain of M28) turns on the ninth NMOS transistor (M26) and causes the low voltage node (VL1) to be at a ground voltage.

而於寫入操作期間內,該寫入控制信號(WC)為邏輯高位準、該反相寫入控制信號(/WC)為邏輯低位準,使得該第十一NMOS電晶體(M28)截止,該第十NMOS電晶體(M27)導通,並使得該第十NMOS電晶體(M27)之汲極呈接地電壓,該接地電壓之該第十NMOS電晶體(M27)之汲極會使得該第九NMOS電晶體(M26)截止,並使得該低電壓節點(VL1)等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M26),藉此得以有效防止寫入邏輯1困難之問題。第6圖所示為第5圖之本發明較佳實施例於寫入期間之簡化電路圖。 During the write operation period, the write control signal (WC) is a logic high level, and the inverted write control signal (/WC) is a logic low level, so that the eleventh NMOS transistor (M28) is turned off. The tenth NMOS transistor (M27) is turned on, and the drain of the tenth NMOS transistor (M27) is grounded, and the drain of the tenth NMOS transistor (M27) of the ground voltage makes the ninth The NMOS transistor (M26) is turned off, and the low voltage node (VL1) is equal to the gate voltage V GS (M26) of the sixth NMOS transistor (M23 ) , thereby effectively preventing the problem of writing logic 1 . Figure 6 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during writing.

接下來依單埠SRAM之4種寫入狀態來說明第6圖之本發明較佳實施例如何完成寫入動作。 Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed depends on the four write states of the SRAM.

(一)節點A原本儲存邏輯0,而現在欲寫入邏輯0: (1) Node A originally stores a logic 0, but now wants to write a logic 0:

在寫入動作發生前(該字元線WL為接地電壓),該第一NMOS電晶體(M11)為導通(ON)。因為該第一NMOS電晶體(M11)為ON,所以當寫入動作開始時,該字元線(WL)由Low(接地電壓)轉High(電源供應電壓VDD)。當該字元線(WL)的電壓大於該第三NMOS電晶體(M13)(即存取電晶體)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為位元線(BL)是接地電壓,所以會將該節點A放電,而完成邏輯0的寫入動作,直到寫入週期結束。 Before the write operation occurs (the word line WL is a ground voltage), the first NMOS transistor (M11) is turned "ON". Since the first NMOS transistor (M11) is ON, the word line (WL) is turned from Low (ground voltage) to High (power supply voltage V DD ) when the write operation starts. When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned from off (OFF) to on ( ON), at this time, since the bit line (BL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle.

(二)節點A原本儲存邏輯0,而現在欲寫入邏輯1: (2) Node A originally stores logic 0, but now wants to write logic 1:

在寫入動作發生前(該字元線WL為接地電壓),該第一NMOS電晶體(M11)為導通(ON)。因為該第一NMOS電晶體(M11)為ON,所以當寫入動作開始時,該字元線(WL)由Low(接地電壓)轉High(該電源供應電壓VDD),該節點A的電壓會跟隨該字元線(WL)的電壓而上升。 Before the write operation occurs (the word line WL is a ground voltage), the first NMOS transistor (M11) is turned "ON". Since the first NMOS transistor (M11) is ON, when the writing operation starts, the word line (WL) is turned from Low (ground voltage) to High (the power supply voltage V DD ), and the voltage of the node A It will rise following the voltage of the word line (WL).

當該字元線(WL)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為該位元線(BL)是High(該電源供應電壓VDD),並且因為該第一NMOS電晶體(M11)仍為ON且該節點B仍處於電壓位準為接近於該電源供應電壓(VDD)之電壓位準的初始狀態,所以該第一PMOS電晶體(P11) 仍為截止(OFF),而該節點A則會朝一分壓電壓位準快速充電,該分壓電壓位準等於(RM11+RM23)/(RM13+RM11+RM23)乘以該電源供應電壓(VDD),其中該RM13表示該第三NMOS電晶體(M13)之導通等效電阻,該RM11表示該第一NMOS電晶體(M11)之導通等效電阻,而該RM23表示該第六NMOS電晶體(M23)之導通等效電阻,此時因為第三NMOS電晶體(M13)仍工作於飽和區(saturation region)且該第一NMOS電晶體(M11)仍工作於線性區(triode region),雖然該第三NMOS電晶體(M13)之導通等效電阻(RM13)會遠大於該第一NMOS電晶體(M11)之導通等效電阻(RM11),但由於該第六NMOS電晶體(M23)係呈二極體連接,因此可於該第一低電壓節點(VL1)處提供一等於該第六NMOS電晶體(M23)之閘-源極電壓VGS(M23)之電壓位準,結果節點A所呈現的該分壓電壓位準,其電壓值會比第4圖之習知5T靜態隨機存取記憶體晶胞之該節點A之電壓位準還要高許多。該還要高許多之分壓電壓位準足以使該第二NMOS電晶體(M12)導通,於是使得節點B放電至一較低電壓位準,該節點B之較低電壓位準會使得該第一NMOS電晶體(M11)之導通等效電阻(RM11)呈現較高的電阻值,該第一NMOS電晶體(M11)之該較高的電阻值會於該節點A獲得較高電壓位準,該節點A之較高電壓位準又會經由該第二反相器(由第二PMOS電晶體P12與第二NMOS電晶體M12所組成),而使得該節點B呈現更低電壓位準,該節點B之更低電壓位準又會經由該第一反相器(由第一PMOS電晶體P11與第一NMOS電晶體M11所組成),而使得該節點A獲得更高電壓位準,依此循環,即可將該節點A充電至該電源供應電壓(VDD),而完成邏輯1的寫入動作。 When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON, because The bit line (BL) is High (the power supply voltage V DD ), and because the first NMOS transistor (M11) is still ON and the node B is still at a voltage level close to the power supply voltage (V DD ) The initial state of the voltage level, so the first PMOS transistor (P11) is still off (OFF), and the node A is rapidly charged toward a divided voltage level, the divided voltage level is equal to (R M11 + R M23 ) / (R M13 + R M11 + R M23 ) multiplied by the power supply voltage (V DD ), wherein the R M13 represents the on-resistance equivalent resistance of the third NMOS transistor (M13), the R M11 Indicates the on-resistance equivalent resistance of the first NMOS transistor (M11), and the R M23 represents the on-resistance equivalent resistance of the sixth NMOS transistor (M23), because the third NMOS transistor (M13) is still operating at this time. saturation region (saturation region) and the first NMOS transistor (M11) is still operating in the linear region (triode region), while guiding the third NMOS transistor (M13) through the equivalent resistance (R M13) may lofty The first NMOS transistor (M11) is turned the equivalent resistance (R M11), but since the sixth NMOS transistor (M23) diodes is connected as a system, it is possible to lower the first node voltage (VL1) at Providing a voltage level equal to the gate-source voltage V GS (M23) of the sixth NMOS transistor (M23), and the resulting voltage level of the node A is higher than that of FIG. The voltage level of the node A of the conventional 5T static random access memory cell is much higher. The much higher voltage division voltage level is sufficient to turn on the second NMOS transistor (M12), thus causing the node B to discharge to a lower voltage level, and the lower voltage level of the node B causes the first The on-resistance equivalent (R M11 ) of an NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) obtains a higher voltage level at the node A. The higher voltage level of the node A is again caused by the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level. The lower voltage level of the node B is again passed through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level. In this cycle, the node A can be charged to the power supply voltage (V DD ), and the logic 1 write operation is completed.

在此值得注意的是,該第一低電壓節點VL1於節點A原本儲存邏輯0,而正寫入邏輯1之期間,係具有等於該第六NMOS電晶體(M23)之閘源極電壓VGS(M23)的電壓位準,而於寫入邏輯1後,又會因經由該第九NMOS電晶體(M26)放電而具有接地電壓之位準。 It should be noted here that the first low voltage node VL1 originally stores a logic 0 at the node A, and has a gate source voltage V GS equal to the sixth NMOS transistor (M23) while the logic 1 is being written. The voltage level of (M23) , after writing logic 1, will have the level of the ground voltage due to discharge through the ninth NMOS transistor (M26).

(三)節點A原本儲存邏輯1,而現在欲寫入邏輯1: (3) Node A originally stores logic 1, but now wants to write logic 1:

在寫入動作發生前(該字元線WL為接地電壓),該第一PMOS電晶體(P11)為導通(ON)。當該字元線(WL)由Low(接地電壓)轉High(該電源供應電壓VDD),且該字元線(WL)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON);此時因為該位元線(BL)是High(該電源供應電壓VDD),並且因為該第一PMOS電晶體(P11)仍為ON,所以該節點A的電壓會維持於該電源供應電壓(VDD)之電壓位準,直到寫入週期結束。 Before the write operation occurs (the word line WL is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line (WL) is turned from Low (ground voltage) to High (the power supply voltage V DD ), and the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M13), The third NMOS transistor (M13) is turned from OFF to ON; at this time, since the bit line (BL) is High (the power supply voltage V DD ), and because the first PMOS transistor (P11) is still ON, so the voltage of the node A will be maintained at the voltage level of the power supply voltage (V DD ) until the end of the write cycle.

(四)節點A原本儲存邏輯1,而現在欲寫入邏輯0: (4) Node A originally stores logic 1, but now wants to write logic 0:

在寫入動作發生前(該字元線WL為接地電壓),該第一PMOS電晶體(P11)為導通(ON)。當該字元線(WL)由Low(接地電壓)轉High(該電源供應電壓VDD),且該字元線(WL)的電壓大於該第三NMOS電晶體(M13)的臨界電壓時,該第三NMOS電晶體(M13)由截止(OFF)轉變為導通(ON),此時因為該位元線(BL)是Low(接地電壓),所以會將該節點A以及該第一低電壓節點(VL1)放電而完成邏輯0的寫入動作,直到寫入週期結束。 Before the write operation occurs (the word line WL is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line (WL) is turned from Low (ground voltage) to High (the power supply voltage V DD ), and the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M13), The third NMOS transistor (M13) is turned from off (OFF) to on (ON). At this time, since the bit line (BL) is Low (ground voltage), the node A and the first low voltage are The node (VL1) is discharged to complete the write operation of logic 0 until the end of the write cycle.

第6圖所示之本發明較佳實施例,於寫入操作時之HSPICE暫態分析模擬結果,如第7圖所示,其係使用TSMC 90奈米CMOS製程參數加以模擬,由該模擬結果可証實,本發明所提出之單埠靜態隨機存取記憶體,能藉由寫入期間提高該第一低電壓節點(VL1)之電壓位準,以有效避免習知具單一位元線之單埠靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 In the preferred embodiment of the present invention shown in FIG. 6, the HSPICE transient analysis simulation result during the write operation, as shown in FIG. 7, is simulated using the TSMC 90 nm CMOS process parameters, from which the simulation result is obtained. It can be confirmed that the static random access memory proposed by the present invention can improve the voltage level of the first low voltage node (VL1) during the writing period, thereby effectively avoiding the single single bit line.埠 Static random access memory cells have the problem of writing logic 1 quite difficult.

(II)讀取模式(read mode) (II) Read mode (read mode)

於讀取操作開始前,該讀取控制信號(RC)、寫入控制信號(WC)及該待機模式控制信號(S)均為邏輯低位準,使得該第十一NMOS電晶體(M28)導通,並使得該第十NMOS電晶體(M27)截止,於是該第十一NMOS電晶體(M28)之汲極呈邏輯高位準,邏輯高位準之該第十一NMOS電晶體(M28)之汲極會導通第九NMOS電晶體(M26),並使得該第一低電壓節點(VL1)呈接地電壓。另一方面,由於該讀取控制信號(RC)為邏輯低位準,使得該第七NMOS電晶體(M24)截止(OFF),並使得該第八NMOS電晶體(M25)導通(ON)。 The read control signal (RC), the write control signal (WC), and the standby mode control signal (S) are both logic low levels before the start of the read operation, so that the eleventh NMOS transistor (M28) is turned on. And causing the tenth NMOS transistor (M27) to be turned off, so that the drain of the eleventh NMOS transistor (M28) is at a logic high level, and the logic high level is the drain of the eleventh NMOS transistor (M28) The ninth NMOS transistor (M26) is turned on, and the first low voltage node (VL1) is grounded. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned "ON".

第6圖所示之本發明較佳實施例係藉由二階段的讀取控制以於提高讀取速度的同時,亦避免無謂的功率耗損,於讀取操作之第一階段,該讀取控制信號(RC)為邏輯高位準,使得該第七NMOS電晶體(M24)導通,由於此時該第八NMOS電晶體(M25)仍導通,於是該第一低電壓節點(VL1)呈較接地電壓為低之該加速讀取電壓(RGND),該較接地電壓為低之該加速讀取電壓(RGND)可有效提高讀取速度。 The preferred embodiment of the present invention shown in FIG. 6 is controlled by two stages to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the reading operation, the reading control The signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the first low voltage node (VL1) is at a ground voltage. To lower the accelerated read voltage (RGND), the accelerated read voltage (RGND), which is lower than the ground voltage, can effectively increase the read speed.

而於讀取操作之第二階段,雖然該讀取控制信號(RC)仍為邏輯高位準,使得該第七NMOS電晶體(M24)仍為導通,惟由於此時該第八NMOS電晶體(M25)截止,於是該第一低電壓節點(VL1)會經由導通的該第九NMOS電晶體(M26)而呈接地電壓,藉此可有效減少無謂的功率消耗。在此值得注意的是,該讀取操作之該第二階段與該第一階段相隔之時間,係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算,並至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間,其值可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路(D1)所提供之延遲時間來調整。再者,無論於讀取操作之第一階段抑是第二階段,該第九NMOS電晶體(M26)均呈導通狀態(由於該第九NMOS電晶體(M26)之閘極為電源供應電壓VDD之位準)。第8圖所示為第5圖之本發明較佳實施例於讀取期間之簡化電路圖。 In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but since the eighth NMOS transistor (at this time) M25) is turned off, so that the first low voltage node (VL1) is grounded via the turned-on ninth NMOS transistor (M26), thereby effectively reducing unnecessary power consumption. It is worth noting here that the second phase of the read operation is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the The gate voltage of the eight NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), and the value thereof can be decreased by the delay time of the third inverter (INV) and the first delay circuit. (D1) The delay time provided is adjusted. Furthermore, the ninth NMOS transistor (M26) is in an on state regardless of the first phase of the read operation or the second phase (since the gate of the ninth NMOS transistor (M26) is substantially the power supply voltage V DD The standard). Figure 8 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during reading.

(III)待機模式(standby mode) (III) Standby mode

首先,說明第5圖之待機啟動電路(4)如何促使單埠SRAM快速進入待機模式,以有效提高SRAM之待機效能:(1)於進入待機模式之前,該反相待機模式控制信號(/S)為邏輯High,該邏輯High之反相待機模式控制信號(/S)使得該第四PMOS電晶體(P41)截止(OFF),並使得該第十二NMOS電晶體(M41)導通(ON);(2)而於進入待機模式後,該反相待機模式控制信號(/S)為邏輯Low,該邏輯Low之反相待機模式控制信號(/S)使得該第四PMOS電晶體(P41)導通(ON),惟於待機模式之初始期間內(該初始期間係等於該反相待機模式控制信號(/S)由邏輯High轉變為邏輯 Low起算,至該第十二NMOS電晶體(M41)之閘極電壓足以關閉該第十二NMOS電晶體(M41)為止之時間,其可藉由該第二延遲電路(D2)所提供之一延遲時間來調整),該第十二NMOS電晶體(M41)仍導通(ON),於是可對該第一低電壓節點(VL1)快速充電到達該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準,亦即單埠SRAM可快速進入待機模式。在此值得注意的是,於待機模式之初始期間後,該第十二NMOS電晶體(M41)關閉並停止供應電流。 First, how the standby start circuit (4) of Fig. 5 causes the 單埠SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: (1) the reverse standby mode control signal (/S) before entering the standby mode. Is logic High, the logic high inversion standby mode control signal (/S) causes the fourth PMOS transistor (P41) to be turned off (OFF), and causes the twelfth NMOS transistor (M41) to be turned on (ON) (2) After entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fourth PMOS transistor (P41) Turned on (ON), but during the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from logic High to logic Low, to the twelfth NMOS transistor (M41) The gate voltage is sufficient to turn off the twelfth NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2), the twelfth NMOS transistor ( M41) is still turned on (ON), so the first low voltage node (VL1) can be quickly charged to reach the sixth NMOS transistor (M2) 3) The voltage level of the threshold voltage (V TM23 ), that is, the 單 SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (M41) is turned off and the supply current is stopped.

請參考第5圖,於待機模式時,該待機模式控制信號(S)為邏輯高位準,而該反相待機模式控制信號(/S)為邏輯低位準,該邏輯低位準之該反相待機模式控制信號(/S)可使得該控制電路(2)中之該第四NMOS電晶體(M21)截止(OFF),而該邏輯高位準之該待機模式控制信號(S)則使得該第五NMOS電晶體(M22)導通(ON),此時該第五NMOS電晶體(M22)係作為等化器(equalizer)使用,因此可藉由呈導通狀態之該第五NMOS電晶體(M22),以使得該第一低電壓節點(VL1)之電壓位準相等於該第二低電壓節點(VL2)之電壓位準,且該等電壓位準均會等於該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準。第9圖所示為第5圖之本發明較佳實施例於待機期間之簡化電路圖。 Referring to FIG. 5, in the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (M21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (M22) is turned on (ON), and the fifth NMOS transistor (M22) is used as an equalizer, so that the fifth NMOS transistor (M22) in an on state can be used. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V TM23 ). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during standby.

接下來說明本發明於待機模式(standby mode)時如何減少漏電流,請參考第9圖,第9圖描述有本發明實施例處於待機模式時所產生之各漏電流(subthreshold leakage current)I1、I2、I3,其中假設SRAM晶胞中之該第一反相器之輸出(即節點A)為邏輯Low(在此值得注意的是,由於待機模式時該第二低電壓節點(VL2)之電壓位準係維持在該第六NMOS 電晶體(M23)之臨界電壓(VTM23)的電壓位準,因此節點A為邏輯Low之電壓位準亦維持在該VTM23的電壓位準),而該第二反相器之輸出(即節點B)為邏輯High(電源供應電壓VDD)。請參考第1b圖之先前技藝與第9圖之本發明實施例,來說明本發明所提出之靜態隨機存取記憶體與第1b圖之6T SRAM於漏電流方面之比較,首先關於流經該第三NMOS電晶體(M13)之漏電流I1,由於本發明於待機模式時節點A之電壓位準係維持在該VTM23的電壓位準,且假設字元線(WL)於待機模式時係設定成接地電壓,而位元線(BL)於待機模式時則設定為該電源供應電壓(VDD),因此本發明之第三NMOS電晶體(M13)的閘源極電壓(VGS)為負值,反觀於待機模式時第1b圖先前技藝之NMOS電晶體(M3)的閘源極電壓(VGS)等於0,根據閘極引發汲極洩漏(Gate Induced Drain Leakage,簡稱GIDL)效應或2005年3月8日第US6865119號專利案第3(A)及3(B)圖之結果可知,對於NMOS電晶體而言,閘源極電壓為-0.1伏特時之次臨界電流約為閘源極電壓為0伏特時之次臨界電流的1%,因此導因於GIDL效應所引發之流經本發明之該第三NMOS電晶體(M13)之漏電流I1遠小於第1b圖先前技藝之NMOS電晶體(M3)者;再者,本發明該第三NMOS電晶體(M13)之汲源極電壓(VDS)為該電源供應電壓(VDD)扣減該VTM23的電壓位準,反觀於待機模式時傳統第1b圖6T靜態隨機存取記憶體之NMOS電晶體(M3)之汲源極電壓(VDS)係等於該電源供應電壓(VDD),根據汲極引發能障下跌(Drain-Induced Barrier Lowering,簡稱DIBL)效應,由於DIBL效應所引發之流經本發明之該第三NMOS電晶體(M13)之漏電流I1亦小於第1b圖先前技藝之NMOS電晶體(M3)者;結果,流經本發明之該第三NMOS電晶體 (M13)之漏電流I1遠小於第1b圖先前技藝之NMOS電晶體(M3)者。 Next, how to reduce leakage current in the standby mode of the present invention will be described. Referring to FIG. 9, FIG. 9 depicts a leakage current I 1 generated when the embodiment of the present invention is in the standby mode. I 2 , I 3 , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage node (VL2) due to the standby mode The voltage level is maintained at the voltage level of the threshold voltage (V TM23 ) of the sixth NMOS transistor (M23), so that the voltage level of the node A is logic Low is also maintained at the voltage level of the V TM23 ) And the output of the second inverter (ie, node B) is a logic high (power supply voltage V DD ). Referring to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 9, the comparison between the static random access memory of the present invention and the 6T SRAM of FIG. 1b in terms of leakage current is first described. Leakage current I 1 of the third NMOS transistor (M13), since the voltage level of the node A is maintained at the voltage level of the V TM 23 in the standby mode, and the word line (WL) is assumed to be in the standby mode. The ground voltage is set, and the bit line (BL) is set to the power supply voltage (V DD ) in the standby mode, so the gate-source voltage (V GS ) of the third NMOS transistor (M13) of the present invention is set. Negative value, in contrast to the standby mode, the gate-source voltage (V GS ) of the prior art NMOS transistor (M3) of Fig. 1b is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect. Or, as shown in the results of Figures 3(A) and 3(B) of the US Pat. No. 6,865,119, issued March 8, 2005, it is known that for an NMOS transistor, the sub-critical current of the gate-source voltage is -0.1 volt is approximately the gate. The source voltage is 1% of the subcritical current at 0 volts, and thus is caused by the GIDL effect and flows through the present invention. The leakage current I 1 of the third NMOS transistor (M13) is much smaller than that of the prior art NMOS transistor (M3) of FIG. 1b; further, the threshold voltage of the third NMOS transistor (M13) of the present invention ( V DS ) deducts the voltage level of the V TM23 for the power supply voltage (V DD ), and the source voltage of the NMOS transistor (M3) of the conventional 1b FIG. 6T SRAM is in the standby mode. (V DS ) is equal to the power supply voltage (V DD ), according to the Drain-Induced Barrier Lowering (DIBL) effect, the third NMOS transistor flowing through the present invention due to the DIBL effect (M13) the drain current I 1 is also smaller than the prior art of FIG. 1b NMOS transistor (M3) are; As a result, the third NMOS transistor (M13) of the present invention to flow through the drain current I 1 is much smaller than the previous section in FIG. 1b The NMOS transistor (M3) of the art.

接著關於流經該第一PMOS電晶體(P11)之漏電流I2,由於待機模式時該第一PMOS電晶體(P11)之源極係為該電源供應電壓(VDD),而該第一PMOS電晶體(P11)之汲極係維持在該該VTM23的電壓位準,因此本發明之該第一PMOS電晶體(P11)之源汲極電壓(VSD)為該電源供應電壓(VDD)扣減該VTM23的電壓位準,反觀於待機模式時第1b圖先前技藝之PMOS電晶體(P1)之源汲極電壓(VSD)係等於該電源供應電壓(VDD),根據DIBL效應,因此流經本發明之該第一PMOS電晶體(P11)之漏電流I2會小於第1b圖先前技藝之PMOS電晶體(P1)者。 Next, regarding the leakage current I 2 flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (V DD ) due to the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the VTM23 , so the source drain voltage (V SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V) DD ) deducting the voltage level of the V TM23 , in contrast to the standby source mode, the source drain voltage (V SD ) of the prior art PMOS transistor (P1) is equal to the power supply voltage (V DD ), according to The DIBL effect, therefore, the leakage current I 2 flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P1) of Figure 1b.

最後,關於流經該第二NMOS電晶體(M12)之漏電流I3,由於待機模式時該第二低電壓節點(VL2)之電壓位準係維持在該VTM23的電壓位準,節點A之電壓位準亦維持在該VTM23的電壓位準,而節點B之電壓位準係等於該電源供應電壓(VDD)且該第二NMOS電晶體(M12)之基底為接地電壓,因此本發明之該第二NMOS電晶體(M12)的基源極電壓(VBS)為負值,且該第二NMOS電晶體(M12)之汲源極電壓(VDS)為該電源供應電壓(VDD)扣減該VTM23的電壓位準,反觀於待機模式時第1b圖先前技藝之NMOS電晶體(M2)的基源極電壓(VBS)等於0,且NMOS電晶體(M2)之汲源極電壓(VDS)等於該電源供應電壓(VDD),根據本體效應(body effect)及DIBL效應可知,流經本發明之該第二NMOS電晶體(M12)之漏電流I3遠小於第1b圖先前技藝之NMOS電晶體(M2)者。由上述分析可知,本發明所提出之單埠靜態隨機存取記憶體與第1b圖先前技藝相較具有較低之漏電流。 Finally, regarding the leakage current I 3 flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the VTM23 in the standby mode, the node A The voltage level is also maintained at the voltage level of the V TM23 , and the voltage level of the node B is equal to the power supply voltage (V DD ) and the base of the second NMOS transistor (M12) is the ground voltage, so The base-source voltage (V BS ) of the second NMOS transistor (M12) of the invention is a negative value, and the 汲 source voltage (V DS ) of the second NMOS transistor (M12) is the power supply voltage (V) DD ) deducting the voltage level of the V TM23 , in contrast to the standby mode, the base-source voltage (V BS ) of the prior art NMOS transistor (M2) of FIG. 1b is equal to 0, and the NMOS transistor (M2) The source voltage (V DS ) is equal to the power supply voltage (V DD ). According to the body effect and the DIBL effect, the leakage current I 3 flowing through the second NMOS transistor (M12) of the present invention is much smaller than the first 1b is a prior art NMOS transistor (M2). It can be seen from the above analysis that the 單埠 static random access memory proposed by the present invention has a lower leakage current than the prior art of Fig. 1b.

(IV)保持模式(hold mode) (IV) hold mode

保持模式時,由於該第一低電壓節點(VL1)與該第二低電壓節點(VL2)均設定成接地電壓,其工作原理相同於第3圖傳統具單一位元線之5T SRAM晶胞,於此不再累述。 In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to a ground voltage, the working principle is the same as that of the conventional 5T SRAM cell with a single bit line in FIG. This is not repeated here.

【發明功效】 【Effects of invention】

本發明所提出之單埠靜態隨機存取記憶體,具有如下功效:(1)快速進入待機模式:由於本發明所提出之單埠靜態隨機存取記憶體設置有待機啟動電路(4)以促使SRAM快速進入待機模式,並藉此以謀求提高單埠SRAM之待機效能;(2)避免寫入邏輯1困難之問題:本發明所提出之單埠靜態隨機存取記憶體於寫入操作時,可藉由提高該第一低電壓節點(VL1)之電壓位準以有效避免習知具單一位元線之單埠SRAM存在寫入邏輯1相當困難之問題;(3)高讀取速度並避免無謂的功率消耗:本發明所提出之單埠靜態隨機存取記憶體係採用二階段讀取操作,於讀取操作之第一階段藉由將該第一低電壓節點(VL1)設定成較接地電壓為低之該加速讀取電壓(RGND)以有效提高讀取速度,而於讀取操作之第二階段則藉由將該第一低電壓節點(VL1)設定回接地電壓,以便減少無謂的功率消耗;(4)低待機電流:由於本發明所提出之單埠靜態隨機存取記憶體於待機模式時,可藉由呈導通狀態之該第五NMOS電晶體(M22),以使得該第一低電壓節點(VL1)之電壓位準相等於該第二低電壓節點(VL2)之電壓位準,並使得該等電壓位準均等於該第六NMOS電晶體(M23)之臨界電壓的位準,因此本發明所提出之單埠靜態隨機存取記憶體亦具備低待機電流之功效;(5)低電晶體數:對於具有1024列1024行之SRAM陣列而言,傳統第1b圖6T 靜態隨機存取記憶體陣列共需1024×1024×6=6,291,456顆電晶體,而本發明所提出之靜態隨機存取記憶體僅至少需1024×1024×5+1024×16+6=5,259,270顆電晶體,其減少16.4%之電晶體數。 The static random access memory proposed by the present invention has the following effects: (1) fast entry standby mode: since the static random access memory proposed by the present invention is provided with a standby start circuit (4) to promote SRAM quickly enters the standby mode, and thereby seeks to improve the standby performance of the SRAM; (2) avoids the problem of writing logic 1: the static random access memory proposed by the present invention is in the write operation. The problem of writing the logic 1 can be effectively avoided by increasing the voltage level of the first low voltage node (VL1); (3) high read speed and avoidance Unnecessary power consumption: The static random access memory system proposed by the present invention employs a two-stage read operation in which the first low voltage node (VL1) is set to a ground voltage in the first phase of the read operation. The accelerated read voltage (RGND) is low to effectively increase the read speed, and in the second phase of the read operation, the first low voltage node (VL1) is set back to the ground voltage to reduce unnecessary power. Consumption; (4) low waiting Current: Since the static random access memory proposed by the present invention is in the standby mode, the fifth NMOS transistor (M22) in an on state can be used to make the first low voltage node (VL1) The voltage level is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the level of the threshold voltage of the sixth NMOS transistor (M23), and thus the present invention proposes單埠Static random access memory also has the effect of low standby current; (5) Low transistor number: For SRAM array with 1024 columns and 1024 rows, the traditional 1b Figure 6T The static random access memory array requires a total of 1024 × 1024 × 6 = 6,291,456 transistors, and the static random access memory proposed by the present invention only needs at least 1024 × 1024 × 5 + 1024 × 16 + 6 = 5,259,270 Crystal, which reduces the number of transistors by 16.4%.

雖然本發明特別揭露並描述了所選之較佳實施例,但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本發明的精神與範圍。因此,所有相關技術範疇內之改變都包括在本發明之申請專利範圍內。 While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

1‧‧‧SRAM晶胞 1‧‧‧SRAM cell

2‧‧‧控制電路 2‧‧‧Control circuit

3‧‧‧預充電電路 3‧‧‧Precharge circuit

4‧‧‧待機啟動電路 4‧‧‧Standby start circuit

P11‧‧‧第一PMOS電晶體 P11‧‧‧First PMOS transistor

P12‧‧‧第二PMOS電晶體 P12‧‧‧Second PMOS transistor

M11‧‧‧第一NMOS電晶體 M11‧‧‧First NMOS transistor

M12‧‧‧第二NMOS電晶體 M12‧‧‧Second NMOS transistor

M13‧‧‧第三NMOS電晶體 M13‧‧‧ Third NMOS transistor

A‧‧‧儲存節點 A‧‧‧ storage node

B‧‧‧反相儲存節點 B‧‧‧ Inverting storage node

VDD‧‧‧電源供應電壓 V DD ‧‧‧Power supply voltage

BL‧‧‧位元線 BL‧‧‧ bit line

WL‧‧‧字元線 WL‧‧‧ character line

S‧‧‧待機模式控制信號 S‧‧‧Standby mode control signal

/S‧‧‧反相待機模式控制信號 /S ‧‧‧Inverted standby mode control signal

VL1‧‧‧第一低電壓節點 VL1‧‧‧ first low voltage node

VL2‧‧‧第二低電壓節點 VL2‧‧‧ second low voltage node

M21‧‧‧第四NMOS電晶體 M21‧‧‧4th NMOS transistor

M22‧‧‧第五NMOS電晶體 M22‧‧‧ Fifth NMOS transistor

M23‧‧‧第六NMOS電晶體 M23‧‧‧ sixth NMOS transistor

M24‧‧‧第七NMOS電晶體 M24‧‧‧ seventh NMOS transistor

M25‧‧‧第八NMOS電晶體 M25‧‧‧8th NMOS transistor

M26‧‧‧第九NMOS電晶體 M26‧‧‧Ninth NMOS transistor

M27‧‧‧第十NMOS電晶體 M27‧‧‧ tenth NMOS transistor

M28‧‧‧第十一NMOS電晶體 M28‧‧‧11th NMOS transistor

RC‧‧‧讀取控制信號 RC‧‧‧ read control signal

RGND‧‧‧加速讀取電壓 RGND‧‧‧Accelerated reading voltage

WC‧‧‧寫入控制信號 WC‧‧‧ write control signal

/WC‧‧‧反相寫入控制信號 /WC‧‧‧Inverted write control signal

C‧‧‧節點 C‧‧‧ node

D1‧‧‧第一延遲電路 D1‧‧‧First delay circuit

P31‧‧‧第三PMOS電晶體 P31‧‧‧ Third PMOS transistor

P‧‧‧預充電信號 P‧‧‧Precharge signal

M41‧‧‧第十二NMOS電晶體 M41‧‧‧12th NMOS transistor

P41‧‧‧第四PMOS電晶體 P41‧‧‧4th PMOS transistor

D2‧‧‧第二延遲電路 D2‧‧‧second delay circuit

INV‧‧‧第三反相器 INV‧‧‧ third inverter

Claims (8)

一種單埠靜態隨機存取記憶體,包括:一記憶體陣列,該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成,每一列記憶體晶胞與每一行記憶體晶胞均包含有複數個記憶體晶胞(1);複數個控制電路(2),每一列記憶體晶胞設置一個控制電路(2);複數個預充電電路(3),每一行記憶晶胞設置一個預充電電路(3);以及一待機啟動電路(4),該待機啟動電路(4)係促使該單埠靜態隨機存取記憶體快速進入待機模式,以有效提高該單埠靜態隨機存取記憶體之待機效能;其中,每一記憶體晶胞(1)更包含:一第一反相器,係由一第一PMOS電晶體(P11)與一第一NMOS電晶體(M11)所組成,該第一反相器係連接在一電源供應電壓(VDD)與一第一低電壓節點(VL1)之間;一第二反相器,係由一第二PMOS電晶體(P12)與一第二NMOS電晶體(M12)所組成,該第二反相器係連接在該電源供應電壓(VDD)與一第二低電壓節點(VL2)之間;一儲存節點(A),係由該第一反相器之輸出端所形成;一反相儲存節點(B),係由該第二反相器之輸出端所形成;一第三NMOS電晶體(M13),係連接在該儲存節點(A)與一對應之位元線(BL)之間,且閘極連接至一對應之字元線(WL);其中,該第一反相器和該第二反相器係呈交互耦合連接,亦即該第一反相器之輸出端(即該儲存節點A)係連接至該第二反相器之輸入端,而該第二反相器之輸出端(即該反相儲存節點B)則連接至該第一反相器之輸入端;而每一控制電路(2)更包含:一第四NMOS電晶體(M21)、一第五NMOS電晶體(M22)、一第六NMOS電晶體(M23)、一第七NMOS電晶體(M24)、一第八NMOS電晶體(M25)、一第九NMOS電晶體(M26)、一第十NMOS電晶體(M27)、一第十一NMOS電晶體(M28)、一讀取 控制信號(RC)、一第三反相器(INV)、一第一延遲電路(D1)、一加速讀取電壓(RGND)、一寫入控制信號(WC)、一反相寫入控制信號(/WC)、一待機模式控制信號(S)以及一反相待機模式控制信號(/S);其中,該第四NMOS電晶體(M21)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與該第二低電壓節點(VL2);該第五NMOS電晶體(M22)之源極、閘極與汲極係分別連接至該第二低電壓節點(VL2)、該待機模式控制信號(S)與該第一低電壓節點(VL1);該第六NMOS電晶體(M23)之源極係連接至接地電壓,而閘極與汲極連接在一起並連接至該第一低電壓節點(VL1);該第七NMOS電晶體(M24)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M25)之汲極、該讀取控制信號(RC)與該第一低電壓節點(VL1);該第八NMOS電晶體(M25)之源極、閘極與汲極係分別連接至該加速讀取電壓(RGND)、該第一延遲電路(D1)之輸出與該第七NMOS電晶體(M24)之源極;該第一延遲電路(D1)係連接在該第三反相器(INV)之輸出與該第八NMOS電晶體(M25)之閘極之間;該第三反相器(INV)之輸入係供接收該讀取控制信號(RC),而輸出則連接至該第一延遲電路(D1)之輸入;該第九NMOS電晶體(M26)之源極、閘極與汲極係分別連接至接地電壓、該第十NMOS電晶體(M27)之汲極和該第十一NMOS電晶體(M28)與該第一低電壓節點(VL1);該第十NMOS電晶體(M27)之源極、閘極與汲極係分別連接至接地電壓、該寫入控制信號(WC)與該第九NMOS電晶體(M26)之閘極;該第十一NMOS電晶體(M28)之源極、閘極與汲極係分別連接至該反相待機模式控制信號(/S)、該反相寫入控制信號(/WC)與該第十NMOS電晶體(M27)之汲極;其中,對於非讀取模式期間之該讀取控制信號(RC)係設定為該加速讀取電壓(RGND)之位準,以防止該第七NMOS電晶體(M24)於非讀取 模式期間之漏電流;再者,該待機啟動電路(4)係設計成於進入待機模式之一初始期間內,對該第一低電壓節點(VL1)處之寄生電容快速充電至該第六NMOS電晶體(M23)之臨界電壓(VTM23)的電壓位準。 A static random access memory, comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each row of memory The unit cell comprises a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory crystals The cell is provided with a pre-charging circuit (3); and a standby starting circuit (4) for causing the static random access memory to quickly enter the standby mode to effectively improve the static random random Accessing the standby performance of the memory; wherein each memory cell (1) further comprises: a first inverter, comprising a first PMOS transistor (P11) and a first NMOS transistor (M11) The first inverter is connected between a power supply voltage (V DD ) and a first low voltage node (VL1); and a second inverter is connected by a second PMOS transistor (P12). And a second NMOS transistor (M12) connected to the power supply (V DD) between the node and a second low voltage (VL2); a storage node (A), the line is formed by a first output terminal of the inverter; inverting a storage node (B), the Department of Forming an output of the second inverter; a third NMOS transistor (M13) is connected between the storage node (A) and a corresponding bit line (BL), and the gate is connected to a corresponding a word line (WL); wherein the first inverter and the second inverter are connected in an alternating coupling, that is, an output end of the first inverter (ie, the storage node A) is connected to An input end of the second inverter, and an output end of the second inverter (ie, the inverting storage node B) is connected to an input end of the first inverter; and each control circuit (2) The method further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), and an eighth NMOS transistor ( M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control signal (RC), and a third inverter ( INV), a first delay circuit (D1), an accelerated reading power (RGND), a write control signal (WC), an inverted write control signal (/WC), a standby mode control signal (S), and an inverted standby mode control signal (/S); wherein the The source, gate and drain of the four NMOS transistors (M21) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and the second low voltage node (VL2); the fifth NMOS a source, a gate and a drain of the crystal (M22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and the first low voltage node (VL1); the sixth NMOS The source of the transistor (M23) is connected to the ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); the source and gate of the seventh NMOS transistor (M24) The pole and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); and the eighth NMOS transistor (M25) a source, a gate and a drain are respectively connected to the accelerated read voltage (RGND), an output of the first delay circuit (D1), and a source of the seventh NMOS transistor (M24); the first delay circuit (D1) Connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving the read control signal ( RC), and the output is connected to the input of the first delay circuit (D1); the source, the gate and the drain of the ninth NMOS transistor (M26) are respectively connected to a ground voltage, the tenth NMOS transistor a drain of (M27) and the eleventh NMOS transistor (M28) and the first low voltage node (VL1); a source, a gate and a drain of the tenth NMOS transistor (M27) are respectively connected to a ground voltage, the write control signal (WC) and a gate of the ninth NMOS transistor (M26); the source, the gate and the drain of the eleventh NMOS transistor (M28) are respectively connected to the opposite a phase standby mode control signal (/S), the inverted write control signal (/WC) and a drain of the tenth NMOS transistor (M27); wherein the read control signal during the non-read mode ( RC) is set to the level of the accelerated read voltage (RGND) to prevent leakage current of the seventh NMOS transistor (M24) during the non-read mode; further, the standby start circuit (4) is designed Entering During one of the standby modes, the parasitic capacitance at the first low voltage node (VL1) is rapidly charged to the voltage level of the threshold voltage ( VTM23 ) of the sixth NMOS transistor (M23). 如申請專利範圍第1項所述之單埠靜態隨機存取記憶體,其中,該反相待機模式控制信號(/S)係由該待機模式控制信號(S)經一反相器而獲得,且該反相寫入控制信號(/WC)係由該寫入控制信號(WC)經另一反相器而獲得。 The static random access memory according to claim 1, wherein the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter. And the inverted write control signal (/WC) is obtained by the write control signal (WC) via another inverter. 如申請專利範圍第2項所述之單埠靜態隨機存取記憶體,該寫入控制信號(WC)為一寫入致能(Write Enable,簡稱WE)信號與該對應之字元線(WL)信號的及閘(AND gate)運算結果,亦即僅於該寫入致能(WE)信號與該對應之字元線(WL)信號均為邏輯高位準時,該寫入控制信號(WC)方為邏輯高位準。 The write control signal (WC) is a write enable (WE) signal and the corresponding word line (WL), as described in claim 2, the static random access memory. The AND gate operation result of the signal, that is, the write control signal (WC) only when the write enable (WE) signal and the corresponding word line (WL) signal are both at a logic high level The party is logically high. 如申請專利範圍第3項所述之單埠靜態隨機存取記憶體,該讀取控制信號(RC)為一讀取致能(Read Enable,簡稱RE)信號與該對應之字元線(WL)信號的及閘(AND gate)運算結果,亦即僅於該讀取致能(RE)信號與該對應之字元線(WL)信號均為邏輯高位準時,該讀取控制信號(RC)方為邏輯高位準。 The read control signal (RC) is a Read Enable (RE) signal and the corresponding word line (WL) as claimed in claim 3 of the SRAM. The AND gate operation result of the signal, that is, the read control signal (RC) only when the read enable (RE) signal and the corresponding word line (WL) signal are both at a logic high level The party is logically high. 如申請專利範圍第4項所述之單埠靜態隨機存取記憶體,其中,每一預充電電路(3)係由一第三PMOS電晶體(PP31)以及一預充電信號(P)所組成;其中,該第三PMOS電晶體(P31)之源極、閘極與汲極係分別連接至電源供應電壓(VDD)、該預充電信號(P)與該對應之位元線(BL),以便於一預充電期間,藉由邏輯低位準之該預充電信號(P),以將該對應之位元線(BL)預充電至該電源供應電壓(VDD)之位準。 A static random access memory according to claim 4, wherein each precharge circuit (3) is composed of a third PMOS transistor (PP31) and a precharge signal (P). Wherein the source, the gate and the drain of the third PMOS transistor (P31) are respectively connected to a power supply voltage (V DD ), the precharge signal (P) and the corresponding bit line (BL) In order to facilitate the precharge signal (P) by a logic low level during a precharge period, the corresponding bit line (BL) is precharged to the level of the power supply voltage (V DD ). 如申請專利範圍第5項所述之單埠靜態隨機存取記憶體,其中,該待機啟動電路(4)係由一第四PMOS電晶體(P41)、一第十二NMOS電晶體(M41)、一第二延遲電路(D2)以及該反相待機模式控制信號(/S)所組成;其中,該第四PMOS電晶體(P41)之源極、閘極與汲極係分別連接至電源供應電壓(VDD)、該反相待機模式控制信號(/S)與該第十二NMOS 電晶體(M41)之汲極;該第十二NMOS電晶體(M41)之源極、閘極與汲極係分別連接至該第一低電壓節點(VL1)、該第二延遲電路(D2)之輸出與該第四PMOS電晶體(P41)之汲極;該第二延遲電路(D2)之輸入連接至該反相待機模式控制信號(/S),而該延遲電路(D1)之輸出則連接至該第十二NMOS電晶體(M41)之閘極。 The static random access memory according to claim 5, wherein the standby starting circuit (4) is a fourth PMOS transistor (P41) and a twelfth NMOS transistor (M41). a second delay circuit (D2) and the inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fourth PMOS transistor (P41) are respectively connected to a power supply a voltage (V DD ), the inverted standby mode control signal (/S) and a drain of the twelfth NMOS transistor (M41); a source, a gate and a gate of the twelfth NMOS transistor (M41) The poles are respectively connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fourth PMOS transistor (P41); the input connection of the second delay circuit (D2) Up to the inverted standby mode control signal (/S), and the output of the delay circuit (D1) is connected to the gate of the twelfth NMOS transistor (M41). 如申請專利範圍第6項所述之單埠靜態隨機存取記憶體,其中,該待機啟動電路(4)進入待機模式之該初始期間係等於該反相待機模式控制信號(/S)由邏輯高位準轉變為邏輯低位準起算,至該第十二NMOS電晶體(M41)之閘極電壓足以關閉該第十二NMOS電晶體(M41)為止之時間,其可藉由該第二延遲電路(D2)所提供之一延遲時間來調整。 The static random access memory according to claim 6, wherein the initial period of the standby start circuit (4) entering the standby mode is equal to the inverted standby mode control signal (/S) by logic The high level is converted to a logic low level, until the gate voltage of the twelfth NMOS transistor (M41) is sufficient to turn off the twelfth NMOS transistor (M41), which can be performed by the second delay circuit ( D2) One of the delay times provided to adjust. 如申請專利範圍第7項所述之單埠靜態隨機存取記憶體,其中,讀取操作係可再細分成二個階段,於該讀取操作之第一階段係藉由將該第一低電壓節點(VL1)設定成較接地電壓為低之該加速讀取電壓(RGND)以有效提高讀取速度,而於該讀取操作之第二階段則藉由將該第一低電壓節點(VL1)設定回接地電壓,以便減少無謂的功率消耗,該讀取操作之該第二階段與該第一階段間隔之時間,係等於該讀取控制信號(RC)由邏輯低位準轉變為邏輯高位準起算,至該第八NMOS電晶體(M25)之閘極電壓足以關閉該第八NMOS電晶體(M25)為止之時間,其可藉由該第三反相器(INV)之下降延遲時間與該第一延遲電路(D1)所提供之另一延遲時間來調整。 The static random access memory as described in claim 7, wherein the read operation can be further subdivided into two stages, and the first stage of the read operation is performed by the first low The voltage node (VL1) is set to be lower than the ground voltage by the accelerated read voltage (RGND) to effectively increase the read speed, and in the second phase of the read operation by the first low voltage node (VL1) Setting back to the ground voltage to reduce unnecessary power consumption, the second phase of the read operation is separated from the first phase by the read control signal (RC) from a logic low level to a logic high level Calculating, until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), which can be delayed by the third inverter (INV) The other delay time provided by the first delay circuit (D1) is adjusted.
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TWI618084B (en) * 2017-06-23 2018-03-11 修平學校財團法人修平科技大學 Seven transistor dual port static random access memory

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