TWI529715B - Single port static random access memory (3) - Google Patents

Description

單埠Static random access memory (3)

The invention relates to a single port static random access memory (SRAM), in particular to an effective improvement of the standby performance of the 單埠SRAM, and can effectively improve the reading speed and effectively reduce Leakage current and can solve the problem that SRAM is difficult to write logic 1 with a single bit line.

As is shown in FIG. 1a, the static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of memory blocks (memory block, MB _1). , MB _{2 ,} etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL _{2 ,} etc.), each word line corresponding to a plurality of columns of memory One of the body cells; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _{m ,} etc.), each bit line pair corresponding to a plurality of rows of memory cells One row, and each bit line pair is composed of one bit line (BL ₁ ... BL _m ) and one complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b is a schematic diagram of a 6T單埠 SRAM cell, in which PMOS transistors (P1) and (P2) are called load transistors, NMOS transistors. (M1) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is word line, and BL And BLB are respectively a bit line and a complementary bit line. Since the 單埠SRAM cell requires six transistors, and the current driving capability between the driving transistor and the access transistor is greater than (ie, the cell ratio) is usually set between 2.2 and 3.5, resulting in the difficulty of high integration and high price.

The HSPICE transient analysis results of the 6T單埠 SRAM cell shown in Figure 1b during the write operation, as shown in Figure 2, are simulated using the TSMC 90 nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T 單埠 SRAM cell with only a single bit line, compared to the 6T 單埠 SRAM cell of Figure 1b. The random access memory cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T單埠 SRAM cell does not change the PMOS transistors P1 and P2. And the channel width-to-length ratio of the NMOS transistors M1, M2, and M3 is relatively difficult to write logic 1 in the case of maintaining a static noise margin (SNM). Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 3 shows the HSPICE transient analysis simulation results of the 5T SRAM cell during write operation. As shown in Figure 4, it uses TSMC 90 nm CMOS. The process parameters are simulated. From the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.

In the past, there have been many techniques for a 5T SRAM cell with a single bit line, such as the "Memory System" proposed in Patent Document 1 (US Pat. No. 7,706,062 B2, April 27, 1999), Patent Literature 2 (TWI404065, August 1, 102, TWI404065) "Standard Static Random Access Memory with Improved Word Line Voltage Level in Write Operation", Patent Document 3 (June 1st, TW201118873A) No.) "Standard Static Random Access Memory with Reduced Power Supply Voltage During Write Operation" and Patent Document 4 (No. TW201117210A, May 16, 100) Access to memory, these patents can effectively solve the problem of writing logic 1 difficult, but since these patents do not take into account the reduction of standby power and 45 nm operating voltage will be reduced to 1.1 ± 30% caused by reading There are still problems with speed reduction and so on, so there is still room for improvement.

In the past, there have been many techniques for reducing the standby current, such as the "double-static static random access memory with discharge path" proposed in Patent Document 5 (No. TW M393773, December 1, 1999), Patent Document 6 ( "Static random access memory (SRAM) with "Serial random access memory" proposed in TW I307890, March 21, 1998, and Patent Document 7 (US Pat. No. 7,382,674 B2, June 3, 1997) "Static random access memory device and method of reducing standby current", Patent Document 8 (US Pat. No. 7,725,085 B2, August 7, 1996), Patent Document 9 (September 19, 1995) "SRAM employing virtual rail scheme stable against various process-voltage-temperature variations", No. US7110317 B2), Non-Patent Document 10 (Tae-Hyoung Kim et al.," A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode", IEEE Journal of Solid-State Circuits ., Vol. 64, pp 1785 - 1795, 2009.) 8T SRAM and Non-Patent Document 11 (Ding-Ming Kwai, "Mod Eling of SRAM Standby Current by Three-Parameter Lognormal Distribution", Design, and Testing, 2009. MTDT '09. IEEE International Workshop on Memory Technology, pp 77 - 82, Aug. 31 2009-Sept. 2009.) In the standby operation, the source voltages of the driving transistors (ie, the NMOS transistors M1 and M2 of FIG. 1b) in all the memory cells are from the original. The ground voltage is increased to a predetermined voltage higher than the ground voltage to reduce the power consumption of the standby operation, but the predetermined voltage is generated only by charging the parasitic capacitance by the leakage current of the transistor, thereby causing static randomization. The speed at which the access memory enters the standby mode is extremely slow, and thus results in a lack of standby performance: that is, the patent documents or the non-patent literature lack a standby start circuit to cause the SRAM to quickly enter the standby mode.

In view of this, the main object of the present invention is to provide a 單埠 static random access memory capable of effectively causing the SRAM to quickly enter the standby mode by the standby start circuit, thereby effectively improving the standby performance of the SRAM.

A secondary object of the present invention is to provide a 單埠 static random access memory that can be used to effectively avoid the problem of writing logic 1 by the control circuit to effectively avoid the existence of a single bit line SRAM.

Still another object of the present invention is to provide a 單埠 static random access memory capable of effectively reducing leakage current in a standby mode by a control circuit.

Another object of the present invention is to provide a 單埠 static random access memory capable of The control circuit is used to effectively increase the reading speed.

Another object of the present invention is to provide a 單埠 static random access memory that can be controlled by two stages to improve read speed while avoiding unnecessary power consumption.

The present invention provides a 單埠 static random access memory, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), and a standby start circuit (4), the memory array The memory cell consists of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells is provided with a control circuit, and each of the memory cells (1) includes a first inverter (by a a first PMOS transistor P11 and a first NMOS transistor M11, a second inverter (composed of a second PMOS transistor P12 and a second NMOS transistor M12) and an access transistor (consisting of the third NMOS transistor M13). Each control unit (2) is connected to a source of the first NMOS transistor (M11) of each memory cell of the corresponding column memory cell and a source of the second NMOS transistor (M12) In order to control the source voltage of the first NMOS transistor (M11) and the source voltage of the second NMOS transistor (M12) in response to different operation modes, thereby effectively preventing the write logic in the write mode 1 difficult problem, in the read mode, can improve the reading speed, but also avoid unnecessary power consumption, in the standby mode, can effectively reduce the leakage current, while maintaining the original electrical mode characteristic. Moreover, the design of the standby start circuit (4) is effective to prompt the 單埠SRAM to quickly enter the standby mode, and thus effectively improve the standby performance of the 單埠SRAM.

BLB ₁ ^... BLB _m ‧‧‧complementary bit line

BLB‧‧‧complementary bit line

MB ₁ ^... MB _k ‧‧‧ memory block

WL ₁ ^... WL _n ‧‧‧ wordline

BL ₁ ^... BL _m ‧‧‧ bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

V _DD ‧‧‧Power supply voltage

BL‧‧‧ bit line

WL‧‧‧ character line

S‧‧‧Standby mode control signal

/ S ‧‧‧Inverting standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

WC‧‧‧ write control signal

/WC‧‧‧Inverted write control signal

C‧‧‧ node

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

M41‧‧‧12th NMOS transistor

P41‧‧‧4th PMOS transistor

D2‧‧‧second delay circuit

INV‧‧‧ third inverter

Figure 1a shows a conventional static random access memory; 1b is a schematic circuit diagram showing a conventional 6T static random access memory cell; FIG. 2 is a timing chart showing a write operation of a conventional 6T static random access memory cell; and FIG. 3 is a conventional display Schematic diagram of a 5T static random access memory cell; Fig. 4 shows a write operation timing diagram of a conventional 5T static random access memory cell; Fig. 5 shows a preferred embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6 is a simplified circuit diagram showing a preferred embodiment of the present invention in FIG. 5 during writing; FIG. 7 is a timing chart showing the writing operation of the preferred embodiment of the present invention in FIG. 5; The figure shows a simplified circuit diagram of the preferred embodiment of the present invention in FIG. 5 during reading; and FIG. 9 is a simplified circuit diagram showing the preferred embodiment of the present invention in FIG. 5 during standby.

According to the above main object, the present invention provides a 單埠 static random access memory, which mainly includes a memory array composed of a plurality of column memory cells and a plurality of row memory cells, each A column of memory cells and each row of memory cells include a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharges Circuit (3), each row of memory cells is provided with a precharge circuit (3); and a standby start circuit (4), which causes the SRAM to quickly enter standby mode to effectively improve the standby performance of the SRAM. .

For convenience of explanation, the static random access memory shown in FIG. 5 has only one memory cell (1), one word line (WL), one bit line (BL), and one control circuit (2). A precharge circuit (3) and a standby start circuit (4) are described as embodiments. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11) and a second inverter (by a second PMOS) Crystal P12 and a second NMOS transistor M12), a third NMOS transistor (M13), wherein the first inverter and the second inverter are connected in an alternating coupling, that is, the first inverter The output (ie node A) is connected to the input of the second inverter, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the first inverter The output (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell.

Referring again to FIG. 5, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS device. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control Signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a write control signal (WC), and an inverted write control signal ( /WC), a standby mode control signal (S) and an inverted standby mode control signal (/S). a source, a gate and a drain of the fourth NMOS transistor (M21) are respectively connected to a ground voltage, the reverse standby mode control signal (/S) and a second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (M22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); The source of the six NMOS transistor (M23) is connected to the ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) The gate and the drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); and the eighth NMOS transistor (M25) The source, gate and drain are connected to the accelerated read voltage (RGND), An output of the first delay circuit (D1) and a source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected to an output of the third inverter (INV) and the eighth Between the gates of the NMOS transistor (M25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1) The source, the gate and the drain of the ninth NMOS transistor (M26) are respectively connected to a ground voltage, a drain of the tenth NMOS transistor (M27), and the eleventh NMOS transistor (M28) a drain and the first low voltage node (VL1); a source, a gate and a drain of the tenth NMOS transistor (M27) are respectively connected to the standby mode control signal (S), the write control signal ( WC) and a gate of the ninth NMOS transistor (M26) and a drain of the eleventh NMOS transistor (M28); and a source, a gate and a drain of the eleventh NMOS transistor (M28) They are respectively connected to the inverted standby mode control signal (/S), the inverted write control signal (/WC) and the drain of the tenth NMOS transistor (M27). It should be noted here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter; the inverted write control signal (/WC) is The write control signal (WC) is obtained via an inverter.

The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage (ie, the first low voltage node VL1) of the driving transistor (ie, the first NMOS transistor M11) closer to the bit line (BL) is set to be a predetermined voltage higher than the ground voltage (ie, The gate-source voltage V _{GS(M23) of} the sixth NMOS transistor (M23) and the source voltage of the other driving transistor (ie, the second NMOS transistor M12) in the selected unit cell (ie, the second The low voltage node VL2) is set to the ground voltage to prevent the difficulty of writing logic 1.

In the first phase of the read mode, the closer cell line (BL) in the selected cell will be selected. The source voltage of the driving transistor (ie, the first NMOS transistor M11) (ie, the first low voltage node VL1) is set to be the accelerated reading voltage (RGND) lower than the ground voltage, the grounding voltage The accelerated read voltage (RGND) is low to effectively increase the read speed, and in the second phase of the read mode, the drive transistor closer to the bit line (BL) in the selected cell is selected (ie, the first The source voltage of an NMOS transistor M11) is set back to the ground voltage to reduce unnecessary power consumption, wherein the second phase of the read mode is separated from the first phase by the read control signal (RC) The time from the logic low level to the logic high level, and until the gate voltage of the eighth NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), the value can be obtained by the third The falling delay time of the inverter (INV) is adjusted with the delay time provided by the first delay circuit (D1).

In the standby mode, the source voltage of the driving transistor in all the memory cells is set to the predetermined voltage higher than the ground voltage to reduce the leakage current; and in the hold mode, the driving power in the memory cell is The source voltage of the crystal is set to the ground voltage to maintain the original retention characteristics. The detailed operating voltage levels are shown in Table 1.

The write control signal (WC) in Table 1 is an AND gate operation result of a Write Enable (WE) signal and a corresponding word line (WL) signal. When the write enable (WE) signal and the corresponding word line (WL) signal are both at a logic high level, the write control signal (WC) is a logic high level; the read control signal (RC) is A read enable (RE) signal and a corresponding word line (WL) signal are gated. It is worth noting here that the unselected word line and the unselected positioning element line are set to a floating state, and the read control signal (RC) is set to the acceleration during the non-read mode. The level of the read voltage (RGND) is read to prevent leakage current of the seventh NMOS transistor (M24).

Referring to FIG. 5, the precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P), and the source and gate of the third PMOS transistor (P31). Connected to the power supply voltage (V _DD ), the pre-charge signal (P) and the corresponding bit line (BL), respectively, to facilitate the pre-charging signal by logic low level during pre-charging ( P), pre-charging the corresponding bit line (BL) to the level of the power supply voltage (V _DD ).

Referring to FIG. 5 again, the standby starting circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2), and the reverse standby. The mode control signal (/S) is composed of. The source, the gate and the drain of the fourth PMOS transistor (P41) are respectively connected to a power supply voltage (V _DD ), the inverted standby mode control signal (/S) and the twelfth NMOS transistor ( a drain of M41); a source, a gate and a drain of the twelfth NMOS transistor (M41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) a drain of the fourth PMOS transistor (P41); an input of the second delay circuit (D2) is coupled to the inverted standby mode control signal (/S), and an output of the delay circuit (D1) is coupled to the The gate of the twelfth NMOS transistor (M41).

The working principle of the preferred embodiment of the present invention in FIG. 5 is as follows:

(I) write mode

Before the start of the write operation, the write control signal (WC) is a logic low level, and the inverted write control signal (/WC) is a logic high level, so that the eleventh NMOS transistor (M28) is turned on (ON). And causing the tenth NMOS transistor (M27) to be turned off (OFF), so that the drain of the eleventh NMOS transistor (M28) is at a logic high level, and the logic is at a high level of the eleventh NMOS transistor ( The drain of M28) turns on the ninth NMOS transistor (M26) and causes the low voltage node (VL1) to be at a ground voltage.

During the write operation period, the write control signal (WC) is a logic high level, and the inverted write control signal (/WC) is a logic low level, so that the eleventh NMOS transistor (M28) is turned off. The tenth NMOS transistor (M27) is turned on, and the drain of the tenth NMOS transistor (M27) is at a logic low level, and the logic low level of the drain of the tenth NMOS transistor (M27) causes the The ninth NMOS transistor (M26) is turned off, and the low voltage node (VL1) is equal to the gate voltage V _{GS (M26)} of the sixth NMOS transistor (M23 ₎ , thereby effectively preventing writing logic 1 from being difficult The problem. Figure 6 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during writing.

Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed depends on the four write states of the SRAM.

(1) Node A originally stores a logic 0, but now wants to write a logic 0:

Before the write operation occurs (the word line WL is a ground voltage), the first NMOS transistor (M11) is turned "ON". Since the first NMOS transistor (M11) is ON, the word line (WL) is turned from Low (ground voltage) to High (power supply voltage V _DD ) when the write operation starts. When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) is turned from off (OFF) to on ( ON), at this time, since the bit line (BL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle.

(2) Node A originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the word line WL is a ground voltage), the first NMOS transistor (M11) is turned "ON". Since the first NMOS transistor (M11) is ON, when the writing operation starts, the word line (WL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the node A It will rise following the voltage of the word line (WL).

When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) is turned from OFF to ON, because The bit line (BL) is High (the power supply voltage V _DD ), and because the first NMOS transistor (M11) is still ON and the node B is still at a voltage level close to the power supply voltage (V _{DD )} The initial state of the voltage level, so the first PMOS transistor (P11) is still off (OFF), and the node A is rapidly charged toward a divided voltage level, the divided voltage level is equal to (R _M11 + R _M23 ) / (R _M13 + R _M11 + R _M23 ) multiplied by the power supply voltage (V _DD ), wherein the R _M13 represents the on-resistance equivalent resistance of the third NMOS transistor (M13), the R _M11 Indicates the on-resistance equivalent resistance of the first NMOS transistor (M11), and the R _M23 represents the on-resistance equivalent resistance of the sixth NMOS transistor (M23), because the third NMOS transistor (M13) is still operating at this time. saturation region (saturation region) and the first NMOS transistor (M11) is still operating in the linear region (triode region), while guiding the third NMOS transistor (M13) through the equivalent resistance (R _M13) may lofty The first NMOS transistor (M11) is turned the equivalent resistance (R _M11), but since the sixth NMOS transistor (M23) diodes is connected as a system, it is possible to lower the first node voltage (VL1) at Providing a voltage level equal to the gate-source voltage V _{GS (M23)} of the sixth NMOS transistor (M23), and the resulting voltage level of the node A is higher than that of FIG. The voltage level of the node A of the conventional 5T static random access memory cell is much higher. The much higher voltage division voltage level is sufficient to turn on the second NMOS transistor (M12), thus causing the node B to discharge to a lower voltage level, and the lower voltage level of the node B causes the first The on-resistance equivalent (R _M11 ) of an NMOS transistor (M11) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) obtains a higher voltage level at the node A. The higher voltage level of the node A is again caused by the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12), so that the node B exhibits a lower voltage level. The lower voltage level of the node B is again passed through the first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor M11), so that the node A obtains a higher voltage level. In this cycle, the node A can be charged to the power supply voltage (V _DD ), and the logic 1 write operation is completed.

It should be noted here that the first low voltage node VL1 originally stores a logic 0 at the node A, and has a gate source voltage V _GS equal to the sixth NMOS transistor (M23) while the logic 1 is being written. The voltage level of _(M23) , after writing logic 1, will have the level of the ground voltage due to discharge through the ninth NMOS transistor (M26).

(3) Node A originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the word line WL is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line (WL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M13), The third NMOS transistor (M13) is turned from OFF to ON; at this time, since the bit line (BL) is High (the power supply voltage V _DD ), and because the first PMOS transistor (P11) is still ON, so the voltage of the node A will be maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the word line WL is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line (WL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M13), The third NMOS transistor (M13) is turned from off (OFF) to on (ON). At this time, since the bit line (BL) is Low (ground voltage), the node A and the first low voltage are The node (VL1) is discharged to complete the write operation of logic 0 until the end of the write cycle.

In the preferred embodiment of the present invention shown in FIG. 6, the HSPICE transient analysis simulation result during the write operation, as shown in FIG. 7, is simulated using the TSMC 90 nm CMOS process parameters, from which the simulation result is obtained. It can be confirmed that the static random access memory proposed by the present invention can improve the voltage level of the first low voltage node (VL1) during the writing period, thereby effectively avoiding the single single bit line.埠 Static random access memory cells have the problem of writing logic 1 quite difficult.

(II) Read mode (read mode)

The read control signal (RC), the write control signal (WC), and the standby mode control signal (S) are both logic low levels before the start of the read operation, so that the eleventh NMOS transistor (M28) is turned on. And causing the tenth NMOS transistor (M27) to be turned off, so that the drain of the eleventh NMOS transistor (M28) is at a logic high level, and the logic high level is the drain of the eleventh NMOS transistor (M28) The ninth NMOS transistor (M26) is turned on, and the first low voltage node (VL1) is grounded. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned "ON".

The preferred embodiment of the present invention shown in FIG. 6 is controlled by two stages to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the reading operation, the reading control The signal (RC) is at a logic high level, so that the seventh NMOS transistor (M24) is turned on. Since the eighth NMOS transistor (M25) is still turned on at this time, the first low voltage node (VL1) is at a ground voltage. To lower the accelerated read voltage (RGND), the accelerated read voltage (RGND), which is lower than the ground voltage, can effectively increase the read speed.

In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (M24) is still turned on, but since the eighth NMOS transistor (at this time) M25) is turned off, so that the first low voltage node (VL1) is grounded via the turned-on ninth NMOS transistor (M26), thereby effectively reducing unnecessary power consumption. It is worth noting here that the second phase of the read operation is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the The gate voltage of the eight NMOS transistor (M25) is sufficient to turn off the eighth NMOS transistor (M25), and the value thereof can be decreased by the delay time of the third inverter (INV) and the first delay circuit. (D1) The delay time provided is adjusted. Furthermore, the ninth NMOS transistor (M26) is in an on state regardless of the first phase of the read operation or the second phase (since the gate of the ninth NMOS transistor (M26) is substantially the power supply voltage V _DD The standard). Figure 8 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during reading.

(III) Standby mode

First, how the standby start circuit (4) of Fig. 5 causes the 單埠SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: (1) the reverse standby mode control signal (/S) before entering the standby mode. Is logic High, the logic high inversion standby mode control signal (/S) causes the fourth PMOS transistor (P41) to be turned off (OFF), and causes the twelfth NMOS transistor (M41) to be turned on (ON) (2) After entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fourth PMOS transistor (P41) Turned on (ON), but during the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from logic High to logic Low, to the twelfth NMOS transistor (M41) The gate voltage is sufficient to turn off the twelfth NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2), the twelfth NMOS transistor ( M41) is still turned on (ON), so the first low voltage node (VL1) can be quickly charged to reach the sixth NMOS transistor (M2) 3) The voltage level of the threshold voltage (V _TM23 ), that is, the 單_埠 SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (M41) is turned off and the supply current is stopped.

Referring to FIG. 5, in the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (M21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (M22) is turned on (ON), and the fifth NMOS transistor (M22) is used as an equalizer, so that the fifth NMOS transistor (M22) in an on state can be used. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the sixth NMOS transistor (M23) The voltage level of the threshold voltage (V _TM23 ). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during standby.

Next, how to reduce leakage current in the standby mode of the present invention will be described. Referring to FIG. 9, FIG. 9 depicts a leakage current I ₁ generated when the embodiment of the present invention is in the standby mode. I ₂ , I ₃ , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage node (VL2) due to the standby mode The voltage level is maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so that the voltage level of the node A is logic Low is also maintained at the voltage level of the V _TM23 ) And the output of the second inverter (ie, node B) is a logic high (power supply voltage V _DD ). Referring to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 9, the comparison between the static random access memory of the present invention and the 6T SRAM of FIG. 1b in terms of leakage current is first described. Leakage current I _{1 of the} third NMOS transistor (M13), since the voltage level of the node A is maintained at the voltage level of the V _{TM 23} in the standby mode, and the word line (WL) is assumed to be in the standby mode. The ground voltage is set, and the bit line (BL) is set to the power supply voltage (V _DD ) in the standby mode, so the gate-source voltage (V _GS ) of the third NMOS transistor (M13) of the present invention is set. Negative value, in contrast to the standby mode, the gate-source voltage (V _GS ) of the prior art NMOS transistor (M3) of Fig. 1b is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect. Or, as shown in the results of Figures 3(A) and 3(B) of the US Pat. No. 6,865,119, issued March 8, 2005, it is known that for an NMOS transistor, the sub-critical current of the gate-source voltage is -0.1 volt is approximately the gate. The source voltage is 1% of the subcritical current at 0 volts, and thus is caused by the GIDL effect and flows through the present invention. The leakage current I _{1 of} the third NMOS transistor (M13) is much smaller than that of the prior art NMOS transistor (M3) of FIG. 1b; further, the threshold voltage of the third NMOS transistor (M13) of the present invention ( V _DS ) _deducts the voltage level of the V _TM23 for the power supply voltage (V _DD ), and the source voltage of the NMOS transistor (M3) of the conventional 1b FIG. 6T SRAM is in the standby mode. (V _DS ) is equal to the power supply voltage (V _DD ), according to the Drain-Induced Barrier Lowering (DIBL) effect, the third NMOS transistor flowing through the present invention due to the DIBL effect (M13) the drain current I ₁ is also smaller than the prior art of FIG. 1b NMOS transistor (M3) are; As a result, the third NMOS transistor (M13) of the present invention to flow through the drain current I ₁ is much smaller than the previous section in FIG. 1b The NMOS transistor (M3) of the art.

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) due to the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the _VTM23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V) _DD ) deducting the voltage level of the V _TM23 , in contrast to the standby source mode, the source drain voltage (V _SD ) of the prior art PMOS transistor (P1) is equal to the power supply voltage (V _DD ), according to The DIBL effect, therefore, the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P1) of Figure 1b.

Finally, regarding the leakage current I ₃ flowing through the second NMOS transistor (M12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the _VTM23 in the standby mode, the node A The voltage level is also maintained at the voltage level of the V _TM23 , and the voltage level of the node B is equal to the power supply voltage (V _DD ) and the base of the second NMOS transistor (M12) is the ground voltage, so The base-source voltage (V _BS ) of the second NMOS transistor (M12) of the invention is a negative value, and the 汲 source voltage (V _DS ) of the second NMOS transistor (M12) is the power supply voltage (V) _DD ) deducting the voltage level of the V _TM23 , in contrast to the standby mode, the base-source voltage (V _BS ) of the prior art NMOS transistor (M2) of FIG. 1b is equal to 0, and the NMOS transistor (M2) The source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and the DIBL effect, the leakage current I ₃ flowing through the second NMOS transistor (M12) of the present invention is much smaller than the first 1b is a prior art NMOS transistor (M2). It can be seen from the above analysis that the 單埠 static random access memory proposed by the present invention has a lower leakage current than the prior art of Fig. 1b.

(IV) hold mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to a ground voltage, the working principle is the same as that of the conventional 5T SRAM cell with a single bit line in FIG. This is not repeated here.

【Effects of invention】

The static random access memory proposed by the present invention has the following effects: (1) fast entry standby mode: since the static random access memory proposed by the present invention is provided with a standby start circuit (4) to promote SRAM quickly enters the standby mode, and thereby seeks to improve the standby performance of the SRAM; (2) avoids the problem of writing logic 1: the static random access memory proposed by the present invention is in the write operation. The problem of writing the logic 1 can be effectively avoided by increasing the voltage level of the first low voltage node (VL1); (3) high read speed and avoidance Unnecessary power consumption: The static random access memory system proposed by the present invention employs a two-stage read operation in which the first low voltage node (VL1) is set to a ground voltage in the first phase of the read operation. The accelerated read voltage (RGND) is low to effectively increase the read speed, and in the second phase of the read operation, the first low voltage node (VL1) is set back to the ground voltage to reduce unnecessary power. Consumption; (4) low waiting Current: Since the static random access memory proposed by the present invention is in the standby mode, the fifth NMOS transistor (M22) in an on state can be used to make the first low voltage node (VL1) The voltage level is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the level of the threshold voltage of the sixth NMOS transistor (M23), and thus the present invention proposes單埠Static random access memory also has the effect of low standby current; (5) Low transistor number: For SRAM array with 1024 columns and 1024 rows, the traditional 1b Figure 6T The static random access memory array requires a total of 1024 × 1024 × 6 = 6,291,456 transistors, and the static random access memory proposed by the present invention only needs at least 1024 × 1024 × 5 + 1024 × 16 + 6 = 5,259,270 Crystal, which reduces the number of transistors by 16.4%.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

M11‧‧‧First NMOS transistor

M12‧‧‧Second NMOS transistor

M13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

V _DD ‧‧‧Power supply voltage

BL‧‧‧ bit line

WL‧‧‧ character line

S‧‧‧Standby mode control signal

/ S ‧‧‧Inverting standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

M21‧‧‧4th NMOS transistor

M22‧‧‧ Fifth NMOS transistor

M23‧‧‧ sixth NMOS transistor

M24‧‧‧ seventh NMOS transistor

M25‧‧‧8th NMOS transistor

M26‧‧‧Ninth NMOS transistor

M27‧‧‧ tenth NMOS transistor

M28‧‧‧11th NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

WC‧‧‧ write control signal

/WC‧‧‧Inverted write control signal

C‧‧‧ node

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

M41‧‧‧12th NMOS transistor

P41‧‧‧4th PMOS transistor

D2‧‧‧second delay circuit

INV‧‧‧ third inverter

Claims (8)

A static random access memory, comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each row of memory The unit cell comprises a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory crystals The cell is provided with a pre-charging circuit (3); and a standby starting circuit (4) for causing the static random access memory to quickly enter the standby mode to effectively improve the static random random Accessing the standby performance of the memory; wherein each memory cell (1) further comprises: a first inverter, comprising a first PMOS transistor (P11) and a first NMOS transistor (M11) The first inverter is connected between a power supply voltage (V _DD ) and a first low voltage node (VL1); and a second inverter is connected by a second PMOS transistor (P12). And a second NMOS transistor (M12) connected to the power supply (V _DD) between the node and a second low voltage (VL2); a storage node (A), the line is formed by a first output terminal of the inverter; inverting a storage node (B), the Department of Forming an output of the second inverter; a third NMOS transistor (M13) is connected between the storage node (A) and a corresponding bit line (BL), and the gate is connected to a corresponding a word line (WL); wherein the first inverter and the second inverter are connected in an alternating coupling, that is, an output end of the first inverter (ie, the storage node A) is connected to An input end of the second inverter, and an output end of the second inverter (ie, the inverting storage node B) is connected to an input end of the first inverter; and each control circuit (2) The method further includes: a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), and an eighth NMOS transistor ( M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control signal (RC), and a third inverter ( INV), a first delay circuit (D1), an accelerated reading power (RGND), a write control signal (WC), an inverted write control signal (/WC), a standby mode control signal (S), and an inverted standby mode control signal (/S); wherein the The source, gate and drain of the four NMOS transistors (M21) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and the second low voltage node (VL2); the fifth NMOS a source, a gate and a drain of the crystal (M22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and the first low voltage node (VL1); the sixth NMOS a source of the transistor (M23) is connected to the ground voltage, and a gate is connected to the drain and connected to the first low voltage node (VL1); a source of the seventh NMOS transistor (M24), a gate and a drain are respectively connected to a drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); and the eighth NMOS transistor (M25) a source, a gate and a drain are respectively connected to the accelerated read voltage (RGND), an output of the first delay circuit (D1), and a source of the seventh NMOS transistor (M24); the first delay Circuit D1) is connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for receiving the read control a signal (RC), and an output is connected to an input of the first delay circuit (D1); a source, a gate and a drain of the ninth NMOS transistor (M26) are respectively connected to the ground voltage, the tenth a drain of the NMOS transistor (M27) and the eleventh NMOS transistor (M28) and the first low voltage node (VL1); a source, a gate and a drain of the tenth NMOS transistor (M27) Connected to the standby mode control signal (S), the write control signal (WC) and the gate of the ninth NMOS transistor (M26); the source and gate of the eleventh NMOS transistor (M28) And the drain line are respectively connected to the inverted standby mode control signal (/S), the inverted write control signal (/WC) and the drain of the tenth NMOS transistor (M27); wherein, for non-reading The read control signal (RC) during the mode is set to the level of the accelerated read voltage (RGND) to prevent leakage current of the seventh NMOS transistor (M24) during the non-read mode; Standby start circuit (4) is designed to rapidly charge the parasitic capacitance at the first low voltage node (VL1) to the threshold voltage ( _VTM23 ) of the sixth NMOS transistor (M23) during an initial period of entering the standby mode Voltage level; it is worth noting here that the drain of the tenth NMOS transistor (M27), the drain of the eleventh NMOS transistor (M28), and the gate of the ninth NMOS transistor (M26) The poles are connected together and form a node (C), and the logic high level of the node (C) is the power supply voltage (V _DD ) deducting the threshold voltage of the eleventh NMOS transistor (M28) (V _TM28 The voltage level, so when the static random access memory is in the non-write mode (in this case, the inverted write control signal (/WC) is a logic high level), the node (C) The power supply voltage (V _DD ) is deducted from the voltage level of the threshold voltage (V _TM28 ) of the eleventh NMOS transistor (M28) instead of the voltage level of the power supply voltage (V _DD ). Therefore, it can have a lower power consumption; and when it is subsequently entered into the write mode (in this case, the write control signal (WC) is a logic high level), since it can be quickly stored The charge of the node (C) is discharged through the tenth NMOS transistor (M27) to the ninth NMOS transistor (M26) sufficient to turn off the node (C) as a gate, so that the write can be entered relatively quickly. mode. The static random access memory according to claim 1, wherein the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter, And the inverted write control signal (/WC) is obtained by the write control signal (WC) via another inverter. The write control signal (WC) is a write enable (WE) signal and the corresponding word line (WL), as described in claim 2, the static random access memory. The AND gate operation result of the signal, that is, the write control signal (WC) only when the write enable (WE) signal and the corresponding word line (WL) signal are both at a logic high level The party is logically high. The read control signal (RC) is a Read Enable (RE) signal and the corresponding word line (WL) as claimed in claim 3 of the SRAM. The AND gate operation result of the signal, that is, the read control signal only when the read enable (RE) signal and the corresponding word line (WL) signal are both at a logic high level The (RC) side is logically high. The static random access memory according to claim 4, wherein each precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P). Wherein the source, the gate and the drain of the third PMOS transistor (P31) are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding bit line (BL) In order to facilitate the precharge signal (P) by a logic low level during a precharge period to precharge the corresponding bit line (BL) to the level of the power supply voltage (V _DD ). The static random access memory according to claim 5, wherein the standby starting circuit (4) is a fourth PMOS transistor (P41) and a twelfth NMOS transistor (M41). a second delay circuit (D2) and the inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fourth PMOS transistor (P41) are respectively connected to the power source a supply voltage (V _DD ), a reverse standby mode control signal (/S) and a drain of the twelfth NMOS transistor (M41); a source and a gate of the twelfth NMOS transistor (M41) The drain is connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fourth PMOS transistor (P41); the input of the second delay circuit (D2) Connected to the inverting standby mode control signal (/S), and the output of the delay circuit (D1) is connected to the gate of the twelfth NMOS transistor (M41). The static random access memory according to claim 6, wherein the initial period of the standby start circuit (4) entering the standby mode is equal to the inverted standby mode control signal (/S) by logic The high level is converted to a logic low level, until the gate voltage of the twelfth NMOS transistor (M41) is sufficient to turn off the twelfth NMOS transistor (M41), which can be performed by the second delay circuit ( D2) One of the delay times provided to adjust. The static random access memory as described in claim 7, wherein the read operation can be further subdivided into two stages, and the first stage of the read operation is performed by the first low The voltage node (VL1) is set to be lower than the ground voltage by the accelerated read voltage (RGND) to effectively increase the read speed, and in the second phase of the read operation by the first low voltage node ( VL1) set back to the ground voltage to reduce unnecessary power consumption, the read operation The time between the second phase and the first phase is equal to the read control signal (RC) is changed from a logic low level to a logic high level, and the gate voltage of the eighth NMOS transistor (M25) is sufficient. The time until the eighth NMOS transistor (M25) is turned off can be adjusted by the falling delay time of the third inverter (INV) and another delay time provided by the first delay circuit (D1).