M302763 八、新型說明： 【新型所屬之技術領域】 本創作係有關一種雙埠SRAM， 適用於單位元線同時讀寫之低雷壓告 Μ尤‘種可降低漏電流扣业喂current)且可 之低電壓雙埠SRAM晶胞(duai pGrt SRAM cell)。 【先前技術】M302763 VIII, new description: [New technology field] This creation is related to a kind of double-twist SRAM, which is suitable for the low-voltage pressure of the unit element line at the same time reading and writing, which can reduce the leakage current buckle industry to feed current) Low-voltage dual-cell SRAM cell (duai pGrt SRAM cell). [Prior Art]
’靜態隨機存取記憶體(SRAM)的 操作則^為簡易且毋須更新操作，因此具有高速化及消耗功率低^優點。 目前以行動電話為代表之行動電子設備所_之半導航憶裝置 記憶體在電腦工業中扮演著無可或缺的角色 在電源關後仍祕存資料，而區分為動態隨機名 ，係以 Μ為主流。此乃祕SRAM拥電流小，適於連續賴綱、連續待機時 間盡可％延長之手機。第1圖所示即是6T靜態隨機存取記憶體(sram)晶胞之 電路不思圖，其中，PMOS電晶體pi和p2稱為負載電晶體，碰和M2稱為驅 =電晶體，M3和M4稱為存取電晶體，WL為字元線(w〇rd _，而BL及腦 分別為位元線及互補位元線，由於該SRAM晶胞需要6個電晶體，且驅動電晶 •體與存取電晶體間的電流驅動能力比(即單元比率(cell ratio))通常設定在2至3 之間，而導致存在有高集積化困難及價格高等缺失。 ^用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種方式係揭 路於第2圖中。第2圖顯示一個單端5T靜態隨機存取記憶體(SRAM)晶胞之電 =示意圖，與第1圖之6T靜態隨機存取記憶體(SRAM^$胞相比，此種5T靜態 Ik機存取§己憶體(SRAM)晶胞比6Τ靜態隨機存取記憶體(sram)晶胞少一個電晶 體及少一條位元線，惟該5T靜態隨機存取記憶體(SRAM)晶胞存在寫入邏輯1 相當困難之問題。茲考慮記憶晶胞左側節點A原本儲存邏輯0的情況，由於節 點A之電荷僅單獨自位元線BL傳送，因此很難將節點a中先前寫入的邏輯〇 盖寫成邏輯1。 用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之另一種方式係 M302763 =於第3圖中。第3圖顯示一個4T靜態隨機存取記憶體(SRAM)晶胞之電路示 思圖’與第1圖之6T靜態隨機存取記憶體(SRAM)晶胞相比，此種4T靜態隨機 存取圮憶體(SRAM)晶胞比6T靜態隨機存取記憶體(SRAM)晶胞少二個電晶體， 惟該4T靜態隨機存取記憶體(SRam)晶胞存在消耗功率大之缺失，這是因為存 在一個電流固定流經電阻R1、R2，對於記憶晶胞内兩個特定狀態中之任一狀態 =百，其中一個電阻的功能在於提升並補償驅動電晶體及存取電晶體的漏電 流，而另一個電阻則作為一個限制流到儲存邏輯〇之節點的電流。 延續上述記憶晶胞電晶體數減少的進展，下一個合理的電晶體數減少將是 把電晶體數減少到3個，比前述4T靜態隨機存取記憶體(SRAM)晶胞的電晶體 數少1 ’第4圖顯示此種3T靜態隨機存取記憶體(sram)晶胞之電路示意圖，其 除了存在寫入邏輯1相當困難之外，並且由於電阻R1、R2之電阻值必須極高， 在10億到100億歐姆的範圍中，以便保持儘量低的待機功率消耗。結果，這些 電阻的恢復時間過長，導致無法適當地提升及/或保持記憶晶胞内的穩定高位準^ 接下來討論靜態隨機存取記憶體(SRAM)之單埠及雙埠架構，第丨圖之6丁 靜態隨機存取記憶體(SRAM)晶胞即是單埠靜態隨機存取記憶體(SRAM)晶胞 之例其係使用兩條位元線BL及BLB做讀寫的動作，也就是讀與寫均是經 ，同樣的一對位元線來達成，是以在同一時間内只能進行讀或寫的動作，因此: 當欲設計具有同時讀寫能力之雙埠靜態隨機存取記憶體時，便需要多加入兩顆 存取電晶體以及另一對位元線（請參考第5圖所示電路，其中及wblb 為寫入用位元線對、RBL及RBLB為讀取用位元線對、WWL為寫入用字元線、 RWL為讀取用字元線），這使得記憶晶胞的面積大大地增加，如果我們能夠簡化 5己憶晶胞的架構，使得一條位元線負責讀取的動作，而另一條位元線負責寫入 的動作，則在設計雙埠靜態隨機存取記憶體時，記憶晶胞便不需要多加入兩顆 電晶體及另一對位元線，這樣記憶晶胞的面積便會減小許多。傳統的單埠靜熊 入 機存取記憶體晶胞之所以不採用這種方法，是因為如前所述之無法 邏輯1的問題。 一 馬 為了於雙埠靜態隨機存取記憶體中實現僅以一條位元線負責讀取的動作、 另一條位元線負責寫入的動作、以及解決寫入邏輯丨困難之問題，於公告日民 國90年5月11日公告之我國專利公告第434537號「適用於單位元線二日^讀 之低電壓靜態隨機存取記憶體的六顆電晶體雙埠記憶單元電路」專利案之第 M302763 4⑻^即提iH種解決方案，第6圖即該專利案之帛4(a)圖(電路示意圖），該專 利案係將驅動電晶體Mn3之源極由原本之接地變更為連接至寫入用字元線 WWL經證實，其不但能實現僅以一條位元線負責讀取的動作，而另一條位 70線負責寫入的動作之單位元線同時讀寫的功能，並且也可操作於i伏特之低 電源電壓，同時亦能解決習知寫入邏輯丨困難之問題。 ;雖說該巾華民國專利公告第物抓號專繼已提出_種良好的解決方案， 惟f利案於讀取SRAM晶胞所儲存之資料後，肖需對所讀取之資料執行反相 ，輯操作，這是由於第6圖之雙埠SRAM晶胞於讀取動作時係讀取儲存於右側 I，η2之資料，仍有改進空間存在。再者，該專觀並未對如何減少漏電 巧作進一步指明，例如，於讀取操作期間，對於右側節點以所儲存之資料為邏 肇輯Low之該等非選擇(n〇nselected)雙埠靜態隨機存取記憶體晶胞(該非選擇雙埠 SRAM曰曰胞之讀取用字元線RWL係呈L〇w狀態）而言，會在讀取用位元線 RBL、存取電晶體論2、驅動電晶體Mn4、以及接地之間形成漏電流(iea]dng CUITent)路徑，該等非選擇雙埠SRAM晶胞之漏電流會干擾選擇(selected)雙埠 晶胞(該選擇雙埠SRAM晶胞之讀取用字元線RWL係呈狀態)之正 吊4取操作’而導致降低感測容限(sense margin)，嚴重的話，甚至會造成讀 取錯誤之問題，因此亦仍有改進空間存在。此外，該專利案並未對如何減少待 機模式時之漏電流作進一步指明。 —有鑑於此，本創作之主要目的係提出一種於讀取雙埠SRAM晶胞所儲存之 • 資料後’無須再對所讀取之資料執行反相邏輯操作之運算。 本創作之次要目的係提出一種雙埠SRAM晶胞，其能有效降低讀取干擾， 並可藉此以有效提感測容限及有效提高讀取可靠度。 本創作之再一目的係提出一種雙埠SRAM晶胞，其能有效降低待機模式時 之漏電流。 【新型内容】 本創作提出一種具低漏電流之雙埠SRAM，其係包括複數個雙埠sram晶胞 ⑴’該等雙埠SRAM晶胞⑴係連接在高電壓節點(VH)與低電壓節點(VL)之間； 一第一偏壓電路(2)，該第一偏壓電路(2)係用以接收第一控制信號(SAP)，且於 M302763 δ亥第控制彳s號(SAP)為代表主動模式(actjve m〇(je)之邏輯低位準時，將高電 供應電壓(hvdd)供應至該高電壓節點(VH)，而於該第一控制信號(8Αρ)ϋ 待機模式(standby mode)之邏輯高位準時，則將低電源供應電壓(1^〇〇)供應至ς 高電壓節點(VH);以及-第二偏壓電路(3)，該第二偏壓電路(3)係用以接收^ 二控制信號(SAN)，且霞第三控制錢(SAN)為代表主_紅邏輯高位準 時，將接地電壓供應至該低電壓節點(VL)，而於該第二控制信號(SAN)為代表 待機模式之邏輯低位準時，則將較接地電壓為高之一電壓供應至該低電壓節點 (VL)。每-雙埠SRAM晶胞⑴更包含：—第一反相器，係由第一pM〇s電晶體㈣ 與第一NMOS電晶體(Ml)所組成；一第二反相器，係由第二脱〇|§電晶體㈣與 第二NMOS電晶體(Ml)所組成；一儲存節點(A)，係由該第一反相器之輸出端^ 馨形成，-反相儲存節點(B)，係由該第二反相器之輸出端所形成；一寫入用選擇 電晶體(MWS) ’係連接在該齡節點(A)與寫人用位元線(WBL)之間，且間極連 接至寫入用字元線(WWL); -讀取用選擇電晶體(MRS)，其一端連接至讀取用位 元線(RBL)，另一端與反相電晶體(MINV)相連接，而閘極則連接至讀取用字元 線(RWL);以及一反相電晶體(MINV)，其一端與該讀取用選擇電晶體⑽^相連 接，另一端連接至接地，而閘極則連接至反相儲存節點(B)。 該第一反相器和該第二反相器係呈交互耦合連接，亦即該第一反相器之輸出 (即儲存節點A)係連接該第二反相器之輸入，而該第二反相器之輸出（即反相儲存 節點B)則賴該第一反相器之輸人，並且該第一反相器之輸出(儲存節點a)係用 φ於儲存SRAM晶胞之資料，而該第二反相器之輸出(反相儲存節點B)則用於儲存 SRAM晶胞之反相資料；同時將用於儲存SRA]y^a胞反相資料之反相儲存節點b 經由該反相電晶體(MINV)及該讀取用選擇電晶體(MRS)而連接至讀取用位元線 (RBL)，藉此，即能解決先前技藝於讀取SRAM晶胞所儲存之資料後，尚需對所 讀取之資料再執行反相邏輯操作之問題。此外，本創作亦具有低讀取干擾、高 讀取可靠度、電路結構簡單、以及低次臨界漏電流等多重功效。 【實施方式】 根據上述之目的，本創作提出一種具低漏電流之雙埠SRAM，該具低漏電流 之雙埠SRAM如第7圖所示，其係包括複數個雙埠SRAM晶胞(1)，該等雙埠81^ M302763 晶胞(1)係連接在高電壓節點(VH)與低電壓節點(VL)之間；一第一偏壓電路 f :偏壓電路(2細以接收第-控制信號(SAp)，且於該第—㈣信號 為代表主動模式(activemode)之邏輯低位準時，將高電源供應電 該高電壓_则，祕該第-控繼號⑽)域表待顧式(_^二 之邏輯高辦時’麟低電職應賴(LVdd)做域冑賴_(卿；以及 -第二偏壓電路(3) ’該第二偏壓電路(3)個以接收第二控制信號(san)，且於 該第二控制信號(SAN)為代表主動模式之邏輯高位準時，將接地電壓供應至該低 電鮮點(VL)，祕該f二㈣信號(SAN)域树顧紅賴低位準時， 則將健地賴為高之-電驗應至該低領雜(VL);其巾，每-雙蟑sram 晶胞⑴更包含：一第一反相器，係由第一PMOS電晶體(P1)與第一麵〇8電晶體 籲_所組成；-第二反減’係由第：PM〇s電晶體㈣與第工應⑽電晶體_ 所組成；-儲存節點(A) ’係由該第一反相旨之輸出端所形成；一反相儲存節點 (B) ’係由該第二反相器之輸出端所形成；一寫入用選擇電晶體(mws)，係連接 在该儲存節點(A)與寫入用位元線(WBL)之間，且閘極連接至寫入用字元線 (WWL); -讀取用選擇電晶體(MRS)，其一端連接至讀取用位元線(rbl)，另^ 端與反相電晶體(MINV)相連接，而閘極則連接至讀取用字元線(RWL);以及一 反相電晶體(MINV)，其一端與該讀取用選擇電晶體(MRS)相連接，另一端連接 至接地，而閘極則連接至反相儲存節點(B)。 請再參考第7圖，該第一反相器和該第二反相器係呈交互耦合連接，亦即該 第一反相器之輸出（即節點A)係連接該第二反相器之輸入，而該第二反相器之輸 出（即節點B)則連接該第一反相器之輸入，並且該第一反相器之輸出（節點A)係用 於健存SRAM晶胞之資料，而該第二反相器之輸出（節點B)則用於儲存81^^晶 胞之反相資料，同時將該第一反相器之第一NMOS電晶體(Ml)之源極連接至寫 入用子元線(WWL) ’而该用於儲存SRAM晶胞反相資料之節點b則經由該反相電 晶體(MINV)及該讀取用選擇電晶體(MRS)連接至讀取用位元線(rbl)。再者，該 第一偏壓電路(2)係由一第三PMOS電晶體(P21)、一第四PMOS電晶體(P22)以及 一第三反相器(123)所組成，該第三PMOS電晶體(P21)之源極、閘極與汲極係分 別連接至该局電源供應電壓(HVdd)、該第一控制信號(SAP)與該高電壓節點 (VH) ’该第四PMOS電晶體(P22)之源極、閘極與沒極係分別連接至該低電源供 應電壓(LVDD)、該第三反相器(123)之輸出端與該高電壓節點(VH)，而該第三反 9 M302763 相器(12=之輪入端則用以接收該第一控制信號(SAp)。此外，該第二偏壓電路⑴ 係由一第=_s電晶體_)以及一第四_8電晶體(M32)所組成，該第三 NMOS^^iyBl)之源極、_與祕齡财接至接地電壓、該第二控 號(酬與該低電壓節點(VL)，該第_〇s電晶體(觀)之源 齡 電壓，而巧與汲極係連接在—起，並連接至該低縣節點(vl)。 接 ^此值付注意的是，本創作為了防止感·限(s_啊㈤降低，於是 將該讀取用字το線(RWL)於非操作期間之電壓位準設定成低於接地電壓(例如 -0.5伙特）’亦即’ _取用字元線(RWL)於讀取操作期間係設定為該高電源供庳 電壓(HVDD) ’而於讀取操作以外之期_設定為低於接地電壓之電壓㈣ 入操作期間係設定為該高電源供應 電屋(hvdd)，而於寫入操作以外之期間則設定為接地電壓。 .茲依雙埠SRAMU作料制第7圖之摘作健實補•作原理如 下· (I)主動模式(active mode) 此時第-控制信號(SAP)為邏輯低位準，而第二控制信號(_為邏輯高位 準，《輯低位準之帛-控制信號⑽)可使得__偏壓電路⑺中之第三黯^ =體通）’於是可將高電源供應電壓(HVdd)供應至高電壓節點 (W)，而該邏Μ位準之第二㈣錢(SAN)可使得第二偏魏路⑴中之第 二NM0S電晶體(M31) on(導通）’於是可將低麵節點(vl)拉下至接地電壓。 $來依雙璋SRAM晶胞之4種寫入狀態說明第7圖之本創條佳實施 何完成寫入動作。 (一）郎點A原本儲存邏輯〇，而現在欲寫入邏輯〇 ，寫入動作發生前(寫人时元線佩騎地電壓），讀賴字元線rwl 為低於接地電壓之電壓位準(例如_〇.5伏特），第一應〇s電晶體m為 ON(導通）。因為第-nm〇s電晶體M1為〇N，所以當寫入動作開始時， 寫入用字兀線WWL由Low(接地電麵High(高電源供應電壓焉〇)，節 點A的電壓會跟隨寫入用字元線WWL的電壓而上升。當寫入用字元線 WWL的電壓大於寫入用選擇電晶體MWS的臨界電壓時，寫入用選擇電晶 體MWS由OFF(截止)轉變為0N(導通)，此時因為寫入用位元線佩是接 地電壓’所以會將節點A放電。t寫人鱗結束，寫人財元線wwl由 M3 02763The operation of the SRAM is simple and does not require an update operation, so it has the advantages of high speed and low power consumption. At present, the mobile electronic device represented by mobile phone is the indispensable role in the computer industry. After the power is turned off, the data is still secret, and it is divided into dynamic random names. For the mainstream. This is the secret SRAM with small current, suitable for continuous mobile phones, and the continuous standby time can be extended by the mobile phone. Figure 1 shows the circuit of a 6T static random access memory (sram) cell. The PMOS transistors pi and p2 are called load transistors, and the M2 is called drive = transistor, M3. And M4 is called access transistor, WL is word line (w〇rd _, and BL and brain are bit line and complementary bit line respectively, since the SRAM cell needs 6 transistors and drives the crystal • The current drive capability ratio between the body and the access transistor (ie, the cell ratio) is usually set between 2 and 3, resulting in high integration difficulties and high price defects. ^ Used to reduce 6T static One way to count the number of transistors in a random access memory (SRAM) cell is shown in Figure 2. Figure 2 shows the electrical = schematic of a single-ended 5T static random access memory (SRAM) cell. Compared with the 6T static random access memory (SRAM^$ cell) of Fig. 1, this 5T static Ik machine accesses the suffix (SRAM) unit cell ratio 6 Τ static random access memory (sram) unit cell There is one less transistor and one less bit line. However, it is quite difficult to write the logic 1 in the 5T static random access memory (SRAM) cell. In the case where the node A on the left side of the cell originally stores a logic 0, since the charge of the node A is transmitted only from the bit line BL alone, it is difficult to write the previously written logic of the node a to a logic 1. To reduce the 6T static random Another way to access the number of transistors in a memory cell (SRAM) cell is M302763 = in Figure 3. Figure 3 shows a circuit diagram of a 4T static random access memory (SRAM) cell. Compared with the 6T static random access memory (SRAM) cell in Figure 1, the 4T static random access memory (SRAM) cell is less than the 6T static random access memory (SRAM) cell. The transistor, but the 4T static random access memory (SRam) unit cell has a large power consumption loss, because there is a current fixed through the resistors R1, R2, for the two specific states in the memory cell One state = one hundred, one of the functions of the resistor is to raise and compensate the leakage current of the driving transistor and the access transistor, and the other resistor acts as a current limiting the current flowing to the node storing the logic 。. Progress in the reduction of the number of crystals, the next The reduction in the number of transistors will reduce the number of transistors to three, which is less than the number of transistors in the 4T static random access memory (SRAM) cell. The fourth figure shows such 3T static random access memory. Schematic diagram of a sram cell, which is quite difficult except for the presence of write logic 1, and because the resistance of resistors R1, R2 must be extremely high, in the range of 1 billion to 10 billion ohms, in order to keep it as low as possible Standby power consumption. As a result, the recovery time of these resistors is too long, resulting in an inability to properly boost and/or maintain a stable high level in the memory cell. Next, we discuss the static random access memory (SRAM) and double埠Architecture, the sixth figure of the SRAM cell is the SRAM cell. It uses two bit lines BL and BLB for reading. The written action, that is, the reading and writing are the same, the same pair of bit lines are achieved, so that only the reading or writing can be performed at the same time, therefore: when designing a pair with simultaneous literacy埠 Static random access memory, you need to add two more Access transistor and another pair of bit lines (refer to the circuit shown in Figure 5, where wblb is the write bit line pair, RBL and RBLB are the read bit line pair, WWL is written Using the word line, RWL is the read word line), which greatly increases the area of the memory cell, if we can simplify the structure of the 5 cell, so that a bit line is responsible for the reading action, and The other bit line is responsible for the write operation. When designing the dual-bit static random access memory, the memory cell does not need to add two transistors and another pair of bit lines, so that the area of the memory cell It will be much reduced. The reason why the traditional 單埠 熊 bear access memory cell does not use this method is because of the problem of logic 1 as described above. In order to solve the problem that only one bit line is responsible for reading, the other bit line is responsible for writing, and solving the problem of writing logic, in order to realize the problem of reading only one bit line in double-click static random access memory, China National Patent Bulletin No. 434537, published on May 11, 1990, "Six-Cell Double-Cell Memory Unit Circuit for Low-Voltage Static Random Access Memory (Reading for Two-Dimensional Unit Line)" M302763 4(8)^ is the iH type solution, and the sixth figure is the 帛4(a) diagram (circuit diagram) of the patent case, which changes the source of the driving transistor Mn3 from the original ground to the connection to the write It has been confirmed by the word line WWL that it can realize the function of reading only one bit line, and the other line of 70 lines is responsible for reading and writing the unit line of the action, and can also operate. The low supply voltage of i volts can also solve the problem of the difficulty of writing logic. Although the towel of the Republic of China patent notice has been proposed as a good solution, after reading the data stored in the SRAM cell, Xiao needs to invert the data read. The operation is due to the fact that the double-sided SRAM cell of Fig. 6 reads the data stored on the right side I, η2 during the reading operation, and there is still room for improvement. Moreover, the spectacle does not further specify how to reduce the leakage, for example, during the read operation, the non-selected (n〇nselected) pairs of the stored data for the right node are logically Low. The static random access memory cell (the read word line RWL of the non-selected double-埠 SRAM cell is in the L〇w state), will be in the read bit line RBL, access transistor theory 2. A path of leakage current (iea]dng CUITent) is formed between the driving transistor Mn4 and the ground. The leakage current of the non-selected double-turn SRAM cell interferes with the selected double-turn cell (the selected double-turn SRAM) The read cell line RWL of the unit cell is in the state of "suspension 4 operation" resulting in lowering the sense margin, and in serious cases, even causing reading errors, so there is still improvement. Space exists. In addition, the patent does not further specify how to reduce leakage current in standby mode. - In view of this, the main purpose of this creation is to propose an operation that performs an inverse logic operation on the read data after reading the data stored in the dual-slice SRAM cell. The second objective of this creation is to propose a double-turn SRAM cell, which can effectively reduce the read interference, and can effectively improve the sensing tolerance and effectively improve the read reliability. A further object of the present invention is to propose a double-turn SRAM cell which can effectively reduce leakage current in standby mode. [New content] This paper proposes a double-drain SRAM with low leakage current, which includes a plurality of double-埠sram cells (1)' These double-turn SRAM cells (1) are connected to high-voltage nodes (VH) and low-voltage nodes. Between (VL); a first bias circuit (2) for receiving the first control signal (SAP), and controlling the 彳s number at M302763 SAP) supplies a high power supply voltage (hvdd) to the high voltage node (VH) on behalf of the active mode (actjve m〇(je) logic low level on time), and in the first control signal (8Αρ)ϋ standby mode ( The logic high level of standby mode) supplies a low power supply voltage (1^〇〇) to the high voltage node (VH); and a second bias circuit (3), the second bias circuit ( 3) is used to receive the ^2 control signal (SAN), and the third control money (SAN) represents the main_red logic high level on time, the ground voltage is supplied to the low voltage node (VL), and the second The control signal (SAN) is a logic low level on behalf of the standby mode, and a voltage higher than the ground voltage is supplied to the low voltage node (VL). Each - double 埠 SRAM cell (1) The method comprises: a first inverter, which is composed of a first pM〇s transistor (4) and a first NMOS transistor (M1); and a second inverter, which is composed of a second dislocation|§ transistor (4) and a second NMOS transistor (M1); a storage node (A) formed by the output of the first inverter, and an inverted storage node (B), the second inverter The output terminal is formed; a write select transistor (MWS) is connected between the age node (A) and the write bit line (WBL), and the interpole is connected to the write word line (WWL); - Read Selective Transistor (MRS) with one end connected to the read bit line (RBL), the other end connected to the inverting transistor (MINV), and the gate connected to the read Using a word line (RWL); and an inverting transistor (MINV), one end of which is connected to the read select transistor (10), the other end is connected to ground, and the gate is connected to the inverting storage node ( B) The first inverter and the second inverter are connected in an alternating coupling, that is, the output of the first inverter (ie, storage node A) is connected to the input of the second inverter, and The output of the second inverter That is, the inverting storage node B) depends on the input of the first inverter, and the output of the first inverter (storage node a) uses φ to store the data of the SRAM cell, and the second inversion The output of the device (inverting storage node B) is used to store the inverted data of the SRAM cell; at the same time, the inverting storage node b for storing the SRA]y^a cell inversion data is passed through the inverting transistor (MINV) And the read selection transistor (MRS) is connected to the read bit line (RBL), thereby solving the previous technique for reading the data stored in the SRAM cell, and still need to read the read Take the data and then perform the inverse logic operation. In addition, this creation has multiple effects such as low read disturb, high read reliability, simple circuit structure, and low sub-critical leakage current. [Embodiment] According to the above object, the present invention proposes a double-turn SRAM with low leakage current, which is shown in FIG. 7 and includes a plurality of double-turn SRAM cells (1). ), the double 埠 81 ^ M302763 unit cell (1) is connected between the high voltage node (VH) and the low voltage node (VL); a first bias circuit f: the bias circuit (2 Receiving a first control signal (SAp), and when the first (four) signal is a logic low level representing an active mode, the high power supply is supplied with the high voltage _, then the first control number (10) domain table Waiting for the style (_^2 logic high office time] Lin low electricity job should rely on (LVdd) do domain _ _ (Qing; and - second bias circuit (3) 'The second bias circuit ( 3) to receive the second control signal (san), and when the second control signal (SAN) is a logic high level representing the active mode, the ground voltage is supplied to the low power point (VL), the secret is f (4) The signal (SAN) domain tree is dependent on the low-level punctuality, then the health ground is high - the test should be to the low-collar (VL); its towel, each-double sram cell (1) contains: one An inverter, consisting of the first P The MOS transistor (P1) is composed of the first surface 电8 transistor _ _; the second inverse reduction is composed of: PM 〇s transistor (4) and DM (10) transistor _; - storage node ( A) ' is formed by the output of the first inversion; an inverting storage node (B) ' is formed by the output of the second inverter; a write selection transistor (mws) Connected between the storage node (A) and the write bit line (WBL), and the gate is connected to the write word line (WWL); - a read select transistor (MRS), One end is connected to the read bit line (rbl), the other end is connected to the inverting transistor (MINV), and the gate is connected to the read word line (RWL); and an inverting transistor ( MINV), one end of which is connected to the read select transistor (MRS), the other end is connected to ground, and the gate is connected to the inverting storage node (B). Please refer to Fig. 7, the first The phase converter and the second inverter are connected in an alternating coupling, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the output of the second inverter is (ie node B) then connect the first The input of the inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store 81^^ Inverting data of the unit cell, and simultaneously connecting the source of the first NMOS transistor (M1) of the first inverter to the write sub-element (WWL)' for storing the SRAM cell inversion data The node b is connected to the read bit line (rbl) via the inverting transistor (MINV) and the read select transistor (MRS). Further, the first bias circuit (2) is The third PMOS transistor (P21), a fourth PMOS transistor (P22) and a third inverter (123), the source, the gate and the gate of the third PMOS transistor (P21) The poles are respectively connected to the local power supply voltage (HVdd), the first control signal (SAP) and the high voltage node (VH) 'the source, the gate and the immersion of the fourth PMOS transistor (P22) Connected to the low power supply voltage (LVDD), the output of the third inverter (123) and the high voltage node (VH), and the third reverse 9 M302763 phase (12= For receiving the first control signal (SAp) . In addition, the second bias circuit (1) is composed of a =_s transistor_) and a fourth_8 transistor (M32), the source of the third NMOS^iyBl), and the secret age Connected to the ground voltage, the second control number (reward to the low voltage node (VL), the source voltage of the first _ s transistor (view), and the connection with the 汲 系 ,, and connected To the lower county node (vl). It is important to note that this creation is to prevent the sense limit (s_ah (five) from decreasing, so the voltage of the read word το line (RWL) during non-operation period is used. The level is set lower than the ground voltage (for example, -0.5 nt), that is, the _ fetch word line (RWL) is set to the high power supply voltage (HVDD) during the read operation. The period other than the operation _ is set to a voltage lower than the ground voltage (4). The high power supply house (hvdd) is set during the operation period, and is set to the ground voltage during the period other than the write operation. The material of the production system is summarized as the complement of the work. The principle is as follows: (I) Active mode At this time, the first control signal (SAP) is the logic low level, and the second control signal (_ is The logic high level, "the low level of the threshold - control signal (10) can make the third 黯 = = 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压 偏压W), and the second (four) money (SAN) of the logic level can make the second NM0S transistor (M31) on (the second) in the second partial Wei road (1) can then pull the low-surface node (vl) Down to the ground voltage. $ According to the four types of write state of the SRAM cell, the figure 7 shows how to complete the write operation. (1) Lang Point A originally stored the logic, but now wants to write Into the logic 〇, before the write action occurs (when the person writes the line of the line to ride the ground voltage), the read word line rwl is lower than the ground voltage level (eg _〇.5 volts), the first should 〇s The transistor m is ON (conducting). Since the first-nm 〇s transistor M1 is 〇N, when the write operation starts, the write word line WWL is made of Low (high power supply voltage 焉〇), the voltage of the node A rises following the voltage of the write word line WWL. When the voltage of the write word line WWL is greater than the threshold voltage of the write select transistor MWS The write selection transistor MWS is changed from OFF (off) to 0N (conduction). At this time, because the write bit line is the ground voltage, the node A will be discharged. Line wwl by M3 02763
High變Low時，第- nm〇S電晶體M1仍為〇N，節點A的電壓便跟隨寫 入用字元線WWL的龍逐漸下降至GV，而完成邏㈣的寫入動作。 (二）郎點A原本儲存邏輯〇，而現在欲寫入邏輯1 在寫入動作發生前(寫入用字元、線WWL為接地電壓），讀取用字元線RWL 為低於接地電壓之電壓位準(例如_〇·5伏特），第一函〇8電晶體為⑽ (導，）。因為第_NM〇S電晶體Ml為ON，所以當寫入動作開始時，寫入 用字兀線WWL由Low(接地電壓)轉High(高電源供應電壓，節點a 的會跟隨寫人財元線WWL的·而上升。#寫人时元線wwl 的電壓大於寫入用選擇電晶體MWS的臨界電壓時，寫入用選擇電晶體 MWS由OFF(截止)轉變為0N(導通)，此時因為寫入用位元線抓匕是紐奶， _ 並且因為第—丽⑽電晶體M1仍為⑽，所以會將節點A快速充電，稱 後’待第一 PMOS電晶體P1由OFF(截止)轉變為〇N(導通)時(由於節點B 由High朝Low方向轉變，當節點B之電壓位準下降至足以使第一 pM〇s 電晶體P1導通時，該第-PMOS電晶體P1即由〇FF轉變為〇N)，即可將 節點A充電至高電源供應電壓(HVdd)之^^準。當寫入動作結束，寫入用字 元線WWL由High變Low時，第一 PMOS電晶體P1為⑽，節點a的電 壓即維持在高電源供應電壓(HVDD)之位準，而完成邏輯丨的寫入動作。 (二）節點A原本健存邏輯1，而現在欲寫入邏輯1 在寫入動作發生前(寫入用字元線WWL為接地電壓），讀取用字元線RWL φ 為低於接地電壓之電壓位準(例如-〇·5伏特)，第一 PMOS電晶體P1為ON(導 通）。當寫入用字元線WWL由Low(接地電壓)轉High(高電源供應電壓 HVDD)，且該寫入用字元線WWL的電壓大於寫入用選擇電晶體^^^8的臨 界電壓時，寫入用選擇電晶體MWS由OFF(截止)轉變為on(導通），此時因 為寫入用位元線WBL是High，並且因為第一 PM〇s電晶體ρι仍為〇N， 所以節點A的電壓不會變動，而會平穩地保持在高電源供應電壓(HVdd)之 位準，直到寫入週期結束。 (四）節點A原本儲存邏輯1，而現在欲寫入邏輯〇 在寫入動作發生前(寫入用字元線WWL為接地電壓），讀取用字元線RWL 為低於接地電壓之電壓位準(例如-〇·5伏特)，第一 PMOS電晶體P1為ON(導 通）。當寫入用字元線WWL由Low(接地電壓)轉High(高電源供應電壓 11 M302763 且ί寫入用字元線佩的電壓大於寫入用選擇電晶體麵的臨 氣皆^ 入用選擇電晶體MWS由0FF(截止)轉變為ON(導通），此時因 為罵入用位元線WBL是Lgw，所以會將節點A放電 ， 線WWL由High變Low時’第一 _s電晶體如為:，節 點A的電壓便跟隨寫入用字元線佩的電壓逐漸下降謂，而完成邏輯 0的寫入動作。 圖之本創作較佳實施 緊接著依雙埠SRAM晶胞之二種儲存資料狀態說明第7 例如何完成讀取動作。 (一）節點A儲存邏輯〇 在ti買取動作I生別（頃取用字元線RWL為低於接地電壓之電壓位準，例如 -〇·5伏特），寫入用字元線WWL為接地電壓，第二顧〇8電晶體—為 〇FF(截止），第二PM0S電晶體P2為ON(導通），節點B為High(高電源供 應電壓hvdd)。當讀取動作開始時，讀取用字元線RWL由低於接地電壓之 電^位準轉為High(f|m應電壓HVDD)，JL當該讀取肖？；^RWL的 電壓大於該讀取用選擇電晶體MRS之臨界電壓時，讀取用選擇電晶體MRS 由OFF(截止)轉變為on(導通)，此時由於節點b為High，反相電晶體MINV 為ON(導通）’因此，會在讀取用位元線仙乙、讀取用選擇電晶體隱§、反 相電晶體MINV、及接地間形成電流路徑，此電流路徑即會使讀取用位元線 RBL之電壓位準降低，藉此即可感測出節點a係儲存邏輯〇之資料，並完 成邏輯0的讀取動作。 (二）節點A儲存邏輯1 在讀取動作發生前(讀取用字元線RWL為低於接地電壓之電壓位準(例如 -0.5伏特)），寫入用字元線WWL為接地電壓，第二NMOS電晶體M2為 ON (導通），第二PMOS電晶體P2為OFF(截止），節點B為Low (接地電 壓）。當讀取動作開始時，讀取用字元線RWL由低於接地電壓之電壓位準 轉為High(高電源供應電壓hvdd)，且當該讀取用字元線RWL的電壓大於 該讀取用選擇電晶體MRS之臨界電壓時，讀取用選擇電晶體MRS由 OFF(截止)轉變為ON(導通），此時由於節點B為Low (接地電壓），反相 電晶體MINV為OFF(截止），因此，並不會在讀取用位元線RBL、讀取用 12 M302763 選擇電晶體MRS、反相電晶體MINV、及接地間形成電流路徑，結果，讀 取用位元線RBL之電壓位準能平穩地保持在High狀態，藉此即可感測出節 點A係儲存邏輯1之貧料’並完成邏輯1的讀取動作。 其次，說明本創作所提出之雙埠SRAM如何藉由大幅降低非選擇 (non—)雙埠SRAM晶胞之漏電流(ieaking current)，而達成降低讀取干擾及 提高讀取可靠度之功效。電晶體截止時之漏電流(leakingcurrent)主要是來自次臨 界電流(subthreshold cuirent)，於中華民國94年3月8日公告之美國專利公告第 US6865119鮮利案第3(A)及3(B)圖中，即揭露於當今技術，對於NM〇s電晶體 而言，閘源極電壓為-0.1伏特時之次臨界電流約為閘源極電壓為〇伏特時之次臨 籲界電流的1%，因此，藉由將該讀取用字元線(RWL}於非操作期間之電壓位準設 定成低於接地電壓(例如-ο·5伏特），則可大幅地降低非選擇(n_lec㈣ SRAM晶胞之漏電流。 f (II)待機模式(standbymode) 此時第-控制城(SAP)為邏輯高位準，而第二控制信號(SAN)為邏輯低位 準，該邏輯高位準之第-控制信號(SAP)可使得第一偏麼電路(2)中之第5PM〇s 電晶體(P21) OFF(截止），並使得第四PM〇s電晶體(pm) 〇N(導通），於是可 低電源供應電壓(LVDD)供應至高電壓節點(獨；❿該邏輯低位準之第二控 唬(SAN)可使得第三偏壓電路(3)巾之第三麵⑺ 於此時第二偏壓電路(3)中之第四nm〇s電晶體(M32)仍為〇N(導通），於 將低電壓節點(VL)維持在該第四觀〇8電晶體(M32)之臨界電壓的位準。 接下來說明本_於待赌场tandby mGde)時如何減少漏電流，請 圖，第8圖表示了第7圖雙埠SRAM細寺機模柄所產生之各次臨界漏電产 (subthresholdlea^^ . !2 . ΐ3#σ ^ , ^SRAM ^ :接地電壓)，而反相儲存節點⑻為邏輯峨高電源供應電壓 DD)。明再多考苐6圖之先前技藝（我國專利公告第434537號）與第 ，，施例，流經寫人用選擇電晶體(刪)之漏電η，由於待機模= 二二子魂WWf係為接地電壓，因此流經寫入用選擇電晶體⑽ws)之漏電 、第6圖之先前技藝（先前技藝中之跑〇8電晶體論i即相當於本創作實 13 M302763When High becomes Low, the first-nm 〇S transistor M1 is still 〇N, and the voltage of the node A gradually falls to the GV following the write word line WWL, and the logic (four) write operation is completed. (2) Lang point A originally stores logic 〇, but now wants to write logic 1 before the write operation occurs (write character, line WWL is ground voltage), read word line RWL is lower than ground voltage The voltage level (for example, _ 〇 · 5 volts), the first function 8 transistor is (10) (guide,). Since the _NM〇S transistor M1 is ON, when the write operation starts, the write word line WWL is turned from Low (ground voltage) to High (high power supply voltage, and node a will follow the writer's finances. When the voltage of the writing time line wwl is greater than the threshold voltage of the writing selection transistor MWS, the writing selection transistor MWS is turned from OFF (off) to 0N (conducting). Because the write bit line is a new milk, _ and because the first (10) transistor M1 is still (10), node A will be quickly charged, and then the first PMOS transistor P1 is turned OFF (cut). When transitioning to 〇N (conduction) (due to the transition of node B from High to Low, when the voltage level of node B drops enough to turn on the first pM〇s transistor P1, the first PMOS transistor P1 is 〇FF is changed to 〇N), and node A can be charged to the high power supply voltage (HVdd). When the write operation ends and the write word line WWL changes from High to Low, the first PMOS transistor P1 is (10), and the voltage of node a is maintained at the level of the high power supply voltage (HVDD), and the write operation of the logic 完成 is completed. A originally saves logic 1, and now wants to write logic 1 before the write operation occurs (write word line WWL is the ground voltage), and the read word line RWL φ is lower than the ground voltage. (For example, -5 volts), the first PMOS transistor P1 is ON (on). When the write word line WWL is turned from Low (high voltage) to High (high power supply voltage HVDD), and the write is used When the voltage of the word line WWL is greater than the threshold voltage of the write selection transistor ^^^8, the write selection transistor MWS changes from OFF (off) to on (on), at this time because of the write bit line WBL is High, and since the first PM〇s transistor ρι is still 〇N, the voltage of the node A does not fluctuate, but is smoothly maintained at the level of the high power supply voltage (HVdd) until the end of the write cycle. (4) Node A originally stores logic 1, and now writes logic 前 before the write operation occurs (write word line WWL is the ground voltage), and the read word line RWL is lower than the ground voltage. The voltage level (for example, -5 volts), the first PMOS transistor P1 is ON (on). When the write word line WWL is low (grounded) Press) to High (high power supply voltage 11 M302763 and ί write word line line is higher than the input selection transistor surface.) The input selection transistor MWS is changed from 0FF (off) to ON ( Turn on), at this time, since the bit line WBL for the intrusion is Lgw, the node A is discharged, and when the line WWL is changed from High to Low, the first _s transistor is:, the voltage of the node A follows the writing. The voltage of the word line is gradually decreased, and the write operation of the logic 0 is completed. The present invention is preferably implemented in accordance with the state of the two stored data states of the double-chip SRAM cell. (1) Node A stores logic 买 Buying action I in ti (taking the word line RWL as a voltage level lower than the ground voltage, for example, -5 volts), writing the word line WWL to ground The voltage, the second 〇8 transistor - is 〇 FF (off), the second PMOS transistor P2 is ON (conducting), and the node B is High (high power supply voltage hvdd). When the read operation starts, the read word line RWL is turned from the level lower than the ground voltage to High (f|m should be the voltage HVDD), and JL is the read mode? When the voltage of ^RWL is greater than the threshold voltage of the read selection transistor MRS, the read selection transistor MRS is changed from OFF (off) to on (on), and at this time, since the node b is High, the inverting transistor MINV is ON. Therefore, a current path is formed between the read bit line, the read transistor, the inverting transistor MINV, and the ground. This current path will cause reading. The voltage level of the bit line RBL is lowered, thereby sensing that the node a stores the logic data and completes the logic 0 reading operation. (2) Node A storage logic 1 Before the read operation occurs (the read word line RWL is a voltage level lower than the ground voltage (for example, -0.5 volt)), the write word line WWL is the ground voltage. The second NMOS transistor M2 is ON (on), the second PMOS transistor P2 is OFF (off), and the node B is Low (ground voltage). When the read operation starts, the read word line RWL is turned from the voltage level lower than the ground voltage to High (high power supply voltage hvdd), and when the voltage of the read word line RWL is greater than the read When the threshold voltage of the transistor MRS is selected, the read selection transistor MRS is turned from OFF (turned) to ON (on), and at this time, since the node B is Low (ground voltage), the inverting transistor MINV is OFF (cutoff) Therefore, the current path is not formed between the read bit line RBL, the read 12 M302763 select transistor MRS, the inverting transistor MINV, and the ground. As a result, the voltage of the read bit line RBL is read. The level can be kept in the High state smoothly, thereby sensing that the node A stores the logic 1 of the logic 1 and completes the logic 1 reading operation. Secondly, it shows how the double-turn SRAM proposed in this paper can reduce the read interference and improve the read reliability by greatly reducing the leakage current of the non-selective (non-) double-turn SRAM cell. The leakage current at the turn-off of the transistor is mainly derived from the subcritical current (subsreshold cuirent), and is disclosed in the US Patent Publication No. US6865119, No. 3 (A) and 3 (B) of the Republic of China on March 8, 1994. In the figure, it is disclosed in the current technology. For the NM〇s transistor, the subcritical current when the gate source voltage is -0.1 volt is about 1% of the secondary threshold current when the gate source voltage is 〇V. Therefore, by setting the voltage level of the read word line (RWL) during the non-operation period to be lower than the ground voltage (for example, -ο·5 volts), the non-selection (n_lec(four) SRAM crystal can be greatly reduced). The leakage current of the cell f (II) standby mode (standbymode) At this time, the first control city (SAP) is a logic high level, and the second control signal (SAN) is a logic low level, and the logic high level is the first control signal. (SAP) can make the 5th PM〇s transistor (P21) in the first bias circuit (2) OFF (cut), and make the fourth PM〇s transistor (pm) 〇N (conducting), so that it can be low The power supply voltage (LVDD) is supplied to the high voltage node (alone; the logic low level second control (SAN) can make the third bias The third side of the road (3) towel (7) is at this time the fourth nm 〇s transistor (M32) in the second bias circuit (3) is still 〇N (conducting), at the low voltage node (VL) Maintain the level of the threshold voltage of the fourth transistor 8 (M32). How to reduce the leakage current when the TD is used in the casino, please see Figure 8, Figure 7 shows the double 埠The critical leakage current produced by the SRAM fine temple machine mold handle (subthresholdlea^^ . !2 . ΐ3#σ ^ , ^SRAM ^ : ground voltage), and the inverting storage node (8) is the logic high power supply voltage DD) Ming will test the previous skills of the 6th figure (China Patent Announcement No. 434537) and the first, the example, the leakage η of the selected transistor (deleted) through the writer, because the standby mode = the second and second sons WWf is The grounding voltage, therefore, the leakage of the input transistor (10) ws), the prior art of Figure 6 (the previous technique of the run-on 8 crystal theory i is equivalent to this creation 13 M302763
施例中之該寫入用選擇電晶體MWS)具有相同的漏電流；關於流經第一 PMOS 電晶體(P1)之漏電流I2，由於待機模式時該高電壓節點(VH)係具有低電源供應電 壓(LVdd)之電壓位準，該低電源供應電壓(lvdd)之電壓位準係小於該高電源供應 電壓(HVDD)，又因為該反相儲存節點b為邏輯High(高電源供應電壓hvdd)， 因此流經第一 PMOS電晶體(Pi)之漏電流l2係遠小於第6圖之先前技藝者（先 前技藝中之PMOS電晶體Mpl即相當於本創作實施例中之該第一 pM〇S電晶體 P1);關於流經第二NMOS電晶體(M2)之漏電流13,由於待機模式時該低電壓 節點(VL)係維持在該第四電晶體(M32)之臨界電壓的位準，又因為該儲 存節點A為邏輯Low(接地電壓），因此流經該第二NM〇s電晶體(m2)之漏電流 I3係遠小於第6圖之先前技藝者（先前技藝中之_〇8電晶體即相當於本 •創作實施例中之該第二NMOS電晶體M2);關於流經讀取用選擇電晶體(mrs) 之漏電流I4,由於待機模式時該讀取用字元線(RWL)係設定成低於接地電壓(例 如-0.5伏特)之電壓位準，又因為該反相儲存節點B為邏輯扭幽(高電源供應電壓 HVDD)，於疋可將該讀取用選擇電晶體之源極電壓固定在該第四 電晶體(M32)之臨界電壓的位準，因此可大幅減少流經該讀取用選擇電晶體 (MRS)之漏電流14〇 [由以上分析可知，本創作於待機模式m〇(je)時確實可有效減少漏 電流。 · φ 【創作功效】 本創作所提出之雙埠SRAM，具有如下功效·· (1) 頃取結果與雙埠SRAM晶胞所儲存之資料相同··由於本創作所提出之雙埠 SRAM晶胞於讀取時，係將用於儲#SRAM晶胞反相資料之節點B，經由反 相$晶體(MINV)及讀取用選擇電晶體(MRS)所組成的反相放大器，而連接 至讀取用位元線(RBL)，因此，讀取結果係與雙埠SRAM晶胞所儲存之資料 相同； ' (2) 低讀取干擾及高讀取可靠度：由於本創作所提出之雙淳8麵晶胞於讀取 時’係將棘肖字磁(RWL)於雜作綱之雜辦奴絲於接地電屢 (例如-0.5伏特），結果，可藉由大幅地降低非選擇(n〇nseiected)雙淳8麵 晶胞之漏電流，而有效達成降低讀取干擾及提高讀取可靠度之功效； M302763 簡單之功效 ⑶結構簡單·由於本創作所提出之雙埠SRAM晶胞可有效實現僅以一條讀取用 位兀，(RBL)負責讀取的動作、僅以一條寫入用位元線(wbl)負責寫入的動 單位元線啊賴的魏，因此本創作所提&之雙勒亦具備結構 ⑷低次臨界漏電流··由於本創作所提出之雙埠SRAi·待麵鱗，高電壓節 點=1)係為低電源供應電壓(LVdd)之電壓位準，而低電壓節點外)係固定 在，_M〇S電晶體(M32)之臨界電壓的位準，且讀取用字元線(RWL)之 電壓位準係固定在低於接地電壓(例如-〇·5伏之， 提出之雙埠SRAM亦具備低次臨界漏電流之功效。 匕本創作所 士可作侧揭露並贿了輯之最佳實關，但舉凡熟悉本技術之人 m任㈣式或是細紅可能賴化均未麟本齡的精神與範圍。因 ’有相關技術範缚内之改變都包括在本創作之申請專利範圍内。 15 M302763 【圖式簡單說明】 第1圖係顯不習知6τ靜態隨機存取記憶體(SRAM)晶胞之電音 第2圖係顯不習知5τ靜態隨機存取記憶體(SRAM)晶胞之電路示=圖: 第3圖係顯不習知4Τ靜態隨機存取記憶體(SRAM)晶胞之電路示· ，4圖係顯不習知3T靜態隨機存取記憶體(祖冲晶胞之電路示意二； ，5圖係顯不習知雙埠靜態賴存取記憶體(SRAM)晶胞之電路示意圖； 第6圖係顯不我國專利公告第434537號之習知雙璋靜態隨機存取 (SRAM)晶胞之電路示意圖； 丨心體 第7圖係顯不本創作所提出之雙埠靜態隨機存取記憶體(SRAM)之電路示音 圖； 〜 第8圖係顯不第7圖雙埠SRAM於待機模式時所產生之各次臨界漏電流。 【主要元件符號說明】 A 儲存節點 B 反相儲存節點 BL 位元線 BLB 互補位元線 RBL 讀取用位元線 RBLB 讀取用互補位元線 WBL 寫入用位7〇線 WBLB 寫入用互補位元線 Ml NMOS電晶體 M2 NMOS電晶體 M3 NMOS電晶體 M4 NMOS電晶體 M5 NMOS電晶體 M6 M0S電晶體 Mpl PMOS電晶體 Mp2 PM0S電晶體 Mnl NMOS電晶體 Mn2 NMOS電晶體 Mn3 NMOS電晶體 Mn4 NMOS電晶體 MRS 讀取用選擇電晶體 MWS 寫入用選擇電晶體 MINV 反相電晶體 Vdd 電源電壓 nl 儲存節點 n2 反相儲存節點 PI PM0S電晶體 P2 PM0S電晶體 RWL 讀取用字元線 WWL 寫入用字元線 R1 電阻器 R2 電阻器 1 SRAM晶胞 2 第一偏壓電路 3 第二偏壓電路 SAP 第一控制信號 SAN 第二控制信號 HVdd 高電源供應電壓 LVDD低電源供應電壓 VH 高電壓節點 M302763 VL 低電壓節點 P21 第三PMOS電晶體 P22 第四PMOS電晶體 123 第三反相器 M31 第三NMOS電晶體 M32 第四NMOS電晶體 WL 字元線 17The write select transistor MWS) has the same leakage current in the embodiment; with respect to the drain current I2 flowing through the first PMOS transistor (P1), the high voltage node (VH) has a low power supply due to the standby mode. The voltage level of the supply voltage (LVdd), the voltage level of the low power supply voltage (lvdd) is less than the high power supply voltage (HVDD), and because the inverting storage node b is logic High (high power supply voltage hvdd) Therefore, the leakage current l2 flowing through the first PMOS transistor (Pi) is much smaller than that of the prior art of FIG. 6 (the PMOS transistor Mpl in the prior art is equivalent to the first pM in the present embodiment). S transistor P1); regarding the leakage current 13 flowing through the second NMOS transistor (M2), the low voltage node (VL) is maintained at the level of the threshold voltage of the fourth transistor (M32) due to the standby mode And because the storage node A is a logic Low (ground voltage), the leakage current I3 flowing through the second NM〇s transistor (m2) is much smaller than that of the prior art of FIG. 6 (in the prior art) 8 transistor is equivalent to the second NMOS transistor M2) in the present embodiment; By selecting the leakage current I4 of the transistor (mrs), the read word line (RWL) is set to a voltage level lower than the ground voltage (for example, -0.5 volts) in the standby mode, and because of the inverted storage Node B is a logic twist (high power supply voltage HVDD), and the source voltage of the read selection transistor can be fixed at the threshold voltage of the fourth transistor (M32), thereby being greatly reduced. The leakage current flowing through the read selection transistor (MRS) is 14 〇 [It can be seen from the above analysis that the leakage current can be effectively reduced in the standby mode m 〇 (je). · φ [Creation Efficacy] The double-twisted SRAM proposed by this creation has the following effects: (1) The result is the same as that stored in the double-埠 SRAM cell. · Due to the creation of the double-埠 SRAM cell At the time of reading, the node B for storing the #SRAM cell inversion data is connected to the read via an inverting amplifier composed of an inversion $crystal (MINV) and a read selection transistor (MRS). The bit line (RBL) is taken, so the reading result is the same as that stored in the double-turn SRAM cell; ' (2) Low read disturb and high read reliability: due to the proposed double vision When the 8-sided unit cell is read, it is used to make the spine of the sinusoidal magnetic (RWL) in the miscellaneous syllabus of the grounding power (for example, -0.5 volts). As a result, the non-selection can be greatly reduced (n 〇nseiected) The leakage current of the double-sided 8-sided unit cell, effectively achieving the effect of reducing read interference and improving read reliability; M302763 Simple effect (3) Simple structure · Due to the double-埠 SRAM cell proposed by this creation Implements only one read bit, (RBL) is responsible for reading, only one write bit line (wbl) The unit that is responsible for the writing of the unit line is the Wei, so the double-learned by the creation of this creation also has the structure (4) low-threshold leakage current ······························ Node=1) is the voltage level of the low power supply voltage (LVdd), and the low voltage node is fixed at the level of the threshold voltage of the _M〇S transistor (M32), and the word line for reading is used. The voltage level of (RWL) is fixed below the grounding voltage (for example, -〇·5 volts, and the proposed double-turn SRAM also has the effect of low-minal leakage current. 匕This creation can be exposed and bribed. The best practice of the series, but the people who are familiar with the technology, m (4) or fine red may not be the spirit and scope of the age. Because of the changes in the relevant technical constraints are included in this creation Within the scope of the patent application. 15 M302763 [Simple description of the diagram] Figure 1 shows the unknown electrical sound of the 6τ static random access memory (SRAM) unit cell. Figure 2 is not known 5τ static random access The circuit of the memory (SRAM) cell shows = Figure: Figure 3 shows the unknown 4 Τ static random access memory (SRAM) cell The circuit shows · 4, the system is not well-known 3T static random access memory (the circuit diagram of the ancestral cell is two; 5, the system is not known to the dual-static static access memory (SRAM) cell Circuit diagram; Figure 6 shows the circuit diagram of the conventional double-static static random access (SRAM) unit cell of No. 434537 of the Chinese Patent Publication No. 434537; the figure 7 of the heart-shaped body is not static The circuit diagram of the random access memory (SRAM); ~ Figure 8 shows the critical leakage current generated by the dual-SRAM in the standby mode. [Description of main component symbols] A Storage node B Inverting storage node BL Bit line BLB Complementary bit line RBL Read bit line RBLB Read complementary bit line WBL Write bit 7 line WBLB Write Complementary bit line M1 NMOS transistor M2 NMOS transistor M3 NMOS transistor M4 NMOS transistor M5 NMOS transistor M6 M0S transistor Mpl PMOS transistor Mp2 PM0S transistor Mnl NMOS transistor Mn2 NMOS transistor Mn3 NMOS transistor Mn4 NMOS Transistor MRS Read Selective Crystal MWS Write Selective Crystal MINV Inverting Transistor Vdd Supply Voltage nl Storage Node n2 Inverting Storage Node PI PM0S Transistor P2 PM0S Transistor RWL Read Character Line WWL Write Word line R1 Resistor R2 Resistor 1 SRAM cell 2 First bias circuit 3 Second bias circuit SAP First control signal SAN Second control signal HVdd High power supply voltage LVDD Low power supply voltage VH high Voltage node M302763 VL low voltage node P21 third PMOS transistor P22 fourth PMOS transistor 123 third inverter M31 third NMOS transistor M32 fourth NMOS transistor WL word Yuan line 17