M358390 五、新型說明： 【新型所屬之技術領域】 本創作係有關一種寫入操作時降低電 R , Δ 之早埠靜_機存取 嶺體（statlcRandomAccessMe軸^，簡稱 SRAM)，尤指一 決習知單埠靜態隨機存取記憶體中寫 取記憶體。 巾寫人_ 1 _之科靜態隨機存 【先前技術】 記憶體在電腦工業中扮演著無可或缺的角色。通常，記憶體可依昭 其能否在電源關閉後仍能保存資料’而區分為動態隨機存取記情體 (DRAM)及靜紐齡取錢鄭。臟賴存取記情體 (D麵)具有面積小及價格低等優點，但操作時必須不時地更新㈣㈣ 賜止資湘漏糕㈣失，而導畴在有高献_及消耗功率大 等缺失。相反地，靜態隨機存取記憶體(SRA_操作則較為簡易且毋 須更新操作，因此具有高速化及消耗功率低等優點。 目前以行«話為代表之行動電子設備所採狀半導體記憶裝 置，係以SRAM為主流。此乃由於SRAM待用電流小，適於連續通話 時間、連續待機時間盡可能延長之手機。 靜態隨機存取記憶體(SRAM)主要包括一記憶體陣列（mem〇ry array),該記憶體陣列係由複數列記憶體晶胞（a pluraiky 〇f⑺奶〇f memory cells)與複數行§己憶體晶胞（a〇f⑺丨^皿似 cells)所組成，每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個 έ己憶體晶胞，複數條字元線(w〇rdIine)，每一字元線對應至複數列記憶 體曰曰胞中之列’以及複數位元線對iinepajrs)，每一位元線對係對 應至複數行6己憶體晶胞中之一行，且每一位元線對係由一位元線及一 互補位元線所組成。 M358390 第1圖所示即是6T靜態隨機存取記憶體(SRAM)晶胞之電路示意 圖’其中，PMOS電晶體P1和P2稱為負載電晶體（load transistor)， Ml和M2稱為驅動電晶體（driving transistor)，M3和M4稱為存取電 晶體（access transistor)，WL 為字元線(word line)，而 BL 及 BLB 分別 為位元線（bit line)及互補位元線（complementary bit line)，由於該 SRAM晶胞需要6個電晶體，且驅動電晶體與存取電晶體間的電流驅 動能力比(即單元比率(cell rati〇))通常設定在2至3之間，而導致存在有 南集積化困難及價格高等缺失。第1圖所示6T靜態隨機存取記憶體晶 胞，於寫入操作時之HSPICE暫態分析模擬結果，如第2圖所示，其係 以level奶模型且使用TSMC ο·%微米CM〇s製程參數加以模擬(其 PMOS電晶體和電晶體之零基底偏壓臨限電壓值v讯〇分別為 -0.7866083V和0.582913V)，其中，PMOS電晶體P卜p2之通道寬長 比均為(W/L)=(lpm/i.4pm)，NM〇S電晶體M1和M2之通道寬長比均 為〇ν/ί)=(2μηι/0·35μιη)，而NMOS電晶體M3和M4之通道寬長比則 均為(鳳)=(1#111/0.354111)。 用來減少6Τ靜態隨機存取記憶體(8καμ、Θβ胞之電晶體數之一種 方式係揭路於第3圖中。第3圖顯示—讎具單—位元線之π靜態隨 機存取記《晶胞之電路示賴，與第丨圖之6Τ靜態隨機存取記憶體 晶胞相比，此種5了靜態隨赫取記顏晶胞比6Τ靜態隨機存取記憶 體晶胞少-個f晶體及少—條位元線，惟該5了靜騎機存取記憶體晶 胞存在寫人邏輯丨相當困難之問題。时慮記憶晶胞左側節點A原本 儲存邏輯0的情況，由於節，點A之電荷僅單獨自位元線(bl)傳送，因 此很難將節點A中先前寫入的邏輯〇蓋寫成邏輯卜第3圖所示π靜 鑛機存取記《晶胞，於寫人操作時之HSpiCE暫態分析模擬結果， =第4圖所不，其係以levd 49模型且使用丁复〇·35微米c则製 參數加以拉擬(其PM〇s電晶體和_s電晶體之零基底偏壓臨限電 4 M358390 壓值VTH0分別為_〇.7866〇睛和〇582913v)，其中，ρΜ〇§電晶體. P2之通道寬長比均為(W/L)=(W1.4_，麵〇8電晶體⑽和Μ: 之通道寬長比均為(W/LH2Mm/0.35Mm)，而nm〇s f晶體Μ3之通道 寬長比則均為(W/L)=(l、m/0_35_，由該模擬結果可註實，具單一位 元線之5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。 有鑑於此’本創作之主要目的係提出一種寫入操作時降低電源電壓 、 之科靜祕機存取記讎，其崎由寫人操作畴低《電壓以有 ‘ 辦免5Τ靜態隨機存取記髓晶胞存在寫人邏輯〖相當困難之問題。 Φ <本創作之次要目的係提出另一種寫入操作時降低電源電壓之單埠 靜態隨機存取記賴，其僅於寫人邏輯丨時方降低電源電壓，俾藉此 以有效避免ST靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問 題。 【新型内容】 本創作提出-種寫人猶_低電職壓之科靜級機存取記 思體/、係b括德體陣列，心己憶體陣列係由複數列記憶體晶胞 與複數行記賴晶胞所域，每—列記憶體晶胞與每—行記憶體晶胞 • 各包括有複數個記憶體晶胞⑴；複數條字元線，每-字元線對應至 . 概舰髓晶财之—列；概條位元線，每-位元_對應至複 • 數行記憶體晶胞中之—行；以及複數個寫人電壓控制電路⑵，每一 列記憶體晶胞設置-個寫入電壓控制電路。該等寫入電壓控制電路⑵ 於對應之第-控制信號（CTL1)為代表選定寫入狀態之邏輯高位準時， 將-低電源供應電壓(lvdd)供應至一高龍節點(VH)，其中該第一控 制U虎（CTL1)為-寫入致能（WriteEnable，簡稱職）信號與對應 之字元線(WL)信號的及閘（ANDgate)運算結果，亦即僅於該寫入致 能（WE)信號與該對應之字元線(WL)錢均為邏輯高位準時，該第 5 M358390 -控制信號（CTL1)方為賴高位準；而於對應之該第—控制信號 jCTLl)為代表非選定寫入狀態之邏輯低位準時，則將一高電源供應 賴(HVDD)供應至該高電_點_。結果，本麟可藉由寫入操; %降低電源f壓以有效避免寫人邏輯丨相當困難之問題。 本創作提出另—種寫人操作時降低電源電壓之單埠靜態隨機存取 記憶體，其係包括-記憶體_，該記憶體陣列係由複數列記憶體晶 胞與複數行記題晶胞顺成，每—航憶體晶胞與每 胞各包括有魏個記憶體晶胞⑴；複數條字元線，每—字元雜; 域數列記憶體晶胞巾之—列；複數條位元線，每—位元線係對應至 硬數行記憶體晶胞中之—行；以及複數個寫入電壓控制電路⑵，每 一行記憶體晶胞設置_個寫人電壓控制電路1等寫人龍控制電路 =)於對應之第二控制信號（CTL2)為代表敎寫入邏輯丨狀態之邏 輯d準f將低電源供應電壓(LVdd)供應至一冑電壓節點(呢）， 射該第二控制信號（CTU)為—寫人致能（獅^嫌，_呢） 信號與對應之位元、_L)信號軌閘（ANDgate)聽結果，亦即僅 於該寫入致能（WE)錢與該對應之位元_l)錢均為邏輯高位 準時，該第二控制信號（CTL2)方為邏輯高位準；而於對應之該第二 控制《(CTL2)為代表非選定寫入邏輯i狀態之邏輯低位準時，則 將該高電源供應龍(HVdd)供應至該高電壓節點(VH)。結果，可藉由 僅於寫入賴1勃降低電《壓財效避免寫人邏輯i相當困難之 問題。 田u雖又 【實施方式】 【第1實施例】 根據上述之主要目的，本創作提出—種寫人操作時降低電源電壓之 單埠靜態隨機存取記憶體，該寫人操作時降低電源電壓之科靜態隨 M358390 機存取記憶體係包括一記憶體陣列，該記憶體陣列係由複數列記憶體 晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞與每一行記憶體 晶胞各包括有複數個s己憶體晶胞（1 )，複數條字元線，每__字元線璧士 應至複數列記憶體晶胞中之一列；複數條位元線，每一位元線係對應 至複數行記憶體晶胞中之一行；以及複數個寫入電壓控制電路（2)， 每一列記憶體晶胞設置一個寫入電壓控制電路。 為了便於說明起見’第5圖所示之寫入操作時降低電源電壓之單棒 靜態隨機存取記憶體僅以一個記憶體晶胞（1)、一條字元線（WL)、 一條位元線(BL)以及一寫入電壓控制電路（2)做為實施例來說明。該 記憶體晶胞（1)係包括一第一反相器(由第一 PM0S電晶體ρι與第一 NMOS電晶體Ml所組成）、一第二反相器（由第二PM〇s電晶體p2與 第二NMOS電晶體M2所組成）以及一第三nm〇s電晶體（M3)，其 中，该第一反相器和該第二反相器係呈交互耦合連接，亦即該第一反 相器之輸出（即節點A)係連接該第二反相器之輸入，而該第二反相器之 輸出(即節點B)财接該第-反相ϋ之輸人，並且該第-反相器之輸出 (節點Α)係用於儲存SRAM晶胞之資料，而該第二反相器之輪出㈤點 )則用於儲存SRAM晶胞之反相資料。該第三刪〇s電晶體（M3) 係做為存取電晶體使帛，其問轉連接至—字元線 (WL) ’该字凡線’)於選定（Μ—)時係為具—高電源供應電壤 (HVDD)之邏輯雨位準，而於非選定（n_taed)時則為具—接地電 之邏輯低位準。 請再參考第5圖，該寫入電產控制電路⑵係由-第三PM〇s % M358390 晶體(P21)、一第四PMOS電晶體(P22)以及一第三反相器(123)所組成， δ亥第二PMOS電晶體(P21)之源極、閘極與沒極係分別連接至該高電源 供應電壓(hvdd)、一第一控制信號（CTL1)與一高電壓節點(VH);該 第四PMOS電晶體(P22)之源極、閘極與汲極係分別連接至一低電源供 應電壓(LVDD)、該反相器(123)之輸出端與該高電壓節點(VH)，而該第 二反相器(123)之輸入端則用以接收該第一控制信號（ctli)。其中， «亥苐控制k號（CTL1)為一寫入致能（WriteEnable，簡稱WE)作 號與-字元線(WL)信號的及閘（ANDgate)運算結果，亦即僅於該寫 入致能（WE)信號與該字元線(WL)信號均為邏輯高位準時，該第一 控制信號（CTL1)方為代表選定寫人狀態之邏輯高位準；而於該第一 控制信號（CTL1)為代表非選定寫人狀態之邏輯低辦時，則將一高 電源供應電壓(HVDD)供應至該高電壓節點(VH) 當該第-控制信號（CTL1)為代表選定寫入狀態之邏輯高位準時， 該邏輯高鱗之該第-控制信號（CTL1)可使得該寫人電壓控制電路 ⑵中之第三PM0S電晶體(p21) 〇FF(截止），並使得第四pM〇s電 晶體(P22) 〇稱通），於是可將該低電源供應電壓(LVdd)供應至該高電 壓節點(VH);而於該第一控制信號（CTL1)為代表非選定寫人狀態之 邏輯低位準時，則該邏輯低鱗之該第__㈣錢（ctli)可使得該 寫入電壓控制電路⑵巾之第三刚〇8電晶體(p21)⑽(導⑷，於是 可將該高電源供應電壓(hvddM共應至該高電壓節點(VH)。 接下來依單埠靜態隨機存取記憶晶胞之4種寫入狀態來說明第$圖 之本創作第1實施例如何完成寫入動作。 M358390 (一） 節點A原本儲存邏輯〇，而現在欲寫入邏輯〇 : 在寫入動作發生前(字元線WL為接地電壓），第一 NMOS電晶體 M1為0Ν(導通），該高電源供應電壓(HVDD)供應至該電壓節點(VH)。 因為第一NMOS電晶體Ml為ON’所以當寫入動作開始時，字元線(wl) 由Low(接地電壓)轉High(高電源供應電壓瓜^)，節點a的電壓會跟 隨字兀線(WL)的電壓而上升。當字元線(WL)的電壓大於第三電 晶體（M3)(即存取電晶體）的臨界電壓時，第三_〇8電晶體（M3) 由OFF(截止)轉變為ON(導通），此時因為位元線（BL)是接地電壓， 馨 所以會將節點A放電，而完成邏輯〇的寫入動作，直到寫入週期結束。 在此值得注意的是，該電壓節點(VH)於寫入初期係具有該低電源供應 電壓(LVDD)之位準，而於寫入週期結束後則具有該高電源供應電壓 (hvdd)之位準。 (二） 節點A原本儲存邏輯〇，而現在欲寫入邏輯i : 在寫入動作發生前(字元線WL為接地電壓），第一 _〇8電晶體 Ml為〇N($通）’ s亥尚電源供應電塵供應至該電壓節點(Μ)。 因為第- NMO S f晶體Μ1為〇Ν，所以當寫人動作開始時，字元線(肌) • 由L〇W(接地電塵)轉High(高電源供應電壓HVDD)，節，點A的電壓會跟 . 隨字儿線(WL)的電壓而上升。當字元線(WL)的電壓大於第三麵〇8電 • 晶體（M3)的臨界電塵時，第三NMOS電晶體（M3)由〇FF(截止） 轉變為ON(導通），此時因為位元線（BL)是剛(高電源供應電壓 hvdd)，並且因為第一圓〇8電晶體M1仍為〇n，所以會將節點a快 速充電；於節點A快速充電中，由於該賴節點(VH)會由該高電源供 應電虔(hvdd)之位準下降至該低電源供應電壓(Lv如)之位準，因此有 助於第一 PMOS電晶體P1由〇FF(截止)轉變為〇N(導通），待第一 觸電謝i⑽止)轉變為QN_時(節點B由_ 朝Low方向轉變，當節點B之輸立準下降至足以使第—pM〇s電晶 M358390 體P1導通時’該第一 PM0S電晶體ρι即由〇即轉變為⑽，即可將 節點A充電至高電源供應電壓(HVdd)扣減該第三麗〇s電晶體⑽） 的臨界電__祕應辑LVdd)崎巾讀大者，喊成邏輯i 的寫入動作。在此值付注意的是，由於該電壓節障晰寫入初期係 具有該低電祕應電壓(LVdd)之辦，秘寫人職結束彳細具有該高 電源供應賴(hvdd)之鱗，因此，寫人週騎束後，該節點A會被 充電至該高電源供應電壓(HVDD)之位準。 (三）節點A原本儲存邏輯丨，而現在欲寫入邏輯i : • 在寫入動作發生前(字元線脱為接地電壓），第- PMOS電晶體 P1為ON(導通），該高電源供應電壓(HVdd)供應至該電壓節點㈣。 當字元線(WL)由Low(接地電壓)轉High(高電源供應電壓取㈤），且該 字元線_的電壓大於第三丽⑽電晶體（M3) 壓時1 三NMOS電晶體（M3)由〇FF(截止)轉變為〇N(導通）；待該低電源 供應電壓(lvdd)供應至電源節點(Vdd)後，此時因為位元線（bl)是M358390 V. New description: [New technology field] This creation is about a kind of low-voltage R, Δ early _ _ access ridge (static RandomAccessMe axis ^, SRAM for short), especially a decision The memory is written in the static random access memory. Tow writer _ 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Usually, the memory can be divided into dynamic random access memory (DRAM) and static age to withdraw money according to whether it can save data after the power is turned off. Dirty access to the case (D face) has the advantages of small area and low price, but it must be updated from time to time during operation (4) (4) The loss of the capital is missing (4), and the domain is high and consumes a lot of power. Wait for the missing. On the contrary, the SRAM_ operation is relatively simple and does not require an update operation, so it has the advantages of high speed and low power consumption. At present, the semiconductor memory device of the mobile electronic device represented by the line «words, SRAM is the mainstream. This is because the SRAM has a small standby current and is suitable for mobile phones with continuous talk time and continuous standby time. The static random access memory (SRAM) mainly includes a memory array (mem〇ry array). The memory array is composed of a plurality of memory cells (a pluraiky 〇 f (7) milk memory f memory cells) and a plurality of rows of § memory cells (a 〇 f (7) 丨 ^ dish-like cells), each column of memory The unit cell and each row of memory cells each include a plurality of cells, a plurality of word lines (w〇rdIine), and each word line corresponds to a column of the plurality of memory cells. 'and the complex bit line pair iinepajrs), each bit line pair corresponds to one of the plurality of rows of 6 memory cells, and each bit line pair is composed of one bit line and one complementary bit line Composed of. M358390 Figure 1 is a schematic diagram of a 6T static random access memory (SRAM) cell. 'The PMOS transistors P1 and P2 are called load transistors, and Ml and M2 are called drive transistors. (driving transistor), M3 and M4 are called access transistors, WL is a word line, and BL and BLB are bit lines and complementary bit lines, respectively. Line), since the SRAM cell requires 6 transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, cell ratio) is usually set between 2 and 3, resulting in There are difficulties in South Accumulation and high prices. The 6T static random access memory cell shown in Figure 1 shows the HSPICE transient analysis simulation results during the write operation. As shown in Fig. 2, it is in the level milk model and uses TSMC ο·% micron CM〇 The s process parameters are simulated (the zero-substrate bias voltage values of the PMOS transistor and the transistor are -0.7866083V and 0.582913V, respectively), wherein the channel width to length ratio of the PMOS transistor P and p2 are both (W/L)=(lpm/i.4pm), the channel width to length ratio of NM〇S transistors M1 and M2 are 〇ν/ί)=(2μηι/0·35μιη), and NMOS transistors M3 and M4 The channel width to length ratio is (Feng) = (1#111/0.354111). One way to reduce the number of cells of 6 Τ static random access memory (8καμ, Θβ cell is shown in Fig. 3. Fig. 3 shows π static random access of the single-bit line of the cookware) "The circuit of the unit cell shows that compared with the 6 Τ static random access memory cell of the figure ,, the 5 static 随 记 记 晶 晶 晶 晶 比 Τ Τ 少 少 少 少 少 个 个 个 个f crystal and less-strip line, but the 5th static riding machine access memory cell has a problem of writing logic. It is difficult to remember the memory node on the left side of the node A originally stored logic 0, due to the festival The charge of point A is only transmitted from the bit line (bl) alone, so it is difficult to write the previously written logic in node A as the logic π. The HSpiCE transient analysis simulation results during the human operation, = Fig. 4, which is based on the levd 49 model and using the Ding Fu 〇 35 μm c-parameter parameters (the PM 〇s transistor and _s The zero-substrate bias of the transistor is limited to 4 M358390. The voltage value VTH0 is _〇.7866〇 and 〇582913v, respectively, where ρΜ〇§ P2 channel width to length ratio is (W / L) = (W1.4_, face 〇 8 transistor (10) and Μ: the channel width to length ratio are (W / LH2Mm / 0.35Mm), and nm 〇sf crystal通道3 channel width to length ratio is (W / L) = (l, m / 0_35_, can be injected by the simulation results, 5T static random access memory cell with a single bit line exists write logic 1 The problem is quite difficult. In view of this, the main purpose of this creation is to reduce the power supply voltage during the write operation, and to access the memory of the computer. The writer operates the domain low and the voltage is available. 5 Τ Static random access memory cell has a writing logic 〖very difficult problem. Φ < The second purpose of this creation is to propose another type of write operation to reduce the power supply voltage after static random access logging, It is quite difficult to reduce the power supply voltage only when writing the logic of the human body, so as to effectively avoid the problem that the ST static random access memory cell has a logic 1 written. [New content] This creation proposes a kind of writing _ The low-voltage occupational pressure static class machine access to the body of the body /, the system of the b-letter array, the heart of the body array is composed of complex columns of memory The unit cell and the plurality of rows are recorded in the cell, each column memory cell and each row memory cell unit each includes a plurality of memory cells (1); a plurality of word lines, each word line Corresponding to. The ship's nucleus - the column; the bit line, each bit _ corresponds to the complex line of the memory cell; and a plurality of write voltage control circuits (2), each column The memory cell is provided with a write voltage control circuit. The write voltage control circuit (2) will supply a low power supply voltage when the corresponding first control signal (CTL1) is at a logic high level representing the selected write state (lvdd). Supplying to a high dragon node (VH), wherein the first control U tiger (CTL1) is a write enable (WriteEnable) signal and an associated word line (WL) signal AND gate (ANDgate) The result of the operation, that is, when the write enable (WE) signal and the corresponding word line (WL) are both at a logic high level, the 5th M358390 - control signal (CTL1) is a high level; When the corresponding first-control signal jCTL1) is a logic low level representing the unselected write state, then Lai high power supply (HVDD) power supply to the high point _ _. As a result, Ben Lin can reduce the problem of writing logic by using the write operation; % to reduce the power supply f pressure. This creation proposes another type of static random access memory that reduces the power supply voltage during a human operation, which includes a memory _, which is composed of a plurality of columns of memory cells and a plurality of rows of cells. Shun Cheng, each - the memory cell and each cell include a Wei memory cell (1); a plurality of word lines, each word-character; a field array of memory cells - column; a plurality of bits a meta-line, each-bit line corresponds to a row in a hard-line memory cell; and a plurality of write voltage control circuits (2), each row of memory cell sets _ a write voltage control circuit 1 and the like The human dragon control circuit =) supplies the low power supply voltage (LVdd) to a voltage node (?) in response to the corresponding second control signal (CTL2) representing the logic 敎 state of the write logic 准 state, The second control signal (CTU) is - the write enable (Lion, _?) signal and the corresponding bit, _L) signal gate (ANDgate) listening results, that is, only the write enable (WE) The money and the corresponding bit _l) money are both at the logic high level, and the second control signal (CTL2) is a logic high The corresponding high power supply (HVdd) is supplied to the high voltage node (VH) when the corresponding second control "(CTL2) is a logic low level representing a non-selected write logic i state. As a result, it is quite difficult to reduce the writing logic by simply relying on the writing of Lai. [Field] [Embodiment] [First Embodiment] According to the above main object, the present invention proposes a static random access memory for reducing the power supply voltage during a human operation, which reduces the power supply voltage during the operation of the writer. The static memory with the M358390 machine access memory system includes a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each row of memory cells The cells each include a plurality of s-resonant unit cells (1), a plurality of word lines, each __ character line gentleman should belong to one of the plurality of memory cells; a plurality of bit lines, each The bit line corresponds to one of the plurality of rows of memory cells; and a plurality of write voltage control circuits (2), each column of memory cells being provided with a write voltage control circuit. For convenience of explanation, the single-bar static random access memory that reduces the power supply voltage during the write operation shown in FIG. 5 has only one memory cell (1), one word line (WL), and one bit. The line (BL) and a write voltage control circuit (2) are described as an embodiment. The memory cell (1) includes a first inverter (composed of a first PMOS transistor ρι and a first NMOS transistor M1) and a second inverter (by a second PM 〇s transistor) P2 is formed by the second NMOS transistor M2) and a third nm 〇s transistor (M3), wherein the first inverter and the second inverter are connected in an alternating coupling, that is, the first The output of the inverter (ie, node A) is connected to the input of the second inverter, and the output of the second inverter (ie, node B) is connected to the input of the first-inverted ,, and the - The output of the inverter (node Α) is used to store the data of the SRAM cell, and the round (5) point of the second inverter is used to store the inverted data of the SRAM cell. The third 〇s transistor (M3) is used as an access transistor to make 帛, and its connection is connected to the word line (WL) 'the word 'line') when selected (Μ-) - The logic of the high power supply (HVDD) is the logic level, and when it is not selected (n_taed), it is the logic low level of the grounding. Referring again to FIG. 5, the write power control circuit (2) is composed of a -third PM 〇s % M358390 crystal (P21), a fourth PMOS transistor (P22), and a third inverter (123). The source, the gate and the immersion of the second PMOS transistor (P21) are connected to the high power supply voltage (hvdd), a first control signal (CTL1) and a high voltage node (VH), respectively. The source, gate and drain of the fourth PMOS transistor (P22) are respectively connected to a low power supply voltage (LVDD), an output of the inverter (123) and the high voltage node (VH) And the input end of the second inverter (123) is configured to receive the first control signal (ctli). Wherein, «H苐 control k number (CTL1) is a write enable (WriteEnable, WE for short) and an AND gate operation result of the word line (WL) signal, that is, only the write When the enable (WE) signal and the word line (WL) signal are both logic high, the first control signal (CTL1) is a logic high level representing the selected write state; and the first control signal (CTL1) When a logic low represents a non-selected write state, a high power supply voltage (HVDD) is supplied to the high voltage node (VH) when the first control signal (CTL1) is a logic representing the selected write state. When the high level is on time, the first control signal (CTL1) of the logic scale can cause the third PMOS transistor (p21) 〇 FF (off) in the write voltage control circuit (2), and make the fourth pM 〇 s transistor (P22) nickname, then the low power supply voltage (LVdd) can be supplied to the high voltage node (VH); and the first control signal (CTL1) is a logic low level representing the unselected write state , the __(four) money (ctli) of the logic low scale can make the write voltage control circuit (2) Just 〇8 transistor (p21) (10) (guide (4), then the high power supply voltage (hvddM should be shared to the high voltage node (VH). Next, depending on the static random access memory cell, 4 writes The state of the present invention is explained in the first embodiment of the present invention. M358390 (1) Node A originally stores the logical 〇, but now wants to write the logical 〇: before the write action occurs (word line WL For the ground voltage), the first NMOS transistor M1 is 0 Ν (on), and the high power supply voltage (HVDD) is supplied to the voltage node (VH). Since the first NMOS transistor M1 is ON', when the write operation starts When the word line (wl) is turned from Low (ground voltage) to High (high power supply voltage), the voltage of node a rises following the voltage of the word line (WL). When the word line (WL) When the voltage is greater than the threshold voltage of the third transistor (M3) (ie, accessing the transistor), the third _8 transistor (M3) is turned from OFF (off) to ON (on), at this time because of the bit line ( BL) is the ground voltage, so it will discharge node A and complete the logic 写入 write operation until the end of the write cycle. It should be noted that the voltage node (VH) has the level of the low power supply voltage (LVDD) at the beginning of writing, and has the level of the high power supply voltage (hvdd) after the end of the writing period. (2) Node A originally stores the logic 〇, but now wants to write logic i: Before the write action occurs (word line WL is the ground voltage), the first _8 transistor M1 is 〇N ($pass)' s Haishang power supply is supplied to the voltage node (Μ). Since the -NMO S f crystal Μ1 is 〇Ν, when the writing action starts, the word line (muscle) • turns from L〇W (grounded dust) to High (high power supply voltage HVDD), node, point A The voltage will rise with the voltage of the word line (WL). When the voltage of the word line (WL) is greater than the critical electric dust of the third surface 〇8 electric crystal (M3), the third NMOS transistor (M3) is changed from 〇FF (off) to ON (conducting). Because the bit line (BL) is just (high power supply voltage hvdd), and because the first circular 电8 transistor M1 is still 〇n, node a will be quickly charged; in node A fast charging, due to the reliance The node (VH) will fall from the level of the high power supply (hvdd) to the level of the low power supply voltage (Lv, for example), thereby facilitating the transition of the first PMOS transistor P1 from 〇FF (off) For 〇N (conduction), when the first electric shock X (10) is changed to QN_ (node B is changed from _ to the Low direction, when the input of the node B is lowered enough to make the first pM〇s electro-crystal M358390 When P1 is turned on, 'the first PM0S transistor ρι is converted from 〇 to (10), and the node A can be charged to the high power supply voltage (HVdd) to deduct the critical power of the third 〇 s transistor (10). Should be compiled LVdd) Kasuga to read the big, shouted into the logic i write action. Pay attention to this value, because the voltage barrier is written in the early stage, it has the low-voltage secret voltage (LVdd), and the secret writer has the high power supply (hvdd) scale. Therefore, after the writer is riding the beam, the node A will be charged to the level of the high power supply voltage (HVDD). (3) Node A originally stores the logic 丨, but now wants to write logic i: • Before the write action occurs (the word line is off to ground voltage), the PMOS transistor P1 is ON (on), the high power supply The supply voltage (HVdd) is supplied to the voltage node (four). When the word line (WL) is turned from Low (ground voltage) to High (high power supply voltage is taken (5)), and the voltage of the word line_ is greater than the voltage of the third (10) transistor (M3), a three-NMOS transistor ( M3) is changed from 〇FF (cutoff) to 〇N (conducting); after the low power supply voltage (lvdd) is supplied to the power supply node (Vdd), at this time, because the bit line (bl) is
High(高電源供應電壓hvdd)，並且因為第_ pM〇s電晶體ρι仍為 ON，所以節‘點A㈣壓會降低至高·供應電壓取⑽扣減該第三 φ 醒⑽電㈤體（M3)賊界電壓或該低電源供應電壓(LVDD)兩者中之 較大者，朗冑人職結束該㈣雜應電壓_如)供紅電壓節點 (VH) ° (四）節點A原本儲存邏輯丨，而現在欲寫入邏輯〇 : 在寫入動作發生前(字元線WL為接地電壓），第一 pM〇s電晶體 P1為ΟΝ(‘通），5亥咼電源供應電屢(hvdd)供應至電壓節點(vh)。當 字元線(WL)由Low(接地電壓)轉High(高電源供應電壓，且該字 元線(WL)的電壓大於第三電晶體（M3)的臨界電壓時，第三 NM〇S電晶體⑽）由OFF(截止)轉變為ON(導通），此時因為位元 線（BL)是Low (接地電壓），所以會將節點a放電而完成邏輯〇的 10High (high power supply voltage hvdd), and because the _pM〇s transistor ρι is still ON, the node 'point A (four) voltage will decrease to high · supply voltage take (10) deduct the third φ wake up (10) electric (five) body (M3 The larger of the thief boundary voltage or the low power supply voltage (LVDD), the reading of the (4) hybrid voltage _, for example, the red voltage node (VH) ° (four) node A original storage logic丨, and now want to write logic 〇: Before the write action occurs (word line WL is the ground voltage), the first pM 〇s transistor P1 is ΟΝ ('pass), 5 咼 咼 power supply repeatedly (hvdd ) supplied to the voltage node (vh). When the word line (WL) is turned from Low (ground voltage) to High (high power supply voltage, and the voltage of the word line (WL) is greater than the threshold voltage of the third transistor (M3), the third NM〇S is electrically The crystal (10)) changes from OFF (off) to ON (on). At this time, since the bit line (BL) is Low (ground voltage), the node a is discharged to complete the logic 〇 10
M358390 寫入動作朗寫人週期結束。在此值得注意的是，該雜節點⑽) 於寫入初_具有該低電源供應m(LVdd)之位準，祕寫人週期結束 後則具有該高電源供應電壓(HVdd)2位準。 第5圖所示之本創作第】實施例，於寫入操作時之HSpiCE暫態分 析权U如第6圖所不，其係以levd 49模型且使用tsmc 微米CMOS製程參數加以模擬(其pM〇s電晶體和應⑶電晶體之零 基底偏壓臨限賴值Vth。分顺_α786_ν和Q5829i3v)，其中: PMOS電晶體π、P2之通道寬長比均為(狐)$㈣㈣，聰 電晶體Ml和M2之通道寬長比均為(w/Lmim/〇 35_，而應⑽ 電晶體M3之通道寬長比則均為_=(1 3_㈣㈣，由該模擬结果 可言正實，補觸糾之寫碌作日梅低麵健之單轉態隨機存 取記憶體，能藉㈣人猶時降低電源賴，以有效避免習知5Τ靜態 Ik機存取記憶體晶胞存在寫入邏輯丨相當困難之問題。 【弟2實施例】 根據上述之次要目的，本創作提出提出另—種寫人操作時降低電源 電壓之單轉態雜存取記，隨，該冑人操作時降低電源電壓之單璋 靜態隨機存取記㈣係包括-記，該記憶断列係由複數列 記憶體晶胞減數行記謹晶朗組成，每—顺憶體晶胞與每一行 吕己憶體晶胞各包括有複數個記憶體晶胞（丨）；複數條字元線> 丁 元線對ω數列記憶體晶胞中之一列;複數條位元:二丄::: 係對應至複數行記憶體晶胞中之-行；以及複數個寫人電壓控制=路 (2)，每一行記憶體晶胞設置一個寫入電壓控制電路。 二 為了便於說明起見，第7圖所示之寫入操作時降低電源電壓之科 靜態隨機存取記憶體僅以一個記憶體晶胞（η 、— 條子元線（WL)、 11 M358390 一條位元線(BL)以及一寫入電壓控制電路（2)做為實施例來說明。該 記憶體晶胞（1)係包括一第一反相器(由第一 PMOS電晶體P1與第— NMOS電晶體Ml所組成）、一第二反相器(由第二PMOS電晶體η與 第二NMOS電晶體M2所組成）以及一第三NMOS電晶體（M3)，其 中’該第一反相器和該第二反相器係呈交互耦合連接，亦即該第—反 相器之輸出（即節點A)係連接該第二反相器之輸入，而該第二反相器之 輸出（即節點B)則連接該第一反相器之輸入，並且該第一反相器之輪出 (節點A)係用於儲存SRAM晶胞之資料，而該第二反相器之輸出（節點 B)則用於儲存SRAM晶胞之反相資料。該第三NMOS電晶體（M3) 係做為存取電晶體使用，其閘極係連接至一字元線(WL)，該字元線(WL) 於選定時係為具一高電源供應電壓(HVDD)之邏輯高位準，而於非選定 時則為具一接地電壓之邏輯低位準。 請再參考第7圖，該寫入電壓控制電路（2)係由一第三PM〇s電 晶體(P21)、一第四PMOS電晶體(P22)以及一反相器(123)所組成，該 第二PMOS電晶體(P21)之源極、閘極與沒極係分別連接至該高電源供 應電壓(hvdd)、一第二控制信號（CTL2)與一高電壓節點(VH);該第 四PMOS電晶體(P22)之源極、閘極與汲極係分別連接至一低電源供應 電壓(LVDD)、該反相器(123)之輸出端與該高電壓節點(VH),而該第三 反相器(123)之輸入端則用以接收該第二控制信號（crL2)。其中，該 弟一控制仏號（CTL2)為一寫入致能（Write Enable，簡稱WE)信號 與一位元線(BL)信號的及閘（ANDgate)運算結果，亦即僅於該寫入 致能（WE)信號與該位元線(BL)信號均為邏輯高位準時，該第二控 12 M358390 希】仏號（CTL2)方為代表選定寫入邏輯1狀態之邏輯高位準；而於該 第二控制信號（CTL2)為代表非選定寫入邏輯！狀態之邏輯低位準時， 則將-兩Ί源供應電壓(取⑽)供應至該高電壓節點(VH) 當§亥第二控制信號（CTL2)為代表選定寫入邏輯1狀態之邏輯高 位準時’ _輯高轉之該第二控制魏⑽⑵可麟該寫入電壓 控制電路（2)中之第2PM〇s電晶體(p21) 〇FF(截止），並使得第四 PMOS電曰曰體(pa) 〇N(導通），於是可將該低電源供應電壓(LVDD)供應M358390 Write action ends the end of the human cycle. It is worth noting here that the hybrid node (10) has the level of the low power supply m (LVdd) at the beginning of the write, and the high power supply voltage (HVdd) 2 level after the end of the secret writer period. In the fifth embodiment of the present invention shown in FIG. 5, the HSpiCE transient analysis right U in the write operation is as shown in FIG. 6, which is simulated by the levd 49 model and using tsmc micron CMOS process parameters (its pM 〇s transistor and (3) transistor zero base bias threshold value Vth. 顺 _α786_ν and Q5829i3v), where: PMOS transistor π, P2 channel width to length ratio are (fox) $ (four) (four), Cong The channel width-to-length ratio of the transistors M1 and M2 are both (w/Lmim/〇35_, and the channel width-to-length ratio of the transistor M3 should be _=(1 3_(four)(4)), and the simulation result can be positive and true. Correctly write the work of the Japanese low-healthy single-state random access memory, can borrow (four) people to reduce the power supply, in order to effectively avoid the knowledge of 5 Τ static Ik machine access memory cell exists write logic丨The problem is quite difficult. [Embodiment 2] According to the above secondary purpose, the author proposes to propose a single-transition miscellaneous access record for reducing the power supply voltage during the operation of the writer, and the power supply is reduced when the monk operates. Voltage-single-stationary static random access memory (4) is a memory cell The number of lines is composed of Jinglang, each of the memory cells and each line of the unit cell includes a plurality of memory cells (丨); a plurality of word lines > Ding Yuan line pairs of ω series memory One of the unit cells; a plurality of bits: two::: corresponds to the line in the memory cell of the complex line; and a plurality of write voltage control = way (2), each line of memory cells Set a write voltage control circuit. 2. For the sake of convenience, the static random access memory for reducing the power supply voltage during the write operation shown in Fig. 7 is only one memory cell (η, - strip sub-line (WL), 11 M358390 A bit line (BL) and a write voltage control circuit (2) are described as an embodiment. The memory cell (1) includes a first inverter (by the first a PMOS transistor P1 and a first NMOS transistor M1), a second inverter (composed of the second PMOS transistor η and the second NMOS transistor M2), and a third NMOS transistor (M3), Wherein the first inverter and the second inverter are connected in an alternating coupling, that is, the output of the first inverter That is, node A) is connected to the input of the second inverter, and the output of the second inverter (ie, node B) is connected to the input of the first inverter, and the first inverter is turned out. (Node A) is used to store the data of the SRAM cell, and the output of the second inverter (Node B) is used to store the inverted data of the SRAM cell. The third NMOS transistor (M3) is used. For access to the transistor, the gate is connected to a word line (WL) which, when selected, has a logic high level with a high power supply voltage (HVDD). When selected, it has a logic low level with a ground voltage. Referring again to FIG. 7, the write voltage control circuit (2) is composed of a third PM 〇s transistor (P21), a fourth PMOS transistor (P22), and an inverter (123). a source, a gate, and a gate of the second PMOS transistor (P21) are respectively connected to the high power supply voltage (hvdd), a second control signal (CTL2), and a high voltage node (VH); The source, gate and drain of the four PMOS transistors (P22) are respectively connected to a low power supply voltage (LVDD), an output of the inverter (123) and the high voltage node (VH), and the The input of the third inverter (123) is used to receive the second control signal (crL2). Wherein, the control code (CTL2) is a write enable (WE) signal and an AND gate operation result of a bit line (BL) signal, that is, only the write When the enable (WE) signal and the bit line (BL) signal are both logic high, the second control 12 M358390 仏 仏 (CTL2) side represents the logic high level of the selected write logic 1 state; The second control signal (CTL2) represents the unselected write logic! When the logic low state of the state is on, the two supply voltages (take (10)) are supplied to the high voltage node (VH) when the second control signal (CTL2) is the logic high level of the selected write logic 1 state. The second control Wei (10) (2) can write the second PM 〇s transistor (p21) 〇 FF (off) in the voltage control circuit (2), and make the fourth PMOS electric body (pa) ) 〇N (conducting), so the low power supply voltage (LVDD) can be supplied
至該二電壓即點(VH);而於該第二控制信號（CTL2)為代表非選定寫 入邏輯1狀態之邏輯低位树，職邏輯低位準之該第二控制信號 (CT^2)可使知该寫入電壓控制電路⑵中之第三刚電晶體(pa) ON(導通），於是可將該高電源供應電壓㈣㈤)供應至該高電壓節點 (VH) 〇 本創作所提出之第2實施例，可藉由僅於寫人邏輯1時方降低電源 電壓以有效避免寫人轉丨相當_之問題。由於其寫人原理相仿於 第1實施例，在此不再贅述。 〜雖然本創作特別揭露並描述了所選之較佳實施例，但舉凡熟悉本技 可嫩何形概略可能物⑽㈣本創作的精 13 M358390 【圖式簡單說明】 第1圖係顯示習知6丁靜態隨機存取記憶體晶胞之電路示意圖· 第2圖係顯示習減靜態隨機存取記憶體晶胞之寫人動作時序圖. 第3圖係顯示習知5T靜態隨機存取記憶體晶胞之電路示意圖. 第4圖係顯示習知5T靜態隨機存取記憶體晶胞之寫入動作時序圖. 第5圖係顯示本創作第1實施例所提出之寫入操作時降低電源電壓之 早埠靜態隨機存取記憶體晶胞之電路示意圖； 第6圖係顯示本創作第i實施 之寫人操作時降低電源電壓之 早車靜想隨機存取記憶體晶胞之寫入動作日 第7圖係顯示本創作第2實施例所 H 之寫入刼作時降低電源電壓之 早車靜紙機存取記憶體晶胞之電路示意圖。 【主要元件符號說明】 P1 第一 PMOS電晶體 Ml 第一 NMOS電晶體 M3 第三NMOS電晶體 BL 位元線 WL 字元線 A 儲存節點 hvdd 高電源供應電壓 1 SRAM晶胞 P21 第三PMOS電晶體 123 第三反相器 CTL2 第二控制信號 P2 第二PMOS電晶體 M2 第二NM〇s電晶體 M4 第四NMOS電晶體 BLB 互補位元線 VH 高電壓節點 B 反相儲存節點 LVdd 低電源供應電壓 2 寫入電壓控制電路 P22 第四PM〇s電晶體 CTL1 第—控制信號 14Up to the second voltage is a point (VH); and the second control signal (CTL2) is a logic low-level tree representing a state of non-selected write logic 1; the second control signal (CT^2) of the lower logic level of the logic logic can be The third positive transistor (pa) in the voltage control circuit (2) is turned ON, so that the high power supply voltage (4) (f) can be supplied to the high voltage node (VH). In the second embodiment, the problem of lowering the power supply voltage by merely writing the logic of the person 1 can effectively avoid the problem that the writer turns. Since the principle of writing is similar to that of the first embodiment, it will not be described herein. ~ Although the present invention specifically discloses and describes the preferred embodiment selected, it is familiar with the skill of the present invention. (10) (4) The fine 13 M358390 of this creation [Simple description of the drawing] The first figure shows the conventional 6 Schematic diagram of the unit cell of the static random access memory cell. Fig. 2 shows the timing diagram of the writing action of the unit cell of the static random access memory. Fig. 3 shows the conventional 5T static random access memory crystal. Schematic diagram of the circuit of the cell. Fig. 4 is a timing chart showing the write operation of the conventional 5T static random access memory cell. Fig. 5 is a diagram showing the reduction of the power supply voltage during the write operation proposed in the first embodiment of the present invention. The schematic diagram of the circuit of the static random access memory cell is shown in the early stage; the sixth figure shows the write operation day of the early-time random access memory cell of the early-vehicle reduced power supply voltage during the writing operation of the i-th implementation of the present invention. 7 is a schematic diagram showing the circuit of the early car static machine accessing the memory cell by lowering the power supply voltage during the writing operation of the second embodiment of the present invention. [Main component symbol description] P1 first PMOS transistor M1 first NMOS transistor M3 third NMOS transistor BL bit line WL word line A storage node hvdd high power supply voltage 1 SRAM cell P21 third PMOS transistor 123 third inverter CTL2 second control signal P2 second PMOS transistor M2 second NM〇s transistor M4 fourth NMOS transistor BLB complementary bit line VH high voltage node B inverting storage node LVdd low power supply voltage 2 write voltage control circuit P22 fourth PM〇s transistor CTL1 first - control signal 14