JP2012089205A - Associative storage device - Google Patents

Associative storage device Download PDF

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Publication number
JP2012089205A
JP2012089205A JP2010235522A JP2010235522A JP2012089205A JP 2012089205 A JP2012089205 A JP 2012089205A JP 2010235522 A JP2010235522 A JP 2010235522A JP 2010235522 A JP2010235522 A JP 2010235522A JP 2012089205 A JP2012089205 A JP 2012089205A
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search
line
connected
plurality
power supply
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Japanese (ja)
Inventor
Mihoko Akiyama
Futoshi Igaue
Yasumitsu Murai
Aiko Nakajima
Hiroaki Tanizaki
愛子 中嶋
太 伊賀上
泰光 村井
実邦子 秋山
弘晃 谷崎
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Renesas Electronics Corp
ルネサスエレクトロニクス株式会社
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Abstract

An associative memory device capable of high-speed search without generating a soft error and a standby current is provided.
An associative memory cell includes a tunnel magnetoresistive element TMR having one end connected to a search line SL, a capacitor element C5 connected to the other end of the tunnel magnetoresistive element TMR, and the other end of the tunnel magnetoresistive element TMR. Between the first MOS transistor N4, the control electrode of which is connected to the word line RWL, and between the match line ML and the ground power supply, and the control electrode of the tunnel magnetoresistive element TMR. And a second MOS transistor N2 receiving a voltage generated at the other end.
[Selection] Figure 1

Description

  The present invention relates to an associative memory device.

  A content addressable memory (CAM) incorporated in a network router or the like, which is one of the associative memory devices, has all data stored in the array and a given search in addition to the data read / write function. It has a search function that performs a match determination with data in parallel, and is used for searching for an IP address from a routing table stored in advance. In recent years, CAM memories in network routers are required to be increased in speed and capacity due to an increase in network speed, an increase in servers, and an increase in users of the Internet.

  In recent CAM memory development, advanced miniaturization processes have been adopted for speeding up. However, off-leakage current, gate leakage current, and standby leakage current of SRAM (Static Random Access Memory) are increasing, and overall consumption is increasing. The proportion of the standby current such as the off-leakage current, the gate leakage current, etc. in the current is increasing as a countermeasure against the pipeline configuration of Patent Document 1 (US Pat. No. 6,191969) and Patent Document 2 The reduction of the active current has been proposed by lowering the voltage of the match line precharge power source of Japanese Patent Application Publication No. 2007-317342.

  However, the conventional CAM memory composed of SRAM has the problem that the overall current consumption cannot be reduced unless the standby leakage current of the SRAM, which is increased due to process miniaturization, is suppressed, and the thermal design of the chip becomes difficult. Large capacity is difficult.

  Further, the process of determining the match / mismatch state of the match line by the operation of the N channel MOS transistor (hereinafter referred to as the search transistor) that pulls the match line indicating the state of the search result of the CAM memory to the ground level or the match amplifier circuit is a process. However, there is a problem that speeding up cannot be achieved only by miniaturization.

  The reason why the above-described search transistor pulling out the match line to the ground cannot be speeded up is that 1 bit of the CAM memory constituted by the conventional SRAM is 2 bits of the SRAM memory (12 transistors) and the search transistor (4 transistors). This is because the number of elements is large (16 transistors). Therefore, various stresses (STI stress: Shallow Trench Isolation stress, PSE stress: Poly Space Effects stress, etc.) peculiar to layouts with high transistor occupancy occur, lowering the current drive capability of the search transistor, and miniaturizing the search transistor This is because, since the size is reduced, the amount of variation due to local variations in threshold value is increased.

  The reason why the process for determining the match / mismatch state of the match line by the above-described match amplifier circuit cannot be accelerated is that the time required for the search transistor to pull the match line to the ground due to the increase in speed (in the conventional CAM, 1/2 of the search operation cycle). ) Is shortened and the amplitude level of the match line is reduced, and further, the small amplitude of the match line needs to be amplified at high speed. However, due to miniaturization, the variation in pair transistors increases and the amplifier sensitivity tends to deteriorate. Because there is.

  The CAM memory realizes a high-speed search memory by simultaneously searching all the stored data in the memory array in parallel. On the other hand, the CAM memory indicates a search line indicating the state of the search data, a match of the search results, and a mismatch state. Since all the match lines are activated, a very large current consumption and current change (di / dt) noise are generated during the search. There is a problem that the bypass capacitor capacity of the power supply voltage on the substrate required to suppress noise increases due to an increase in di / dt that increases in proportion to an increase in capacity and speed.

  For these problems, for example, Patent Document 3 (Japanese Patent Laid-Open No. 2002-334585), Patent Document 4 (Japanese Patent Laid-Open No. 2005-259206), Patent Document 5 (Japanese Patent Laid-Open No. 2004-86934), and Patent Document 6 (Japanese Patent Laid-Open No. 2002-197853) solves the problems of SRAM soft error and standby leak by configuring the CAM array with MRAM (Magnetic Random Access Memory).

US Pat. No. 6,919,969 JP 2007-317342 A JP 2002-334585 A JP 2005-259206 A JP 2004-86934 A JP 2002-197853 A

  However, Patent Document 3 has a problem that the search cannot be performed faster than the conventional SRAM configuration. The reason for this is that in MRAM, data High and Low are distinguished by their resistance values large and small, but the resistance ratio is at most about twice. Therefore, in the current sense circuit configuration as shown in FIGS. 4 and 9 of Patent Document 3, it is impossible to perform a conventional high-speed operation exceeding 300 MHz.

  Even in Patent Documents 4 to 6, similarly, since the resistance ratio of about twice is determined, the search cannot be performed at high speed. In Patent Document 4, since a search is performed while data is written to the MRAM, the MRAM writing speed (about 100 MHz) is slow, so that a high-speed search operation is impossible. In Patent Document 6, a reference resistor is generated to generate a reference current and a current sense circuit is used. However, noise resistance is weak and high-speed operation is impossible.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an associative memory device that does not generate a soft error and a standby current, has little current change (di / dt) noise, and can perform a high-speed search.

  An associative memory device according to an embodiment of the present invention is an associative memory device capable of detecting coincidence or mismatch between stored data and search data. The associative memory device includes a memory array including a plurality of associative memory cells arranged in a matrix, a plurality of match lines each connected to a plurality of associative memory cells belonging to a corresponding entry in the memory array, A plurality of determination circuits each outputting a search determination signal representing a match or mismatch between the data stored in the associative memory in the entry of the memory array and the search data in accordance with the voltage of the match line; When searching, a plurality of search lines for supplying a voltage corresponding to the value of the search data to a plurality of associative memories belonging to a column in the memory array, and a plurality of associative memory cells each belonging to a corresponding entry in the memory array A plurality of word lines connected to each other and a first driver for outputting a one-shot pulse having a predetermined width to the search line when the search data has a predetermined value. The associative memory cell is provided between a tunnel magnetoresistive element having one end connected to the search line, a capacitive element connected to the other end of the tunnel magnetoresistive element, and the other end of the tunnel magnetoresistive element and the ground power supply. The control electrode is provided between the first MOS transistor connected to the word line, the first inverter having the other end of the tunnel magnetoresistive element as an input, the match line and the ground power supply, And a second MOS transistor receiving the output voltage of one inverter.

  According to the content addressable memory device of one embodiment of the present invention, soft errors, standby current and current change (di / dt) noise are reduced, and high-speed search is possible.

It is a figure showing the circuit structure of the CAM basic cell of 1st Embodiment. It is a figure which shows the truth value of the CAM basic cell of FIG. It is an operation | movement waveform diagram in case the search result of the CAM basic cell of FIG. 1 does not correspond. FIG. 6 is an operation waveform diagram when the search results of the CAM basic cell in FIG. 1 match. FIG. 6 is an operation waveform diagram when search data of the CAM basic cell in FIG. 1 is mask data. It is a figure showing the circuit structure of the TCAM (TernaryCAM) basic cell of 1st Embodiment. It is a figure which shows the truth value of the TCAM basic cell of FIG. It is a figure showing the relationship between search data and the data transmitted to search line SL and / SL. It is a figure showing the structure of the content addressable memory device which has the TCAM basic cell of 1st Embodiment. It is a figure showing the structure of the TCAM array mat of the content addressable memory device of FIG. FIG. 11 is a diagram illustrating a configuration of one entry (0th entry) in the TCAM array mat in FIG. 10. FIG. 10 is an operation waveform diagram at the time of search in the associative memory device of FIG. 9. It is an operation waveform diagram when writing “0” to the CAM basic cell. It is an operation waveform diagram when writing “1” to the CAM basic cell. It is an operation | movement waveform diagram when reading data from a CAM basic cell. It is a figure showing the structure of ML precharge circuit. It is an operation waveform diagram at the time of precharge of the match line ML. It is a layout diagram of a transistor layer and a wiring layer of a CAM array mat. It is a layout diagram of the third layer metal layer, the fourth layer metal layer, and the tunnel magnetoresistive element TMR of the CAM array mat. It is sectional drawing perpendicular | vertical to the board | substrate of the layout of a CAM array mat. It is a layout diagram of a transistor layer and a wiring layer of a TCAM array mat. It is a layout diagram of the third layer metal layer, the fourth layer metal layer, and the tunnel magnetoresistive element TMR of the TCAM array mat. It is a figure showing the circuit structure of the CAM basic cell of 2nd Embodiment. It is a figure showing the circuit structure of the TCAM basic cell of 2nd Embodiment. It is a figure showing the structure of the match amplifier (determination circuit) and ML precharge circuit of 2nd Embodiment. FIG. 6 is an operation waveform diagram for explaining the operation of the match amplifier. It is a figure showing the circuit structure of the TCAM basic cell of 3rd Embodiment. It is a figure showing the structure of the content addressable memory device which has the TCAM basic cell of 3rd Embodiment. It is a figure showing the structure of the TCAM array mat of the content addressable memory device of FIG. FIG. 30 is a diagram illustrating a configuration of one entry (0th entry) in the TCAM array mat in FIG. 29. It is a figure showing the structure of SL precharge circuit. It is an operation waveform diagram at the time of precharge of the search line SL. It is a figure showing the circuit structure of the TCAM basic cell of 4th Embodiment. FIG. 34 is an operation waveform diagram at the time of search in the content addressable memory device having the TCAM basic cell of FIG. 33.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
(CAM basic cell)
FIG. 1 is a diagram illustrating a circuit configuration of a CAM basic cell according to the first embodiment.

  A conventional CAM basic cell is configured based on SRAM. In this configuration, the SRAM is composed of a total of 8 elements including 6 transistors constituting the SRAM and 2 transistors for search. On the other hand, as shown in FIG. 1, the CAM basic cell 12 of the present embodiment includes an inverter IV1, an N channel MOS transistor N2, an N channel MOS transistor N4, a capacitor element C5, and a tunnel magnetoresistive element. It is comprised by TMR and the capacitive element C1.

  The resistance value of tunneling magneto-resistance element TMR changes depending on the direction of magnetization. The smaller resistance value is represented by R, and the larger resistance value is represented by R + ΔR. Here, in the current technology, ΔR <R, and ΔR≈R at the maximum.

  In the CAM basic cell 12 of the embodiment of the present invention, “0” is recorded when the resistance value of the tunnel magnetoresistive element TMR is R, and “1” is stored when the resistance value is R + ΔR. .

  One terminal of tunneling magneto-resistance element TMR is connected to a search line / SL (inverted logic of search data is transmitted), and the other terminal SN is a capacitive element C5 formed of an N-channel MOS transistor and a data read-out terminal. Are connected to the drain of the N-channel MOS transistor N4 and the input of the inverter IV1. In the N-channel MOS transistor constituting the capacitive element C5, the gate is connected to the terminal SN, and the source and drain are connected to the ground.

  N channel MOS transistor N4 has its gate connected to read word line RWL and its source connected to ground.

  N channel MOS transistor N2 has its drain connected to match line ML, its source connected to ground, and its gate connected to output terminal / SN of inverter IV1.

  Further, a capacitive element C1 formed of an N channel MOS transistor is connected between the power supply line MLVDD and the ground. That is, the N-channel MOS transistor constituting the capacitive element C1 has a gate connected to the power supply line MLVDD and a source and a drain connected to the ground.

  When viewed from the search line / SL side, the tunnel magnetoresistive element TMR capacitive element C5 forms a low-pass filter. Here, when the resistance value R + ΔR of the tunnel magnetoresistive element TMR is 30K and the capacity of the capacitive element C5 is 20 fF, the tunnel magnetoresistive element TMR and the capacitive element C5 have a delay element of about 600 ps or a pulse having a width of 600 ps or more. A low-pass filter that passes is formed. When the resistance value R of the tunnel magnetoresistive element TMR is 15K and the capacity of the capacitive element C5 is 20 fF, the tunnel magnetoresistive element TMR and the capacitive element C5 are low-pass elements that allow a delay element of about 300 ps or a pulse having a width of 300 ps or more to pass through. A pass filter is formed.

  When the stored data is “0”, the low-pass filter passes a pulse of 300 ps or more. Therefore, when a one-shot pulse having a width of 500 ps is applied to the search line / SL during data search, this one-shot The pulse is output to the terminal / SN.

  On the other hand, when the stored data is “1”, the low-pass filter passes a pulse having a width of 600 ps or more. Therefore, when a one-shot pulse having a width of 500 ps is applied to the search line / SL during data search. The one-shot pulse is not output to the terminal / SN.

Digit line DL is supplied with a magnetizing current during data writing.
The search line / SL also serves as the bit line BL, and a write current is supplied during data writing.

  In the conventional SRAM configuration, since the number of transistors is large, the transistor density is increased. For this reason, there has been a problem that the on-current of the search transistor deteriorates due to the STI stress, which has been a problem in recent years, and the search speed deteriorates. Further, since the number of internal nodes is large, the line capacity and parasitic capacitance of the internal nodes increase due to miniaturization, and there are problems of access deterioration and increase in current consumption. There are also problems of increased standby leakage current and soft errors in the SRAM.

  Since the CAM basic cell of the embodiment of the present invention does not include SRAM, these problems are improved.

  Furthermore, since the SRAM is not arranged in the transistor layer, the CAM basic cell according to the embodiment of the present invention has the following advantages. In the CAM memory, the match lines ML are precharged in order to discharge and charge all the match lines ML in the array. Therefore, there is a problem that the time change di / dt of the current is very large. In order to reduce power supply noise due to time variation di / dt of current, conventionally, a large-capacity bypass capacitor is provided on the substrate to increase the substrate mounting area. On the other hand, the CAM basic cell according to the embodiment of the present invention includes a capacitor element C5 (MOS capacitor) for reducing power supply noise due to current change di / dt in the transistor layer in which the conventional SRAM is arranged. It is installed locally.

(Truth table of CAM basic cell)
FIG. 2 is a diagram illustrating truth values of the CAM basic cell of FIG.

  As shown in FIG. 2, the CAM basic cell of the present embodiment operates with the same truth table as the CAM basic cell having a normal SRAM configuration.

  When the data transmitted to search line SL is “1” and the data transmitted to search line / SL is “0” (L level one-shot pulse), the resistance value of tunneling magneto-resistance element TMR is R + ΔR. In this case, the terminal SN is “1” (H level), the terminal / SN is “0” (L level), the match line ML is “1” (H level), and the search result is Hit (match).

  When the data transmitted to the search line SL is “1” and the data transmitted to the search line / SL is “0” (L level one-shot pulse), the resistance value of the tunnel magnetoresistive element TMR is R. In this case, the terminal SN is “0” (L level), the terminal / SN is “1” (H level), the match line ML is “0” (L level), and the search result is Miss (mismatch).

In the case of data “0” transmitted through the search line SL, a match state is not determined and a mask state is entered.
(Operation of CAM basic cell)
FIG. 3 is an operation waveform diagram when the search results of the CAM basic cells in FIG. 1 do not match.

  Referring to FIG. 3, the level of search line / SL is “1” during standby. In the search active period, when the search data is “1”, an L level one-shot pulse having a width of 500 ps is transmitted to the search line / SL. When the search data is “0”, the level of the search line / SL remains “H” during standby.

  In FIG. 3, the search data is “1”, the stored data is “0”, that is, the resistance value of the tunnel magnetoresistive element TMR is R, specifically, 15 KΩ.

  In this case, since the time constant τ0 (approximately 15 KΩ × 20 fF = 300 ps) of the low-pass filter is smaller than the width of the one-shot pulse (500 ps), the one-shot pulse is not filtered. As a result, the potential of the output terminal / SN of the inverter IV1 becomes “H”. As a result, the voltage of the match line ML is pulled out to the ground, so that the level of the match line ML changes to “L”, and the search result becomes mismatch (Miss).

FIG. 4 is an operation waveform diagram in the case where the search results of the CAM basic cells in FIG. 1 match.
In FIG. 4, the search data is “1”, the stored data is “1”, that is, the resistance value of the tunnel magnetoresistive element TMR is R + ΔR, specifically, 30 KΩ.

  In this case, since the one-shot pulse width (500 ps) is smaller than the time constant τ1 (approximately 30 KΩ × 20 fF = 600 ps) of the low-pass filter, the one-shot pulse is filtered. As a result, the potential of the output terminal / SN of the inverter IV1 remains “L” and does not change. Therefore, since the voltage of the match line ML is not extracted to the ground, the level of the match line ML remains “H” and the search result is “Hit”.

  Using the above characteristics, the value (0/1) of the stored data is compared with the search line / SL = 0 of the search data, and the comparison result is converted to the level (0/1) of the match line ML. As a result, the search result is output to the match line ML.

  FIG. 5 is an operation waveform diagram when search data of the CAM basic cell in FIG. 1 is mask data.

  When the search data is “0”, it is in a mask state. When the search data is “0”, the level of the search line / SL remains “H” during standby. In this case, a one-shot pulse is not generated. As a result, the potential of the output terminal / SN of the inverter IV1 remains “L” regardless of the value of the stored data. Therefore, since the voltage of the match line ML is not extracted to the ground, the level of the match line ML remains “H” and the search result is “Hit”.

(TCAM basic cell)
FIG. 6 is a diagram illustrating a circuit configuration of a TCAM (Ternary CAM) basic cell according to the first embodiment.

  Referring to FIG. 6, this TCAM basic cell 10 includes two (2 bits) CAM basic cells in FIG.

  One of the CAM basic cells constituting the TCAM basic cell 10 is a first partial cell MCX, and the other is a second partial cell MCY.

  In first partial cell MCX, a terminal to which tunneling magneto-resistance element TMRX, N-channel MOS transistor N4, capacitive element C5 and inverter IV1 are connected is represented as SNX, and an output terminal of inverter IV1 is represented as terminal / SNX. Represent. In first partial cell MCX, the gate of N-channel MOS transistor N4 is connected to first read word line RWLX. Tunneling magneto-resistance element TMRX is connected to search line / SL.

  In the second partial cell MCY, a terminal to which the tunnel magnetoresistive element TMRY, the N-channel MOS transistor N4, the capacitive element C5, and the inverter IV1 are connected is represented as SNY, and the output terminal of the inverter IV1 is represented as a terminal / SNY. Represent. In the second partial cell MCY, the gate of the N-channel MOS transistor N4 is connected to the second read word line RWLY. Tunneling magneto-resistance element TMRY is connected to search line SL.

(TCAM basic cell truth table)
FIG. 7 is a diagram showing truth values of the TCAM basic cell of FIG. FIG. 8 is a diagram showing the relationship between search data and data transmitted to search lines SL and / SL.

  As shown in FIG. 7, the TCAM basic cell according to the present embodiment operates with a truth table similar to that of a TCAM basic cell having a normal SRAM configuration.

  When the search data is “0”, that is, the data transmitted to the search line SL is “0” (L-level one-shot pulse) and the data transmitted to the search line / SL is “1”, the tunnel Regardless of the resistance value of the magnetoresistive element TMRY, the terminal / SNY is “0” (L level). When the search data is “1”, that is, the data transmitted to the search line SL is “1” and the data transmitted to the search line / SL is “0” (L-level one-shot pulse), the tunnel Regardless of the resistance value of the magnetoresistive element TMRX, the terminal / SNX is “0” (L level).

  When the search data is “0”, that is, the data transmitted to the search line SL is “0” (L-level one-shot pulse) and the data transmitted to the search line / SL is “1”, the tunnel When the resistance value of the magnetoresistive element TMRX is R (“0” is stored), the terminal / SNX is “1” (H level), and the resistance value of the tunnel magnetoresistive element TMRX is R + ΔR (“1” is stored). Sometimes, the terminal / SNX is “0” (L level).

  When the search data is “1”, that is, the data transmitted to the search line SL is “1” and the data transmitted to the search line / SL is “0” (L-level one-shot pulse), the tunnel When the resistance value of the magnetoresistive element TMRY is R (“0” is stored), the terminal / SNY is “1” (H level), and the resistance value of the tunnel magnetoresistive element TMRY is R + ΔR (“1” is stored). Sometimes, the terminal / SNY becomes “0” (L level).

  When both the terminal / SNX and the terminal / SNY are “0”, the match line ML is “1” (H level), indicating a match (Hit). When either of the terminal / SNX and the terminal / SNY is “1”, the match line ML is “0” (L level), indicating mismatch (Miss). However, when both the resistance value of tunneling magneto-resistance element TMRX and the resistance value of tunneling magneto-resistance element TMRY are R + ΔR (“1” is stored), match line ML always matches regardless of the value of the search data. It becomes “1” (H level) indicating (Hit). When the resistance value of tunnel magnetoresistive element TMRX and the resistance value of tunnel magnetoresistive element TMRY are both R (“0” is stored), match line ML is always inconsistent regardless of the value of the search data. It becomes “0” (L level) indicating (Miss).

  When the data transmitted to the search line SL is “1” and the data transmitted to the search line / SL is “1”, the mask state is entered.

(overall structure)
FIG. 9 is a diagram illustrating the configuration of the content addressable memory device having the TCAM basic cell according to the first embodiment.

  Referring to FIG. 9, this MRAM includes a TCAM array mat 2, an SL driver 3, a BL driver 1, a read sense amplifier 9, a match amplifier (determination circuit) 5, an ML precharge circuit 95, a priority. An encoder 6, a row decoder 7, a DL driver 11, and an array control circuit 8 are provided.

In the TCAM array mat 2, TCAM basic cells are arranged in a matrix.
The SL driver 3 supplies search data to the search lines SL and / SL at the time of data search.

  The BL driver 1 applies a write current in a direction corresponding to the write data to the search lines SL and / SL that also serve as bit lines at the time of data writing.

  The read sense amplifier 9 amplifies the current (data) transmitted through the search lines SL and / SL which also serve as bit lines when reading data.

  A match amplifier (determination circuit) 5 is provided for each entry. When the match amplifier activation signal MAE is activated to “H” level during data search, the voltage of the match line ML is amplified and amplified. An entry search determination signal mao is output according to the voltage.

  The ML precharge circuit 95 is provided for each entry and precharges the match line ML.

  At the time of data search, the priority encoder 6 outputs the row addresses of a plurality of entries that indicate a match in accordance with the priority order.

  The row decoder 7 selects an entry and activates the word lines RWLX and RWLY of the selected entry.

The DL driver 11 applies a magnetizing current to the digit line DL at the time of data writing.
The array control circuit 8 controls the entire MRAM.

  FIG. 10 is a diagram showing the configuration of the TCAM array mat 2 of the associative memory device of FIG. FIG. 11 is a diagram showing the configuration of one entry (0th entry) of TCAM array mat 2 in FIG.

  Referring to FIG. 10 and FIG. 11, the TCAM array mat 2 is composed of 256 entries 14 from 0th to 255th. One entry of the TCAM array mat 2 includes 80-bit (80 pieces) TCAM basic cells 10 arranged in the 80th to 79th columns.

  The TCAM basic cell of the i-th entry is connected to the match line ML <i> and to the power supply line MLVDD <i>. Although not shown, the TCAM basic cell of the i-th entry is connected to the read word lines RWLX <i>, RWLY <i>, and the digit line DL <i> is further arranged.

The TCAM basic cell in the j-th column is connected to search lines SL <j>, / SL <j>.
(Search operation)
FIG. 12 is an operation waveform diagram at the time of search in the associative memory device of FIG.

  In FIG. 12, the resistance value of the tunnel magnetoresistive element TMRX of the first partial cell MCX is R (“0” is stored), and the resistance value of the tunnel magnetoresistive element TMRY of the second partial cell MCY is R + ΔR (“1” is stored). The case of (memory) is shown.

The array control circuit 8 receives a search command SEARCH from the outside.
The array control circuit 8 outputs a clock CAMCLK.

  SL driver 3 sets search lines SL and / SL to the “H” level during standby.

  When array control circuit 8 activates precharge control signal MLPRE to “H” level, ML precharge circuit 95 precharges match line ML to “H” level.

  When a search data DB having a value of “0” is given from the outside, the SL driver 3 outputs a one-shot pulse of “L” level to the search line SL during the search activation period, and sets the search line / SL to “H”. "Keep it at the level." This one-shot pulse is generated by a delay circuit in the SL driver 3, for example. As a result, the output terminal / SNX of the inverter IV1 of the first partial cell MCX remains unchanged at the “L” level. Further, the output terminal / SNY of the inverter IV1 of the second partial cell MXY is at the “H” level. As a result, the potential of the match line ML is pulled out to the “L” level.

  When the match amplifier activation signal MAE is activated to “H” level, the match amplifier 5 amplifies the potential of the match line ML. The match amplifier 5 outputs an “L” level entry search determination signal mao representing Miss since the potential of the match line ML is not equal to or greater than a certain value.

  The priority encoder 6 receives entry search determination signals mao [0] to mao [255] from the match amplifiers 5 of all entries. The priority encoder 6 outputs, to the array control circuit 8, the address (MATCH_ADD) of the entry with the highest priority among the entries that have output the entry search determination signal mao at the “H” level. The array control circuit 8 outputs a search result signal MATCH indicating a match with the address (MATCH_ADD) output from the priority encoder 6.

  On the other hand, when the search data DB having the value “1” is given from the outside, the SL driver 3 outputs a one-shot pulse of “L” level to the search line / SL during the search active period, and sets the search line SL to The “H” level is maintained. As a result, the output terminal / SNX of the inverter IV1 of the first partial cell MCX remains unchanged at the “L” level. Further, the output terminal / SNY of the inverter IV1 of the second partial cell MXY remains at the “L” level. As a result, the potential of match line ML is maintained at the “H” level.

  When the match amplifier activation signal MAE is activated to “H” level, the match amplifier 5 amplifies the potential of the match line ML. Since the potential of the match line ML is equal to or higher than a certain value, the match amplifier 5 outputs an “H” level entry search determination signal mao representing Hit.

  The priority encoder 6 receives entry search determination signals mao [0] to mao [255] from the match amplifiers 5 of all entries. The priority encoder 6 outputs, to the array control circuit 8, the address (MATCH_ADD) of the entry with the highest priority among the entries that have output the entry search determination signal mao at the “H” level. When the entry search determination signals mao [0] to mao [255] are all at “L” level, no address is output. The array control circuit 8 outputs a search result signal MATCH indicating a mismatch.

(Light operation)
FIG. 13 is an operation waveform diagram when “0” is written to the CAM basic cell.

  Referring to FIG. 13, array control circuit 8 receives a write command WRITE, a write address ADD, clock CAMCLK, and write data DB (= “0”) from the outside.

The DL driver 11 supplies the magnetizing current iDL to the digit line DL.
The BL driver 1 uses the write data DB (= “0”) to write to the search line / SL that also serves as the bit line BL in the first direction (for example, the direction from the larger row address to the smaller row address). A current iBL is applied. As a result, the resistance value of the tunnel magnetoresistive element TMR of the CAM basic cell becomes R.

FIG. 14 is an operation waveform diagram when “1” is written to the CAM basic cell.
Referring to FIG. 14, array control circuit 8 receives a write command WRITE, an address ADD to be written, clock CAMCLK, and write data DB (= “1”) from the outside.

The DL driver 11 supplies the magnetizing current iDL to the digit line DL.
The BL driver 1 uses the write data DB (= “1”) to write to the search line / SL that also serves as the bit line BL in the second direction (for example, the direction from the smaller row address to the larger one). A current iBL is applied. As a result, the resistance value of the tunnel magnetoresistive element TMR of the CAM basic cell becomes R + ΔR.

(Read operation)
FIG. 15 is an operation waveform diagram when data is read from the CAM basic cell.

  Referring to FIG. 15, array control circuit 8 receives a read command READ, a read address ADD, and a clock CAMCLK from the outside.

  Row decoder 7 activates read word line RWL of the entry corresponding to applied address ADD to "H" level.

  Depending on the resistance value of the tunnel magnetoresistive element TMR of the CAM basic cell of this entry, the voltage change of the search line / SL differs. When the resistance value of the tunnel magnetoresistive element is R + ΔR (that is, when “1” is stored), the amount of decrease in the voltage of the search line / SL also serving as the bit line BL from the precharge voltage VDD is A small amount. On the other hand, when the resistance value of the tunnel magnetoresistive element is R + ΔR (that is, when “1” is stored), the voltage of the search line / SL also serving as the bit line BL decreases from the precharge voltage VDD. The amount is large.

  The read sense amplifier 9 amplifies the voltage of the search line / SL, thereby outputting “0” or “1” data to the outside.

(Precharge match line ML)
FIG. 16 shows a configuration of the ML precharge circuit.

Referring to FIG. 16, this ML precharge circuit 95 is provided for each entry.
ML precharge circuit 95 includes a P-channel MOS transistor 191 provided between power supply VDD and internal node ND1, and a P-channel MOS transistor 192 provided between node ND1 and node ND2. P channel MOS transistor 192 has its gate receiving precharge control signal MLPRE_N. The gate of P-channel MOS transistor 191 receives delayed precharge control signal MLPRE_N_dly. The delayed precharge control signal MLPRE_N_dly is a signal obtained by delaying the precharge control signal MLPRE_N by a predetermined time.

  Node ND1 is connected to power supply line MLVDD. Power supply line MLVDD is connected to capacitive element C1 included in the TCAM basic cell included in one entry. The total value of the capacities of all the capacitive elements C1 included in one entry is CV.

Node ND2 is connected to match line ML. Let CC be the parasitic capacitance of the match line ML.
(Operation waveform during precharge of match line ML)
FIG. 17 is an operation waveform diagram when the match line ML is precharged.

  Referring to FIG. 17, first, the potential of power supply line MLVDD is precharged to VDD, and charges are accumulated in capacitive element C1 in the basic cell.

  When array control circuit 8 activates precharge control signal MLPRE_N to “L” level, P-channel MOS transistor 192 is turned on. As a result, the electric charge of the capacitive element C1 is output, so that the potential of the power supply line MLVDD decreases from VDD and the potential of the match line ML increases. When the total value CV of the capacitances of all the capacitive elements C1 included in one entry is 10 times the parasitic capacitance CC of the match line ML, the match line ML is activated by activating the precharge control signal MLPRE_N. Can be charged to 88% VDD.

  Next, when array control circuit 8 activates delayed precharge control signal MLPRE_N_dly to “L” level, P-channel MOS transistor 191 is turned on. As a result, the potentials of the match line ML and the power supply line MLVDD rise to VDD.

  Thereafter, array control circuit 8 deactivates precharge control signal MLPRE_N to “H” level to turn off P-channel MOS transistor 192. Further, array control circuit 8 deactivates delayed precharge control signal MLPRE_N_dly to “H” level, and turns off P-channel MOS transistor 191.

  When the search result is a match (Hit), the potential of the match line ML is maintained at the “H” level (VDD). However, when the search result is a mismatch (Miss), the potential of the match line ML is “L”. To the level (VSS). FIG. 17 shows a case where the search result is mismatch (Miss).

  As shown in FIG. 17, the change di / dt of the current amount iML flowing through the match line ML uses the local power line MLVDD, and therefore, compared to the case where the match line ML is directly precharged as in the related art. It is characterized by being small. As a result, noise due to a rapid current change di / dt can be greatly reduced.

(CAM layout)
FIG. 18 is a layout diagram of transistor layers and wiring layers of a CAM array mat. P-channel MOS transistor P1 and N-channel MOS transistor N1 constitute inverter IV1. Capacitance elements C1 and C5 are composed of N-channel MOS transistors and are therefore arranged in the transistor layer.

  FIG. 19 is a layout diagram of the third layer metal layer, the fourth layer metal layer, and the tunnel magnetoresistive element TMR of the CAM array mat. 20 is a cross-sectional view taken along line XIX-XIX in FIGS. 18 and 19. In FIG. 19, LV represents a local via, and LS represents a strap wiring.

  As shown in FIG. 20, gate electrodes G1, G2, G3 are formed at a predetermined pitch on the surface of a P-type well PW of a semiconductor substrate.

  Gate electrode G1 is a gate electrode of N-channel MOS transistor N2. A terminal / SN is connected to the gate electrode G1. N-type impurities are diffused on both sides of gate electrode G1 to form source S1 and drain D1 of N-channel MOS transistor N2. Drain D1 is connected to match line ML of third layer metal interconnection M2 through through hole TH and electrode EL. The source S1 is connected to VSS (ground).

  Gate electrode G3 is the gate electrode of N-channel MOS transistor N4. A read word line RWL is connected to the gate electrode G3. N-type impurities are diffused on both sides of gate electrode G3 to form source S2 and drain D2 of N-channel MOS transistor N4. The source S2 is connected to VSS (ground). The drain D2 is connected to the terminal SN through the through hole TH and the electrode EL. This terminal SN is connected to tunneling magneto-resistance element TMR via electrode EL. Tunneling magneto-resistance element TMR is connected to search line / SL through through hole TH. The drain D1 is connected to VSS (ground).

  The gate electrode G2 is a gate electrode of an N-channel MOS transistor that constitutes the capacitive element C5. The gate electrode is connected to the terminal SN. N-type impurities are diffused on both sides of the gate electrode G3 to form the source and drain of this N-channel MOS transistor. This source is shared with the source S1 of the N-channel MOS transistor N2. This drain is shared with the source S2 of the N-channel MOS transistor N4.

(TCAM layout)
FIG. 21 is a layout diagram of transistor layers and wiring layers of a TCAM array mat.

  FIG. 22 is a layout diagram of the third layer metal layer, the fourth layer metal layer, and the tunnel magnetoresistive element TMR of the TCAM array mat.

  Referring to FIGS. 21 and 22, TAM basic cell layout units 100 and 200 are composed of two CAM basic cell layout units 12 and 220, respectively.

[Second Embodiment]
(CAM basic cell)
FIG. 23 is a diagram illustrating a circuit configuration of a CAM basic cell according to the second embodiment.

  The CAM basic cell 112 of FIG. 23 differs from the CAM basic cell 12 of the first embodiment shown in FIG. 1 in that the CAM basic cell 112 of FIG. 23 includes an N-channel MOS transistor N20.

  The output of inverter IV1 is connected to the gate of N channel MOS transistor N2 and the gate of N channel MOS transistor N20.

  N-channel MOS transistor N20 is connected to first match line MLo and first power supply node VSSo. On the other hand, the N-channel MOS transistor N2 is connected to the second match line MLe and the second power supply node VSSe.

  The array control circuit 8 alternately applies “L” level pulses having a certain width to the potential of the first power supply node VSSo and the second power supply node VSSe. The period of these pulses is twice the period of the clock CLK.

(TCAM basic cell)
FIG. 24 is a diagram illustrating a circuit configuration of the TCAM basic cell according to the second embodiment.

  The TCAM basic cell 110 of FIG. 24 is different from the TCAM basic cell 10 of the first embodiment shown in FIG. 6 in that the TCAM basic cell 110 of FIG. 24 includes an N-channel MOS transistor N20.

  The output of inverter IV1 is connected to the gate of N channel MOS transistor N2 and the gate of N channel MOS transistor N20.

  N-channel MOS transistor N20 is connected to first match line MLo and first power supply node VSSo. On the other hand, the N-channel MOS transistor N2 is connected to the second match line MLe and the second power supply node VSSe.

  As in the case of the CAM basic cell, the array control circuit 8 alternately applies “L” level pulses having a certain width to the potential of the first power supply node VSSo and the second power supply node VSSe. The period of these pulses is twice the period of the clock CLK.

(Match amplifier)
FIG. 25 is a diagram illustrating configurations of a match amplifier (determination circuit) and an ML precharge circuit according to the second embodiment.

  Referring to FIG. 25, ML precharge circuit 96 includes a P channel MOS transistor 55 and a P channel MOS transistor 56.

  The P-channel MOS transistor 55 is provided between the VDD power supply and the second match line MLe. P channel MOS transistor 55 has its gate receiving precharge control signal MLPRE_Ne. The P channel MOS transistor 56 is provided between the VDD power source and the first match line MLo. The gate of P-channel MOS transistor 56 receives precharge control signal MLPRE_No.

  The match amplifier 85 includes an inverter 53, an inverter 54, a multiplexer 52, and a latch circuit 51.

  The inverter 53 is connected to the second match line MLe, and outputs to the multiplexer 52 an entry search second determination signal “maoe” obtained by inverting the voltage of the second match line MLe.

  The inverter 54 is connected to the first match line MLo and outputs an entry search first determination signal “maoo” obtained by inverting the voltage of the first match line MLo to the multiplexer 52.

  The multiplexer 52 receives the entry search second determination signal maoe and the entry search first determination signal maoo, and outputs the entry search second determination signal maoe and the entry search first determination signal as signals to be output at the rising timing of the clock CLK. Switch maoo alternately.

  The latch circuit 51 latches the output of the multiplexer 52 and outputs the entry search determination signal mao.

(Operation waveform)
FIG. 26 is an operation waveform diagram for explaining the operation of the match amplifier.

  FIG. 26 shows a case where a one-shot pulse is always applied to the search line SL and Miss (L level) is set for both the first match line MLo and the second match line MLe.

  Referring to FIG. 26, array control circuit 8 receives clock CLK having a period of “1.65 ns” from the outside.

  The array control circuit 8 applies an “L” level pulse having a constant width of “3.3 ns” to the potential of the first power supply node VSSo and the second power supply node VSSe. The pulse applied to the second power supply node VSSe is delayed by “1.65 ns” from the pulse applied to the first power supply node VSSo.

  In response to the potential of the first power supply node VSSo becoming the “L” level, the level of the first match line MLo changes. Further, the level of the second match line MLe changes in response to the potential of the second power supply node VSSe becoming the “L” level.

  The match amplifier 85 amplifies the voltages of the first match line MLo and the second match line MLe, alternately selects the voltages of the first match line MLo and the second match line MLe, and outputs them as the entry search determination signal mao. .

  This solves the problem that the search operation frequency cannot be increased because the search operation frequency becomes 600 MHz, which is twice the conventional 300 MHz, and the high-speed operation of the amplifiers (inverters 53 and 54) is difficult. be able to.

[Third Embodiment]
(TCAM basic cell)
FIG. 27 is a diagram illustrating a circuit configuration of a TCAM basic cell according to the third embodiment.

  The TCAM basic cell of FIG. 27 is different from the TCAM basic cell 10 of the first embodiment shown in FIG. 6 in that the TCAM basic cell 151 of FIG. 27 is replaced with the capacitive element C1 connected to the power line MLVDD. The capacitor element C2 connected to the power supply line SLVDD and the capacitor element C2 connected to the power supply line SLVDDN are provided.

  The N-channel MOS transistor constituting the capacitive element C2 has a gate connected to the power supply line SLVDD or the power supply line SLVDDN, and a source and a drain connected to the ground.

(Constitution)
FIG. 28 is a diagram illustrating a configuration of an associative memory device having a TCAM basic cell according to the third embodiment.

The associative memory device of FIG. 28 is different from the associative memory device of the first embodiment shown in FIG.
The ML precharge circuit 96 and the TCAM array mat 102 are different from each other, and an SL precharge circuit 92 is provided.

  In TCAM array mat 102, power supply lines MLVDD are not disposed, but power supply lines SLVDD and SLVDDN are disposed.

  The configuration of ML precharge circuit 96 does not include P-channel MOS transistor 191 connected to power supply line MLVDD in FIG.

  FIG. 29 is a diagram showing the configuration of the TCAM array mat of the associative memory device of FIG. FIG. 30 shows a structure of one entry (0th entry) in the TCAM array mat of FIG.

  Referring to FIGS. 29 and 30, the TCAM array mat is composed of 256 entries of 0th to 255th. One entry of the TCAM array mat includes 80-bit (80) TCAM basic cells arranged in the 80th to 79th columns.

  The TCAM basic cell of the i-th entry is connected to the match line ML <i>, and the TCAM basic cell of the j-th column is connected to the search lines SL <j>, / SL <j> and the power supply line SLVDD <j>. , SLVDDN <j>.

(SL precharge circuit)
FIG. 31 shows a configuration of the SL precharge circuit.

Referring to FIG. 31, SL precharge circuit 92 is provided for each search line.
The SL precharge circuit 02 includes a P-channel MOS transistor 193 provided between the power supply VDD and the internal node ND3, and a P-channel MOS transistor 194 and an N-channel MOS transistor provided between the internal node ND3 and the ground. 195 and an inverter IV99.

  The gate of P channel MOS transistor 193 receives delayed search control signal SLE_N_dly. Inverter IV99 receives search control signal SLE_N. The delayed search control signal SLE_N_dly is a signal obtained by delaying the search control signal SLE_N by a predetermined time.

  Node ND1 is connected to power supply line SLVDD. Power supply line SLVDD is connected to capacitive element C2 included in a TCAM basic cell connected to one search line SL. Let CS be the total value of the capacitive elements C2 of the TCAM basic cells connected to one search line SL.

  The output of inverter IV99 is connected to search line SL. Let CD be the parasitic capacitance of the search line SL.

(Operation waveform when search line SL is precharged)
FIG. 32 is an operation waveform diagram when the search line SL is precharged.

  Referring to FIG. 32, first, the potential of power supply line SLVDD is precharged to VDD, and charges are accumulated in capacitive element C2 in the basic cell.

  When array control circuit 8 activates search control signal SLE_N to “L” level, P-channel MOS transistor 194 is turned on and N-channel MOS transistor 195 is turned off. As a result, the charge of the capacitive element C2 is output, so that the potential of the power supply line SLVDD decreases from VDD and the potential of the search line SL increases. When the total value CS of the capacitances of all the capacitive elements C2 included in one column is 10 times the parasitic capacitance of the search line SL with respect to CD, the search line SL is activated by activating the search control signal SLE_N. Can be charged to 88% VDD.

  Next, when array control circuit 8 activates delay search control signal SLE_N_dly to “L” level, P-channel MOS transistor 193 is turned on. As a result, the potentials of the search line SL and the power supply line SLVDD rise to VDD.

  Thereafter, array control circuit 8 deactivates search control signal SLE_N to “H” level, turns off P-channel MOS transistor 194 and turns on N-channel MOS transistor 195. As a result, the potential of the search line SL is pulled out to the “L” level (VSS). Furthermore, array control circuit 8 deactivates delay search control signal SLE_N_dly to “H” level, and turns off P-channel MOS transistor 193. While the P-channel MOS transistor 194 is on, the potential of the power supply line SLVDD maintains the “H” level (VDD).

  As shown in FIG. 32, the change di / dt in the amount of current iSL flowing through the search line SL is smaller than in the conventional case where the search line SL is directly precharged without using the power supply line SLVDD. There are features. As a result, noise due to a rapid current change di / dt can be greatly reduced. Further, unlike the conventional case, it is not necessary to install a large-capacity bypass capacitor on the substrate in order to reduce power supply noise due to di / dt, and the substrate mounting area can be reduced.

[Fourth Embodiment]
(TCAM basic cell)
FIG. 33 is a diagram illustrating a circuit configuration of a TCAM basic cell according to the fourth embodiment.

  The TCAM basic cell 310 of FIG. 33 differs from the TCAM basic cell 10 of the first embodiment shown in FIG. 6 in that the TCAM basic cell 310 of FIG. 33 has the other ends (N of the tunnel magnetoresistive elements TMRX and TMRY). The terminal connected to the channel MOS transistor N4 and the capacitive element C4) is directly connected to the gate of the N-channel MOS transistor N2 without going through the inverter IV1.

  The TCAM basic cell 310 operates in substantially the same manner as the TCAM basic cell 10 of the first embodiment shown in FIG.

(Overall operation)
FIG. 34 is an operation waveform diagram at the time of search in the content addressable memory device having the TCAM basic cell of FIG.

  The operation waveform of FIG. 34 differs from the operation waveform of the first embodiment of FIG. 12 in that, in FIG. 34, when the search data is “0”, the one-shot pulse of “H” level is applied to the search line SL. When the search data is “1”, an “H” level one-shot pulse is applied to the search line / SL.

  In FIG. 34, the voltage of the match line ML is determined not by the voltages of the terminals / SNX and / SNY but by the voltages of the terminals SNX and SNY. This is because the terminals SNX and SNY are connected to the gate of an N-channel MOS transistor N2 provided between the match line ML and the ground.

  The voltage of the terminals SNX and SNY is shorter than the voltage of the terminals / SNX and / SNY of the first embodiment via the inverter IV1, but the period of maintaining the power supply voltage VDD is short, but the threshold of the N-channel MOS transistor N2 Is appropriately set, the voltage of the match line ML can be changed depending on the voltage levels of the terminals SNX and SNY.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 BL driver, 2,102 TCAM array mat, 3 SL driver, 5,85 match amplifier, 6 priority encoder, 7 row decoder, 8 array control circuit, 9 read sense amplifier, 10, 12, 110, 151, 310 basic cell , 11 DL driver, 14,114 entry, 51 latch circuit, 52 multiplexer, 92 SL precharge circuit, 95, 96 ML precharge circuit, 55, 56, 191, 192, 193, 194, 195 P-channel MOS transistor, ML , MLo, MLe match line, RWL, RWLX, RWLY read word line, DL digit line, SL (/ BL), / SL (BL) search line, MLVDD, SLVDD, SLVDDN power supply line, C1, C2, C5 capacitive element , N2, N , N20 N-channel MOS transistor, IV1, 53, 54 inverter, SN, / SN, SNX, / SNX, SNY, / SNY terminals, TMR, TMRX, TMRY tunnel magnetoresistive element, MCX, MCY memory cell, VSSo, VSSe power supply node.

Claims (10)

  1. An associative memory device capable of detecting coincidence or mismatch between stored data and search data,
    A memory array including a plurality of associative memory cells arranged in a matrix;
    A plurality of match lines each connected to a plurality of associative memory cells belonging to a corresponding entry in the memory array;
    A plurality of determination circuits each outputting a search determination signal representing a match or mismatch between the data stored in the associative memory in the entry of the memory array and the search data in accordance with the voltage of the match line;
    A plurality of search lines each supplying a voltage according to a value of the search data to a plurality of associative memories belonging to a column in the memory array during data search;
    A plurality of word lines each connected to a plurality of associative memory cells belonging to a corresponding entry in the memory array;
    A first driver that outputs a one-shot pulse of a predetermined width to the search line when the search data has a predetermined value;
    The associative memory cell is
    A tunnel magnetoresistive element having one end connected to the search line;
    A capacitive element connected to the other end of the tunnel magnetoresistive element;
    A first MOS transistor provided between the other end of the tunnel magnetoresistive element and a ground power supply and having a control electrode connected to the word line;
    An associative memory device comprising: a second MOS transistor provided between the match line and the ground power supply, the control electrode receiving a voltage generated at the other end of the tunnel magnetoresistive element.
  2. The associative memory device further includes:
    Digit lines each supplying a magnetizing current to a plurality of associative memory cells belonging to a corresponding entry in the memory array;
    A second driver for supplying the magnetizing current to the digit line during data writing;
    The associative memory device according to claim 1, further comprising a third driver that supplies a write current having a direction corresponding to a value of write data to the search line at the time of data writing.
  3. The associative memory cell further includes:
    2. The content addressable memory device according to claim 1, further comprising an inverter having an input terminal connected to the other end of the tunnel magnetoresistive element and an output terminal connected to a control electrode of the second MOS transistor.
  4. The associative memory device further includes:
    Each includes a plurality of auxiliary wirings provided corresponding to one of the plurality of match lines,
    The associative memory cell further includes:
    Including a capacitive element connected to the auxiliary wiring;
    Each first precharges the auxiliary wiring to a positive power supply voltage, accumulates charges in a plurality of capacitive elements connected to the auxiliary wiring, and then stores the charges accumulated in the capacitive elements in the match line The content addressable memory device according to claim 1, further comprising: a plurality of precharge circuits that output the match line and the auxiliary wiring to the positive power supply voltage.
  5. The precharge circuit is
    A first precharging MOS transistor provided between the power supply of the positive power supply voltage and a first internal node and receiving a first control signal at a control electrode;
    A second precharge MOS transistor provided between the first internal node and the second internal node and receiving a second control signal at a control electrode;
    The first internal node is connected to the auxiliary wiring, the second internal node is connected to the match line,
    The associative memory device further includes:
    5. The content addressable memory according to claim 4, further comprising a control circuit that activates the second control signal at a predetermined time interval and activates the first control signal after a predetermined time after the activation of the second control signal. apparatus.
  6.   5. The content addressable memory device according to claim 4, wherein the capacitive element is formed of a MOS transistor having a source and a drain connected to the ground power supply.
  7. The associative memory device further includes:
    Each includes a plurality of auxiliary wirings provided corresponding to one of the plurality of search lines,
    The associative memory cell further includes:
    Including a capacitive element connected to the auxiliary wiring;
    Each first precharges the auxiliary wiring to a positive power supply voltage, accumulates charges in a plurality of capacitive elements connected to the auxiliary wiring, and then stores the charges accumulated in the capacitive elements in the search line. The associative memory device according to claim 1, further comprising: a plurality of precharge circuits that output the search line and the auxiliary line to the positive power supply voltage.
  8. The first driver is:
    A precharge MOS transistor provided between the power supply of the positive power supply voltage and the first internal node and receiving a first control signal at a control electrode;
    An inverter that is provided between the first internal node and a ground power supply, receives a second control signal at an input, and has an output connected to the search line;
    The first internal node is connected to the auxiliary wiring;
    The associative memory device further includes:
    The associative memory according to claim 7, further comprising a control circuit that activates the second control signal at a predetermined time interval and activates the first control signal after a predetermined time after the activation of the second control signal. apparatus.
  9.   The content addressable memory device according to claim 6, wherein the capacitive element is formed of a MOS transistor having a source and a drain connected to the ground power supply.
  10. An associative memory device capable of detecting coincidence or mismatch between stored data and search data,
    A memory array including a plurality of associative memory cells arranged in a matrix;
    A plurality of first and second match lines each connected to a plurality of associative memory cells belonging to a corresponding entry in the memory array;
    Retrieval determination, each representing a match or mismatch between data stored in an associative memory in an entry of the memory array and search data in accordance with the voltage of the first match line or the voltage of the second match line A plurality of determination circuits for outputting signals;
    A plurality of search lines each supplying a voltage according to a value of the search data to a plurality of associative memories belonging to a column in the memory array during data search;
    A plurality of word lines each connected to a plurality of associative memory cells belonging to a corresponding entry in the memory array;
    A first driver that outputs a one-shot pulse of a predetermined width to the search line when the search data has a predetermined value;
    The associative memory cell is
    A tunnel magnetoresistive element having one end connected to the search line;
    A capacitive element connected to the other end of the tunnel magnetoresistive element;
    A first MOS transistor provided between the other end of the tunnel magnetoresistive element and a ground power supply and having a control electrode connected to the word line;
    A second MOS transistor provided between the first match line and a first power supply node, the control electrode receiving a voltage generated at the other end of the tunnel magnetoresistive element;
    A third MOS transistor provided between the second match line and a second power supply node, the control electrode receiving a voltage generated at the other end of the tunnel magnetoresistive element;
    The determination circuit alternately uses the voltages of the first power supply node and the second power supply node as a ground voltage, amplifies the voltage of the first match line and the voltage of the second match line, and after amplification An associative memory device that alternately selects the voltage of the first match line and the voltage of the second match line and outputs the voltage as the search determination signal.
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JP2013200920A (en) * 2012-03-26 2013-10-03 Tohoku Univ Nonvolatile memory device

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US6191973B1 (en) * 1999-09-27 2001-02-20 Motorola Inc. Mram cam
WO2002061755A1 (en) * 2001-01-31 2002-08-08 Motorola, Inc., A Corporation Of The State Of Delaware Content addressable magnetic random access memory
JP2002334585A (en) * 2001-05-02 2002-11-22 Sony Corp Semiconductor memory
US20060067098A1 (en) * 2004-09-30 2006-03-30 Richard Ferrant Content addressable memory cell including resistive memory elements
WO2008040561A2 (en) * 2006-10-06 2008-04-10 Crocus Technology S.A. System and method for providing content-addressable magnetoresistive random access memory cells

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US6191973B1 (en) * 1999-09-27 2001-02-20 Motorola Inc. Mram cam
WO2002061755A1 (en) * 2001-01-31 2002-08-08 Motorola, Inc., A Corporation Of The State Of Delaware Content addressable magnetic random access memory
JP2002334585A (en) * 2001-05-02 2002-11-22 Sony Corp Semiconductor memory
US20060067098A1 (en) * 2004-09-30 2006-03-30 Richard Ferrant Content addressable memory cell including resistive memory elements
WO2008040561A2 (en) * 2006-10-06 2008-04-10 Crocus Technology S.A. System and method for providing content-addressable magnetoresistive random access memory cells

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