201030749 六、發明說明： 【發明所屬之技術領域】 本發明係有關於-種寫人操作時提高寫人用字元線電壓位準之雙 淳靜態隨機存取記憶體（StaticRand〇mAc⑽M_^，簡稱⑽⑷， 尤才曰種可降低漏電流(leakage eurrent)、降低讀取干擾、提高讀取可 . *度以及能解決f知具單-位元線之雙璋SRAM寫人邏輯1困難之雙 槔靜態隨機存取記憶體。 φ 【先前技術】 記憶體在電腦工業中扮演著無可或缺的角色。通常，記憶體可依照 其能否在《咖後仍祕存資料而區分為揮發性記舰和非揮發性 己it體s巾揮發性^憶體可再區分為動態隨機存取記憶體 及靜態隨機存取記憶體(SRAM)兩種。動態'隨機存取記舰(〇麵)具 有面積小及雜低等優點，但操作時必鮮時地更新(她,以防止資 料因漏電流而遺失，而導致存在有高速化賺及消耗辨大等缺失。 相反地’靜態隨機存取記憶體(SRAM)的操作則較為帛易且毋須更新操 ⑩ 作，因此具有高速化及消耗功率低等優點。 目前以行動電話為代表之行動電子設備所採用之半導體記憶裝 . 置，係以SRAM為主流。此乃由於SRAM待機電流小，適於連續通話 時間、連續待機時間盡可能延長之手機。 靜態隨機存取記憶體(SRAM)主要包括一記憶體陣列（mem〇ry array) ’該記憶體陣列係由複數列記憶體晶胞（a pluralky 〇f _s # memory cells)與複數行記憶體晶胞（aplurality〇fe〇lumns〇fmemwy cells)所組成’每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個 記憶體晶胞；複數條字元線(wordline)，每一字元線對應至複數列記憶 體晶胞中之一列，以及複數位元線對(bit line pairs)，每一位元線對係對 3 201030749 應至複數行記憶體晶胞中之一行，且每一位元線對係由一位元線及一 互補位元線所組成。 第1圖所示即是6T靜態隨機存取記憶體(SRAM)晶胞之電路示意 圖，其中’ PMOS電晶體P1和P2稱為負載電晶體（load transistor)， 和M2稱為驅動電晶體（driving transistor) ’ M3和M4稱為存取電 晶體（access transistor)，WL 為字元線(wordline)，而 BL 及 BLB 分別 為位元線（bit line)及互補位元線（complementary bit line)，由於該 SRAM晶胞需要6個電晶體，且驅動電晶體與存取電晶體間的電流驅 • 動能力比(即單元比率(cell ratio))通常設定在2至3之間，而導致存在有 咼集積化困難及價格高等缺失。第1圖所示6T靜態隨機存取記憶體晶 胞，於寫入操作時之HSPICE暫態分析模擬結果，如第2圖所示，其係 以1evel 49模型且使用TSMC 0.35微米CMOS製程參數加以模擬。 用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種 方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5T靜態隨 機存取記健晶胞之電路*意g，鄕丨圖之6了靜諷齡取記憶體 晶胞相比，此種5T靜態隨機存取記憶體晶胞比6T靜態隨機存取記憶 ® 體晶胞少一個電晶體及少一條位元線’惟該5Τ靜態隨機存取記憶體晶 胞存在寫人邏輯1相當困難之問題。兹考慮記憶晶胞左側節點Α原本 ' 儲存邏輯0的情況，由於節點A之電荷僅單獨自位元線(BL)傳送，因 此很難將節點A中先前寫入的邏輯0蓋寫成邏輯1。第3圖所示5T靜 態隨機存取記憶體晶胞，於寫入操作時之HSpiCE暫態分析模擬結果， 如第4圖所示，其係以level 49模型且使用tsmc 〇 %微米製 _參數加&翻_ ’由雜_果可㉛實，具單—位元狀5了靜態隨機 存取》己_體晶胞存在寫人邏輯丨相當固難之問題。 接下來討論義賴麵龍(SRAM)之料&料雜，第丨 圖之6τ靜態隨機存取記憶體(sram)晶胞即是單璋靜態隨機存取記憶 4 201030749 體(SRAM)晶胞之—例，其係使用兩條位元線bl及此 作是讀與寫均是經由同樣的—對位元線來達成，是以 間内4進仃讀或寫的動作，因此，當欲設計具有同時讀寫能力之雙 埠靜態隨機存取記憶體時，便需要多加入兩顆存取電晶體以 位元線（請參考第5圖所示電路，其中狐及狐B為寫入用位^ 對RBL: RBLB為讀取用位元線對、wwl為寫人用字元線、&饥 S子元線）這使得記憶晶胞的面積大大地增加’如果我們妒热 簡化=aa胞的架構，使得—條位元線貞責讀取魏作，㈣—條位 元線負責“_作’财設計雙轉祕機躲鎌情曰 胞便《要多加人兩顆電_及另—對位元線，這樣記憶晶胞的= 便會減小許雙琿靜騎機存取記憶體晶胞之所以不採 種方法，是因為如麵述之無法達絲人邏輯1的問題。 有鑑於此本發明之主要目的係提出一種寫入操作時提高寫 元線電壓位準之雙埠靜態隨機存取記憶體，其能藉由寫入操作時提古 寫入用字元線電壓位準以有效避免習知具單一位元線之雙轉態隨: 存取讀體晶胞存在寫人邏輯丨相當雌之問題。 本發明作之次要目的係提出一種寫 壓位準之料觸«存取記麵，魏辑電 流，而於讀取時則能降低讀取干擾和提高讀取可靠度機i夺之漏電 【發明内容】 本發明提出―種寫人操作時提高寫人时元線電做準之雙槔靜 態隨機存取記憶體（Dua丨PGrt SRAM)，其係包括—記憶體陣列， 憶體陣列鶴概列記賴晶雜概行記鋪晶鱗組成，每_；列 記憶體晶胞與每-行記碰晶胞各包括有複數個記憶·胞⑴一 第-偏壓電路⑵，·-第二偏麼電路⑴。該等記憶體晶胞⑴係連 5 201030749 接在回電麼節點(VH)與一低電堡節點(VL)之間，該等記麵晶胞⑴ 於寫入操作時，將—寫人㈣賴應電氧供應至—寫入用字元 ' ^ )該寫人用電源供應M(WVdd)之位準係設定至少為一高電 原供應電壓(HVDD)加上一寫入用選擇電晶體(Mws)之臨界電壓之位 _ 準俾藉由寫入操作時提高寫入用字元線(WWL)之電虔位準以有效避 免寫人邏輯1相當馨之問題；而於待機模式(standby福6)時，則藉 由將1電源供應電壓(LVdd)供應至該高電壓節點㈣以及將較接地 M為间之—雙供應至該低電轉點㈣，財麟低靜態隨機存 取。己隱體之功率消耗；再者，於讀取操作時，藉由將一讀取用字元線 _)於非選擇(n〇nselected)時之電壓位準設定成低於接地電壓(例如 0.5伏特），以有效降低讀取干擾並提高讀取可靠度。、结果，本發明所 提出之寫入操作時提高寫入用字元線電壓位準之雙璋靜態隨機存取記 憶體，不但可有效避免習知具單_位元線之雙槔sram所存在寫入邏 輯相田困難之問題，並且也能兼具待機模式時降低漏電流與讀取干 擾和高可靠度等功效。 ' _ 【實施方式】 根據上述之主要目的，本發明提出__種寫人操作時提高寫入用字元 • 線電壓位準之雙埠靜態隨機存取記憶體，該寫入操作時提高寫入用字 • 元線電壓位準之雙琿靜態隨機存取記憶體係包括-記憶體陣列，該纪 憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞雖成，每一列 圮憶體晶胞與每-行記憶體晶胞各包括有複數個記憶體晶胞⑴；一 第一偏壓電路（2);以及一第二偏壓電路（3)。 為了便於說明起見’第6圖所示之寫人操作時提高寫人用字元線電 壓位準之雙槔靜態義存取記憶體僅以—個記憶體晶胞⑴、一條寫 入用字元線（WWL)、-條讀取时元線（RWL)、—條寫入用位元 6 201030749 線CWBL)、一條讀取用位元線(RBL)、一第一偏壓電路（2)、以及一 第二偏壓電路（3)做為實施例來說明。該記憶體晶胞（〗）係連接在 一高電壓節點(VH)與一低電壓節點(VL)之間，且包括一第一反相器(由 第一PMOS電晶體P1與第一 nmos電晶體M1所組成）、一第二反相 - 器（由第二PMOS電晶體P2與第二NMOS電晶體M2所組成）、一寫入 • 用選擇電晶體(MWS)、一讀取用選擇電晶體(MRS)、以及一反相電晶體 (MINV) ’其中’該第一反相器和該第二反相器係呈交互耦合連接，亦 即該第一反相器之輸出（即儲存節點A)係連接該第二反相器之輸入，而 ❿ 該第二反相器之輸出（即反相儲存節點B)則連接該第一反相器之輸入， 並且該第一反相器之輸出(儲存節點A)係用於儲存SRAM晶胞(1)之資 料’而該第二反相器之輸出(反相儲存節點B)則用於儲存SRam晶胞(1) 之反相資料，該寫入用選擇電晶體(MWS)，係連接在該儲存節點(A)與 寫入用位元線(WBL)之間，且閘極連接至該寫入用字元線(WWL);該 讀取用選擇電晶體(MRS)之一端連接至該讀取用位元線(rbl)，另一端 與該反相電晶體(MINV)相連接，而閘極則連接至該讀取用字元線 (RWL);而該反相電晶體(MINV)之一端與該讀取用選擇電晶體(mrs) φ 相連接，另一端連接至該低電壓節點(VL)，而閘極則連接至該反相儲 存節點(B)。 . 請再參考第6圖，該第一偏壓電路(2)係由一第三PM〇s電晶體 (P21)、一第四PM0S電晶體(P22)以及一第三反相器(123)所組成，該第 三PMOS電晶體(P21)之源極、閘極與沒極係分別連接至一高電源供應 電壓(HVDD)、一第一控制信號(SAP)與該高電壓節點(yjj);該第四 PMOS電晶體(P22)之源極、閘極與没極係分別連接至一低電源供應電 壓(LVDD)、該第三反相器(123)之輸出端與該高電壓節點_)，而該第 三反相器(123)之輸入端則用以接收該第一控制信號(sap)。再者，該第 二偏壓電路(3)係由一第三NMOS電晶體(M31)以及一第四NMOS電晶 201030749 體(M32)所組成’該第三譲08電晶體_)之源極 '開極與沒極係分 別連接至接地電壓、一第二控制信號^蝴與該低電壓節點㈤，該第 四NMOS電晶體_)之源極係連接至接地電壓，而閉極與汲極係=接 在一起，並連接至該低電壓節點(YL)。 ， 在此值·意的是’本發縣了防止感測容限(Sense margin)降 低，於是將該讀取用字元線(RWL)於非選擇(n〇nselected)時之電屢位準 設定成低於接地電壓(例如_〇.5伏特），亦即，該讀取用字元線(概)於 讀取操作期間係設定為該高電源供應電壓，加），而於讀取操作以外 ❿ 之期間則設定為低於接地電壓之電壓位準(例如-0.5伏特），至於該寫入 用字元線(WWL)於寫人操作顧係設定為__寫人用電源供應電壓 (wvDD)之位準，該寫入用電源供應電壓(WVdd)之位準係設定至少為 -高電源供應電麼(hvdd)加上該寫入用選擇電晶體(MWS)之臨界電壓 之位準，而於寫入操作以外之期間則設定為接地電壓。 兹依雙琿SRAM之;η作赋·第"之本發難佳實施例的工 作原理如下： (I)主動模式(active mode) 參 此時第一控制信號(SAP)為邏輯低位準，而第二控制信號(SAN)為 邏輯高位準，該邏輯低位準之第一控制信號(SAp)可使得第一偏壓電路 ' (2)中之第：PMOS電晶體(P21)〇N(導通），於是可將高電源供應電廢 . (HVDD)供應至鬲電壓節點(VH);而該邏輯高位準之第二控制信號(SAN) 可使得第二偏壓電路(3)中之第三nmos電晶體(M31) ON(導通），於 是可將低電壓節點(VL)拉下至接地電壓。 接下來依雙埠靜態隨機存取記憶晶胞之4種寫入狀態來說明第6圖 之本發明如何完成寫入動作。 (一）儲存節點(A)原本儲存邏輯〇，而現在欲寫入邏輯〇 ··201030749 VI. Description of the Invention: [Technical Field] The present invention relates to a double-static static random access memory (StaticRand〇mAc(10)M_^, abbreviation for improving the voltage level of a character line for writing a person during operation (10)(4), Youcai can reduce the leakage current (leakage eurrent), reduce the read interference, improve the readability, and can solve the problem that the double-sink SRAM of the single-bit line has a difficult logic. Static Random Access Memory φ [Prior Art] Memory plays an indispensable role in the computer industry. Usually, memory can be classified as volatile according to whether it is still secret data after coffee. The volatility and non-volatile body of the ship can be further divided into dynamic random access memory and static random access memory (SRAM). The dynamic 'random access memory ship (〇面) has The advantages of small area and low frequency, but the operation must be updated freshly (she, in order to prevent the data from being lost due to leakage current, resulting in the lack of high-speed profit and consumption, etc.. Conversely, 'static random access memory The operation of the body (SRAM) is more There is no need to update the operation, so it has the advantages of high speed and low power consumption. Currently, the semiconductor memory device used in mobile electronic devices represented by mobile phones is based on SRAM. This is due to the small standby current of the SRAM. A mobile phone suitable for continuous talk time and continuous standby time as long as possible. The static random access memory (SRAM) mainly includes a memory array (mem〇ry array) 'the memory array is composed of a plurality of columns of memory cells (a pluralky 〇f _s # memory cells) and a plurality of memory cells (aplurality〇fe〇lumns〇fmemwy cells) composed of 'each column of memory cells and each row of memory cells each including a plurality of memories a unit cell; a word line, each word line corresponding to one of a plurality of columns of memory cells, and a plurality of bit line pairs, each bit line pair 3 201030749 should be one of the rows of memory cells, and each bit line pair consists of one bit line and one complementary bit line. Figure 1 shows 6T static random access memory ( SRAM) unit cell Circuit diagram, where 'PMOS transistors P1 and P2 are called load transistors, and M2 is called driving transistors' M3 and M4 are called access transistors, WL is word The word line, and BL and BLB are the bit line and the complementary bit line, respectively. Since the SRAM cell requires 6 transistors, and drives the transistor and the access transistor. The current drive ratio (ie, cell ratio) is usually set between 2 and 3, resulting in a lack of accumulation and high price. The 6T static random access memory cell shown in Figure 1 shows the HSPICE transient analysis simulation results during the write operation. As shown in Figure 2, it is modeled using the 1evel 49 model and using TSMC 0.35 micron CMOS process parameters. simulation. One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a circuit with a single bit line of 5T static random access memory cell * meaning g, Figure 6 of the static sarcasm compared to the memory cell, this 5T static random memory Taking a memory cell is one transistor less than a 6T static random access memory device cell and one bit line is left. However, it is quite difficult to write a human logic 1 in the cell of the static random access memory cell. Consider the case where the left side of the memory cell Α originally 'stores logic 0', since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 3 shows the 5T SRAM cell, the HSpiCE transient analysis simulation result during the write operation, as shown in Figure 4, which is in the level 49 model and uses tsmc 〇% micron _ parameters Add & _ _ 'from the _ fruit can be 31, with a single-bit shape 5 static random access 》 _ body cell has a problem of writing human logic is quite difficult. Next, we discuss the material of the SRAM and the material of the SRAM. The 6τ static random access memory (SRAM) cell is the single-station static random access memory 4 201030749 (SRAM) cell For example, the use of two bit lines bl and the fact that both reading and writing are achieved through the same-to-bit line, is an in-between read or write operation, therefore, when When designing a dual-static SRAM with simultaneous read and write capability, it is necessary to add two access transistors to the bit line (refer to the circuit shown in Figure 5, where Fox and Fox B are used for writing) Bit ^ For RBL: RBLB is the bit line pair for reading, wwl is the character line for writing, and the star line of the hunger S) This greatly increases the area of the memory cell. 'If we simplify the heat =aa The structure of the cell makes it possible to read Wei Zuo, (4) - the line of the line is responsible for "_" the design of the dual-transfer secret machine to hide the sputum, "you need to add two people _ and another - the bit line, such that the memory cell = will reduce the reason why Xu Shuangjing rides the memory cell to access the memory cell because it is not described The problem of the Fadassian logic 1 is that the main purpose of the present invention is to provide a dual-static static random access memory that improves the writing voltage line level during a write operation, which can be raised by a write operation. The ancient write word line voltage level is used to effectively avoid the double-transition state with a single bit line: the access read cell has the problem that the write logic is quite female. The secondary purpose of the present invention is A kind of writing pressure level is proposed to touch the access surface, and the current is reduced, and when reading, the reading interference can be reduced and the reading reliability can be improved. The invention proposes that When writing a person's operation, the dual-static static random access memory (Dua丨PGrt SRAM) is improved when the writer is working. The system includes a memory array, and the memory array is listed in the Lai Jing. The crystal scale composition, each of the _; column memory cell and each row of the touch cell comprises a plurality of memory cells (1) a first-bias circuit (2), a second circuit (1). Body cell (1) is connected to 5 201030749 between the return node (VH) and a low-power buck node (VL) When the writing unit (1) is in the writing operation, the writing source (4) is supplied with the electric oxygen to the writing character '^), and the writing power supply M (WVdd) is set to at least A high-voltage original supply voltage (HVDD) plus a threshold voltage for writing a select transistor (Mws) _ quasi-俾 improves the write level of the write word line (WWL) by a write operation In order to effectively avoid the problem of writing logic 1 is quite pleasing; in standby mode (standby 6), by supplying 1 power supply voltage (LVdd) to the high voltage node (4) and the grounding M is between - Dual supply to the low power transfer point (four), Cai Lin low static random access. The power consumption of the hidden body; in addition, in the read operation, by a read word line _) non-selection (n The voltage level at 〇nselected) is set lower than the ground voltage (for example, 0.5 volts) to effectively reduce read disturb and improve read reliability. As a result, the double-static static random access memory for improving the voltage level of the write word line during the write operation proposed by the present invention can effectively avoid the existence of the double 槔 sram with a single _ bit line. It is difficult to write logic phase, and it can also reduce leakage current and read interference and high reliability in standby mode. _ [Embodiment] According to the above main object, the present invention proposes a 埠 埠 埠 埠 埠 • • • • • • 写入 写入 写入 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 写入 写入 写入 写入 写入 写入 写入 写入 写入Incorporating Words • The line-voltage level of the double-sand static random access memory system includes a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column The memory cells and each of the memory cells each include a plurality of memory cells (1); a first bias circuit (2); and a second bias circuit (3). For the sake of convenience, in the case of the writer's operation shown in FIG. 6, the double-bit static memory access memory for increasing the voltage level of the character line for writing is only one memory cell (1), one word for writing. Yuan line (WWL), - strip read time line (RWL), - strip write bit 6 201030749 line CWBL), a read bit line (RBL), a first bias circuit (2) And a second bias circuit (3) is described as an embodiment. The memory cell (〗) is connected between a high voltage node (VH) and a low voltage node (VL), and includes a first inverter (by the first PMOS transistor P1 and the first nmos) a crystal M1, a second inverter (composed of a second PMOS transistor P2 and a second NMOS transistor M2), a write transistor, a select transistor (MWS), and a read select a crystal (MRS), and an inverting transistor (MINV) 'where the first inverter and the second inverter are connected in an alternating coupling, that is, an output of the first inverter (ie, a storage node) A) is connected to the input of the second inverter, and 输出 the output of the second inverter (ie, the inverting storage node B) is connected to the input of the first inverter, and the first inverter is The output (storage node A) is used to store the data of the SRAM cell (1) and the output of the second inverter (inverting storage node B) is used to store the inverted data of the SRam cell (1). The write select transistor (MWS) is connected between the storage node (A) and the write bit line (WBL), and the gate is connected to the write word line (WWL); Read One end of the selective transistor (MRS) is connected to the read bit line (rbl), the other end is connected to the inverting transistor (MINV), and the gate is connected to the read word line (RWL) And one end of the inverting transistor (MINV) is connected to the read selection transistor (mrs) φ, the other end is connected to the low voltage node (VL), and the gate is connected to the reverse phase storage Node (B). Referring again to FIG. 6, the first bias circuit (2) is composed of a third PM〇s transistor (P21), a fourth PMOS transistor (P22), and a third inverter (123). The source, the gate and the immersion of the third PMOS transistor (P21) are respectively connected to a high power supply voltage (HVDD), a first control signal (SAP) and the high voltage node (yjj) a source, a gate, and a gate of the fourth PMOS transistor (P22) are respectively connected to a low power supply voltage (LVDD), an output of the third inverter (123), and the high voltage node _), and the input of the third inverter (123) is used to receive the first control signal (sap). Furthermore, the second bias circuit (3) is composed of a third NMOS transistor (M31) and a fourth NMOS transistor 201030749 body (M32), which is the source of the third 譲08 transistor _ The pole 'open and the poleless are respectively connected to the ground voltage, a second control signal and the low voltage node (5), the source of the fourth NMOS transistor _) is connected to the ground voltage, and the closed pole and the 闭The poles are connected together and connected to the low voltage node (YL). In this value, it means that 'the county has prevented the Sense margin from decreasing, so the read word line (RWL) is used for non-selection (n〇nselected). Set to be lower than the ground voltage (eg, _〇.5 volts), that is, the read word line (roughly) is set to the high power supply voltage during the read operation, plus), and the read operation The period other than ❿ is set to a voltage level lower than the ground voltage (for example, -0.5 volts), and the write word line (WWL) is set to __ write power supply voltage for the writer operation ( The level of wvDD), the level of the write power supply voltage (WVdd) is set to at least - the high power supply (hvdd) plus the threshold voltage of the write select transistor (MWS) And set to ground voltage during periods other than the write operation. The working principle of the embodiment of the present invention is as follows: (I) active mode, the first control signal (SAP) is a logical low level, and The second control signal (SAN) is a logic high level, and the logic low level first control signal (SAp) can make the first bias circuit '(2): PMOS transistor (P21) 〇N (conducting ), then the high power supply can be discharged. (HVDD) is supplied to the 鬲 voltage node (VH); and the logic high level second control signal (SAN) can make the second bias circuit (3) The three nmos transistor (M31) is ON (on), so the low voltage node (VL) can be pulled down to ground. Next, how the present invention of Fig. 6 completes the write operation will be described in accordance with the four write states of the double random SRAM cell. (1) The storage node (A) originally stores the logical 〇, but now wants to write the logic 〇 ··
在寫入動作發生前(寫入用字元線WWL為接地電壓），第一 NMOS 8 201030749 電晶體(Ml)為ON(導通），該高電源供應電壓(HVdd)供應至該高電壓節 點(VH)。因為第一 電晶體(M1)為〇N，所以當寫入動作開始時， 寫入用字元線(WWL)由Low(接地電壓)轉High(寫入用電源供應電壓 (WVDD))。當寫入用字元線(WWL)的電壓大於第三丽〇8電晶體 - (即存取電晶體）的臨界電壓時，第三NMOS電晶體（M3)由OFF(載 止)轉變為ON(導通），此時因為寫入用位元線（WBL)是Low(接地電 壓）’所以會將儲存節點(A)放電，而完成邏輯〇的寫入動作，直到寫入 週期結束。 ❿ （二）儲存節點⑷原本儲存邏輯0，而現在欲寫入邏輯1 :Before the write operation occurs (the write word line WWL is the ground voltage), the first NMOS 8 201030749 transistor (M1) is ON (on), and the high power supply voltage (HVdd) is supplied to the high voltage node ( VH). Since the first transistor (M1) is 〇N, the write word line (WWL) is turned from Low (ground voltage) to High (write power supply voltage (WVDD)) when the write operation is started. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third MN8 transistor (ie, the access transistor), the third NMOS transistor (M3) is turned from OFF (loaded) to ON. (ON) At this time, since the write bit line (WBL) is Low (the ground voltage), the storage node (A) is discharged, and the write operation of the logic 完成 is completed until the end of the write cycle. ❿ (2) The storage node (4) originally stored logic 0, but now wants to write logic 1:
在寫入動作發生前(寫入用字元線WWL為接地電壓），第一 NMOS 電晶體(Ml)為ON (導通），該高電源供應電壓(HVdd)供應至該高電壓 節點(VH)。因為第一 電晶體(M1)為〇N，所以當寫入動作開始 時，寫入用字元線(WWL)由Low(接地電壓)轉High(寫入用電源供應電 壓(WVdd))。當寫入用字元線(WWL)的電壓大於第三nmos電晶體 (M3)的臨界電壓時，第三麵〇8電晶體（M3)由〇FF(截止)轉變為 ON(導通）’此時因為寫入用位元線（WBL)是扭辦高電源供應電壓 參 HVDD) ’所以會對儲存節點(A)快速充電；於儲存節點(a)充電中，由於 該該寫入用電源供應電壓(WVdd)之位準係設定至少為該高電源供應電 壓(HVDD)加上該寫入用選擇電晶體(MWS)之臨界電壓之位準，且該寫 • 人職驗應賴(WVDD)係鶴冑人料讀(WWL)，因此有助 於反相儲存節點(B)由High(電源電壓Vd_ Low(接地電壓)方向轉 變’ ¥反相儲存節點(B)之電壓位準下降至足以使第_ pM〇s電晶體(pl) 導通時’該第一 PMOS電晶體(pi)即由〇FF轉變為㈣，而完成邏輯 1的寫入動作。 (一)儲存節點(A)原本儲存邏輯卜而現在欲寫入邏輯【： 在寫入動作發生前(寫人肖？元線為接地電壓），第__ pM〇s 9 201030749 電晶體(P1)為ON(導if)，該高電雜應賴(j^)供應至該電壓節點 (VH)。當寫入用字元線(WWL)由L〇w(接地電壓)轉扭㈣寫入用電源供 應電壓(wvDD)) ’且該寫入用字元線(WWL)的電壓大於第三醒〇8電 b曰體（M3)的臨界電壓時，第三顧⑽電晶體（M3)自〇FF(截幻 轉變為ON(導通广此時因為寫入用位元線（WBL)是High(高電源供 . 應電壓，並且因為第一 PMOS電晶體(P1)仍為ON，所以儲存節 點(A)的電麼不會變動’而會平穩地保持在高電源供應電壓㈣如)之位 準’直到寫入週期結束。 Ο (四)儲存節點(A)原本儲存邏輯1，而現在欲寫入邏輯〇: 在寫入動作發生前(寫入用字元線WWL為接地電壓），第一 pM〇s 電晶體(P1)為ON(導通），該高電源供應電壓(HVdd)供應至電壓節點 (VH)。當寫入用字元線由L〇w(接地電壓)轉High(寫入用電源供 應電壓(WVDD))，且該寫入用字元線(WWL)的電壓大於第三電 b曰體（M3)的臨界電壓時，第三電晶體（M3)由〇FF(截止) 轉變為ON(導通），此時因為寫入用位元線（WBL)是Low (接地電 壓）且因為該寫入用電源供應電壓(胃〇〇)之位準係設定至少為該高電 φ 源供應電壓(HVDD)加上該寫入用選擇電晶體(MWS)之臨界電壓之位 準，所以會將儲存節點(A)快速放電而完成邏輯〇的寫入動作，直到寫 • 入週期結束。 緊接著依雙埠SRAM晶胞之二種儲存資料狀態說明第6圖之本發 明較佳實施例如何完成讀取動作。 (一）儲存節點(A)儲存邏輯〇 在讀取動作發生前(讀取用字元線(RWL)為低於接地電壓之電壓位 準’例如-0.5伏特），寫入用字元線(WWL)為接地電壓，第二_〇8電 晶體(M2)為0FF(截止），第二PMOS電晶體(P2)為ON (導通），反相儲 存節點(B)為High(高電源供應電壓HVDD)。當讀取動作開始時，讀取用 201030749 字元線(RWL)由低於接地電壓之電壓位準轉為High(高電源供應電壓 HVDD)，且當該讀取用字元線(RWL)的電壓大於該讀取用選擇電晶體 (MRS)之臨界電壓時，讀取用選擇電晶體(MRS)由OFF(截止)轉變為 ON(導通），此時由於反相儲存節點(B)為High(高電源供應電壓HVDD)， 反相電晶體(MINV)為ON(導通），因此，會在讀取用位元線(RBL)、讀 取用選擇電晶體(MRS)、反相電晶體(MINV)、及接地間形成電流路徑， 此電流路徑即會使讀取用位元線(RBL)之電壓位準降低，藉此即可感測 出儲存節點(A)係儲存邏輯〇之資料，並完成邏輯〇的讀取動作。Before the write operation occurs (the write word line WWL is the ground voltage), the first NMOS transistor (M1) is turned ON, and the high power supply voltage (HVdd) is supplied to the high voltage node (VH). . Since the first transistor (M1) is 〇N, the write word line (WWL) is turned from Low (ground voltage) to High (write power supply voltage (WVdd)) when the write operation is started. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third nmos transistor (M3), the third face 电8 transistor (M3) is changed from 〇FF (off) to ON (on)' Because the write bit line (WBL) is the high power supply voltage reference HVDD) 'so the storage node (A) is quickly charged; in the storage node (a) charging, because of the write power supply The voltage (WVdd) level is set to at least the high power supply voltage (HVDD) plus the threshold voltage of the write select transistor (MWS), and the write service should depend on (WVDD) It is a crane reading (WWL), so it helps the inverting storage node (B) to turn from High (power supply voltage Vd_ Low (ground voltage) direction' ¥ the voltage level of the inverting storage node (B) drops enough When the _pM〇s transistor (pl) is turned on, the first PMOS transistor (pi) is converted from 〇FF to (4), and the logic 1 write operation is completed. (1) The storage node (A) is originally stored. Logic Bu and now want to write logic [: Before the write action occurs (write the human? The line is the ground voltage), the first __ pM〇s 9 201030749 transistor (P1) is ON (guide if The high-voltage hybrid (j^) is supplied to the voltage node (VH). When the write word line (WWL) is twisted by L〇w (ground voltage) (4), the power supply voltage for writing (wvDD) )) 'and the voltage of the write word line (WWL) is greater than the threshold voltage of the third 〇8 electric b body (M3), the third (10) transistor (M3) is 〇FF (the interception transition) It is ON (conducting wide at this time because the write bit line (WBL) is High (high power supply voltage, and because the first PMOS transistor (P1) is still ON, so the storage node (A) is charged? Will not change 'and will be kept at a high power supply voltage (four) such as the level ' until the end of the write cycle. Ο (d) storage node (A) originally stored logic 1, and now want to write logic 〇: Before the write operation occurs (the write word line WWL is the ground voltage), the first pM〇s transistor (P1) is turned ON, and the high power supply voltage (HVdd) is supplied to the voltage node (VH). When the write word line is turned from L 〇 w (ground voltage) to High (write power supply voltage (WVDD)), and the voltage of the write word line (WWL) is greater than the third electric b body ( M3) of the threshold voltage, the third The crystal (M3) is changed from 〇FF (off) to ON (on), because the write bit line (WBL) is Low (ground voltage) and because of the write power supply voltage (stomach sputum) The level setting is at least the high-voltage φ source supply voltage (HVDD) plus the threshold voltage of the write select transistor (MWS), so the storage node (A) is quickly discharged to complete the logic 〇 Write the action until the end of the write-in period. The preferred embodiment of the present invention of Figure 6 illustrates how the read operation is accomplished, in accordance with the two stored data states of the dual SRAM cell. (1) The storage node (A) stores logic 写入 before the read operation occurs (the read word line (RWL) is a voltage level lower than the ground voltage 'eg -0.5 volts), and the write word line ( WWL) is the ground voltage, the second _8 transistor (M2) is 0FF (off), the second PMOS transistor (P2) is ON (on), and the inverting storage node (B) is High (high power supply voltage) HVDD). When the read operation starts, the read with the 201030749 word line (RWL) is turned from the voltage level lower than the ground voltage to High (high power supply voltage HVDD), and when the read word line (RWL) When the voltage is greater than the threshold voltage of the read select transistor (MRS), the read select transistor (MRS) transitions from OFF (turned) to ON (on), at which time the inverted storage node (B) is High. (High power supply voltage HVDD), Inverting transistor (MINV) is ON (conducting), so it will be used in the read bit line (RBL), the read select transistor (MRS), and the inverting transistor ( A current path is formed between the MINV) and the ground, and the current path lowers the voltage level of the read bit line (RBL), thereby sensing the storage node (A) storing the logical data. And complete the logic 〇 read action.
(二)儲存節點(A)儲存邏輯1 在讀取動作發生前(讀取用字元線(RWL)為低於接地電壓之電壓位 準(例如-0.5伏特)）’寫入用字元線(WWL)為接地電壓，第二νμμ電 晶體(M2)為ON (導通）’第二PMOS電晶體(P2)為OFF(載止），反相儲 存節點⑻為Low(接地電壓）。當讀取動作開始時，讀取用字元線(RWL) 由低於接地電壓之電壓位準轉為High(高電源供應電壓HVdd)，且當該 讀取用字元線(RWL)的電壓大於該讀取用選擇電晶體(MRS)之臨界電 壓時，讀取用選擇電晶體(MRS)由OFF(截止)轉變為0N(導通），此時由 於反相儲存節‘點(B)為Low(接地電壓），反相電晶體(娜^)為〇FF(截 止），因此，並不會在讀取用位元線(RBL)、讀取用選擇電晶體(mrs)、 反相電曰曰體(MINV)、及接地間形成電流路徑，結果，讀取用位元線(仙[) 之電壓位準能平穩地保持在High狀態，藉此即可❹賊存節點⑷ 係儲存邏輯1之資料’並完成邏輯1的讀取動作。 第6圖所7F之本發明第1實施例味寫人操作時之HSPICE暫態分 析模擬結果’如第7 _示’其係以_ 49模型且使用㈣ 微米CMOS製轉數加峨擬，由賴減果可註實，本發明所提出 操作啸高寫人时元線電壓鱗之雙轉誠機存取記憶 祕由寫入操作時提高寫人財元線電壓鱗，以有效避免習知 201030749 具單-位元線之雙埠靜態隨機存取記憶體晶胞存在寫入邏輯 1相當困 難之問題。 最後，說明本發明所提m操作時提高寫人用字元線電壓位準 之雙埠靜態隨機存取記憶體如何藉由降低非選擇(n〇nsdected)雙璋 • SRAM㉟胞之漏電流(leaking emTent)，而達成降低讀取干擾及提高讀取 可靠度之功效。於讀取操作期間，非選擇雙埠SRAM晶胞之讀取用選 擇電sb體(MRS)係呈OFF (截止)狀態，但觸取闕擇電晶體(歇8)截 止時仍會有漏電流存在，該漏電流路徑係形成於讀_低_^、 • 讀取用選擇電晶體(MRS)、反相電晶體(MINV)及接地之間，此漏電流 路徑即會產生讀取干擾並降低讀取可靠度。本發明將該反相電晶體 (MINV)之-端與該讀取闕擇電晶體她》相連接，另—端連接低電 壓節點(VL) ’而其閘極則連接至反相儲存節點(B)，其雖無法阻斷非選 擇SRAM晶胞之漏電流路徑’但仍可藉由將該讀取用字元線(rwl)設 定成低於接地電壓但高於產生閘極引發沒極沒漏(細論⑽以如 Leakage，GIDL)電流之電廢位準(例如_〇 5伏特），以降低非選擇雙埠 曰曰曰胞之漏電流。事實上電晶體截止時之漏電流(減哗 ^ 主要疋來自次臨界電流(subthreshold current)，於2005年3月8日之美 國專利第US6865119號案第3(A)及3(B)圖中，即揭露對於麵〇|§電晶 體而5，閘源極電壓為-0.1伏特時之次臨界電流約為閘源極電塵為〇伏 - 特時之次臨界電流的1%，因此，藉由將該讀取用字元線(rwl)設定 成低於接地電麼但高於產生閘極引發汲極茂漏仰叫電流之電麼位準 (例如-0.5伏特)，確實可大幅地降低非選擇雙埠8趣晶胞之漏電流， 並能謀求降低讀取干擾及提高讀取可靠度之功效。 (11)待機模式(standby mode) 此時該第一控制信號(SAP)為邏輯高位準，而該第二控制信號(SAN) 12 201030749 為邏輯低位準，該邏輯高位準之該第一控制信號(SAp)可使得第一偏壓 電路(2)中之第三PMOS電晶體(P21) OFF (截止），並使得第四PM〇s電 晶體(P22) ON(導通），於是可將該低電源供應電壓(LVdd)供應至該高電 壓節點(VH);而該邏輯低位準之該第二控制信號(SAN)可使得第二偏 壓電路(3)中之第三NMOS電晶體(M31) OFF (截止），由於此時第二偏 壓電路(3)中之第四nm〇s電晶體(M32)仍為〇N (導通），於是可將該低 電壓節點(VL)維持在該第四NMOS電晶體(M32)之臨界電壓的位準。 接下來說明本發明於待機模式(standby mode)時如何減少漏電流， 〇 請參考第8圖，第8圖表示了第6圖雙埠SRAM處於待機模式時所產 生之各次臨界漏電流(subthreshold leakage current)!!、I2、13 和 Μ，在 此值得注意的是，於待機模式時該低電壓節點(VL)係維持在高於接地 電壓之該第四NMOS電晶體(M32)之臨界電壓的位準，而該高電壓節點 (VH)係維持在低於該高電源供應電壓(HVdd)之該低電源供應電壓 (LVDD)之電壓位準，茲以雙埠SRAM晶胞中之儲存節點(a)為邏輯 Low(接地電壓)’而反相儲存節點(B)為邏輯High(高電源供應電壓^耶) 為例來說明各次臨界漏電流Η、I2、13和μ :(2) Storage node (A) storage logic 1 Before the read operation occurs (the read word line (RWL) is a voltage level lower than the ground voltage (for example, -0.5 volt)) 'write word line (WWL) is the ground voltage, the second νμμ transistor (M2) is ON (on), the second PMOS transistor (P2) is OFF (loading), and the inverting storage node (8) is Low (grounding voltage). When the read operation starts, the read word line (RWL) is turned from the voltage level lower than the ground voltage to High (high power supply voltage HVdd), and when the read word line (RWL) voltage When the threshold voltage of the read select transistor (MRS) is larger than the threshold voltage of the read select transistor (MRS), the read select transistor (MRS) is turned from OFF (off) to 0N (on), and at this time, the inverted node 'B (B) is Low (ground voltage), inverting transistor (Na) is 〇FF (off), therefore, it is not in the read bit line (RBL), read select transistor (mrs), inverting A current path is formed between the body (MINV) and the ground. As a result, the voltage level of the read bit line (sin [] can be smoothly maintained in the High state, thereby allowing the node to store the logic (4). 1 data 'and complete the logic 1 read operation. In the first embodiment of the present invention, the HSPICE transient analysis simulation result of the first embodiment of the present invention, as shown in the seventh embodiment, is based on the _49 model and uses (4) micron CMOS system rotation number plus赖减果 can be injected, the operation of the present invention is proposed to operate the whistling high-frequency line scales of the double-turned machine access memory secrets by writing to improve the writing of the financial line voltage scales, in order to effectively avoid the knowledge 201030749 It is quite difficult to write logic 1 in a double-squat static random access memory cell with a single-bit line. Finally, how to improve the leakage current of the non-selective (n〇nsdected) double-strip SRAM35 cell by reducing the double-bit static random access memory of the write word line voltage level when the m operation of the present invention is performed (leaking) emTent), which achieves the effect of reducing read interference and improving read reliability. During the read operation, the read select sb body (MRS) of the non-selected double-turn SRAM cell is in an OFF state, but there is still leakage current when the touch transistor (Stop 8) is turned off. The leakage current path is formed between the read_low_^, the read select transistor (MRS), the inverting transistor (MINV), and the ground, and the leakage current path causes read disturb and decreases. Read reliability. The present invention connects the end of the inverting transistor (MINV) to the read select transistor, the other end is connected to the low voltage node (VL)' and the gate is connected to the inverting storage node ( B), although it cannot block the leakage current path of the non-selected SRAM cell, but can still be set up by setting the read word line (rwl) lower than the ground voltage but higher than the gate. Leakage (details (10) such as Leakage, GIDL) current electrical waste level (eg _ 〇 5 volts) to reduce the leakage current of non-selected double cells. In fact, the leakage current at the turn-off of the transistor (minus 疋^ mainly depends on the subthreshold current, in the 3rd (A) and 3(B) drawings of US Pat. No. 6,865,119, March 8, 2005. That is, for the surface 〇|§ transistor and 5, the secondary critical current when the gate source voltage is -0.1 volt is about 1% of the secondary critical current of the gate source dust. By setting the read word line (rwl) lower than the ground current, but higher than the level of the gate that causes the gate to induce the drain leakage current (for example, -0.5 volts), it can be greatly reduced. Non-selecting the leakage current of the double-celled 8-cell cell, and can reduce the read interference and improve the read reliability. (11) Standby mode The first control signal (SAP) is logic high. The second control signal (SAN) 12 201030749 is a logic low level, and the first high level of the first control signal (SAp) can cause the third PMOS transistor in the first bias circuit (2) ( P21) OFF (off) and make the fourth PM〇s transistor (P22) ON (on), so the low power supply voltage (LVdd) can be supplied Up to the high voltage node (VH); and the logic low level of the second control signal (SAN) can cause the third NMOS transistor (M31) in the second bias circuit (3) to be OFF (cut) due to At this time, the fourth nm 〇s transistor (M32) in the second bias circuit (3) is still 〇N (on), so that the low voltage node (VL) can be maintained in the fourth NMOS transistor ( The level of the threshold voltage of M32) Next, how to reduce the leakage current when the present invention is in the standby mode, please refer to FIG. 8, and FIG. 8 shows the state in which the dual-SRAM is in the standby mode. The resulting threshold leakage currents!!, I2, 13 and Μ, it is worth noting that the low voltage node (VL) is maintained at a higher level than the ground voltage in the standby mode. The level of the threshold voltage of the NMOS transistor (M32), and the high voltage node (VH) is maintained at a voltage level lower than the low power supply voltage (LVDD) of the high power supply voltage (HVdd). The storage node in the double-turn SRAM cell (a) is logic Low (ground voltage)' and the inverting storage node (B) is logic high (high power supply) Pressure ^ yeah) to illustrate each critical leakage current Η, I2, 13 and μ:
φ (一）關於流經寫入用選擇電晶體(MWS)之漏電流II 請參考第5圖之先前技藝與第8圖之本發明實施例，由於待機模式 ' 時寫入用字元線(WWL)係為接地電壓，因此於待機模式初期流經寫入 . 用選擇電晶體(MWS)之漏電流II與第5圖之先前技藝（先前技藝中之 NMOS電阳體M3即相當於本發明實施例中之該寫人用選擇電晶體 MWS)具有相同的漏電流（待機模式初期儲存節點&為接地電壓）， 之後儲存節點(A)即會由接地電壓朝高於接地電壓之該第四電 晶體⑽2)之臨界電壓的位準增加，於此期間由於本發明實施例之該寫 入用選擇電晶體(MWS)之閘源極電壓為負值’而先前技藝中之丽⑽ 電晶體_的閘源極電壓仍維持〇伏特，根據閘極引發汲極&漏((^ 13 201030749φ (1) Regarding the leakage current II flowing through the write selection transistor (MWS), please refer to the prior art of FIG. 5 and the embodiment of the invention of FIG. 8 for writing the word line due to the standby mode ' WWL) is the ground voltage, so it is written in the initial stage of the standby mode. The leakage current II of the selected transistor (MWS) and the prior art of the fifth figure (the prior art NMOS electrical body M3 is equivalent to the present invention) In the embodiment, the writer selects the transistor MWS) to have the same leakage current (the standby mode initial storage node & is the ground voltage), and then the storage node (A) is caused by the ground voltage being higher than the ground voltage. The level of the threshold voltage of the four transistors (10) 2) increases, during which the gate voltage of the write select transistor (MWS) is negative as in the embodiment of the present invention, and the prior art (10) transistor The gate voltage of _ is still maintained at volts, and the gate is induced by the gate &drain; (^ 13 201030749
Induced Drain Leakage , GIDL)效應或2005年3月8日之美國專利第 US6865119號案第3㈧及3⑻圖可知，流經該寫人_擇電晶體(mws) 之漏電流II係遠小於第5圖之先前技藝者。 (二）關於流經第一 PMOS電晶體(P1)之漏電流12 • 由於待機模式時該高電壓節點(VH)係具有該低電源供應電壓 (LVDD)之電壓位準，該低電源供應電壓(lVdd)之電壓位準係小於該高電 源供應電壓(HVDD)，又因為該反相儲存節點(B)於待機模式初期係為高 電源供應電壓(hvdd)之電壓位準，因此根據閘極引發汲極洩漏（gidl ) Φ 效應及汲極引發能障下跌（〇以11111(11^(16〇11知]^代1111§，〇181〇效 應可知，流經第一 PMOS電晶體(P1)之漏電流12係遠小於第5圖之先 前技藝者（先前技藝中之PMOS電晶體P1即相當於本發明實施例中之 該第一 PMOS電晶體P1 )，之後儲存節點(b)即會由該高電源供應電壓 (HVDD)之位準朝該低電源供應電壓(LVdd)之位準減少，於此期間由於 本發明實施例之該第一 PMOS電晶體(P1)之閘源極電壓仍維持正值且 源極電壓仍維持該低電源供應電壓(LVdd)之電壓位準，而先前技藝中之 該PMOS電晶體(P1)的閘源極電壓則維持〇伏特且源極電壓仍維持該高 ❿ 電源供應電壓(HVdd)之電壓位準’因此根據閘極引發j；及極汽漏（gidl) 效應及及極引發能障下跌（DIBL)效應可知，流經該第一 PMOS電晶 • 體(P1)之漏電流12仍小於第5圖之先前技藝者。 . (三）關於流經第二NMOS電晶體(M2)之漏電流13 由於待機模式時該低電壓節點(VL)係維持在該第四NMOS電晶體 (M32)之臨界電壓的位準，又因為該儲存節點(A)於待機模式初期係為接 地電壓，因此根據閘極引發汲極洩漏（GIDL)效應或2〇〇5年3月8 曰之美國專利第US6865119號案第3(A)及3(B)圖可知，流經該第二 NMOS電曰曰體(M2)之漏電流13係遠小於第5圖之先前技藝者（先前技 藝中之NMOS電晶體M2即相當於本發明實施例中之該第二電 14 201030749 晶體M2)，之後儲存節點(a)即會由接地電壓朝高於接地電壓之該第 四NMOS電晶體(M32)之臨界電壓的位準增加，於此期間由於本發明實 施例之該第一NMOS電晶體(M2)之閘源極電壓仍為負值，而先前技藝 中之該NMOS電晶體(M2)的閘源極電壓則維持〇伏特，因此流經該第 . 二_仍電晶體(M2)之漏電流13仍小於第5圖之先前技藝者。 (四）關於流經讀取用選擇電晶體(MRS)之漏電流14 由於待機模式時該讀取用字元線(RWL)係設定成低於接地電壓但 高於產生閘極引發汲極洩漏(GIDL)電流之電壓位準(例如_〇.5伏特），又 〇 因為該反相電晶體(M!NV)導通，於是可將該讀取用選擇電晶體(MRS) 之源極電壓固定在該第四NMOS電晶體(M32)之臨界電壓的位準，因此 根據閘極引發沒極洩漏（GIDL)效應或2005年3月8曰之美國專利第 US6865119號案第3(A)及3(B)圖可知，可大幅減少流經該讀取用選擇 電晶體(MRS)之漏電流14。反觀，第5圖先前技藝中之nm〇s電晶體 (M6)之讀取用字元線(rwl)係為接地電壓，且該_〇8電晶體(M6)之 汲極係為該高電源供應電壓(HVDD)之電壓位準，根據汲極引發能障下 跌（DIBL)效應可知，該較高電位之電晶體(M6)的汲極電壓會 φ 增加流經該NMOS電晶體(M6)之漏電流。 Ιί由以上勿析可知，本發明於待機模式(standby m〇de)時確實可有 • 效減少漏電流。 【發明功效】 本發明所提出之寫入操作時提高寫入用字元線電壓位準之雙埠靜態隨 機存取記憶體，具有如下功效： ⑴降低讀取干擾及提高讀取可靠度：由於本發明所提出之寫入操作時提高 寫入用字元線電壓位準之雙埠靜態隨機存取記憶體於讀取操作時，係 將讀取用子元線(RWL)於非選擇(n〇nselected)時之電壓位準設定成低 於接地電壓但高於產生閘極引發汲極洩漏((311)1^電流之電壓位準(例如 15 201030749 -0.5伏特）’結果’可藉由大幅地降低非選擇(nonseiectecj)雙琿晶 胞之漏電流，而有效達成降低讀取干擾及提高讀取可靠度等功效； (2)低次臨界漏電流：由於本發明所提出之寫入操作時提高寫入用字元線電 壓位準之雙谭靜態隨機存取記憶體於待機模式時，高電壓節點(VH)係 為低電源供應電壓(lvdd)之電壓位準，而低電壓節點(VL)係固定在該 第四NMOS電晶體(M32)之臨界電壓的位準，且讀取用字元線(RWL)^ 電塵位準翻定在低於接地電壓但高於產生難5丨發汲極如耶狐) 電抓之電麼位準(例如·0.5伏特）’因此本發明所提出之寫入操作時提高Induced Drain Leakage (GIDL) effect or the figures 3(8) and 3(8) of US Pat. No. 6,865,119, issued on March 8, 2005, the leakage current II flowing through the write transistor (mws) is much smaller than that of the fifth figure. Former prior art. (2) Leakage current 12 flowing through the first PMOS transistor (P1) • The high voltage node (VH) has a voltage level of the low power supply voltage (LVDD) due to the standby mode, the low power supply voltage The voltage level of (lVdd) is less than the high power supply voltage (HVDD), and because the inverting storage node (B) is at the voltage level of the high power supply voltage (hvdd) at the beginning of the standby mode, according to the gate Initiated bungee leakage (gidl) Φ effect and bungee induced energy barrier drop (〇11111(11^(16〇11知]^代1111§,〇181〇 effect is known to flow through the first PMOS transistor (P1) The leakage current 12 is much smaller than the prior art of FIG. 5 (the PMOS transistor P1 in the prior art is equivalent to the first PMOS transistor P1 in the embodiment of the present invention), and then the storage node (b) is The level of the high power supply voltage (HVDD) decreases toward the low power supply voltage (LVdd). During this period, the gate and source voltages of the first PMOS transistor (P1) are maintained in the embodiment of the present invention. Positive value and the source voltage still maintains the voltage level of the low power supply voltage (LVdd), while the previous technique The gate-source voltage of the PMOS transistor (P1) is maintained at 〇V and the source voltage is still maintained at the voltage level of the ❿ power supply voltage (HVdd), thus the gate is induced according to the gate; The gidl) effect and the extreme induced energy loss (DIBL) effect show that the leakage current 12 flowing through the first PMOS transistor (P1) is still smaller than that of the prior art of Figure 5. (3) Leakage current 13 of the second NMOS transistor (M2), the low voltage node (VL) is maintained at the level of the threshold voltage of the fourth NMOS transistor (M32) due to the standby mode, and because the storage node (A) It is the grounding voltage at the beginning of the standby mode, so it can be seen from the gate-induced drain leakage (GIDL) effect or the third (A) and 3 (B) drawings of US Pat. No. 6,865,119, March 3, 2005. The leakage current 13 flowing through the second NMOS electrode body (M2) is much smaller than that of the prior art of FIG. 5 (the NMOS transistor M2 in the prior art is equivalent to the second battery in the embodiment of the present invention. 14 201030749 Crystal M2), after which the storage node (a) will be grounded by the fourth NMOS transistor (M32) above the ground voltage The threshold voltage is increased. During this period, the gate voltage of the first NMOS transistor (M2) is still a negative value according to the embodiment of the present invention, and the gate source of the NMOS transistor (M2) in the prior art. The pole voltage is maintained at volts, so the leakage current 13 flowing through the second transistor (M2) is still smaller than that of the prior art of Fig. 5. (4) About the selective transistor (MRS) flowing through the reading Leakage current 14 The read word line (RWL) is set to be lower than the ground voltage but higher than the voltage level at which the gate-induced drain leakage (GIDL) current is generated (for example, _〇.5 volts). And, because the inverting transistor (M!NV) is turned on, the source voltage of the read select transistor (MRS) can be fixed at the threshold voltage of the fourth NMOS transistor (M32). Exactly, according to the gate-induced immersion leakage (GIDL) effect or the figures 3(A) and 3(B) of US Pat. No. 6,865, 119, March 8, 2005, the flow through the reading can be greatly reduced. The leakage current 14 of the transistor (MRS) is selected. In contrast, the read word line (rwl) of the nm〇s transistor (M6) in the prior art of FIG. 5 is the ground voltage, and the drain of the _8 transistor (M6) is the high power source. The voltage level of the supply voltage (HVDD), according to the diode-induced energy barrier falling (DIBL) effect, the drain voltage of the higher potential transistor (M6) increases φ through the NMOS transistor (M6). Leakage current. Ιί From the above analysis, the present invention can effectively reduce the leakage current in the standby mode (standby m〇de). [Effect of the Invention] The dual-static static random access memory for improving the voltage level of the write word line during the write operation of the present invention has the following effects: (1) reducing read disturb and improving read reliability: In the write operation of the present invention, the double-click static random access memory for increasing the voltage level of the write word line is used for the read operation, and the read sub-line (RWL) is used for non-selection (n 〇nselected) The voltage level is set lower than the ground voltage but higher than the gate-induced drain leakage ((311)1^ current voltage level (eg 15 201030749 -0.5 volts) 'results' can be To reduce the leakage current of the non-selective (nonseiectecj) double-turn cell, and effectively achieve the effects of reducing read interference and improving read reliability; (2) low-order critical leakage current: due to the write operation proposed by the present invention When the double-bit static random access memory of the write word line voltage level is raised in the standby mode, the high voltage node (VH) is the voltage level of the low power supply voltage (lvdd), and the low voltage node (VL) Is fixed in the fourth NMOS transistor (M32) The level of the boundary voltage, and the reading word line (RWL) ^ electric dust level is set lower than the grounding voltage but higher than the difficulty of generating 5 汲 如 如 ) ) ) ) ) ) ) ) For example, 0.5 volts) 'Therefore, the write operation proposed by the present invention is improved.
^用字元線電_準之雙埠靜騎機存取記憶體亦具備低次 電流之功效； 術之姆凡熟悉本技 :::::此，所有 _二:=:= 201030749 f圖式簡單說明】 第i圖係顯示習知6T靜態隨機存取記憶體晶胞之電路示专圖 第2圖係顯示習知6Τ靜態隨機存取記憶體晶胞之寫 ”、 動作時序圖· 第3圖係顯示習知5Τ靜態隨機存取記憶體晶胞之電路示意圖.， 第4圖係顯示習知5Τ靜態隨機存取記憶體晶胞之寫入動作時序圖 第5圖係顯示習知雙埠靜態隨機存取記憶體晶胞之電路示意圖.， 第6圖係顯示本發騎提出之寫人操作時提絲人用字元=坂 參 之雙埠靜態隨機存取記憶體之電路示意圖； 、模位準 第7圖係顯示本發騎提出之寫人操作時提高寫人財元線電堡 之雙埠靜態隨機存取記憶體之寫入動作時序圖； 第8圖係顯示第6 _人操作時提高寫人用字元線電壓位準之雙璋靜 態隨機存取記憶體於待機模式時所產生之各次臨界漏電流’· 【主要元件符號說明】 Ρ1 第一 PMOS電晶體 Ml 第一 NMOS電晶體 M3 存取電晶體 MWS 寫入用選擇電晶體 MINV 反相電晶體 WWL 寫入用字元線 BL 位元線 WBL 寫入用位元線 A 儲存節點 HV〇d 高電源供應電壓 P2 第二PMOS電晶體 M2 第二NMOS電晶體 M4 存取電晶體 MRS 讀取用選擇電晶體 WL 字元線 RWL 讀取用字元線 BLB 互補位元線 RBL 讀取用位元線 B 反相儲存節點 LVdd 低電源供應電壓 17 201030749 1 SRAM晶胞 2 第一偏壓電路 3 第二偏壓電路 SAP 第一控制信號 SAN 第二控制信號 P21 第三PMOS電晶體 P22 第四PMOS電晶體 123 第三反相器 M31 第三NMOS電晶體 M32 第四NMOS電晶體 VH 高電壓節點 YL 低電壓節點 Vdd 電源電壓^Using the word line electricity _ quasi-double 埠 static rider access memory also has the effect of low-level current; the skill of the martial arts familiar with this technology::::: this, all _ two:=:= 201030749 f Brief Description: The i-th diagram shows the circuit diagram of the conventional 6T static random access memory cell. The second figure shows the write of the conventional 6Τ static random access memory cell. 3 shows a schematic diagram of a conventional 5 Τ SRAM cell. Figure 4 shows a conventional 5 Τ SRAM cell write action timing diagram. Figure 5 shows a conventional double电路Static Schematic diagram of a static random access memory cell. Figure 6 is a schematic diagram showing the circuit of a pair of static random access memory for a wire-receiving character=坂参; The model position of the model position shows that the write operation timing of the double-static static random access memory of the writer's financial line is improved when the writer's operation is performed; the eighth picture shows the sixth _ When the user operates to improve the voltage level of the writing character line, the static random access memory is in the standby mode. Each of the generated critical leakage currents'· [Description of main component symbols] Ρ1 First PMOS transistor M1 First NMOS transistor M3 Access transistor MWS Write selection transistor MINV Inverting transistor WWL Write word Element line BL bit line WBL Write bit line A Storage node HV〇d High power supply voltage P2 Second PMOS transistor M2 Second NMOS transistor M4 Access transistor MRS Read select transistor WL character Line RWL Read word line BLB Complementary bit line RBL Read bit line B Inverting storage node LVdd Low power supply voltage 17 201030749 1 SRAM cell 2 First bias circuit 3 Second bias circuit SAP first control signal SAN second control signal P21 third PMOS transistor P22 fourth PMOS transistor 123 third inverter M31 third NMOS transistor M32 fourth NMOS transistor VH high voltage node YL low voltage node Vdd power supply Voltage