TWI441179B - Dual port sram having a discharging path - Google Patents

Description

Double-turn SRAM with discharge path

The present invention relates to a static random access memory (SRAM) for reducing a power supply voltage during a write operation, and more particularly to a method for reducing leakage current and solving a single method. The double-bit SRAM of the bit line is written into the logic 1 difficult double-static SRAM, and can have high reliability and high stability write operation even at high memory capacity and/or high-speed operation.

Random access memory plays an indispensable role in the computer industry, mainly including dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory (DRAM) has the advantages of small area and low price, but it must be refreshed from time to time to prevent data from being lost due to leakage current, resulting in high speed and power consumption. Missing. Conversely, the operation of the static random access memory (SRAM) is simple and does not require an update operation, so it has the advantages of high speed and low power consumption.

The semiconductor memory devices currently used in mobile electronic devices represented by mobile phones are mainly SRAM. This is due to the small standby current of the SRAM, which is suitable for mobile phones with continuous talk time and continuous standby time.

A static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows of memory cells (a). The plurality of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines, each word line corresponding to a column of a plurality of memory cells; and a plurality of bit line pairs, each bit line pair corresponding to one of the plurality of rows of memory cells, and each bit line pair is A meta-line and a complementary bit line are formed.

Figure 1 is a schematic diagram of a 6T static random access memory (SRAM) cell. The PMOS transistors P1 and P2 are called load transistors, and the NMOS transistors M1 and M2 are called drivers. Driving transistors, NMOS transistors M3 and M4 are called access transistors, WL is a word line, and BL and BLB are bit lines and complementary bits, respectively. A complementary bit line, since the SRAM cell requires six transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, the cell ratio) is usually set at 2 to 3. There is a lack of high accumulation and high price. The 6T SRAM cell shown in Figure 1 shows the HSPICE transient analysis results during the write operation. As shown in Figure 2, it is modeled using the level 49 model using TSMC 0.35 micron CMOS process parameters. simulation.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line. Compared with the 6T SRAM cell of Figure 1, the 5T static random access memory. The bulk cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. In the case of the channel width to length ratio of M2 and M3, there is a problem that writing logic 1 is quite difficult. Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is modeled using the level 49 model using TSMC 0.35 micron CMOS process parameters. Simulation, from the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.

Next, we discuss the static random access memory (SRAM) and dual-layer architecture. The 6T static random access memory (SRAM) cell in Figure 1 is a static random access memory (SRAM) crystal. One example of a cell, which uses two bit lines BL and BLB for reading and writing, that is, both reading and writing are achieved through the same pair of bit lines, so that only reading or reading can be performed at the same time. The action of writing, therefore, when designing a dual-static SRAM with simultaneous read and write capabilities, it is necessary to add two access transistors and another pair of bit lines (please refer to Figure 5). a circuit in which WBL and WBLB are write bit line pairs, RBL and RBLB are read bit line pairs, WWL is a write word line, and RWL is a read word line), which makes the memory crystal The area of the cell is greatly increased. If we can simplify the structure of the memory cell, so that one bit line is responsible for the reading action, and the other bit line is responsible for the writing action, then the double-click static random access memory is designed. When you are in the body, the memory cell does not need to add two transistors and another pair of bit lines. The area of the memory cell is much reduced. The reason why the conventional double-squeezing static random access memory cell does not adopt this method is because the problem of writing logic 1 cannot be achieved as described above.

In view of this, the main object of the present invention is to provide a double-turn SRAM with a discharge path, which can reduce the power supply voltage by a write operation, thereby effectively avoiding the conventional double-static static random access memory having a single bit line. It is quite difficult for the unit cell to write logic 1.

A secondary object of the present invention is to provide a double-turn SRAM with a discharge path, which can effectively reduce leakage current in standby mode.

Still another object of the present invention is to provide a double-turn SRAM having a discharge path capable of high-reliability and high-stability write operation even at high memory capacity and/or high-speed operation.

The invention provides a double-turn SRAM with a discharge path, which comprises a memory array composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each a row of memory cells each including a plurality of memory cells (1); a plurality of first bias circuits (2), each column of memory cells is provided with a first bias circuit (2), the first a bias circuit (2) for receiving a standby mode control signal (S) and a write word line (WWL), the first bias circuit (2) only for the standby mode control signal ( S) supplying a low power supply voltage (LV _DD ) to the logic high level representing the standby mode or the write word line (WWL) representing the logic high level of the selected write state a high voltage node (VH), in addition to supplying a high power supply voltage (HV _DD ) to the high voltage node (VH); a second bias circuit (3), the second bias current The circuit (3) is for receiving the inverted signal of the standby mode control signal (S) (for convenience of explanation, the reverse direction of the standby mode control signal (S) is hereinafter referred to as The number is an inverted standby mode control signal /S), and when the inverted standby mode control signal (/S) is a logic high level representing the active mode, the ground voltage is supplied to the low voltage node (VL), and The inverted standby mode control signal (/S) is a logic low level on behalf of the standby mode, and a voltage higher than the ground voltage is supplied to the low voltage node (VL); and a plurality of discharge paths (4), each A column of memory cells is provided with a discharge path (4). When the write word line (WWL) is a logic high level representing the selected write state, the discharge path provided by the corresponding discharge path (4) can be provided. To discharge the charge stored at the high voltage node (VH) for a predetermined time, and when the standby mode control signal (S) is at a logic high level representing the standby mode, provided by the corresponding discharge path (4) The discharge path is to discharge the charge stored at the high voltage node (VH) for another predetermined time.

According to the above main object, the present invention provides a dual-SRAM SRAM having a discharge path, the double-SRAM SRAM having a discharge path comprising a memory array, the memory array being composed of a plurality of columns of memory cells and a plurality of rows of memory Formed by a unit cell, each column of memory cells and each row of memory cells each include a plurality of memory cells (1); a plurality of first bias circuits (2), each column of memory cells A first bias circuit (2); a second bias circuit (3); and a plurality of discharge paths (4) are provided, and each column of memory cells is provided with a discharge path (4).

For convenience of explanation, the double-sided SRAM for reducing the power supply voltage during the write operation shown in FIG. 6 has only one memory cell (1), one write word line (WWL), and one read word. a source line (RWL), a write bit line (WBL), a read bit line (RBL), a first bias circuit (2), a second bias circuit (3), and A discharge path (4) is illustrated as a preferred embodiment. The memory cell (1) includes a first inverter (composed of the first PMOS transistor P1 and the first NMOS transistor M1) and a second inverter (by the second PMOS transistor P2 and a second NMOS transistor M2), a write select transistor (MWS), a read select transistor (MRS), and an inverting transistor (MINV), wherein the first inverter And the second inverter is in an alternating coupling connection, that is, the output of the first inverter (ie, node A) is connected to the input of the second inverter, and the output of the second inverter is Node B) is connected to the input of the first inverter, and the output of the first inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) Then, the inverted data of the SRAM cell is stored, and the write select transistor (MWS) is connected between the storage node (A) and the write bit line (WBL), and the gate is connected to Write word line (WWL); a read select transistor (MRS), one end of which is connected to the read bit line (RBL), the other end is connected to the inverting transistor (MINV), and the gate Extremely connected to the reading character (RWL); and one end of the inverter transistor (MINV) of the readout selection transistor (MRS) is connected, and the other end connected to ground, while the gate is connected to the inverting storage node (B).

Referring to FIG. 6 again, the first bias circuit (2) is composed of a third PMOS transistor (P21), a fourth PMOS transistor (P22), a third inverter (I23), and a third PMOS transistor (P21). a fifth PMOS transistor (P24), a sixth PMOS transistor (P25), and a fourth third inverter (I26), the source, gate and drain of the third PMOS transistor (P21) Connected to the 汲 terminal of the fifth PMOS transistor (P24), the write word line (WWL) and a high voltage node (VH), respectively; the source and gate of the fourth PMOS transistor (P22) Connected to the low power supply voltage (LV _DD ), the output of the third inverter (I23) and the high voltage node (VH), and the input terminal of the third inverter (I23) And receiving the write word line (WWL); the source, the gate and the drain of the fifth PMOS transistor (P24) are respectively connected to a high power supply voltage (HV _DD ), a standby mode a control signal (S) and a source terminal of the third PMOS transistor (P21); a source, a gate and a drain of the sixth PMOS transistor (P25) are respectively connected to the low power supply voltage (LV _DD ) The output of the fourth inverter (I26) and the high voltage node (V) H), the input end of the fourth inverter (I23) is configured to receive the standby mode control signal (S) and output an inverted standby mode control signal (/S). Furthermore, the second bias circuit (3) is composed of a third NMOS transistor (M31) and a fourth NMOS transistor (M32), the source of the third NMOS transistor (M31), The gate and the drain are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and a low voltage node (VL), and the source of the fourth NMOS transistor (M32) is connected to a ground voltage. The gate is connected to the drain and connected to the low voltage node (VL).

Referring to FIG. 7, the discharge path (4) is composed of a fifth NMOS transistor (M41), a sixth NMOS transistor (M42), a seventh NMOS transistor (M43), and an eighth NMOS transistor. (M44), a seventh PMOS transistor (P45) and a delay circuit (D46), the source, the gate and the drain of the fifth NMOS transistor (M41) are respectively connected to the seventh PMOS a drain of the crystal (P45), the write word line (WWL) and the high voltage node (VH); a source, a gate and a drain of the sixth NMOS transistor (M42) are respectively connected to the a drain of the seventh PMOS transistor (P45), the standby mode control signal (S) and the high voltage node (VH); the source, the gate and the drain of the seventh NMOS transistor (M43) are respectively connected To the ground terminal, the output end of the delay circuit (D46) and the source of the fifth NMOS transistor (M41) and the source of the sixth NMOS transistor (M42); the eighth NMOS transistor (M44) The source, the gate and the drain are respectively connected to a ground voltage, the write word line (WWL) and an input end of the delay circuit (D46); a source and a gate of the seventh PMOS transistor (P45) a pole and a drain are respectively connected to the first bias current The output of the fourth inverter (I26) in the circuit (2) (ie, the inverted standby mode control signal /S), the write word line (WWL), and the input of the delay circuit (D46) end.

Wherein, when the write word line (WWL) is a logic high level representing the selected write state, the discharge path provided by the corresponding discharge path (4) can be stored at the high voltage node (VH). The charge is discharged for a predetermined time, which is equal to the delay time provided by the delay circuit (D46) plus the propagation delay time of the logic low level of the eighth NMOS transistor (M44); When the standby mode control signal (S) is a logic high level representing the standby mode, the discharge path provided by the corresponding discharge path (4) is used to discharge the charge stored at the high voltage node (VH). a predetermined time, the other predetermined time is equal to the delay time provided by the delay circuit (D46) plus the transfer delay time of the seventh PMOS transistor (P45) plus the first bias circuit (2) The fall propagation delay time of the fourth inverter (I26), it is worth noting that the delay circuit (D46) is formed by a series of even inverters, so By changing the number of the even number of inverters The delay time provided by the delay circuit (D46) is such that the write word line (WWL) is a logic high level representing the selected write state or the standby mode control signal (S) is a logic high level representing the standby mode. On time, the discharge path provided by the discharge path (4) can be used to easily discharge the voltage level of the high voltage node (VH) from the level of the high power supply voltage (HV _DD ) to slightly lower than The low power supply voltage (LV _DD ) is leveled by the first bias circuit (2) to accurately fix the voltage level of the high voltage node (VH) to the low power supply voltage (LV) _DD ) The voltage level provided.

It is worth noting here that in order to prevent the sense margin from decreasing, the voltage level of the read word line (RWL) at the nonselected level is set lower than the ground voltage. (eg, -0.5 volts), that is, the read word line (RWL) is set to the high power supply voltage (HV _DD ) during the read operation and low during the read operation. At the voltage level of the ground voltage (for example, -0.5 volts), the write word line (WWL) is set to the high power supply voltage (HV _DD ) during the write operation, and is outside the write operation. The period is set to the ground voltage.

The working principle of the preferred embodiment of the present invention in FIG. 6 is as follows:

(I) active mode

At this time, the standby mode control signal (S) is a logic low level, and the logic low level standby mode control signal (S) is reversed by the fourth inverter (I26) in the first bias circuit (2) The phase output logic high level of the inverted standby mode control signal (/S), the logic high level inverted standby mode control signal (/S) can make the third NMOS of the second bias circuit (3) The transistor (M31) is ON, so the low voltage node (VL) can be pulled down to ground.

The logic low level standby mode control signal (S) can cause the fifth PMOS transistor (P24) in the first bias circuit (2) to be ON (on), and at this time, the write word line (WWL) is a logic low level on behalf of the unselected write state, then the third PMOS transistor (P21) in the first bias circuit (2) is turned ON (on), so that the high power supply voltage can be HVDD) is supplied to the high voltage node (VH); conversely, if the write word line (WWL) is a logic high level representing the selected write state at this time, the first bias circuit (2) is enabled The third PMOS transistor (P21) is turned OFF, and the fourth PMOS transistor (P22) is turned ON, so that the low power supply voltage (LV _DD ) can be supplied to the high voltage node (VH) ).

Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed in accordance with the four write states of the dual SRAM cell.

(1) Node A originally stores a logic 0, but now wants to write a logic 0:

Before the write operation occurs (the write word line WWL is the ground voltage), the first NMOS transistor (M1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the high voltage node (VH). ). Since the first NMOS transistor (M1) is ON, the write word line (WWL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ) when the write operation starts. When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M3) (ie, the access transistor), the third NMOS transistor (M3) is turned from OFF (OFF) to ON ( Turning on, at this time, because the write bit line (WBL) is the ground voltage, node A is discharged, and the logic 0 write operation is completed until the end of the write cycle. It is worth noting here that the high voltage node (VH) has the low power supply voltage (LV _DD ) level at the beginning of writing, and has the high power supply voltage (HV _{DD )} after the end of the write cycle. ) The standard.

(2) Node A originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is the ground voltage), the first NMOS transistor (M1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the high voltage node (VH). ). Since the first NMOS transistor (M1) is ON, when the write operation starts, the write word line (WWL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ), and the voltage of the node A It will rise with the voltage of the word line (WL).

When the voltage of the write word line (WWL) is greater than the threshold voltage of the third NMOS transistor (M3) and the threshold voltage of the fifth NMOS transistor (M41) in the discharge path (4), The third NMOS transistor (M3) is turned from OFF to ON, because the write bit line (WBL) is High (high power supply voltage HV _DD ), and because the first NMOS is The crystal M1 is still ON and the node B is still in an initial discharge state where the voltage level is close to the voltage level of the high power supply voltage (HV _DD ), so the first PMOS transistor P1 is still OFF (cutoff), and the node A fast charge will be to the third NMOS transistor (M3) is turned the equivalent resistance (R _M3) and the first NMOS transistor (M1) is turned the equivalent resistance (R _M1) presented by the dividing voltage level The voltage division level is equal to R _M1 /(R _M3 +R _M1 ) multiplied by the voltage level provided by the high power supply voltage (HV _DD ), since the third NMOS transistor (M3) operates at saturation region (saturation region) and the first NMOS transistor (M1) operates in a linear region based (triode region), thus guiding the third NMOS transistor (M3) through the equivalent resistance (R _M3) will Greater than the first NMOS transistor (M1) is turned the equivalent resistance (R _M1), then node A will show the low level of the divided voltage, which is equal to the conventional value of about 4. FIG 5T of static random-access memory The unit cell was simulated at 0.52 mV during the period from 25 nanoseconds to 30 nanoseconds.

Then, the node B is gradually discharged to a lower voltage level, and the lower voltage level of the node B causes the on-resistance equivalent (R _M1 ) of the first NMOS transistor ( _M1 ) to exhibit a higher resistance value. The higher resistance value of an NMOS transistor (M1) will obtain a higher voltage level at node A, and the higher voltage level of the node A will pass through the second inverter (by the second PMOS transistor P2). And the second NMOS transistor M2 is configured to make the node B exhibit a lower voltage level, and the lower voltage level of the node B is again via the first inverter (by the first PMOS transistor P1 and the first The NMOS transistor M1 is configured to make the node A obtain a higher voltage level, and according to the cycle, the node A can be charged to a high power supply voltage (HV _DD ) to deduct the criticality of the third NMOS transistor (M3). The voltage or the lower of the power supply voltage (LV _DD ) is greater than the write operation of logic 1. It is worth noting here that since the voltage node (VH) has the low power supply voltage (LV _DD ) level at the beginning of writing, the high power supply voltage (HV _{DD ) is present} after the end of the writing period. The level is such that after the end of the write cycle, the node A is charged to the level of the high power supply voltage (HV _DD ).

(3) Node A originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor (P1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the voltage node (VH). . When the write word line (WWL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ), and the voltage of the write word line (WWL) is greater than that of the third NMOS transistor (M3) At the threshold voltage, the third NMOS transistor (M3) is turned from OFF (turned) to ON (on); after the low power supply voltage (LV _DD ) is supplied to the high power supply node (V _DD ), at this time, because of writing The bit line (WBL) is High (high power supply voltage HV _DD ), and since the first PMOS transistor (P1) is still ON, the voltage of the node A is lowered to a high power supply voltage (HV _DD ) minus the first The larger of the threshold voltage of the three NMOS transistor (M3) or the low power supply voltage (LV _DD ), the high power supply voltage (HV _DD ) is supplied to the voltage node (VH) until the end of the write cycle.

(4) Node A originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the write word line WWL is the ground voltage), the first PMOS transistor (P1) is turned ON, and the high power supply voltage (HV _DD ) is supplied to the voltage node (VH). When the write word line (WWL) is turned from Low (ground voltage) to High (high power supply voltage HV _DD ), and the voltage of the write word line (WWL) is greater than that of the third NMOS transistor (M3) At the threshold voltage, the third NMOS transistor (M3) is turned from OFF (off) to ON (on), and at this time, since the write bit line (WBL) is Low (ground voltage), the node A is discharged. The write operation of logic 0 is completed until the end of the write cycle. It is worth noting here that the high voltage node (VH) has the low power supply voltage (LV _DD ) level at the beginning of writing, and has the high power supply voltage (HV _{DD )} after the end of the write cycle. ) The standard.

The preferred embodiment of the present invention, illustrated in Figure 6, then performs the read operation in accordance with the two stored data states of the dual-slide SRAM cell.

(A) node A stores logic 0

Before the read operation occurs (the read word line (RWL) is a voltage level lower than the ground voltage, for example, -0.5 volts), the write word line (WWL) is the ground voltage, and the second NMOS transistor (M2) is OFF (off), the second PMOS transistor (P2) is ON (on), and node B is High (high power supply voltage HV _DD ). When the read operation starts, the read word line RWL is turned from the voltage level lower than the ground voltage to High (high power supply voltage HV _DD ), and when the read word line (RWL) voltage is greater than When the threshold voltage of the selective transistor (MRS) is read, the read selection transistor (MRS) is turned from OFF (turned) to ON (on), and at this time, since the node B is High, the inverted transistor (MINV) ) is ON, so a current path is formed between the read bit line (RBL), the read select transistor (MRS), the inverting transistor (MINV), and the ground. This current path is The voltage level of the read bit line (RBL) is lowered, thereby sensing that node A stores the logic 0 data and completes the logic 0 read operation.

(2) Node A storage logic 1

Before the read operation occurs (the read word line (RWL) is a voltage level lower than the ground voltage (for example, -0.5 volts)), the write word line (WWL) is the ground voltage, and the second NMOS is The crystal (M2) is ON (on), the second PMOS transistor (P2) is OFF (off), and the node B is Low (ground voltage). When the read operation starts, the read word line (RWL) is turned from the voltage level lower than the ground voltage to High (high power supply voltage HV _DD ), and when the read word line (RWL) When the voltage is greater than the threshold voltage of the read select transistor (MRS), the read select transistor (MRS) transitions from OFF (turned) to ON (on), and since node B is Low (ground voltage), The inverting transistor (MINV) is OFF (off), so it is not between the read bit line (RBL), the read select transistor (MRS), the inverting transistor (MINV), and the ground. As a result, the current path is formed, and as a result, the voltage level of the read bit line (RBL) can be smoothly maintained in the High state, thereby sensing that the node A stores the data of the logic 1 and completes the reading of the logic 1. action.

The preferred embodiment of the present invention shown in FIG. 6 shows the HSPICE transient analysis simulation results during the write operation, as shown in FIG. 8, which is simulated with a level 49 model and using TSMC 0.35 micron CMOS process parameters. It can be confirmed from the simulation results that the double-turn SRAM with the discharge path proposed by the present invention can reduce the power supply voltage by the writing operation, thereby effectively avoiding the double-static static random access memory having a single bit line. The presence of a cell in writing logic 1 is quite difficult. Furthermore, the double-turn SRAM with the discharge path proposed by the present invention can be provided by the discharge path provided by the present invention even when operating in a static random access memory having high memory capacity and/or high-speed operation. To effectively improve the reliability and stability of the write operation.

Finally, how the double-turn SRAM with the discharge path proposed by the present invention can reduce the read interference and improve the read reliability by reducing the leakage current of the non-selected double-turn SRAM cell. efficacy. During the read operation, the read select transistor (MRS) of the non-selected double-turn SRAM cell is in an OFF state, but there is still leakage current when the read select transistor (MRS) is turned off. The leakage current path is formed between the read bit line (RBL), the read select transistor (MRS), the inverting transistor (MINV), and the ground, and the leakage current path causes read disturb. And reduce read reliability. The present invention reduces the non-voltage level (e.g., -0.5 volts) by setting the read word line (RWL) to be lower than the ground voltage but higher than the gate-induced drain leakage (GIDL) current. Select the leakage current of the double-turn SRAM cell. In fact, the leakage current at the time of the turn-off of the transistor is mainly from the subthreshold current, which is shown in the figures 3 (A) and 3 (B) of the US Pat. No. 6,865,119, issued March 8, 2005. It is disclosed that for an NMOS transistor, the sub-critical current when the gate-source voltage is -0.1 volt is about 1% of the sub-critical current when the gate-source voltage is 0 volts, and therefore, by reading the character for reading The line (RWL) is set lower than the ground voltage but higher than the voltage level at which the gate-induced drain leakage (GIDL) current is generated, which can significantly reduce the leakage current of the non-selected double-turn SRAM cell and can seek to reduce reading. Take interference and improve read reliability.

(II) Standby mode

At this time, the standby mode control signal (S) is a logic high level, and the logic high level standby mode control signal (S) is reversed by the fourth inverter (I26) in the first bias circuit (2) The phase output logic low level of the inverted standby mode control signal (/S), the logic high level of the standby mode control signal (S) and the logic low level of the inverted standby mode control signal (/S) The fifth PMOS transistor (P24) in the first bias circuit (2) is turned OFF (turned off), and the sixth PMOS transistor (P25) is turned ON (on), so that the low power supply voltage (LV) can be _DD ) is supplied to the high voltage node (VH); in addition, the logic low level of the inverted standby mode control signal (/S) can cause a third NMOS transistor (M31) in the second bias circuit (3) OFF), since the fourth NMOS transistor (M32) in the second bias circuit (3) is still ON (on), the low voltage node (VL) can be maintained at the fourth The level of the threshold voltage of the NMOS transistor (M32).

Next, how to reduce the leakage current in the standby mode of the present invention is described. Please refer to FIG. 9 and FIG. 9 shows the critical leakage current generated by the double-turn SRAM in the standby mode in FIG. 6 (subthreshold leakage). Current) I1, I2, I3, and I4, wherein the storage node A in the double-turn SRAM cell is assumed to be a logical Low (ground voltage), and the inverting storage node (B) is a logic high (high power supply voltage HV _DD ). Referring again to the prior art of FIG. 5 and the embodiment of the present invention of FIG. 9, the comparison of the leakage current I1 flowing through the write select transistor (MWS) is due to the write word line (WWL) in the standby mode. Is a ground voltage, so the leakage current I1 flowing through the write select transistor (MWS) and the prior art of FIG. 5 (the NMOS transistor M3 in the prior art is equivalent to the preferred embodiment of the present invention) The write select transistor MWS) has the same leakage current; with respect to the leakage current I2 flowing through the first PMOS transistor (P1), the high voltage node (VH) has a low power supply voltage due to the standby mode ( LV _DD ) voltage level, the voltage level of the low power supply voltage (LV _DD ) is less than the high power supply voltage (HV _DD ), so the drain can be reduced by reducing the drain (Drain-Induced Barrier Lowering) The effect of the DIBL) is to reduce the leakage current effectively. As a result, the leakage current I2 flowing through the first PMOS transistor (P1) is smaller than that of the prior art of FIG. 5 (the PMOS transistor P1 in the prior art is equivalent to the implementation of the present invention). The first PMOS transistor P1) in the example; about flowing through the second NMOS transistor The comparison of the leakage current I3 of (M2), because the low voltage node (VL) maintains the level of the threshold voltage of the fourth NMOS transistor (M32) in the standby mode, and because the storage node A is logic Low ( Ground voltage), according to the body effect, the threshold voltage of the second NMOS transistor (M2) rises, according to the third (A) and 3 (B) of the US6865119 patent of March 8, 2005 The result (the result shows that for the NMOS transistor, the subcritical current when the gate source voltage is -0.1 volt is about 1% of the subcritical current when the gate source voltage is 0 volt), and thus flows through the first The leakage current I3 of the two NMOS transistors (M2) is much smaller than that of the prior art of FIG. 5 (the NMOS transistor M2 in the prior art is equivalent to the second NMOS transistor M2 in the embodiment of the present invention); By reading the leakage current I4 of the selective transistor (MRS), the read word line (RWL) is set to a voltage level lower than the ground voltage (for example, -0.5 volts) in the standby mode, and because The inverting transistor (MINV) is turned on, so that the source voltage of the read selective transistor (MRS) can be fixed to the fourth NMOS transistor (M32) The level of the threshold voltage, therefore, according to the body effect and the figures 3(A) and 3(B) of the US6865119 patent of March 8, 2005, the result can greatly reduce the flow through the reading selection. Leakage current I4 of the transistor (MRS).

The HSPICE transient analysis simulation results of various processes (TT, SS, FF) and temperature in the standby mode of the double-turn SRAM with discharge path and the prior art of FIG. 5 are shown in Table 1. It is simulated with the level 49 model and using TSMC 0.35 micron CMOS process parameters. From the simulation results, it can be confirmed that the present invention can effectively reduce the leakage current in the standby mode.

【Effects of invention】

The double-turn SRAM with discharge path proposed by the invention has the following effects:

(1) Low read disturb and high read reliability: Since the double-turn SRAM with the discharge path proposed by the present invention is in the read operation, the read word line (RWL) is non-selected. The voltage level is set to be lower than the ground voltage (for example, -0.5 volts). As a result, the leakage current of the non-selected double-turn SRAM cell can be greatly reduced, thereby effectively reducing read disturb and improving reading. Take reliability and other effects;

(2) Low-threshold leakage current: Since the double-turn SRAM with discharge path proposed in the present invention is in the standby mode, the high-voltage node (VH) is the voltage level of the low power supply voltage (LV _DD ), and is low. The voltage node (VL) is fixed to the threshold voltage of the fourth NMOS transistor (M32), and the voltage level of the read word line (RWL) is fixed below the ground voltage (for example, -0.5 volts). The voltage level of the circuit is such that the double-turn SRAM with the discharge path proposed by the present invention also has the effect of low-order critical leakage current;

(3) Avoiding the problem of writing logic 1: The double-turn SRAM with discharge path proposed by the present invention can effectively reduce the voltage level of the high voltage node (VH) during the write operation during the write operation. It is quite difficult to avoid the existence of writing a logic 1 in a double-slot static random access memory cell with a single bit line;

(4) High write reliability and high write stability at high memory capacity and/or high-speed operation: due to the high memory capacity and/or high speed operation of the dual-SRAM SRAM with discharge path proposed by the present invention At the same time, the discharge path (4) provided by the present invention can still be used to effectively improve the reliability and stability of the write operation.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

M3. . . Third NMOS transistor

M4. . . Fourth NMOS transistor

MWS. . . Write transistor

MRS. . . Selective transistor for reading

MINV. . . Inverting transistor

WL. . . Word line

WWL. . . Write word line

RWL. . . Read word line

BL. . . Bit line

BLB. . . Complementary bit line

WBL. . . Write bit line

RBL. . . Read bit line

A. . . Storage node

B. . . Inverting storage node

HV _DD . . . High power supply voltage

LV _DD . . . Low power supply voltage

S. . . Standby mode control signal

/S. . . Inverting standby mode control signal

P21. . . Third PMOS transistor

P22. . . Fourth PMOS transistor

I23. . . Third inverter

P24. . . Fifth PMOS transistor

P25. . . Sixth PMOS transistor

I26. . . Fourth inverter

M31. . . Third NMOS transistor

M32. . . Fourth NMOS transistor

VH. . . High voltage node

VL. . . Low voltage node

M41. . . Fifth NMOS transistor

M42. . . Sixth NMOS transistor

M43. . . Seventh NMOS transistor

M44. . . Eighth NMOS transistor

P45. . . Seventh PMOS transistor

D46. . . Delay circuit

1. . . SRAM cell

2. . . First bias circuit

3. . . Second bias circuit

4. . . Discharge path

Vdd. . . voltage

Figure 1 is a circuit diagram showing a conventional 6T static random access memory cell;

Figure 2 is a timing chart showing the write operation of a conventional 6T static random access memory cell;

Figure 3 is a circuit diagram showing a conventional 5T static random access memory cell;

Figure 4 is a timing chart showing the write operation of a conventional 5T static random access memory cell;

Figure 5 is a schematic circuit diagram showing a conventional double-chip static random access memory cell;

Figure 6 is a circuit diagram showing a double-turn SRAM with a discharge path according to a preferred embodiment of the present invention;

Figure 7 is a circuit diagram showing a discharge path of a double-turn SRAM having a discharge path according to a preferred embodiment of the present invention;

Figure 8 is a timing chart showing the write operation of the preferred embodiment of the present invention in Figure 6;

Figure 9 shows the critical leakage currents generated by the double-turn SRAM in the standby mode in Figure 6.

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

MWS. . . Write transistor

MRS. . . Selective transistor for reading

WWL. . . Write word line

RWL. . . Read word line

WBL. . . Write bit line

RBL. . . Read bit line

A. . . Storage node

B. . . Inverting storage node

HV _DD . . . High power supply voltage

LV _DD . . . Low power supply voltage

S. . . Standby mode control signal

/S. . . Inverting standby mode control signal

VH. . . High voltage node

VL. . . Low voltage node

P21. . . Third PMOS transistor

P22. . . Fourth PMOS transistor

I23. . . Third inverter

P24. . . Fifth PMOS transistor

P25. . . Sixth PMOS transistor

I26. . . Fourth inverter

M31. . . Third NMOS transistor

M32. . . Fourth NMOS transistor

1. . . SRAM cell

2. . . First bias circuit

3. . . Second bias circuit

4. . . Discharge path

MINV. . . Inverting transistor

Claims (8)

A double-turn SRAM with a discharge path includes: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each row of memory cells Each of the cells includes a plurality of memory cells (1); a plurality of first bias circuits (2), each column of memory cells is provided with a first bias circuit (2), the first bias voltage The circuit (2) is configured to receive a standby mode control signal (S) and a write word line (WWL), and only the standby mode control signal (S) is a logic high level representing a standby mode. Supplying a low power supply voltage (LV _DD ) to a high voltage node (VH) while the write word line (WWL) is at a logic high level representing the selected write state, in addition to Supplying a high power supply voltage (HV _DD ) to the high voltage node (VH); a second bias circuit (3) for receiving an inverting standby mode a control signal (/S), and supplying the ground voltage to a low power when the inverted standby mode control signal (/S) is a logic high level representing the active mode a node (VL), and when the inverted standby mode control signal (/S) is a logic low level representing a standby mode, a voltage higher than a ground voltage is supplied to the low voltage node (VL); and a plurality of a discharge path (4), each column of memory cells is provided with a discharge path (4); wherein each memory cell (1) further comprises: a first inverter, which is composed of a first PMOS transistor (P1) And a first NMOS transistor (M1) connected between the high voltage node (VH) and the low voltage node (VL); a second inverter is a second PMOS transistor (P2) and a second NMOS transistor (M2) connected between the high voltage node (VH) and the low voltage node (VL); a storage node ( A) formed by the output of the first inverter; an inverting storage node (B) formed by the output of the second inverter; a write select transistor (MWS) Connected between the storage node (A) and a write bit line (WBL), and the gate is connected to the write word line (WWL); a read select transistor (MRS) , one end connected To the read bit line (RBL), the other end is connected to an inverting transistor (MINV), and the gate is connected to a read word line (RWL); and an inverting transistor ( MINV), one end of which is connected to the read select transistor (MRS), the other end is connected to the low voltage node (VL), and the gate is connected to the inverting storage node (B); wherein the first The inverter and the second inverter are connected in an alternating coupling manner, that is, an output end of the first inverter (ie, storage node A) is connected to an input end of the second inverter, and the second The output of the inverter (ie, the inverting storage node B) is connected to the input end of the first inverter; wherein each of the first bias circuits (2) further comprises: a third PMOS transistor ( P21), the source, the gate and the drain of the third PMOS transistor (P21) are respectively connected to the 汲 terminal of a fifth PMOS transistor (P24), the write word line (WWL) and the a high voltage node (VH); a fourth PMOS transistor (P22), the source, the gate and the drain of the fourth PMOS transistor (P22) are respectively connected to the low power supply voltage (LV _DD ), one Output of the third inverter (I23) And the high voltage node (VH); a third inverter (I23), the input end of the third inverter (I23) is configured to receive the write word line (WWL), and the third The output of the inverter (I23) is connected to the gate of the fourth PMOS transistor (P22); a fifth PMOS transistor (P24), the source and gate of the fifth PMOS transistor (P24) Connected to the high power supply voltage (HV _DD ), the standby mode control signal (S) and the source terminal of the third PMOS transistor (P21), and a sixth PMOS transistor (P25), respectively a source, a gate and a drain of the sixth PMOS transistor (P25) are respectively connected to the low power supply voltage (LV _DD ), an output of a fourth inverter (I26), and the high voltage node (VH) And a fourth inverter (I26), the input of the fourth inverter (I23) is configured to receive the standby mode control signal (S), and to generate the inverted standby mode control signal (/ S); wherein the second bias circuit (3) further comprises: a third NMOS transistor (M31), the source, the gate and the drain of the third NMOS transistor (M31) are respectively connected to Ground voltage, the reverse standby mode control signal (/S And the low voltage node (VL); and a fourth NMOS transistor (M32), the source of the fourth NMOS transistor (M32) is connected to the ground voltage, and the gate is connected to the drain And connected to the low voltage node (VL); wherein each discharge path (4) further comprises: a fifth NMOS transistor (M41), the source, the gate and the 汲 of the fifth NMOS transistor (M41) The poles are respectively connected to the drain of a seventh PMOS transistor (P45), the write word line (WWL) and the high voltage node (VH), and a sixth NMOS transistor (M42), the sixth The source, the gate and the drain of the NMOS transistor (M42) are respectively connected to the drain of the seventh PMOS transistor (P45), the standby mode control signal (S) and the high voltage node (VH); a seventh NMOS transistor (M43), the source, the gate and the drain of the seventh NMOS transistor (M43) are respectively connected to a ground voltage, an output of a delay circuit (D46), and the fifth NMOS transistor a source of (M41) and a source of the sixth NMOS transistor (M42); an eighth NMOS transistor (M44), a source, a gate and a drain of the eighth NMOS transistor (M44) Connect to ground voltage for this write a source line (WWL) and an input terminal of the delay circuit (D46); a seventh PMOS transistor (P45), the source, the gate and the drain of the seventh PMOS transistor (P45) are respectively connected to the opposite a phase standby mode control signal (/S), the write word line (WWL) and an input terminal of the delay circuit (D46); and a delay circuit (D46), the input terminal of the delay circuit (D46) is connected To the drain of the eighth NMOS transistor (M44) and the drain of the seventh PMOS transistor (P45), and the output of the delay circuit (D46) is connected to the seventh NMOS transistor (M43) Gate. A double-turn SRAM having a discharge path as described in claim 1, wherein a logic high level of the write word line (WWL) is a level of the high power supply voltage (HV _DD ). A double-turn SRAM having a discharge path as described in claim 1, wherein the read word line (RWL) is set to the high power supply voltage (HV _DD ) during a read operation, and The period other than the read operation is set to a voltage level lower than the ground voltage. A double-turn SRAM having a discharge path as described in claim 1, wherein the delay circuit (D46) in each of the discharge paths (4) is formed by connecting an even number of inverters to provide A delay time. A double-turn SRAM having a discharge path as described in claim 4, wherein when the write word line (WWL) is a logic high level representing a selected write state, the corresponding discharge path can be used ( 4) A discharge path is provided to discharge the charge stored at the high voltage node (VH) for a predetermined time. A double-turn SRAM having a discharge path as described in claim 5, wherein the predetermined time is equal to the delay time provided by the delay circuit (D46) plus the eighth NMOS transistor (M44) The logic low level is the propagation delay time. A double-turn SRAM having a discharge path as described in claim 4, wherein when the standby mode control signal (S) is a logic high level representing a standby mode, it can be provided by a corresponding discharge path (4) The discharge path is to discharge the charge stored at the high voltage node (VH) for another predetermined time. The double-turn SRAM having a discharge path according to claim 7, wherein the another predetermined time is equal to the delay time provided by the delay circuit (D46), and the seventh PMOS transistor (P45) The transfer delay time and the sum of the fall propagation delay times of the fourth inverter (I26) in the first bias circuit (2).