TWI489457B - Single port sram with standby start-up circuit - Google Patents

Description

Static random access memory with standby start-up circuit

The invention relates to a static random access memory (SRAM) with a standby start circuit, in particular to an effective improvement of the standby performance of the static random access memory, and can effectively reduce Leakage current and can solve the problem of the SRAM write logic 1 with a single bit line is difficult to static random access memory.

Memory plays an indispensable role in the computer industry. Generally, the memory can be classified into non-volatile memory and volatile memory, non-volatile memory, and stored according to whether it can save data after the power is turned off. It will not disappear due to power off or interruption, and the data stored in volatile memory will be eliminated as the power is turned off or interrupted. Common volatile memory types are dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory (DRAM) has the advantages of small area and low price, but it must be refreshed from time to time to prevent data from being lost due to leakage current, resulting in high speed and power consumption. Missing. Conversely, the operation of the static random access memory (SRAM) is simple and does not require an update operation, so it has the advantages of high speed and low power consumption.

The semiconductor memory devices currently used in mobile electronic devices represented by mobile phones are mainly SRAM. This is due to the small standby current of the SRAM, which is suitable for mobile phones with continuous talk time and continuous standby time.

A conventional static random access memory (SRAM), as shown in FIG. 1a, mainly includes a memory array, which is composed of a plurality of memory blocks (MB ₁ , MB). _2, etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells, each column The memory cell and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL _{2 ,} etc.), each word line corresponding to a plurality of columns of memory crystals One of the cells; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _{m ,} etc.), each bit line pair corresponding to one of the plurality of rows of memory cells And each bit line pair is composed of one bit line (BL ₁ ... BL _m ) and one complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b shows the circuit diagram of a 6T static random access memory (SRAM) cell. The PMOS transistors (P1) and (P2) are called load transistors and NMOS transistors (M1). And (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is word line, and BL and BLB They are a bit line and a complementary bit line, respectively. Since the SRAM cell requires six transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, the cell ratio) The (cell ratio) is usually set between 2.2 and 3.5, resulting in the difficulty of high integration and high price.

The HSPICE transient analysis simulation results of the 6T SRAM cell in the write operation shown in Figure 1b, as shown in Figure 2, are simulated in a level 49 model using TSMC 0.18 micron CMOS process parameters. .

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line. Compared with the 6T SRAM cell of Figure 1, the 5T static random access memory. The bulk cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. In the case of the channel width to length ratio of M2 and M3, there is a problem that writing logic 1 is quite difficult. Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is modeled using the level 49 model using TSMC 0.18 micron CMOS process parameters. Simulation, from the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.

To date, many techniques have been proposed for a 5T SRAM cell with a single bit line, such as Non-Patent Document 1 (I. Carlson et al., "A high density, low leakage, 5T SRAM for embedded caches". , "Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, pp. 215-218, 2004.) The 5T SRAM is due to the redesign of the two of the unit cell, the two-load transistor And accessing the channel width-to-length ratio of the transistor to solve the problem of writing logic 1 is difficult, thereby causing damage to the symmetry relationship between the driving transistor and the load transistor in the original unit cell and thus being susceptible to process variation; 5T SRAM of Non-Patent Document 2 (M. Wieckowski et al., "A novel five-transistor (5T) SRAM cell for high performance cache," IEEE Conference on SOC, pp. 1001-1002, 2005.) The access transistor of the long channel length is disposed between the two load transistors in the unit cell to solve the problem of difficulty in writing the logic 1, thereby causing a lack of access speed; Patent Document 3 (June 1, 1998) TW M358390) "When writing operation The low-supply voltage static random access memory can effectively solve the problem of writing logic 1. However, during the write operation, due to the lack of an effective discharge path, it is caused by high memory capacity and/or high-speed operation. There is a lack of low write speed.

In the past, there have been many techniques for reducing the standby current, for example, "Double-埠 Static Random Access Memory with Discharge Path" proposed in Patent Document 4 (No. TW M393773, December 1, 1999), Patent Document 5 ( "Static random access memory" proposed by TW I307890, March 21, 1998, "Static random access memory (SRAM) with patent document 6 (No. US7382674 B2, June 3, 1997) "Static random access memory device and method of reducing standby current", Patent Document 7 (No. US7254085 B2, August 7, 196), Patent Document 8 (September 19, 1995) "SRAM employing virtual rail scheme stable against various process-voltage-temperature variations", No. 5,71,103, B2, Non-Patent Document 9 (Tae-Hyoung Kim et al., "A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode", IEEE Journal of Solid-State Circuits ., Vol. 64, pp 1785-1795, 2009.) 8T SRAM and Non-Patent Document 10 (Ding-Ming Kwai, "Modeling of SR AM Standby Current by Three-Parameter Lognormal Distribution", Design, and Testing, 2009. MTDT '09. IEEE International Workshop on Memory Technology, pp 77-82, Aug. 31 2009-Sept. 2 2009.) In the standby operation, the source voltages of the driving transistors (ie, the NMOS transistors M1 and M2 of FIG. 1b) in all the memory cells are grounded by the original. The voltage is raised to a predetermined voltage higher than the ground voltage to reduce the power consumption of the standby operation, but the predetermined voltage is generated only by charging the parasitic capacitance by the leakage current of the transistor, thereby causing static random storage. The speed at which the memory enters the standby mode is extremely slow, and thus the lack of standby performance is reduced: that is, the patent documents or the non-patent literature lack a standby start circuit to cause the static random access memory to quickly enter the standby mode.

In view of this, the main object of the present invention is to provide a static random access memory with a standby start circuit, which can effectively prompt the static random access memory to enter the standby mode quickly, and thus effectively improve the static state. Standby performance of random access memory.

A secondary object of the present invention is to provide a static random access memory with a standby start circuit, which can effectively avoid the conventional static random access memory cell with a single bit line by the control circuit. There is a problem that writing logic 1 is quite difficult.

Still another object of the present invention is to provide a static random access memory having a standby start circuit capable of effectively reducing leakage current in a standby mode by a control circuit.

The invention provides a static random access memory with a standby starting circuit, which mainly comprises a memory array, a plurality of control circuits (2) and a standby starting circuit (3), wherein the memory array is composed of a plurality of columns The memory cell is composed of a plurality of memory cells, each column of memory cells is provided with a control circuit, and each memory cell (1) includes a first inverter (by a first PMOS The crystal P1 is composed of a first NMOS transistor M1, a second inverter (composed of a second PMOS transistor P2 and a second NMOS transistor M2), and an access transistor (by the third NMOS transistor M3). Each control unit is connected to a source of the first NMOS transistor (M1) and a source of the second NMOS transistor (M2) of each memory cell corresponding to the column memory cell, so as to cope with Controlling the source voltage of the first NMOS transistor (M1) and the source voltage of the second NMOS transistor (M2) in different operation modes, thereby effectively preventing writing logic 1 from being difficult in the write mode The problem is that the leakage current can be effectively reduced in the standby mode, while the original electrical characteristics can be maintained in other modes. Furthermore, the standby start circuit (3) is designed to effectively cause the SRAM to quickly enter the standby mode, thereby effectively improving the standby performance of the SRAM.

According to the above main object, the present invention provides a static random access memory with a standby start circuit, which mainly includes a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows of memory cells. The cell consists of each column of memory cells and each row of memory cells including a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2) And a standby starting circuit (3), which causes the static random access memory to quickly enter the standby mode to effectively improve the standby performance of the static random access memory.

For convenience of explanation, the static random access memory with standby start circuit shown in FIG. 5 has only one memory cell (1), one word line (WL), and one bit line (BL). A control circuit (2) and a standby start circuit (3) are described as embodiments. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P1 and a first NMOS transistor M1) and a second inverter (by a second PMOS) a first NMOS transistor (M3), wherein the first NMOS transistor and the second NMOS transistor are in an inter-coupled connection, that is, the first The output of the inverter (ie node A) is connected to the input of the second inverter, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the first The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell.

Referring again to FIG. 5, the control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS device. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), and a twelfth NMOS transistor (M29), a third PMOS transistor (P21), a fourth PMOS transistor (P22), a third inverter (I21), a first delay circuit (D1), and a write control The signal (CTL) is composed of. The source of the fourth NMOS transistor (M21) is connected to the drain of the seventh NMOS transistor (M24), and the gate is connected to the drain and connected to a first low voltage node (VL1); a source, a gate and a drain of the fifth NMOS transistor (M22) are respectively connected to a ground voltage, an inverted standby mode control signal (/S) and a second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (M23) are respectively connected to the second low voltage node (VL2), a standby mode control signal (S) and the first low voltage node (VL1); The source of the seven NMOS transistor (M24) is connected to the ground voltage, and the gate is connected to the drain and connected to the source of the fourth NMOS transistor (M21); the eighth NMOS transistor (M25) a source, a gate and a drain are respectively connected to the first low voltage node (VL1), the reverse standby mode control signal (/S) and the drain of the ninth NMOS transistor (M26); The source of the NMOS transistor (M26) is connected to the ground voltage, and the gate is connected to the drain and connected to the drain of the eighth NMOS transistor (M25); the tenth NMOS transistor (M27) source The gate and the drain are respectively connected to a ground voltage, a drain of the eleventh NMOS transistor (M28) and a gate of the ninth NMOS transistor (M26); the eleventh NMOS transistor (M28) The source, the gate and the drain are respectively connected to the drain of the twelfth NMOS transistor (M29), the write control signal (CTL) and the gate of the tenth NMOS transistor (M27), a drain of the third PMOS transistor (P21) and a drain of the fourth PMOS transistor (P22); a source, a gate and a drain of the twelfth NMOS transistor (M29) are respectively connected to a ground voltage An output end of the third inverter (I21) and a source of the eleventh NMOS transistor (M28); an input of the third inverter (I21) is connected to the first delay circuit (D1) Output, and the output of the third inverter (I21) is connected to the gate of the twelfth NMOS transistor (M29); the input of the first delay circuit (D1) is connected to the write control signal (CTL) And a gate of the third PMOS transistor (P21) and a gate of the eleventh NMOS transistor (M28); the source, the gate and the drain of the third PMOS transistor (P21) are respectively connected to a power supply voltage (V _DD), the write a signal (CTL), a drain of the fourth PMOS transistor (P22), and a drain of the eleventh NMOS transistor (M28); a source and a gate of the fourth PMOS transistor (P22) a drain line connected to the power supply voltage (V _DD), said third inverter (I21) and the drain of the output PMOS transistor and the third (of P21) of the electrode and the eleventh NMOS transistor (M28 ) The bungee. It is worth noting here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter.

The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage of the driving transistor (ie, the first NMOS transistor M1) closer to the bit line (BL) is in an initial period (the initial period is the first delay) One of the first delay time provided by the circuit (D1) and the sum of the falling delay times provided by the third inverter (I21) is set to be higher than the ground voltage by one of the first predetermined voltages (ie, the ninth NMOS) The gate voltage V _{GS (M26) of the} transistor (M26) and the source voltage of the other driving transistor (ie, the second NMOS transistor M2) in the selected cell (ie, the second low voltage node VL2) Set to ground voltage to prevent difficulty in writing logic 1; in standby mode, set the source voltage of the driving transistor in all memory cells to a second predetermined voltage higher than the ground voltage (ie the fourth NMOS transistor (M21) of the threshold voltage V _TM21 and the seventh NMOS transistor (M24) of the threshold voltage _V TM24 _Sum, V _TM21 + V TM24), in order to reduce leakage current; the other at the time of the mode of the source voltage of the memory cell driving transistor is set to a ground voltage, in order to maintain the stability of reading the detailed working voltage level The standard is as shown in Table 1.

The write control signal (CTL) in Table 1 can be simply a word line (WL), or a Write Enable (WE) signal and a corresponding word line (WL) signal. And an AND gate operation result, when the write enable WE signal and the corresponding word line (WL) signal are both at a logic high level, the write control signal (CTL) side is a logic high level. quasi.

Referring to FIG. 5 again, the standby starting circuit (3) is composed of a fifth PMOS transistor (P31), a sixth PMOS transistor (P32), a fourth inverter (I33), and a second delay. The circuit (D2) is composed of. a source, a gate and a drain of the fifth PMOS transistor (P31) are respectively connected to the power supply voltage (V _DD ), the reverse standby mode control signal (/S) and the sixth PMOS transistor ( a source of P32); a source, a gate and a drain of the sixth PMOS transistor (P32) are respectively connected to the drain of the fifth PMOS transistor (P31), and the fourth inverter (I33) The output is coupled to the first low voltage node (VL1); the input of the fourth inverter (I33) is coupled to the output of the second delay circuit (D2), and the output of the fourth inverter (I33) is Connected to the gate of the sixth PMOS transistor (P32); the input of the second delay circuit (D2) is connected to the inverted standby mode control signal (/S), and the output of the second delay circuit (D2) Then connected to the input of the fourth inverter (I33).

The working principle of the preferred embodiment of the present invention in accordance with FIG. 5 is as follows:

(I) write mode

Before the start of the write operation, the write control signal (CTL) is at a logic low level, such that the third PMOS transistor (P21) is turned "ON", and the eleventh NMOS transistor (M28) is turned off (OFF) Then, the node C is at a logic high level, and the node C of the logic high level turns on the tenth NMOS transistor (M27), and causes the low voltage node (VL1) to be grounded.

And during the initial period of the write operation (the initial period is the sum of the first delay time provided by the first delay circuit (D1) and the fall delay time provided by the third inverter (I21)) The write control signal (CTL) is at a logic high level, and the write inverted delay control signal (/CTL) is still at a logic high level, such that the third PMOS transistor (P21) is turned off, and the eleventh NMOS is turned off. The crystal (M28) is turned on, since the write reverse phase delay control signal (/CTL) is still at a logic high level during the initial period, so that the twelfth NMOS transistor (M29) is turned on, and the fourth PMOS transistor ( P22) is turned off, and the node C is at a logic low level, and the logic low level node C turns off the tenth NMOS transistor (M27), and makes the low voltage node (VL1) equal to the ninth NMOS transistor ( M26) gate source voltage V _{GS (M26)} , thereby effectively preventing the problem of writing logic 1 difficult.

Finally, after the initial period of the write operation, since the write control signal (CTL) is at a logic high level and the write inverted delay control signal (/CTL) is at a logic low level, the third PMOS is The crystal (P21) is turned off, the eleventh NMOS transistor (M28) is turned on, the twelfth NMOS transistor (M29) is turned off, and the fourth PMOS transistor (P22) is turned on, so that the node C is at a logic high level, The logic high level node C turns on the tenth NMOS transistor (M27) and causes the low voltage node (VL1) to be grounded.

Next, how the write operation of the preferred embodiment of the present invention in FIG. 5 is completed depends on the four write states of the SRAM static random access memory cell.

(1) Node A originally stores a logic 0, but now wants to write a logic 0:

Before the write operation occurs (the word line WL is a ground voltage), the first NMOS transistor (M1) is turned "ON". Since the first NMOS transistor (M1) is ON, the word line (WL) is turned from Low (ground voltage) to High (power supply voltage V _DD ) when the write operation starts. When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M3) (ie, the access transistor), the third NMOS transistor (M3) is turned from off (OFF) to on ( ON), at this time, since the bit line (BL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle.

(2) Node A originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the word line WL is a ground voltage), the first NMOS transistor (M1) is turned "ON". Since the first NMOS transistor (M1) is ON, when the write operation starts, the word line (WL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the node A It will rise following the voltage of the word line (WL).

When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M3), the third NMOS transistor (M3) is turned from OFF to ON, because The bit line (BL) is High (the power supply voltage V _DD ), and because the first NMOS transistor (M1) is still ON and the node B is still at a voltage level close to the power supply voltage (V _{DD )} The initial state of the voltage level, so the first PMOS transistor P1 is still off (OFF), and the node A is quickly charged toward a divided voltage level, the divided voltage level is equal to (R _M1 + _{R M25 + R M26) / (} R M3 + R M1 + R M25 + R M26) is multiplied by the power supply voltage (V _DD), wherein the R _M3 represents the third NMOS transistor (M3) is turned the equivalent resistance , R _M1 represents the on-resistance equivalent resistance of the first NMOS transistor (M1), the R _M25 represents the on-resistance equivalent resistance of the eighth NMOS transistor (M25), and the R _M26 represents the ninth NMOS transistor (M26) is the equivalent resistance, because the third NMOS transistor (M3) is still operating in the saturation region and the first NMOS transistor (M1) is still operating in the triode region, although A third NMOS transistor (M3) is turned the equivalent resistance (R _M3) is considerably greater than the first NMOS transistor (M1) is turned the equivalent resistance (R _M1), but because of the ninth NMOS transistor (M26) Is a diode connection, so a voltage level equal to the gate-source voltage V _{GS (M26)} of the ninth NMOS transistor (M26) can be provided at the first low voltage node (VL1), and the result node The voltage-divided voltage level presented by A is much higher than the voltage level of the node A of the conventional 5T SRAM cell of FIG. The much higher voltage division voltage level is sufficient to turn on the second NMOS transistor (M2), thus causing the node B to discharge to a lower voltage level, and the lower voltage level of the node B causes the first The on-resistance equivalent (R _M1 ) of an NMOS transistor (M1) exhibits a higher resistance value, and the higher resistance value of the first NMOS transistor (M1) obtains a higher voltage level at the node A. The higher voltage level of the node A is again caused by a second inverter (composed of the second PMOS transistor P2 and the second NMOS transistor M2), so that the node B exhibits a lower voltage level. The lower voltage level of the node B is again passed through a first inverter (composed of the first PMOS transistor P1 and the first NMOS transistor M1), so that the node A obtains a higher voltage level. In this cycle, the node A can be charged to the power supply voltage (V _DD ), and the logic 1 write operation is completed.

It should be noted here that the first low voltage node VL1 has a voltage level equal to the gate source voltage V _{GS (M26)} of the ninth NMOS transistor (M26) only during the initial period of writing logic 1. .

(3) Node A originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the word line WL is the ground voltage), the first PMOS transistor (P1) is turned "ON". When the word line (WL) turn-by-Low (ground voltage) High (the power supply voltage V _DD), and the voltage of the word line (WL) is greater than the third NMOS transistor (M3) threshold voltage, The third NMOS transistor (M3) is turned from OFF to ON; at this time, since the bit line (BL) is High (the power supply voltage V _DD ), and because the first PMOS transistor (P1) is still ON, so the voltage of the node A will be maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle. It should be noted here that the first low voltage node (VL1) has a voltage level equal to the threshold voltage of the fourth NMOS transistor (M21) after writing logic 1.

(4) Node A originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the word line WL is the ground voltage), the first PMOS transistor (P1) is turned "ON". When the word line (WL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M3), The third NMOS transistor (M3) is turned from OFF to ON. At this time, since the bit line (BL) is Low (ground voltage), the node A and the first low voltage are The node (VL1) is discharged to complete the write operation of logic 0 until the end of the write cycle. It is worth noting here that the first low voltage node (VL1) has a level of ground voltage after writing logic zero.

In the preferred embodiment of the present invention shown in FIG. 5, the HSPICE transient analysis simulation result during the write operation, as shown in FIG. 6, is simulated by the level 49 model and using TSMC 0.18 micron CMOS process parameters. It can be confirmed from the simulation results that the static random access memory proposed by the present invention can improve the voltage level of the first low voltage node (VL1) by writing logic 1, so as to effectively avoid the conventional device. It is quite difficult to write logic 1 in a static random access memory cell with a single bit line.

(II) Standby mode

At this time, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level of the inverted standby mode control signal (/S) can make The fifth NMOS transistor (M22) and the eighth NMOS transistor (M25) in the control circuit (2) are turned off (OFF), and the logic high level of the standby mode control signal (S) makes the first The six NMOS transistor (M23) is turned on (ON), and the sixth NMOS transistor (M23) is used as an equalizer, so that the sixth NMOS transistor (M23) can be turned on. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the fourth NMOS transistor (M21) The sum of the threshold voltage (V _TM21 ) and the threshold voltage (V _TM24 ) of the seventh NMOS transistor (M24), that is, the voltage level of V _TM21 +V _TM24 .

Next, how to reduce leakage current in the standby mode of the present invention will be described. Referring to FIG. 5, FIG. 5 depicts the leakage current I ₁ generated when the embodiment of the present invention is in the standby mode. I ₂ , I ₃ , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage node (VL2) due to the standby mode The voltage level is maintained at the voltage level of the threshold voltage sum (V _TM21 +V _TM24 ) of the fourth NMOS transistor (M21) and the seventh NMOS transistor (M24), so node A is a logic Low. voltage level is also maintained in the V _TM21 + V voltage level of the _TM24), and the second output (i.e., node B) of inverter logic High (the power supply voltage V _DD). Referring to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 5, the comparison between the leakage current of the static random access memory proposed by the present invention and the 6T SRAM of FIG. 1b is first described. Through the leakage current I _{1 of} the third NMOS transistor (M3), since the voltage level of the node A in the standby mode of the present invention is maintained at the voltage level of the V _TM21 + V _{TM 24} , and the word line is assumed (WL In the standby mode, the ground voltage is set. Therefore, the gate-source voltage V _GS of the third NMOS transistor (M3) of the present invention is a negative value, and in the standby mode, the NMOS transistor of the prior art of FIG. 1b (M3) The gate-source voltage V _GS is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect or the third (A) and 3 (B) of US6865119, March 8, 2005 As can be seen from the results of the graph, for the NMOS transistor, the sub-critical current when the gate-source voltage is -0.1 volt is about 1% of the sub-critical current when the gate-source voltage is 0 volt, which is caused by the GIDL effect. I ₁ is much smaller than the first initiator of FIG. 1b the third NMOS transistor (M3) of the leakage current flowing through the present invention prior art NMOS transistor (M3) are; Furthermore, the third NMOS transistor (M3) of the drain source voltage V _DS of the present invention, the deduction of the voltage level V _TM21 + _V TM24 for the power supply voltage V _DD, contrast In the standby mode, the 汲 source voltage V _DS of the NMOS transistor M3 of the conventional 1b to 6T static random access memory is equal to the power supply voltage V _DD , and Drain-Induced Barrier Lowering is caused according to the drain. Abbreviated as DIBL) effect, the leakage current I ₁ flowing through the third NMOS transistor (M3) of the present invention caused by the DIBL effect is also smaller than that of the prior art NMOS transistor (M3) of FIG. 1b; as a result, flowing through the present invention The leakage current I ₁ of the third NMOS transistor (M3) is much smaller than that of the prior art NMOS transistor (M3) of FIG. 1b.

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P1), the source of the first PMOS transistor (P1) is the power supply voltage (V _DD ) due to the standby mode, and the first PMOS transistor (P1) of the drain line is maintained at the V _TM21 + V voltage level _TM24, and thus the present invention the first PMOS transistor (P1) of the drain source voltage for the power supply voltage V _SD ( V _DD ) _deducts the voltage level of the V _TM21 +V _TM24 , and in the standby mode, the source drain voltage V _SD of the prior art PMOS transistor (P1) of FIG. 1b is equal to the power supply voltage (V _DD ). According to the DIBL effect, therefore, the leakage current I ₂ flowing through the first PMOS transistor (P1) will be smaller than that of the prior art PMOS transistor (P1) of FIG. 1b; finally, regarding the flow through the second NMOS transistor ( M2) leakage current I ₃ , since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V _TM21 +V _TM24 in the standby mode, the voltage level of the node A is also maintained at the V The voltage level of _TM21 + V _TM24 , and the voltage level of node B is equal to the power supply voltage (V _DD ) and the base of the second NMOS transistor (M2) is the ground voltage. Therefore, the base-source voltage V _BS of the second NMOS transistor (M2) of the present invention is a negative value, and the 汲 source voltage V _{DS of} the second NMOS transistor (M2) is the power supply voltage (V _DD ). deduct the voltage level V _TM21 + _V TM24, and when in the standby mode on the other hand, prior art of FIG. 1b NMOS transistor (M2) is the base-source voltage V _BS equal to 0, and the NMOS transistor (M2) of the VDS The pole voltage V _DS is equal to the power supply voltage (V _DD ). According to the body effect and the DIBL effect, the leakage current I ₃ flowing through the second NMOS transistor (M2) of the present invention is much smaller than that of the first graph. The NMOS transistor (M2) of the art.

The leakage current (ie, the sum of I ₁ , I _{2 ,} and I ₃ ) in the standby mode of the preferred embodiment of the present invention shown in FIG. 5 and the conventional 1b FIG. 6T static random access memory is as shown in Table 2. It is simulated by the level 49 model and using TSMC 0.18 micron CMOS process parameters. It can be seen from Table 2 that the process TT, SS and FF, the static random access memory proposed in this paper and the traditional 6T static random The access memory reduces leakage current by 90.7%, 31.5%, and 87.3%, respectively.

Finally, explain how the standby start circuit (3) in Figure 5 prompts the SRAM to enter the standby mode quickly, so as to effectively improve the standby performance of the SRAM: (1) On standby Before the mode, the inverted standby mode control signal (/S) is logic High, and the inverted high standby mode control signal (/S) causes the fifth PMOS transistor (P31) to be turned off (OFF), and causes the The sixth PMOS transistor (P32) is turned on (ON); (2) after entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the logic Low is in the standby mode control signal (/) S) turning on the fifth PMOS transistor (P31), but in the initial period of the standby mode (the initial period is one of the second delay time provided by the second delay circuit (D2) and the first The sixth PMOS transistor (P32) is still turned on (the sum of the rising delay times provided by the four inverters (I33)), so that the first low voltage node (VL1) can quickly reach the fourth NMOS crystals (M21) of the threshold voltage (V _TM21) and the seventh NMOS transistor (M24) of the threshold voltage _(V TM24) sum, i.e., _{V TM21} + V TM24 level of voltage, i.e. a single port static random-access memory can quickly enter the standby mode.

【Effects of invention】

The static random access memory with standby start circuit proposed by the invention has the following effects:

(1) Quick entry standby mode: Since the static random access memory cell with the standby start circuit proposed by the present invention is provided with a standby start circuit (3) to prompt the static random access memory to quickly enter standby mode. Mode, and in order to improve the standby performance of the static random access memory;

(2) Avoiding the problem of writing logic 1: The static random access memory with standby start circuit proposed by the present invention can improve the first period by writing logic 1 during the write operation. The voltage level of the low voltage node (VL1) is effective to avoid the problem that it is difficult to write the logic 1 in the static random access memory cell with a single bit line;

(3) Low standby current: Since the static random access memory with the standby start circuit of the present invention is in the standby mode, the sixth NMOS transistor (M23) in the on state can be used to make The voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the fourth NMOS transistor (M21) and the first The sum of the threshold voltages of the seven NMOS transistors (M24), so the static random access memory with the standby start circuit proposed by the present invention also has the effect of low standby current.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

M3. . . Third NMOS transistor

WL. . . Word line

BL. . . Bit line

A. . . Storage node

B. . . Inverting storage node

V _DD . . . Power supply voltage

S. . . Standby mode control signal

/S. . . Inverting standby mode control signal

VL1. . . First low voltage node

VL2. . . Second low voltage node

M21. . . Fourth NMOS transistor

M22. . . Fifth NMOS transistor

M23. . . Sixth NMOS transistor

M24. . . Seventh NMOS transistor

M25. . . Eighth NMOS transistor

M26. . . Ninth NMOS transistor

M27. . . Tenth NMOS transistor

M28. . . Eleventh NMOS transistor

M29. . . Twelfth NMOS transistor

P21. . . Third PMOS transistor

P22. . . Fourth PMOS transistor

1. . . SRAM cell

2. . . Control circuit

3. . . Standby start circuit

I ₁ . . . Leakage current

I ₂ . . . Leakage current

I ₃ . . . Leakage current

BLB ₁ ^... BLB _m . . . Complementary bit line

BLB. . . Complementary bit line

MB ₁ ^... MB _k . . . Memory block

WL ₁ ^... WL _n . . . Word line

BL ₁ ^... BL _m . . . Bit line

/CTL. . . Write inverted delay control signal

CTL. . . Write control signal

I21. . . Third inverter

I33. . . Fourth inverter

P31. . . Fifth PMOS transistor

P32. . . Sixth PMOS transistor

D1. . . First delay circuit

D2. . . Second delay circuit

Figure 1a shows a conventional static random access memory;

Figure 1b is a schematic circuit diagram showing a conventional 6T static random access memory cell;

Figure 2 is a timing chart showing the write operation of a conventional 6T static random access memory cell;

Figure 3 is a circuit diagram showing a conventional 5T static random access memory cell;

Figure 4 is a timing chart showing the write operation of a conventional 5T static random access memory cell;

Figure 5 is a circuit diagram showing the preferred embodiment of the present invention;

Fig. 6 is a timing chart showing the write operation of the preferred embodiment of the present invention in Fig. 5.

P1. . . First PMOS transistor

P2. . . Second PMOS transistor

M1. . . First NMOS transistor

M2. . . Second NMOS transistor

M3. . . Third NMOS transistor

A. . . Storage node

B. . . Inverting storage node

V _DD . . . Power supply voltage

BL. . . Bit line

WL. . . Word line

S. . . Standby mode control signal

/S . . . Inverting standby mode control signal

VL1. . . First low voltage node

VL2. . . Second low voltage node

M21. . . Fourth NMOS transistor

M22. . . Fifth NMOS transistor

M23. . . Sixth NMOS transistor

M24. . . Seventh NMOS transistor

M25. . . Eighth NMOS transistor

M26. . . Ninth NMOS transistor

M27. . . Tenth NMOS transistor

M28. . . Eleventh NMOS transistor

M29. . . Twelfth NMOS transistor

P21. . . Third PMOS transistor

P22. . . Fourth PMOS transistor

1. . . SRAM cell

2. . . Control circuit

3. . . Standby start circuit

I ₁ , I ₂ . . . Leakage current

I ₃ . . . Leakage current

CTL. . . Write control signal

/CTL. . . Inverted write delay control signal

D1. . . First delay circuit

D2. . . Second delay circuit

I21. . . Third inverter

I33. . . Fourth inverter

P31. . . Fifth PMOS transistor

P32. . . Sixth PMOS transistor

Claims (6)

A static random access memory with a standby start circuit, comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells And each row of memory cells includes a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); and a standby start circuit (3) The standby starting circuit (3) causes the static random access memory to quickly enter the standby mode, thereby effectively improving the standby performance of the static random access memory; wherein each memory cell (1) further comprising: a first inverter comprising a first PMOS transistor (P1) and a first NMOS transistor (M1) connected to a power supply voltage (V _DD ) and a first low voltage node (VL1); a second inverter consisting of a second PMOS transistor (P2) and a second NMOS transistor (M2), the first two inverters connected between the system power supply voltage (V _DD) and a second low voltage node (VL2); a reservoir a node (A) formed by an output of the first inverter; an inverting storage node (B) formed by an output of the second inverter; and a third NMOS transistor (M3) Is connected between the storage node (A) and a corresponding one of the bit lines (BL), and the gate is connected to the corresponding one of the word lines (WL); wherein the first inverter and the first The two inverters are connected in an alternating manner, that is, the output end of the first inverter (ie, storage node A) is connected to the input end of the second inverter, and the output end of the second inverter is (ie, the inverting storage node B) is connected to the input end of the first inverter; and each control circuit (2) further comprises: the fourth NMOS transistor (M21), a fifth NMOS transistor (M22) a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), and a tenth NMOS transistor (M27) An eleventh NMOS transistor (M28), a twelfth NMOS transistor (M29), a third PMOS transistor (P21), a fourth PMOS transistor (P22), and a third inverter (I21), a first delay circuit (D1), and a write control a component (CTL); wherein a source of the fourth NMOS transistor (M21) is connected to a drain of the seventh NMOS transistor (M24), and a gate is connected to the drain and connected to the gate a first low voltage node (VL1); a source, a gate and a drain of the fifth NMOS transistor (M22) are respectively connected to a ground voltage, an inverted standby mode control signal (/S) and the second low a voltage node (VL2); a source, a gate and a drain of the sixth NMOS transistor (M23) are respectively connected to the second low voltage node (VL2), a standby mode control signal (S) and the first a low voltage node (VL1); a source of the seventh NMOS transistor (M24) is connected to a ground voltage, and a gate is connected to the drain and connected to a source of the fourth NMOS transistor (M21); a source, a gate and a drain of the eighth NMOS transistor (M25) are respectively connected to the first low voltage node (VL1), the inverted standby mode control signal (/S) and the ninth NMOS transistor ( a drain of M26); a source of the ninth NMOS transistor (M26) is connected to a ground voltage, and a gate is connected to the drain and connected to a drain of the eighth NMOS transistor (M25); The source, the gate and the drain of the ten NMOS transistor (M27) are respectively connected to a ground voltage, a drain of the eleventh NMOS transistor (M28) and a gate of the ninth NMOS transistor (M26); The source, the gate and the drain of the eleventh NMOS transistor (M28) are respectively connected to the drain of the twelfth NMOS transistor (M29), the write control signal (CTL) and the tenth NMOS a gate of the transistor (M27), a drain of the third PMOS transistor (P21), and a drain of the fourth PMOS transistor (P22); a source and a gate of the twelfth NMOS transistor (M29) The pole and the drain are respectively connected to the ground voltage, the output of the third inverter (I21) and the source of the eleventh NMOS transistor (M28); the input of the third inverter (I21) To the output of the first delay circuit (D1), the output of the third inverter (I21) is connected to the gate of the twelfth NMOS transistor (M29) and the fourth PMOS transistor (P22) a gate of the first delay circuit (D1) connected to the write control signal (CTL) and the gate of the third PMOS transistor (P21) and the gate of the eleventh NMOS transistor (M28) The source and gate of the third PMOS transistor (P21) And drain are respectively connected to the power supply line voltage (V _DD), the control signal (CTL), the drain of the fourth PMOS transistor (P22) of the pole and the eleventh NMOS transistor (M28) of the drain And the source, the gate and the drain of the fourth PMOS transistor (P22) are respectively connected to the power supply voltage (V _DD ), the output of the third inverter (I21), and the third PMOS a drain of the crystal (P21) and a drain of the eleventh NMOS transistor (M28); further, the standby start circuit (3) is designed to enter the standby mode during an initial period of the first low The parasitic capacitance at the voltage node (VL1) is rapidly charged to the voltage level of the sum of the threshold voltage ( _VTM21 ) of the fourth NMOS transistor (M21) and the threshold voltage ( _VTM24 ) of the seventh NMOS transistor (M24) quasi. The static random access memory with a standby start circuit as described in claim 1, wherein the reverse standby mode control signal (/S) is inverted by the standby mode control signal (S) Obtained by the phaser. A static random access memory with a standby start circuit as described in claim 1, wherein the write control signal (CTL) is a word line (WL). The static random access memory with a standby start circuit as described in claim 1, wherein the write control signal (CTL) is a write enable (WE) signal and corresponding The AND gate operation result of the word line (WL) signal, that is, when the write enable WE signal and the corresponding word line (WL) signal are both at a logic high level, the write control The signal (CTL) side is at a logic high level. The static random access memory with a standby start circuit as described in claim 1, wherein the standby start circuit (3) is a fifth PMOS transistor (P31) and a sixth PMOS device. a crystal (P32), a fourth inverter (I33) and a second delay circuit (D2); wherein the source, the gate and the drain of the fifth PMOS transistor (P31) are respectively connected to The power supply voltage (V _DD ), the inverted standby mode control signal (/S) and the source of the sixth PMOS transistor (P32); the source and gate of the sixth PMOS transistor (P32) The drain is connected to the drain of the fifth PMOS transistor (P31), the output of the fourth inverter (I33) and the first low voltage node (VL1), respectively; the fourth inverter (I33) The input is connected to the output of the second delay circuit (D2), and the output of the fourth inverter (I33) is connected to the gate of the sixth PMOS transistor (P32); the second delay circuit (D2) The input of the second delay circuit (D2) is connected to the input of the fourth inverter (I33). The static random access memory with a standby start circuit as described in claim 5, wherein the initial period of the standby start circuit (3) entering the standby mode is equal to the second delay circuit (D2) A second delay time is provided and a sum of one of the rise delay times provided by the fourth inverter (I33).