201030748 六、發明說明： 【發明所屬之技術領域】 本發明係有關於-種寫人操作時提高字元線電壓位準之單谭靜態 賴__ ，_ sram)，尤指 -種可解決習知單特態隨機存取記憶體巾寫人邏輯i困難之單痒 (singleport)靜態隨機存取記憶體。 【先前技術】 記憶體在電腦工業巾扮演著無可或缺_色。通常，記舰可依照 其能否在電關閉後舰保存請而區分為揮紐記鐘和非揮發性 記憶體’其中揮發性記憶體可再區分為動態隨機存取記憶體(職^ 及靜態隨機存取記憶體(SRAM)兩種。動態隨機存取記憶體①讀)具 有面積小及雜低等伽’鱗辦必鮮時地靖喊响以防止資 料因漏電流而遺失，而導致存在有高速化困難及消耗功率大等缺失。 相反地，靜態隨機存取記憶體(SRAM)的操作則較為簡易且毋須更新操 作’因此具有高速化及消耗功率低等優點。 目前以行動電話為代表之行動電子設備所採用之半導體記憶裝 置’係以SRAM為主流。此乃由於SRAM待機電流小，適於連續通話 時間、連續待機時間盡可能延長之手機。 靜態隨機存取記憶體(SRAM)主要包括一記憶體陣列（mem〇ry army) ’該記憶體陣列係由複數列記憶體晶胞（a _&1办〇f 以 memory cells)與複數行§己憶體晶胞（a piurai^y cells)所組成，每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個 s己憶體晶胞，複數條字元線(％01>(11丨116)，每一字元線對應至複數列記憶 體晶胞中之一列；以及複數位元線對(bit line pairs)，每一位元線對係對 3 201030748 應至複數行§己憶體晶胞中之一行，且每一位元線對係由一位元線及一 互補位元線所組成。 第1圖所示即是6T靜態隨機存取記憶體(SRAM)晶胞之電路示意 圖’其中’ PMOS電晶體P1和P2稱為負載電晶體（i〇a(j transistor)， . Ml和M2稱為驅動電晶體（driving transistor) ’ M3和M4稱為存取電 晶體（access transistor)，WL 為字元線(wordline)，而 BL 及 BLB 分別 為位元線（bit line)及互補位元線（complementary bit line)，由於該 SRAM晶胞需要6個電晶體，且驅動電晶體與存取電晶體間的電流驅 Ο 動能力比(即單元比率(cellratio))通常設定在2至3之間，而導致存在有 高集積化困難及價格高等缺失。第丨圖所示67靜態隨機存取記憶體晶 胞，於寫入操作時之HSPICE暫態分析模擬結果，如第2圖所示，其係 以level 49模型且使用TSMC 〇·35微米CM〇s製程參數加以模擬。 用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種 方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5T靜態隨 機存取記憶體晶胞之電路示意圖，與第丨圖之6Τ靜態隨機存取記憶體 晶胞相比，此種5T靜態隨機存取記憶體晶胞比6T靜態隨機存取記憶 ® 體晶胞少—個電晶體及少—條位元線，轉5T靜紐齡取記憶體晶 胞存在寫人邏輯1相當困難之醜。兹考慮記憶晶胞左㈣點A原本 -储存邏輯0的情況’由於節點A之電荷僅單獨自位元線(BL)傳送，因 此很難將節點A中先前寫人的邏輯〇蓋寫成邏輯卜第3圖所示灯靜 態隨機存取記憶體晶胞，於寫入操作時之HSpiCE暫態分析模擬結果， 如第4圖所示’其係以level 49模型且使用TSMC 〇·35微米CM〇s製 程參數加以模擬’由賴擬結果可註實，具單一位元線之5τ靜態隨機 存取s己憶體晶胞存在寫入邏輯丨相當困難之問題。 有鑑於此，本發明之主要目的係提出一種寫入操作時提高字元線電 壓位準之料靜崎機存取記紐，錢藉由寫人操作時提高字元線 4 201030748 電壓位準以有效避免寫入邏輯〗相當困難之問題。 【發明内容】 本發明提出-種寫人操作時提高？元線電—位準之單蟑靜態隨機 , 餘讀體’其係包括-記麵陣列，該雜辦列係由複數列記憶 體晶胞與複數行記麵晶胞所組成，每—列記憶體晶胞與每一行記憶 ' 體晶胞各包括有複數個記憶體晶胞⑴；複數條字元線，每-字元^ 對應至複數列記憶體晶胞中之-列；複數條位元線，每一位元線係對 參 應、至複數行記憶體晶胞中之一行；以及複數個字元線電壓控制電路 (2)，每-列記憶體晶胞設置—個字元線電馳制電路。該等字元線 電壓控制電路⑵於誠之字级(WL)為縣高辦，且-寫入致能 (Write E_e ’簡稱WE)信號為代表致能狀態之邏輯高位準時，方 將-寫入用電源供應電壓(WVDD)供應至一存取電壓節點㈣，其中該 寫入用電源供應電壓(wvDD)之位準係設定至少為一電源電壓(v邮加 上-第三NMOS電晶體（M3)之臨界電_位準；而該等字元線電麗 控制電路⑵於對應之字元線_為邏輯高位準，但該寫入致能⑽） ❹ 魏城鱗錄狀紅邏輯低鱗時，聰該·電雜dd)供應至 ，該存取電壓節點(VA);除此之外，則將接地電壓供應至該存取電壓節 。剌VA)。結果’本發明可齡伽寫人操作時提高字猶電壓位準以 有效避免寫入邏輯1相當困難之問題。 【實施方式】 根據^述之主要目的，本發明提丨―職人操料提高字元線 壓位準之早雜親齡取記‘_，該寫人操 準之單埠靜態隨機存取記憶體係包括—記__， 由複數列記憶體晶胞與複數行記憶體晶胞所組成，每 與每-行記憶體晶胞各包財複數個記倾晶胞⑴：複數條字元^胞 5 201030748 每一字元線對應至複數列記憶體晶胞中之一列；複數條位元線，每— 位元線係對應至複數行記憶體晶胞中之一行；以及複數個字元線電壓 控制電路（2)，每一列記憶體晶胞設置一個字元線電壓控制電路。 為了便於說明起見，第5圖所示之寫入操作時提高字元線電壓位準 之單埠靜態隨機存取記憶體僅以一個記憶體晶胞（1)、一條字元線 (WL)、一條位元線(BL)以及一字元線電壓控制電路（2)做為實施例來 說明。該記憶體晶胞（1)係包括一第一反相器(由第一 PMO S電晶體(P i) - 與第一 NM〇S電晶體(Ml)所組成，該第一反相器係連接在一電源電壓 (Vdd)與接地電壓之間）、一第二反相器(由第二PM〇s電晶體p2與第 二_08電晶體M2所組成，該第二反相器係連接在該電源電壓(Vdd) ® 與接地電壓之間）以及一第三NMOS電晶體（M3)，其中，該第一反 相器和該第二反相器係呈交互耦合連接，亦即該第一反相器之輸出（即 節點A)係連接該第二反相器之輸入，而該第二反相器之輸出（即節點 B)則連接該第一反相器之輸入，並且該第一反相器之輸出(儲存節點a) 係用於儲存SRAM晶胞(1)之資料，而該第二反相器之輸出(反相儲存節 點B)則用於儲存SRAM晶胞(1)之反相資料。該第三NM〇s電晶體(M3 ) 係做為存取電晶體（access transistor)使用，其連接在該儲存節點(a) 與該位元線(BL)之間’而閘極則連接至一存取電壓節點(γΑ)β 請再參考第5圖’該字元線電壓控制電路（2)係由一第三PM〇s Φ 電晶體(P21)、一第四PM0S電晶體(P22)、一第三反相器(123)、一第 - 五PMOS電晶體(P24)、一第四NM0S電晶體(M25)以及一第四反相器 (126)所組成’該第三PM0S電晶體(P21)之源極、閘極與汲極係分別連 接至該電源電壓(Vdd)、一寫入致能（WriteEnable，簡稱WE)信號與 該第四PM0S電晶體(P22)之没極端；該第四pm〇S電晶體(P22)之源 極、閘極與汲極係分別連接至一寫入用電源供應電壓(胃〇〇)、該第三 反相器(123)之輸出端與該第五PM0S電晶體(p24)之源極端；該第三反 相器(123)之輸入端用以接收該寫入致能（WE)信號；該第ipM〇s電 晶體(P24)之源極、閘極與汲極係分別連接至該第三pM〇s電晶體(p2 j) 之汲極端和第四PMOS電晶體(P22)之汲極端、一反相字元線_與 該存取電壓節點(VA)，·該第四NM0S電晶體(M25)之源極、閘極與汲 6 201030748 極係分別連接至接地電壓、該反相字元線(AVL)與該存取電壓節點 (VA);而該第四反相器(126)之輸入端則用以接收該字元線(WL)，且輸 出該反相字元線(/WL)。其中，該第三反相器(123)與該第四反相器(126) 之操作電壓係為該電源電壓(Vdd)。 當該字元線電壓控制電路（2)於該字元線(WL)為邏輯高位準，且 該寫入致能（WE)信號為代表致能狀態之邏輯高位準時，可使得該字 元線電壓控制電路（2)中之第三PMOS電晶體(P21) 〇FF(截止），並 使得第四PMOS電晶體(P22) ON(導通）’於是可將該寫入用電源供應 電壓(WVDD)供應至該存取電壓節點(VA)，其中該寫入用電源供應電壓 (WVDD)之位準係設定至少為該電源電壓(Vdd)加上該第三NMOS電晶 體（M3)之臨界電壓的位準。 請再參考第5圖’當該字元線電壓控制電路（2)於該字元線 為邏輯高位準，但該寫入致能（WE)信號為代表非致能狀態之邏輯低 位準時’可使得該字元線電壓控制電路(2)中之第三PMOS電晶體(P21) ON(導通），並使得第四PM〇s電晶體(p22) 〇FF(截止），於是可將該 電源電壓(Vdd)供叙鱗sM_(VA);祕制0元線⑽) 為邏輯低位準時，則可使得該字元線電壓控制電路（2)中之第四_08 電a曰體(M25) ON(導通），於是可將該存取電壓節點(VA)拉下至接地電 壓。 接下來依單埠靜態隨機存取記憶晶胞之4種寫入狀態來說明第5 圖之本發明如何完成寫人動作，在此值得注意的是，於寫人動作期間， 係將該寫人用電源供應電壓(WVdd)供應至該存取電壓節點(va)，且 該寫入用魏供應電壓(WVdd)之辦係蚊至少為該電職壓( 加上該第三NMOS電晶體（M3)之臨界電壓的位準。 (一)儲存節點(A)原本儲存邏輯0，而現在欲寫入邏輯〇 : 在寫入動作發生前(字元線WL為接地電竭，第—丽沉電晶體 _為ON(導通）。而當該存取電壓節點(VA)的電壓大於該第三觸$ 電晶體⑽）（即存取電晶體）的臨界電壓時，該第三觀⑽電晶體 (M3)由0FF(截止)轉變為〇N(導通），此時因為位元線(bl)是㈣接 7 201030748 地電壓）’所以會將儲存節點(A)放電，而完成邏輯〇的寫入動作，直到 寫入週期結束。 (二) 儲存節點(A)原本儲存邏輯〇，而現在欲寫入邏輯j : 在寫入動作發生前(字元線WL為接地電壓），第一 電晶體 (Ml)為ON(導通）。而當該存取電麼節點(VA)的電壓大於該第三丽〇8 電曰曰體（M3)的臨界電壓時，該第三njvios電晶體（m3)由OFF(截 止)轉變為ON(導通），此時因為位元線（BL)是_(電源電壓)， 所以會對儲存節，點(A)快速充電；於儲存節點⑷充電中，由於該寫入用 電源供應電廢(WVDD)之位準係設定至少為該電源電壓()加上該第 三NMOS電晶體（M3)之臨界電壓的位準，且該寫入用電源供應電壓 (WYdd)係供應至該存取電壓節點(VA),因此有助於反相儲存節點(B) 由High(電源電壓Vd仙L〇w(接地電壓)方向轉變，當反相儲存節點⑹ 之電壓位準下降至足以使第—PMC)S電晶體⑻)導通時，該第—pM〇s 電晶體(P1)即由OFF(截止)轉變為ON(導通)，而完成邏輯J的寫入動作。 (三) 儲存節點(A)原本儲存邏輯丨，而現在欲寫入邏輯i : 在寫入動作發生前(字元線WL為接地電壓)，第一 pm〇S電晶體(P1) 為ON(導通)。而當該存取電壓節點(VA)的電壓大於該第三電晶 體（M3)的臨界電壓時’該第三丽⑽電晶體（M3)由〇ff(截止） 轉變為ON(導通）；此時因為位元線（BL)是High(電源電壓)， 並且因為第-PMOS電晶體㈣仍為ON ’所以储存節點(a)的電壓不 會變動’而會平穩地保持在魏源電壓()之位準，直到寫入週期結 束。 (四) 儲存節點(A)原本儲存邏輯丨，而現在欲寫入邏輯〇 : 在寫入動作發生前(字元線WL為接地電壓)，第一 pM〇s電晶體(ρι) 為ON(導通)。而當該存取電壓節點(VA)的電壓大於該第三_〇8電晶 體（M3)的臨界電壓時，該第三丽〇8電晶體（M3)由〇F峨止） 8 201030748 轉變為ON(導通），此時因為位元線（BL)是Low (接地電壓），且 因為該寫人用《供應電壓(WVDD)2位準倾定至少為該電源電壓 (Vdd)加上該第二NMOS電晶體（M3)之臨界電壓的位準，所以會將 儲存節點㈧快速放電而完成邏輯〇的寫入動作，直到寫入週期結束。 冑5晒示之本發明，於寫入操作時之HSPICE暫態分析模擬結 . 果，如第6圖所示，其係以1^149模型且使用TSMC 0.35微米CM(^ 製程參數加以模擬’由賴擬絲可証實，本發明所提&之寫入操作 時㈣字元線電壓辦之科靜_機存取記賴，賴由寫入操作 ® 時提高字元線電慶位準，以有效避免寫入邏輯1相當困難之問題。 【發明功效】 記憶讀料提龄猶Μ轉之科難隨機存取 ⑴，免寫入邏輯i困難之問題：本發明所提出之寫入操作時提高字元線電 壓位準之單轉_齡取輯胁仏操 入 電源供應電壓(wvDD)供應至__存取電_ ^ 鲁 r電^卿一之位準設定至少為一電源電華d);m 提古°^電3, ’即存取電晶體）之臨界電壓的位準，因此可藉由 战找魏雜_辦效避免 (2) 序It前技藝相同：本發明所提出之寫人操作時提高字元線 電魔齡取記麵於讀轉作時，由㈣將該電源201030748 VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a single static static __, _ sram) for improving the voltage level of a word line during a human operation, and in particular Know single-state random access memory towel writes a single-single-single static random access memory. [Prior Art] Memory plays an indispensable role in computer industrial towels. Usually, the ship can be divided into a clock and a non-volatile memory according to whether it can be stored in the back of the ship. The volatile memory can be further divided into dynamic random access memory (services and statics). Two kinds of random access memory (SRAM). The dynamic random access memory (read 1) has a small area and a low level of gamma, and the screams are screaming to prevent the data from being lost due to leakage current. There are shortcomings such as high speed and high power consumption. Conversely, the operation of static random access memory (SRAM) is relatively simple and requires no update operation, thus having the advantages of high speed and low power consumption. Currently, semiconductor memory devices used in mobile electronic devices represented by mobile phones are mainly based on SRAM. This is due to the small standby current of the SRAM, which is suitable for mobile phones with continuous talk time and continuous standby time. Static Random Access Memory (SRAM) mainly includes a memory array (mem〇ry army) 'The memory array is composed of a plurality of columns of memory cells (a _&1 for memory cells) and complex lines § A piurai^y cells, each column of memory cells and each row of memory cells each include a plurality of s-resonant unit cells, a plurality of word lines (%01> 11丨116), each word line corresponds to one of the plurality of column memory cells; and a plurality of bit line pairs, each bit line pair 3 201030748 should be to multiple lines § Recalling one of the cell lines, and each bit line pair is composed of one bit line and one complementary bit line. Figure 1 shows the 6T static random access memory (SRAM) cell Circuit diagram 'where' PMOS transistors P1 and P2 are called load transistors (i〇a(j transistor), . Ml and M2 are called driving transistors' M3 and M4 are called access transistors (access Transistor), WL is the word line, and BL and BLB are the bit line and the complementary bit line (compleme) Ntary bit line), since the SRAM cell requires 6 transistors, and the current drive ratio (ie, cell ratio) between the drive transistor and the access transistor is usually set between 2 and 3. As a result, there is a high accumulation difficulty and a high price. In the figure 67, the static random access memory cell, the HSPICE transient analysis simulation result during the write operation, as shown in Fig. 2, The level 49 model is simulated using the TSMC 3535 micron CM〇s process parameters. One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. 3 is a circuit diagram showing a 5T static random access memory cell with only a single bit line, compared with the 6 Τ static random access memory cell of the second figure, the 5T static random access memory. The unit cell is less than a 6T static random access memory® body cell—a transistor and a small-strip line. It is quite difficult to write a human logic cell with a 5T static age. Cell left (four) point A original - the case of storing logic 0 'due to the festival The charge of A is only transmitted from the bit line (BL) alone, so it is difficult to write the logic of the previous write in node A as the light static random access memory cell shown in Fig. 3, in the write operation. The results of the HSpiCE transient analysis of the time, as shown in Fig. 4, are simulated by the level 49 model and using TSMC 35·35 micron CM〇s process parameters, which can be inferred from the results, with a single bit line The 5τ static random access s memory cell is quite difficult to write logic. In view of this, the main object of the present invention is to provide a device for improving the voltage level of a word line during a write operation, and to increase the voltage level of the word line 4 201030748 by a writer operation. Effectively avoid writing logic is quite difficult. SUMMARY OF THE INVENTION The present invention proposes to improve when writing a person's operation. The line-electricity-level single-stationary static random, the remaining-reading body's system includes a-recorded array, which consists of a plurality of columns of memory cells and a plurality of rows of face cells, each column memory The body cell and each row of memory cells include a plurality of memory cells (1); a plurality of word lines, each of which corresponds to a column of a plurality of columns of memory cells; a plurality of bits Line, each bit line is a pair of rows in the memory cell of the reference to the complex line; and a plurality of word line voltage control circuits (2), each column memory cell is set - a word line Galloping the circuit. The word line voltage control circuit (2) is written by the Chengzhi word level (WL), and the write enable (Write E_e 'WE) signal is a logic high level on behalf of the enable state. Supplying a power supply voltage (WVDD) to an access voltage node (4), wherein the write power supply voltage (wvDD) is set to at least one power supply voltage (v-plus plus - third NMOS transistor (M3) The critical electric_level; and the word line electric control circuit (2) is at the logical high level of the corresponding character line _, but the writing enable (10)) ❹ Weicheng scale recorded red logic low scale The Supreme dd) is supplied to the access voltage node (VA); in addition, a ground voltage is supplied to the access voltage section.剌 VA). As a result, it is quite difficult to increase the word voltage level in the operation of the present invention to effectively avoid writing logic 1. [Embodiment] According to the main purpose of the description, the present invention raises the 职 职 职 操 提高 提高 提高 提高 提高 提高 提高 提高 提高 提高 早 早 早 早 早 早 早 早 早 早 早 早 早 早 單埠 單埠 單埠 單埠 單埠 單埠 單埠 單埠 單埠 單埠Including - __, consisting of a complex column of memory cells and a plurality of rows of memory cells, each with a row of memory cells each of a plurality of cells (1): a plurality of characters ^ 5 201030748 Each word line corresponds to one of a plurality of columns of memory cells; a plurality of bit lines, each of which corresponds to one of a plurality of rows of memory cells; and a plurality of word line voltage controls Circuit (2), each column of memory cells is provided with a word line voltage control circuit. For the sake of convenience of explanation, the word line voltage level is increased during the write operation shown in FIG. 5, and the static random access memory has only one memory cell (1) and one word line (WL). A bit line (BL) and a word line voltage control circuit (2) are described as an embodiment. The memory cell (1) includes a first inverter (consisting of a first PMO S transistor (P i) - and a first NM 〇S transistor (M1), the first inverter system Connected between a power supply voltage (Vdd) and a ground voltage), a second inverter (consisting of a second PM〇s transistor p2 and a second_08 transistor M2, the second inverter is connected Between the power supply voltage (Vdd) ® and the ground voltage) and a third NMOS transistor (M3), wherein the first inverter and the second inverter are in an inter-coupled connection, that is, the first An output of an inverter (ie, node A) is coupled to an input of the second inverter, and an output of the second inverter (ie, node B) is coupled to an input of the first inverter, and the The output of an inverter (storage node a) is used to store the data of the SRAM cell (1), and the output of the second inverter (inverting storage node B) is used to store the SRAM cell (1) Reversed data. The third NM〇s transistor (M3) is used as an access transistor connected between the storage node (a) and the bit line (BL) and the gate is connected to An access voltage node (γΑ)β Please refer to FIG. 5 again. The word line voltage control circuit (2) is composed of a third PM〇s Φ transistor (P21) and a fourth PMOS transistor (P22). a third inverter (123), a pentad PMOS transistor (P24), a fourth NMOS transistor (M25), and a fourth inverter (126) composed of the third PMOS transistor The source, the gate and the drain of (P21) are respectively connected to the power supply voltage (Vdd), a write enable (WE) signal and the fourth PMOS transistor (P22); The source, the gate and the drain of the fourth pm S transistor (P22) are respectively connected to a write power supply voltage (stomach sputum), an output end of the third inverter (123), and the a source terminal of the fifth PMOS transistor (p24); an input of the third inverter (123) for receiving the write enable (WE) signal; a source of the first ipM〇s transistor (P24) , the gate and the bungee are connected to the third The 汲 extreme of the pM〇s transistor (p2 j) and the 汲 terminal of the fourth PMOS transistor (P22), an inverted word line _ and the access voltage node (VA), the fourth NMOS transistor ( M25) source, gate and 汲6 201030748 poles are respectively connected to the ground voltage, the inverted word line (AVL) and the access voltage node (VA); and the fourth inverter (126) The input terminal is configured to receive the word line (WL) and output the inverted word line (/WL). The operating voltage of the third inverter (123) and the fourth inverter (126) is the power supply voltage (Vdd). The word line can be made when the word line voltage control circuit (2) is at a logic high level on the word line (WL) and the write enable (WE) signal is at a logic high level representing an enable state. The third PMOS transistor (P21) 〇 FF (off) in the voltage control circuit (2), and causes the fourth PMOS transistor (P22) to be ON (turn-on), so that the write power supply voltage (WVDD) can be used. Supplying to the access voltage node (VA), wherein the level of the write power supply voltage (WVDD) is set to at least the power supply voltage (Vdd) plus the threshold voltage of the third NMOS transistor (M3) Level. Please refer to FIG. 5 again when the word line voltage control circuit (2) is at a logic high level on the word line, but the write enable (WE) signal is a logic low level on behalf of the non-enable state. The third PMOS transistor (P21) in the word line voltage control circuit (2) is turned ON, and the fourth PM 〇s transistor (p22) 〇 FF (off), so that the power supply voltage can be (Vdd) for the scale sM_(VA); the secret 0-line (10)) is the logic low-level punctuality, which can make the fourth _08 electric a-body (M25) of the word line voltage control circuit (2) ON (on), the access voltage node (VA) can then be pulled down to ground. Next, according to the four writing states of the static random access memory cell, how the invention of FIG. 5 completes the writing action is explained. It is worth noting that during the writing action, the writer is written. The power supply voltage (WVdd) is supplied to the access voltage node (va), and the write power supply voltage (WVdd) is at least the electric occupation voltage (plus the third NMOS transistor (M3) The threshold voltage level. (1) The storage node (A) originally stores logic 0, but now wants to write logic 〇: Before the write action occurs (the word line WL is grounded exhausted, the first - Li Shen The crystal _ is ON (turn-on), and when the voltage of the access voltage node (VA) is greater than the threshold voltage of the third touch transistor (10) (ie, accessing the transistor), the third (10) transistor ( M3) is changed from 0FF (cutoff) to 〇N (conduction). At this time, because the bit line (bl) is (4) connected to 7 201030748 ground voltage), the storage node (A) is discharged, and the writing of the logical volume is completed. Action until the end of the write cycle. (2) The storage node (A) originally stores the logical volume, and now wants to write the logic j: Before the write operation occurs (the word line WL is the ground voltage), the first transistor (M1) is ON (on). And when the voltage of the access node (VA) is greater than the threshold voltage of the third electrode (M3), the third njvios transistor (m3) is turned from OFF (off) to ON ( Turn on), at this time, because the bit line (BL) is _ (supply voltage), the node (A) is quickly charged during the storage node; during the charging of the storage node (4), the power supply for the write is supplied (WVDD). a level of at least the power supply voltage () plus a threshold voltage of the third NMOS transistor (M3), and the write power supply voltage (WYdd) is supplied to the access voltage node (VA), thus contributing to the inverting storage node (B) from High (supply voltage Vd 〇 L 〇 w (ground voltage) direction transition, when the voltage level of the inverting storage node (6) drops enough to make the first - PMC) When the S transistor (8) is turned on, the first -pM〇s transistor (P1) is turned from OFF (turned) to ON (turned on), and the writing operation of the logic J is completed. (3) The storage node (A) originally stores the logic 丨, but now wants to write the logic i: Before the write operation occurs (the word line WL is the ground voltage), the first pm 〇S transistor (P1) is ON ( Turn on). And when the voltage of the access voltage node (VA) is greater than the threshold voltage of the third transistor (M3), the third (10) transistor (M3) is changed from 〇ff (off) to ON (on); Since the bit line (BL) is High (power supply voltage), and because the first PMOS transistor (4) is still ON 'the voltage of the storage node (a) does not fluctuate', it will be smoothly maintained at the Wei source voltage (). Level until the end of the write cycle. (4) The storage node (A) originally stores the logic 丨, but now wants to write the logic 〇: Before the write action occurs (the word line WL is the ground voltage), the first pM〇s transistor (ρι) is ON ( Turn on). When the voltage of the access voltage node (VA) is greater than the threshold voltage of the third _8 transistor (M3), the third 〇8 transistor (M3) is converted to 2010F峨) 8 201030748 ON (on), because the bit line (BL) is Low (ground voltage), and because the writer uses the "supply voltage (WVDD) 2 level to be at least the power supply voltage (Vdd) plus the first The level of the threshold voltage of the two NMOS transistors (M3), so the storage node (8) will be quickly discharged to complete the logic 写入 write operation until the end of the write cycle. In the present invention, the HSPICE transient analysis simulation result at the time of writing operation is as shown in Fig. 6, which is modeled by 1^149 and is simulated using TSMC 0.35 micron CM (^ process parameters) It can be confirmed by Lai Si, the writing operation of the (4) word line voltage in the writing operation of the present invention is improved by the writing operation®, and the word line is updated. In order to effectively avoid the problem of writing logic 1 is very difficult. [Effect of the invention] The memory reading is relatively difficult to access the random access (1), the problem of avoiding the difficulty of writing logic i: the write operation proposed by the present invention Improve the word line voltage level of the single turn _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ); m 提古 ° ^ electricity 3, 'that is access to the transistor's threshold voltage level, so can be found by the war Wei Wei _ effect avoidance (2) order It is the same before the skill: the present invention proposed When writing a person's operation, increase the character line, and when the power is removed from the reading, the power is supplied by (4)
的讀取操作時 x序0 S )所提出之寫入操作時提高字元線電壓位準之單埠靜態 =存取铺體，軸每―列記顏晶胞·置—辨 可節省-個存取電晶體以及一條互補位元線 ，因此整 201030748 ❹During the read operation, the x-sequence 0 S) increases the word line voltage level during the write operation. Static = access to the shop, the axis per column, the unit cell, the set--can save - save Take the transistor and a complementary bit line, so the whole 201030748 ❹
趙而5 ’本發明可則細了靜態隨機麵記顏晶胞具有更高之集積 度。 ”雖^發明剌揭露並描述了所選之較佳實細，但舉凡熟悉本技 術之士可$瞭任何形式或是細紅可能的變化均未脫離本發明的精 神與範^ _此’所有相關技術範_内之改變都包括在本發明之申請 專利範圍内。 10 201030748 【圖式簡單說明】 第1圖係顯示習知6τ靜態隨機存取記憶體晶胞之 =係顯示習知6Τ靜態隨機存取記憶體晶咖 第3圖係顯示習知5Τ靜態隨機存取 動作時序圖； 第4圖係顯示習知5丁靜離隨.體3曰胞之電路示意圖； 5Τ雜_存取記麵晶狀寫 第5圖_示本發明所提出之寫人操作時提高字元H序圖璋 靜態隨機存取記麵之魏示_ . ㈣旱之單埠Zhao and 5' The invention can be used to make the static random surface recording unit cell have a higher degree of accumulation. "While the invention discloses and describes the preferred details of the selection, it is possible that any person who is familiar with the technology can change any form or fine red without departing from the spirit and scope of the present invention. The changes in the related art are included in the scope of the patent application of the present invention. 10 201030748 [Simple description of the drawing] Fig. 1 shows the conventional 6τ static random access memory unit cell = system display conventional 6 Τ static The random access memory crystal coffee figure 3 shows the conventional 5 Τ static random access action timing diagram; the fourth figure shows the circuit diagram of the conventional 5 静 离 随 . 体 体 体 ; ; ; ;; Fig. 5 is a diagram showing the improvement of the character H sequence diagram and the static random access memory surface when the writer operates in the present invention.
第6圖·示本制所提出之寫入操;;時提高社線電壓鱗 靜態隨機存取記憶體之寫入動作時序圖； 【主要元件符號說明】 P1 第一PMOS電晶體 Ml 第一NMOS電晶體 M3 第三NMOS電晶體 BL 位元線 WL 字元線 VA 存取電壓節點 B 反相儲存節點 1 SRAM晶胞 P21 第三PMOS電晶體 123 第三反相器 M25 第四NMOS電晶體 126 第四反相器 P2 第二PMOS電晶體 M2 第二NMOS電晶體 M4 第四NMOS電晶體 BLB 互補位元線 /WL 反相字元線 A 儲存節點 Vdd 電源電壓 2 字元線電壓控制電路 P22 第四PMOS電晶體 P24 第五PMOS電晶體 WVDD 寫入用電源供應電壓 WE 寫入致能Fig. 6 shows the write operation proposed by the system; the timing chart of the write operation of the static voltage random access memory of the social line voltage scale; [Description of main component symbols] P1 first PMOS transistor M1 first NMOS Transistor M3 Third NMOS transistor BL Bit line WL Word line VA Access voltage node B Inverting storage node 1 SRAM cell P21 Third PMOS transistor 123 Third inverter M25 Fourth NMOS transistor 126 Four inverter P2 Second PMOS transistor M2 Second NMOS transistor M4 Fourth NMOS transistor BLB Complementary bit line/WL Inverted word line A Storage node Vdd Power supply voltage 2 Word line voltage control circuit P22 Fourth PMOS transistor P24 fifth PMOS transistor WVDD write power supply voltage WE write enable
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