CN104409094B - The transistor memory unit of subthreshold value 6 - Google Patents
The transistor memory unit of subthreshold value 6 Download PDFInfo
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- CN104409094B CN104409094B CN201410742586.9A CN201410742586A CN104409094B CN 104409094 B CN104409094 B CN 104409094B CN 201410742586 A CN201410742586 A CN 201410742586A CN 104409094 B CN104409094 B CN 104409094B
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Abstract
The invention belongs to integrated circuit memory technical field, specially a kind of transistor memory unit of subthreshold value 6.Its cellular construction includes a phase inverter, a storage PMOS, a power supply feedback pmos and two NMOS transfer tubes.Phase inverter and storage PMOS cross-couplings, form the storage core of memory, and their supply voltage feeds back management and control system by power supply；Two NMOS transfer tubes constitute the reading and writing circuit of memory cell with being connected respectively with two storage nodes；Power supply feedback pipe is used to control the power supply of whole memory cell to supply；Memory cell writes data into memory cell by way of differential bit line, and by data read-out by way of single end bit line, i.e., by transmitting the drop-down path for pulling down pipe formation of NMOS tube and phase inverter by data read-out to bit line.The present invention has less area, low-down leakage current, and higher low voltage operating stability.
Description
Technical field
Technology domain is set the invention belongs to integrated circuit memory, and in particular to a kind of register file (Register
) and SRAM (Static Random Access Memory, SRAM) unit File.
Background technology
With the discovery of technology, power problemses are increasingly paid close attention to by chip designer.And memory, it is used as core
The important component of piece, is normally occupied most of area of chip, dominates the main performance and power consumption of chip.Therefore, drop
The power consumption of low memory can effectively suppress the power consumption consumption of chip.Produced especially for those by the electronics that battery is operated
For product, such as medical device, wireless senser, the portable device such as laptop computer, they have more strict to power consumption consumption
Constraint, the more memory in the urgent need to low-power consumption.
Reduction supply voltage be reduce power consumption consumption be considered as most directly and most efficient method because dynamic power consumption with
Supply voltage square is directly proportional, and quiescent dissipation is mainly leakage power, and it is directly proportional to the index of supply voltage.Tradition
6 pipe (6 Transistors, 6T) SRAM, due to the presence that its memory cell internal read, write is constrained, and easily read a character with two or more ways of pronunciation bad
Phenomenon so that it is difficult in the operating at voltages less than 0.7 volt.Therefore, design all be more willing to using various novel srams come
Carry out working under low pressure instead of 6 pipe SRAM.For example, author J. P. Kulkarni, in magazine " Journal of in 2007
" the mV robust Schmitt trigger based of A 160 are delivered in Solid-State Circuits "
Subthreshold SRAM ", propose 10 transistor memory units of official's schmitt trigger form；, author M. F. in 2011
Chang " delivers " the mV SRAM with of A 130 in magazine in Journal of Solid-State Circuits "
Expanded write and read margins for subthreshold applications ", it is proposed that one can be with
In the pipe SRAM of subthreshold value 9 of 130mV operating at voltages；, author I. J. Chang, in magazine " Journal of in 2009
" 32 kb 10T sub-threshold SRAM array with bit- are delivered in Solid-State Circuits "
The nm CMOS " of interleaving and differential read scheme in 90, it is proposed that with position interleaving function
Subthreshold value 10TSRAM；, author Ming-Hsien Tu, in magazine " Journal of olid-State in 2012
" A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross- are delivered in Circuits "
Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and adaptive
Read Operation Timing Tracing ", it is proposed that a subthreshold value 9TSRAM.Although these SRAM can be in subthreshold
Worked under threshold voltage, still, either these memory cell are to expend substantial amounts of area, or it is exactly that leakage current is too big, or just
It is that reading and writing speed is excessively slow.For these problems, the present invention proposes a kind of transistor memory unit of subthreshold value 6, and it has in low-pressure region area
There is higher job stability, and only need to 6 transistors, with less area, and it can be fed back by internal electric source
Suppress the leakage current of memory cell.
The content of the invention
It is an object of the invention to provide a kind of area it is smaller, can effectively suppress leakage current, can work under low pressure
Sub-threshold memory cell.
The sub-threshold memory cell that the present invention is provided, including：
One phase inverter and a storage PMOS pipe.Wherein, the power end of phase inverter is connected with virtual power supply node, ground
End is with being globally connected.And store the drain terminal of PMOS pipes and be connected with the input of phase inverter, grid is connected with the output of phase inverter,
Source electrode is equally connected with virtual power supply node.That is, phase inverter and storage PMOS pipe cross-couplings, form the storage of memory cell
Core, the input of phase inverter and first storage node and second storage node for being output as memory cell.Wherein, second
Storage node has sound upper pull-up network and pulldown network, and first storage node only has upper pull-up network, and is drawn in the net without under
Network.
One power supply feedback pipe.Wherein, the drain electrode of power supply feedback pipe is connected with virtual power supply node, source electrode and global power
VDD is connected, and grid is then connected with first storage node.That is, source feedback pipe and storage PMOS one power supply closed loop of formation
Backfeed loop.
Two transmission NMOS tubes.Wherein, first transmission NMOS tube drain electrode is connected with second storage node, source electrode and position
Line BL is connected, and grid is then connected with Overall word line WL；Second transmission NMOS tube drain electrode is connected with first storage node, source electrode
It is connected with paratope line BLB, grid is then connected with write word line WWL.
When memory cell is in off working state, cross-coupled feedback ring and power supply closed feedback loop inside storage
Interaction, keeps data storage jointly.
When memory cell carries out write operation, Overall word line WL and write word line WWL is opened, and data pass through complementary bit line BL
Storage node is written to BLB.
When memory cell carries out read operation, Overall word line's WL beginning, and write word line WWL is turned off, data pass through first
The drop-down pipe formation drop-down path of NMOS transfer tubes and phase inverter, by data read-out to bit line BL.Also, deposited due to first
Storage node lacks pulldown network, therefore, in read operation occurs any voltage lifting in second storage node all without destruction
The data of storage, that is, eliminate read a character with two or more ways of pronunciation it is bad.
The 6T sub-threshold memory cells that the present invention is provided have higher job stability under low pressure, and with smaller
Area and sub-threshold current leakage.
Brief description of the drawings
Fig. 1 is the electrical block diagram of the present invention.
Fig. 2 is that the present invention deposits circuit operation schematic diagram under " 0 " state.
Fig. 3 is the circuit operation schematic diagram of the invention deposited under one state.
Fig. 4 is reading circuit operation chart of the present invention.
Fig. 5 is one writing circuit operation schematic diagram of the present invention.
Fig. 6 is that the present invention writes " 0 " circuit operation schematic diagram.
Embodiment
The present invention describes a kind of transistor memory unit of subthreshold value 6, design philosophy of the invention set forth below and example.
Fig. 1 show the circuit structure for the transistor memory unit of subthreshold value 6 that the present invention is realized.Anti-phase PMOS M1 and anti-phase
NMOS tube M2 constitutes a phase inverter, and the power end and virtual power supply node VV of phase inverterDDIt is connected.PMOS M3 drain terminal with
The input QB of phase inverter is connected, and grid is connected with the output Q of phase inverter, source electrode equally with virtual power supply node VVDDIt is connected.That is,
Phase inverter and PMOS pipe M3 cross-couplings, form the storage core of memory cell, and node Q, QB are two storages of memory cell
Node.Wherein, storage node Q has a sound upper pull-up network and pulldown network, and storage node QB only has upper pull-up network, and nothing
Pulldown network.
PMOS M4 drain electrode and virtual power supply node VVDDBe connected, source electrode is connected with global power VDD, and grid then with
Storage node QB is connected.In this way, M4 and M3 one power supply closed feedback loop of formation.
Transmission NMOS tube M5 drain electrode is connected with storage node Q, and source electrode is connected with bit line BL, grid then with Overall word line WL
It is connected；Transmission NMOS tube M6 drain electrode is connected with storage node QB, and source electrode is connected with paratope line BLB, grid then with write word line
WWL is connected.
Fig. 2 represents that the memory cell of the present invention deposits the circuit operation under " 0 " state.Now, Overall word line WL and write word line
WWL is " 0 ", and BL is high level, and BLB is low level, low and Q=" 0 ", QB=" 1 ".M3 is opened, and storage node QB passes through M3
Charged with the M4 power supply backfeed loops constituted, after QB voltage reaches certain value, M1 and M4 shut-offs, M2 are opened.This electricity
The end value of pressure is determined by the sub-threshold current leakage by M4 and M6.Memory cell is protected data with power supply backfeed loop by M2
Hold.
Fig. 3 represents that the memory cell of the present invention deposits the circuit operation under one state.Now, Q=" 1 ", QB=" 0 ", M2 and
M3 is turned off, and M1 and M4 is opened.Storage node Q is charged to high level in advance by the M1 and M4 of stacking, and keeps.Because node QB lacks
Few pulldown network, it is impossible to keep " 0 ", then QB can be charged by M3 sub-threshold current leakage, with the rise of QB voltages,
It can react on M4 grid, suppress node VVDD voltage, will by M3 leakage current due to the reduction of source voltage
Reduce.Simultaneously as the rise of QB voltages, there is voltage difference in QB and bit line BLB, such transfer tube M6 there is also leakage current, from
And ensure QB " 0 " data.Node QB final magnitude of voltage is determined by the leakage current by M3 and M6.Now, memory cell is led to
M1, power supply backfeed loop and M6 is crossed to keep data.
Fig. 4 represents the circuit operation under the memory cell reading mode of the present invention.When memory cell carries out read operation, write word line
WWL remains low, and Overall word line WL is height, and BL preliminary fillings are high and floating.Data are read on bit line by M2 and M5.Reading behaviour
During work, due to the presence of process deviation, node Q magnitude of voltage is likely to be breached a high level, but because node QB is without under
NMOS tube is drawn, then the magnitude of voltage of this lifting will be unable to the value for influenceing to have QB.And in traditional memory cell, because technique is inclined
This read a character with two or more ways of pronunciation that difference is produced can not badly avoid.Therefore, in other words, the present invention completely eliminate read a character with two or more ways of pronunciation it is bad.
Fig. 5 represents the circuit operation under the memory cell one writing pattern of the present invention.It is global when memory cell carries out one writing
The all saltus steps of wordline WL and write word line are high level, and BL is charged to high level in advance, and BLB pulled down to low level.Node QB is by M6
" 0 " is pulled to completely, and then, node Q is charged to " 1 " by M1, M4 and M5 collective effect.
Fig. 6 represents that the memory cell of the present invention writes the circuit operation under " 0 " pattern.Now, BLB is charged to high level in advance,
And BL pulled down to low level.Node Q is pulled to " 0 " by M5 completely, then, and node QB is fed back to the collective effect with M6 by power supply
It is charged to " 1 ".The write operation mode of this difference has larger static noise limit.
Claims (4)
1. a kind of transistor memory unit of subthreshold value 6, it is characterised in that including：
One phase inverter and a storage PMOS；Wherein, the power end of phase inverter is connected with virtual power supply node, ground terminal with it is complete
It is local to be connected；The drain terminal of storage PMOS pipes is connected with the input of phase inverter, and grid is connected with the output of phase inverter, and source electrode is same
It is connected with virtual power supply node, i.e. phase inverter and storage PMOS pipe cross-couplings, forms the storage core of memory cell, it is anti-phase
First storage node and second storage node of the input of device with being output as memory cell；Wherein, second storage node
With sound upper pull-up network and pulldown network, first storage node only has upper pull-up network, no pulldown network；The phase inverter
By anti-phase PMOS（M1）With anti-phase NMOS tube（M2）Constitute；
One power supply feedback pipe；The drain electrode of power supply feedback pipe is connected with virtual power supply node, source electrode and global power VDD phases
Even, grid is connected with first storage node, i.e. power supply feedback pipe is returned with storage PMOS one power supply closed loop feedback of formation
Road；
Two transmission NMOS tubes；Wherein, first transmission NMOS tube drain electrode is connected with second storage node, source electrode and bit line BL
It is connected, grid is then connected with Overall word line WL；Second transmission NMOS tube drain electrode is connected with first storage node, source electrode and mutual
Cover line BLB is connected, and grid is then connected with write word line WWL.
2. the transistor memory unit of subthreshold value 6 according to claim 1, it is characterised in that：When memory cell is in inoperative shape
During state, the cross-coupled feedback ring inside storage is interacted with power supply closed feedback loop, and data storage is kept jointly.
3. the transistor memory unit of subthreshold value 6 according to claim 1, it is characterised in that：When memory cell carries out write operation,
Overall word line WL and write word line WWL is opened, and data are written to storage node by complementary bit line BL and BLB.
4. the transistor memory unit of subthreshold value 6 according to claim 1, it is characterised in that：When memory cell carries out read operation,
Overall word line's WL beginning, and write word line WWL is turned off, data are formed down by the drop-down pipe of first NMOS transfer tube and phase inverter
Path is drawn, by data read-out to bit line BL.
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| CN107369466B (en) * | 2017-06-19 | 2019-09-10 | 宁波大学 | A kind of three wordline storage units based on FinFET |
| CN107369469B (en) * | 2017-06-19 | 2020-04-17 | 宁波大学 | Five-tube storage unit based on FinFET device |
| CN111916125B (en) * | 2020-07-15 | 2023-04-25 | 电子科技大学 | SRAM (static random Access memory) storage unit circuit capable of improving read-write speed and stability under low pressure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1505152A (en) * | 2002-11-29 | 2004-06-16 | 国际商业机器公司 | Reduced integrated circuit chip leakage and method of reducing leakage |
| US7672152B1 (en) * | 2007-02-27 | 2010-03-02 | Purdue Research Foundation | Memory cell with built-in process variation tolerance |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1505152A (en) * | 2002-11-29 | 2004-06-16 | 国际商业机器公司 | Reduced integrated circuit chip leakage and method of reducing leakage |
| US7672152B1 (en) * | 2007-02-27 | 2010-03-02 | Purdue Research Foundation | Memory cell with built-in process variation tolerance |
Non-Patent Citations (1)
| Title |
|---|
| 65nm工艺高性能SRAM的研究与实现;温亮;《中国优秀硕士学位论文全文数据库 信息科技辑》;20120415(第4期);全文 * |
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