CN102157195B - Low-voltage static random access memory unit, memory and writing operation method - Google Patents
Low-voltage static random access memory unit, memory and writing operation method Download PDFInfo
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- CN102157195B CN102157195B CN 201110115338 CN201110115338A CN102157195B CN 102157195 B CN102157195 B CN 102157195B CN 201110115338 CN201110115338 CN 201110115338 CN 201110115338 A CN201110115338 A CN 201110115338A CN 102157195 B CN102157195 B CN 102157195B
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Abstract
The invention discloses a low-voltage static random access memory unit, a memory and a writing operation method, which relate to the field of memories. The low-voltage static random access memory unit comprises a word writing line, a bit reading line, a word reading line, a first bit writing line, a second bit writing line, N-channel metal oxide semiconductor (NMOS) tubes mn0 to mn3, a P-channel metal oxide semiconductor (PMOS) tubes mp0 and phase inverters inv1 to inv2, wherein the grid electrode of the mn0 is connected with the word reading line; the source electrode of the mn0 is connected with the bit reading line; the drain electrode of the mn0 is connected with a node n0; the grid electrode of the mn1 is connected with a node q; the source electrode of the mn1 is connected with the node n0; the drain electrode of the mn1 is connected with the second bit writing line; the grid electrode of the mn2 is connected with a node qb; the source electrode of the mn2 is connected with the first bit writing line; the drain electrode of the mn2 is connected with the node n0; the grid electrode of the mn3 is connected with the word writing line; the source electrode is connected with a node qbt; and the drain electrode of the mn3 is connected with the node n0. The low-voltage static random access memory unit has high stability, and a bit crossing structure can be used in the process of distributing the memories, so that the problem of false reading is not generated.
Description
Technical field
The present invention relates to the memory technology field, particularly a kind of low-voltage static random access memory cell.
Background technology
The benefit of bringing in order to take full advantage of the integrated circuit technology progress obtains larger integrated level, and the size of cmos device becomes more and more less.Yet along with the further raising of technology, the diversity in the chip manufacture process is so that the parameter of cmos device such as threshold voltage etc., also larger random fluctuation can occur.For this symmetric element circuit of device that strongly depends on of static RAM (SRAM), the inconsistent meeting of device parameters causes very circuit stability and seriously influences.In addition, the decline of supply voltage has more aggravated this impact.
In addition, the variation of technique and voltage also can make soft error rate (soft error rate) increase.Experiment shows, the every reduction by 10% of supply voltage, and device size reduces 8%, can make soft error rate improve 18%.For all the foregoing reasons, use tradition 6 pipe static random access memory cell structures to be difficult to guarantee its normal operation under low voltage.
As shown in Figure 1, show the single-ended static random access memory cell of a kind of 8 pipes of the prior art, it has solved the stability problem of static RAM under the low-voltage.This structure has increased mn0 and two NMOS pipes of mn1 in traditional 6 pipe units, avoided the interference of read operation to former storage data, and then improved the stability of static RAM.Yet this structure can not as traditional 6 pipe units, effectively be processed many bits soft error.In the storer that is made of tradition 6 pipe static random access memory cells, its integral structure layout's mode adopts a decussate texture, namely comes from different logic words with the adjacent bit in the delegation.Use this layout, can guarantee that an error bit in the multi-bit errors comes from different words.Also namely, only have a bit to be affected in each word.In this case, can use ECC (error correction code, error correcting code) effectively to identify a mistake in the word.Yet this structure is difficult to be applied in the single-ended static random access memory cell of above-mentioned 8 pipes.Its reason is as follows: when write operation is carried out in a certain position in the single-ended static random access memory cell to this 8 pipe, go together and the not selected unit of different lines with selected unit, can be in a kind of identical with read operation " voltage bias " situation (also being " vacation is read " phenomenon), and then destroyed former storage data, affected the stability of unit.Therefore, if use upper rheme decussate texture, different words is arranged in in the delegation, " vacation is read " situation inevitably can occur.For " vacation is read " unit, the raising of the stability that the single-ended static random access memory cell of 8 pipes brings will not exist.Fig. 1 is the single-ended static random access memory cell circuit structure diagrams of a kind of 8 pipes of the prior art.The single-ended static random access memory cell of this kind 8 pipes is compared with 6 pipe static random access memory cells before, and stability has great raising.But the single-ended static random access memory cell of this kind 8 pipes when carrying out memory layout, must use non-position decussate texture (otherwise " vacation is read " problem that causes can inevitably reduce the false stability of reading the unit).Therefore, can not guarantee that an error bit in the multi-bit errors comes from different words, also just can not use ECC to carry out correction process.
Summary of the invention
The technical matters that (one) will solve
The technical problem to be solved in the present invention is: how a kind of low-voltage static random access memory cell is provided, and it has higher stability, and supports the position decussate texture.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of low-voltage static random access memory cell, it comprises: write word line WWL, sense bit line RBL, readout word line RWL, the first write bit line WBL, the second write bit line WBLB, NMOS pipe mn0～mn3, PMOS pipe mp0, phase inverter inv1～inv2;
The grid of described NMOS pipe mn0 connects readout word line RWL, and its source electrode connects sense bit line RBL, its drain electrode connected node n0;
The grid connected node q of described NMOS pipe mn1, its source electrode connects described node n0, and its drain electrode connects the second write bit line WBLB;
The grid connected node qb of described NMOS pipe mn2, its source electrode connects the first write bit line WBL, and its drain electrode connects described node n0;
The grid of described NMOS pipe mn3 connects write word line WWL, its source electrode connected node qbt, and its drain electrode connects described node n0;
The grid of described PMOS pipe mp0 connects write word line WWL, and its source electrode connects described node qb, and its drain electrode connects described node qbt;
The input end of described phase inverter inv1 connects described node q, and its output terminal connects described node qb;
The input end of described phase inverter inv2 connects described node qbt, and its output terminal connects described node q.
Preferably, described phase inverter inv1～inv2 connects to form by NMOS pipe and PMOS pipe.
Preferably, the annexation of NMOS pipe and PMOS pipe is among the described phase inverter inv1: described NMOS pipe source ground, described PMOS pipe source electrode connects power supply, the grid of the grid of described NMOS pipe and described PMOS pipe is connected to each other the input end that consists of described phase inverter inv1, and the drain electrode of the drain electrode of described NMOS pipe and described PMOS pipe is connected to each other the output terminal that consists of described phase inverter inv1.
The present invention also provides a kind of low-voltage static RAM, and described low-voltage static RAM is spliced by a plurality of described low-voltage static random access memory cells.
The present invention also provides a kind of and utilizes described low-voltage static random access memory cell to carry out the method for write operation: when carrying out write operation, the voltage of readout word line RWL and write word line WWL is set to respectively 0 and VDD; When needs were written as 0 with node q, then the voltage of the first write bit line WBL and the second write bit line WBLB was set to VDD; When needs were written as VDD with node q, then the first write bit line WBL and the second write bit line WBLB voltage were set to 0.
(3) beneficial effect
Low-voltage static random access memory cell of the present invention, storer and write operation method, read-write operation separates, and write bit line (the first write bit line WBL and the second write bit line WBLB) and write word line WWL co-controlling write operation, has higher stability, and when carrying out memory layout, can use a decussate texture, can not cause " vacation is read " problem.
Description of drawings
Fig. 1 is the single-ended static random access memory cell circuit structure diagrams of a kind of 8 pipes of the prior art;
Fig. 2 is a decussate texture (a) and non-position decussate texture (b) contrast schematic diagram;
Fig. 3 is the described low-voltage static random access memory cell of embodiment of the invention circuit structure diagram.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for explanation the present invention, but are not used for limiting the scope of the invention.
Fig. 2 is a decussate texture and non-position decussate texture contrast schematic diagram.As shown in Figure 2, wherein (a) part represents the position decussate texture, and the described low-voltage static random access memory cell of the embodiment of the invention adopts this kind position decussate texture; (b) part represents non-position decussate texture, and traditional single-ended static random access memory cell of 8 pipes adopts the non-position of this kind decussate texture.
Fig. 3 is the described low-voltage static random access memory cell of embodiment of the invention circuit structure diagram.As shown in Figure 3, this low-voltage static random access memory cell comprises: write word line WWL, sense bit line RBL, readout word line RWL, the first write bit line WBL, the second write bit line WBLB, NMOS pipe mn0～mn3, PMOS pipe mp0, phase inverter inv1～inv2;
The grid of described NMOS pipe mn0 connects readout word line RWL, and its source electrode connects sense bit line RBL, its drain electrode connected node n0;
The grid connected node q of described NMOS pipe mn1, its source electrode connects described node n0, and its drain electrode connects the second write bit line WBLB;
The grid connected node qb of described NMOS pipe mn2, its source electrode connects the first write bit line WBL, and its drain electrode connects described node n0;
The grid of described NMOS pipe mn3 connects write word line WWL, its source electrode connected node qbt, and its drain electrode connects described node n0;
The grid of described PMOS pipe mp0 connects write word line WWL, and its source electrode connects described node qb, and its drain electrode connects described node qbt;
The input end of described phase inverter inv1 connects described node q, and its output terminal connects described node qb;
The input end of described phase inverter inv2 connects described node qbt, and its output terminal connects described node q.
Described phase inverter inv1～inv2 forms by NMOS pipe and PMOS pipe.
The annexation of NMOS pipe and PMOS pipe is among described phase inverter inv1 and the inv2: described NMOS pipe source ground, described PMOS pipe source electrode connects power supply, the grid of the grid of described NMOS pipe and described PMOS pipe is connected to each other the input end that consists of described phase inverter inv1, and the drain electrode of the drain electrode of described NMOS pipe and described PMOS pipe is connected to each other the output terminal that consists of described phase inverter inv1.
A kind of low-voltage static RAM, it is spliced by a plurality of described low-voltage static random access memory cells.Be connected to each other with the word line of low-voltage static random access memory cell adjacent in the delegation that (write word line WWL is connected to each other, readout word line RWL is connected to each other), the bit line of adjacent low-voltage static random access memory cell is connected to each other that (sense bit line RBL is connected to each other in the same row, the first write bit line WBL is connected to each other, and the second write bit line WBLB is connected to each other).
The source electrode of described NMOS pipe mn0～mn3 and PMOS pipe mp0 and drain electrode all can switches, namely need not to distinguish source electrode and the drain electrode of NMOS pipe mn0～mn3 and PMOS pipe mp0.
Wherein, write word line WWL, the first write bit line WBL and the second write bit line WBLB only are used to write operation, and readout word line RWL and sense bit line RBL then only are used for read operation.When read states and steady state (SS) (state when not carrying out read operation and write operation), the voltage of the first write bit line WBL and the second write bit line WBLB remains respectively VDD (operating voltage) and 0, NMOS pipe mn1 and mn2 consist of the structure with inverter function, make the logic level of node n0 opposite with node q.When this low-voltage static random access memory cell is carried out read operation, then readout word line RWL is become high level, the level of node n0 is sent to sense bit line RBL by NMOS pipe mn0, to finish the read operation to this low-voltage static random access memory cell.This read operation does not produce former storage data and disturbs, therefore the SNM (static-noise-margin during this read operation, SNM during static noise margin) with steady state (SS) is the same, by two mutually phase inverter inv1 and inv2 decisions of coupling in this low-voltage static random access memory cell.And for existing 6 pipe static random access memory cells, when it is carried out read operation, wherein deposit the node of " 0 " can be drawn high by the preliminary filling high level on its bit line, greatly reduced SNM.Therefore, compare with 6 pipe static random access memory cells before, the stability of low-voltage static random access memory cell of the present invention has great raising.
When described low-voltage static random access memory cell is carried out write operation, the voltage of readout word line RWL and write word line WWL is respectively 0 and VDD, and the voltage of the first write bit line WBL and the second write bit line WBLB then is VDD (when needs are written as 0 with the voltage of the node q of this low-voltage static random access memory cell) or 0 (when needs are written as VDD with the voltage of the node q of this low-voltage static random access memory cell).At this moment, the working condition of NMOS pipe mn1 and mn2 then is similar to NMOS transfer tube (signal on the first write bit line WBL and the second write bit line WBLB is transferred to node n0), the signal of the first write bit line WBL and the second write bit line WBLB manages mn1, mn2 by NMOS and mn3 is sent to node qbt, finally finishes the write operation to node q and qb.For being in the second low-voltage static random access memory cell with delegation with described low-voltage static random access memory cell, although the voltage of the write word line WWL of this second low-voltage static random access memory cell is VDD, but the voltage of its first write bit line WBL and the second write bit line WBLB is retained as respectively VDD and 0, NMOS pipe mn1 and mn2 working method are similar to phase inverter, and coupling is interference-free with the data that keep the upper storage of node q and qb mutually with phase inverter inv2.Therefore, for this kind low-voltage static random access memory cell, if use the position decussate texture can not produce " vacation is read " phenomenon.And for being in the 3rd low-voltage static random access memory cell of same row with described low-voltage static random access memory cell, because the voltage of its write word line WWL is 0, so that its NMOS pipe mn3 cut-off, the 3rd low-voltage static random access memory cell is not subjected to the impact of himself the first write bit line WBL and the second write bit line WBLB.
To sum up, the described low-voltage static random access memory cell of the embodiment of the invention, storer, write operation method, read-write operation separates, and write bit line (the first write bit line WBL and the second write bit line WBLB) and write word line WWL co-controlling write operation, so have higher stability.And when carrying out memory layout, can use a decussate texture, can not cause " vacation is read " problem, therefore, can guarantee that an error bit in the multi-bit errors comes from different words, can use ECC to carry out correction process.
Above embodiment only is used for explanation the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; in the situation that do not break away from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (5)
1. a low-voltage static random access memory cell is characterized in that, comprising: write word line WWL, sense bit line RBL, readout word line RWL, the first write bit line WBL, the second write bit line WBLB, NMOS pipe mn0～mn3, PMOS pipe mp0, phase inverter inv1～inv2;
The grid of described NMOS pipe mn0 connects readout word line RWL, and source electrode connects sense bit line RBL, drain electrode connected node n0;
The grid connected node q of described NMOS pipe mn1, source electrode connects described node n0, and drain electrode connects the second write bit line WBLB;
The grid connected node qb of described NMOS pipe mn2, source electrode connects the first write bit line WBL, and drain electrode connects described node n0;
The grid of described NMOS pipe mn3 connects write word line WWL, source electrode connected node qbt, and drain electrode connects described node n0;
The grid of described PMOS pipe mp0 connects write word line WWL, and source electrode connects described node qb, and drain electrode connects described node qbt;
The input end of described phase inverter inv1 connects described node q, and output terminal connects described node qb;
The input end of described phase inverter inv2 connects described node qbt, and output terminal connects described node q;
And during steady state (SS), the voltage of the first write bit line WBL and the second write bit line WBLB remains respectively operating voltage and 0.
2. low-voltage static random access memory cell as claimed in claim 1 is characterized in that, described phase inverter inv1～inv2 connects to form by NMOS pipe and PMOS pipe.
3. low-voltage static random access memory cell as claimed in claim 2, it is characterized in that, the annexation of NMOS pipe and PMOS pipe is among the described phase inverter inv1: described NMOS pipe source ground, described PMOS pipe source electrode connects power supply, the grid of the grid of described NMOS pipe and described PMOS pipe is connected to each other the input end that consists of described phase inverter inv1, and the drain electrode of the drain electrode of described NMOS pipe and described PMOS pipe is connected to each other the output terminal that consists of described phase inverter inv1.
4. a low-voltage static RAM is characterized in that, described low-voltage static RAM is spliced by a plurality of claims 1 or 2 or 3 described low-voltage static random access memory cells.
5. a method of utilizing claim 1 or 2 or 3 described low-voltage static random access memory cells to carry out write operation is characterized in that, when carrying out write operation, the voltage of readout word line RWL and write word line WWL is set to respectively 0 and VDD; When needs were written as 0 with node q, then the voltage of the first write bit line WBL and the second write bit line WBLB was set to VDD; When needs were written as VDD with node q, then the first write bit line WBL and the second write bit line WBLB voltage were set to 0.
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| CN103117093B (en) * | 2012-12-20 | 2018-10-30 | 中国科学院微电子研究所 | A kind of scrubbing method applied to intertexture SRAM soft fault preventing cumulative effects |
| CN103137190B (en) * | 2013-02-06 | 2015-10-28 | 西安交通大学 | A kind of row realizing subthreshold value work interlock SRAM structure |
| CN105489241B (en) * | 2014-10-13 | 2018-07-03 | 中芯国际集成电路制造(上海)有限公司 | Static RAM |
| CN104409095B (en) * | 2014-12-09 | 2017-07-28 | 复旦大学 | 8 pipes storage submatrix array structure with position interleaving function |
| CN104575591B (en) * | 2015-02-06 | 2017-10-24 | 中国科学院微电子研究所 | Storage chip, memory cell and its driving method |
| CN105869668B (en) * | 2016-03-25 | 2018-12-07 | 西安交通大学 | Flouride-resistani acid phesphatase double interlocking applied to Dynamic voltage scaling system deposits type storage unit |
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| US5303190A (en) * | 1992-10-27 | 1994-04-12 | Motorola, Inc. | Static random access memory resistant to soft error |
| CN101458720B (en) * | 2007-12-13 | 2010-09-29 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing proximity effect of SRAM trap |
| US7782656B2 (en) * | 2008-07-23 | 2010-08-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM with improved read/write stability |
| US8111542B2 (en) * | 2008-11-19 | 2012-02-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | 8T low leakage SRAM cell |
| CN102034531A (en) * | 2010-05-28 | 2011-04-27 | 上海宏力半导体制造有限公司 | Static random access memory for reducing reading interference |
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