CN107393584B - A kind of single-ended reading storage unit of full swing based on FinFET - Google Patents
A kind of single-ended reading storage unit of full swing based on FinFET Download PDFInfo
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- CN107393584B CN107393584B CN201710462410.1A CN201710462410A CN107393584B CN 107393584 B CN107393584 B CN 107393584B CN 201710462410 A CN201710462410 A CN 201710462410A CN 107393584 B CN107393584 B CN 107393584B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
The invention discloses a kind of single-ended reading storage units of full swing based on FinFET, including write word line, write bit line, reverse phase write bit line, readout word line, sense bit line, first FinFET pipe, 2nd FinFET pipe, 3rd FinFET pipe, 4th FinFET pipe, 5th FinFET pipe, 6th FinFET pipe, 7th FinFET pipe, 8th FinFET pipe and the 9th FinFET pipe, first FinFET pipe, 2nd FinFET pipe and the 7th FinFET pipe are respectively the p-type FinFET pipe of Low threshold, 3rd FinFET pipe, 4th FinFET pipe, 5th FinFET pipe, 6th FinFET pipe and the 9th FinFET pipe are respectively to manage for the N-type FinFET of Low threshold , the 8th FinFET pipe is that the N-type FinFET of high threshold is managed；Advantage is in the case where not influencing circuit function, and delay, power consumption and power-consumption design are smaller, and data will not malfunction when read operation, and circuit stability is higher.
Description
Technical field
The present invention relates to a kind of storage units, store more particularly, to a kind of single-ended reading of full swing based on FinFET
Unit.
Background technique
As process enters nanoscale, power consumption becomes the problem of IC designer must not be not concerned with.In big portion
Point digital display circuit in memory power consumption occupy way circuit power consumption ratio it is increasing.Static random access memory
(SRAM, Static Random Access Memory), is an important component part in memory, thus is designed high
Stability low-power consumption SRAM has important research significance.Static random access memory is mainly by storage array and other peripheries
Circuit is constituted, and storage array is made of storage unit, and storage unit is the core of static random access memory, storage unit
Performance directly determine the performance of static random access memory.
It with the continuous diminution of transistor size, is limited by short-channel effect and present production process, common CMOS
The space that transistor size reduces extremely reduces.When the size reduction of common CMOS transistor is to 20nm or less, the leakage of device
Electric current can be increased sharply, cause biggish circuit leakage power consumption.Also, circuit short-channel effect becomes readily apparent from, and device becomes
It is rather unstable, significantly limit the raising of circuit performance.FinFET manages (fin field-effect transistor, Fin Field-
Effect Transistor) it is a kind of 3D transistor that new Complementary MOS (CMOS) transistor is novel for one kind,
The channel of FinFET pipe using zero doping or it is low-doped, channel is enclosed by three bread of grid.This special three-dimensional structure increases
Strong controls of the grid to channel, greatly inhibit short-channel effect, it is suppressed that the leakage current of device.FinFET pipe has
Low in energy consumption, the small advantage of area is increasingly becoming and takes over conventional CMOS devices, continues one of improved device of Moore's Law.
Traditional storage unit for using FinFET to design is storage unit classical in BSIMIMG technology library.
The circuit diagram of classical storage unit is as shown in Figure 1 in BSIMIMG technology library.The storage unit managed by six FinFET (M1, M2,
M3, M4, M5 and M6) composition, wherein FinFET pipe M1 and FinFET pipe M3 constitutes a phase inverter, FinFET pipe M2 and FinFET
Pipe M4 constitutes another phase inverter.The storage unit may destroy the data value of storage point storage in read operation, simultaneously as
Voltage may be compressed when read operation causes to read there are the partial pressure of bit line capacitance, if this compressed will lead to institute greatly
Data are read just with storing data on the contrary, thus leading to corrupt data when read operation, circuit function is unstable；Also, by
The pulldown network that FINFET pipe M3 and FINFET pipe M4 is constituted has the road of two leakage currents when storage unit is in hold mode
Diameter, so leakage current is larger, it is larger so as to cause leakage power consumption, while it is also larger to be delayed, this is unfavorable for fast and stable access number
According to.
In view of this, one kind is designed in the case where not influencing circuit performance, and delay, power consumption and power-consumption design are smaller, read
For operation hour according to that will not malfunction, the single-ended reading storage unit of the higher full swing based on FinFET of circuit stability has weight
Want meaning.
Summary of the invention
Technical problem to be solved by the invention is to provide one kind in the case where not influencing circuit performance, delay, power consumption
Smaller with power-consumption design, data will not malfunction when read operation, the higher full pendulum based on FinFET of circuit stability
Single-ended reading storage unit.
The technical scheme of the invention to solve the technical problem is: a kind of full swing list based on FinFET
Read storage unit, including write word line, write bit line, reverse phase write bit line, readout word line, sense bit line, the first FinFET pipe, second in end
FinFET pipe, the 3rd FinFET pipe, the 4th FinFET pipe, the 5th FinFET pipe, the 6th FinFET pipe, the 7th FinFET pipe, the
Eight FinFET pipe and the 9th FinFET pipe, the first FinFET pipe, the 2nd FinFET pipe and the described the 7th
FinFET pipe is respectively the p-type FinFET pipe of Low threshold, and the 3rd FinFET pipe, the 4th FinFET are managed, are described
The 5th FinFET pipe, described 6th FinFET pipe and the 9th FinFET pipe be respectively N-type for Low threshold
FinFET pipe, the 8th FinFET pipe are that the N-type FinFET of high threshold is managed, the source electrode of the first FinFET pipe, institute
The source electrode for the 2nd FinFET pipe stated is connected with the source electrode of the 7th FinFET pipe and its connecting pin is the full swing
The single-ended power end for reading storage unit, the single-ended power end for reading storage unit of the full swing is for accessing external power supply, institute
The drain electrode, described of the front gate for the first FinFET pipe stated, the backgate of the first FinFET pipe, the 2nd FinFET pipe
The front gate of the 3rd FinFET pipe, drain electrode of the 4th FinFET pipe, the drain electrode of the 5th FinFET pipe, described
The backgate of 5th FinFET pipe, the front gate of the 7th FinFET pipe, the backgate of the 7th FinFET pipe and described
The front gate of 8th FinFET pipe connects and its connecting pin is the single-ended reversed-phase output for reading storage unit of the full swing, described
The drain electrode of the first FinFET pipe, front gate of the 2nd FinFET pipe, the backgate of the 2nd FinFET pipe, described
The drain electrode of 3rd FinFET pipe, the front gate of the 4th FinFET pipe, the drain electrode of the 6th FinFET pipe and described
The back-gate connection of 6th FinFET pipe and its connecting pin are the single-ended output end for reading storage unit of the full swing, described the
The source electrode of three FinFET pipes, the backgate of the 3rd FinFET pipe, the source electrode of the 4th FinFET pipe, the described the 4th
The backgate of FinFET pipe is connected with the source electrode of the 8th FinFET pipe and its connecting pin is that the single-ended reading of the full swing is deposited
The ground terminal of storage unit, the single-ended ground terminal for reading storage unit of the full swing is for accessing greatly, and the described the 5th
The source electrode of FinFET pipe is connected with the reverse phase write bit line, the front gate of the 5th FinFET pipe, the described the 6th
The front gate of FinFET pipe is connected with the write word line, and the source electrode of the 6th FinFET pipe is connected with the write bit line,
The backgate of 8th FinFET pipe, the front gate of the 9th FinFET pipe, the backgate of the 9th FinFET pipe and
The described readout word line connection, the drain electrode of the 7th FinFET pipe, the drain electrode of the 8th FinFET pipe and described the
The drain electrode of nine FinFET pipes connects, and the source electrode of the 9th FinFET pipe is connected with the sense bit line.
The quantity of the fin of the first FinFET pipe is 1, and the quantity of the fin of the 2nd FinFET pipe is 1, described
The quantity of fin of the 3rd FinFET pipe be 1, the quantity of the fin of the 4th FinFET pipe is 1, the 5th FinFET
The quantity of the fin of pipe is 1, and the quantity of the fin of the 6th FinFET pipe is 1, the quantity of the fin of the 7th FinFET pipe
It is 1, the quantity of the fin of the 8th FinFET pipe is 1, and the quantity of the fin of the 9th FinFET pipe is 1.
The threshold voltage of the first FinFET pipe is 0.3v, and the threshold voltage of the 2nd FinFET pipe is
0.3v, the threshold voltage of the 3rd FinFET pipe are 0.3v, and the threshold voltage of the 4th FinFET pipe is 0.3v, institute
The threshold voltage for the 5th FinFET pipe stated is 0.3v, and the threshold voltage of the 6th FinFET pipe is 0.3v, described the
The threshold voltage of seven FinFET pipes is 0.3v, and the threshold voltage of the 8th FinFET pipe is 0.6v, the described the 9th
The threshold voltage of FinFET pipe is 0.3v.The circuit keeps power consumption lower on the basis of guaranteeing has the faster speed of service.
Compared with the prior art, the advantages of the present invention are as follows pass through the first FinFET pipe, the 2nd FinFET pipe, third
FinFET pipe, the 4th FinFET pipe, the 5th FinFET pipe, the 6th FinFET pipe, the 7th FinFET pipe, the 8th FinFET pipe and the
Nine FinFET manage this nine FinFET pipes and constitute the single-ended reading storage unit of full swing based on FinFET, in write operation,
Write word line WWL is high level, the 5th FinFET pipe and the conducting of the 6th FinFET pipe, is write by write bit line WBL to output end Q
Enter operation, write operation is carried out to reversed-phase output Qb by reverse phase write bit line WBLb；In read operation, readout word line RWL is height
Level, the conducting of the 9th FinFET pipe, the 8th FinFET pipe is according to the conditional conducting of storage value of reversed-phase output Qb, to make
Sense bit line RBL discharges over the ground, and when wherein Qb is " 1 ", the 8th FinFET pipe conducting, RBL is discharged over the ground by the 8th FinFET pipe,
The 8th FinFET pipe ends when Qb is " 0 ", and RBL voltage is constant, the 7th FinFET pipe, the 8th FinFET pipe and the 9th FinFET pipe
Reversed-phase output and sense bit line is isolated, does not affect the numerical value of reversed-phase output Qb, the data of reversed-phase output Qb will not be by
It influences, while the value of reversed-phase output Qb manages the phase inverter constituted with the 8th FinFET pipe to the 7th by the 7th FinFET
The connecting pin Qbb of the drain electrode of FinFET pipe, the drain electrode of the 8th FinFET pipe and the drain electrode of the 9th FinFET pipe, so that the end Qbb is
From 0 to power vd D full swing, so that the sensitivity read improves, the noise margin of read operation can be greatly improved, so that RSNM
It is of substantially equal with the SNM during holding, it solves after voltage divided, it is possible to be compressed to out and now read out data inversion mistake
Problem, data will not malfunction when read operation, and circuit stability is higher, while also substantially increasing under the operation voltage of low-voltage
RSNM, during non-reading, when readout word line RWL is low level, the cut-off of the 8th FinFET pipe and the 9th FinFET pipe is so that reverse phase
The data of output end are not influenced by the external world, while reducing leakage current, simultaneously because read-write operation leads to device most after separating
Small size requires will not be too stringent, and all transistors can go minimum breadth length ratio, so that sram cell is with feature
Size reduce when at low supply voltages can be more stable work；First FinFET pipe, the 2nd FinFET pipe and the 7th FinFET
The backgate of pipe connects front gate, reduces leakage current, and the backgate ground connection of the 3rd FinFET pipe and the 4th FinFET pipe reduces circuit power consumption,
5th FinFET pipe and the 6th FinFET pipe are connected to dynamic memory point, guarantee that electric current is read in circuit work, the 8th FinFET pipe is
High threshold FinFET pipe, the 7th FinFET pipe and the 9th FinFET pipe are that Low threshold FinFET is managed, and are guaranteeing that circuit function is correct
On the basis of, guarantee during holding and leakage current will not change reading end data during write operation；Thus the present invention is not influencing
In the case where circuit performance, delay, power consumption and power-consumption design are smaller, and data will not malfunction when read operation, circuit stability
It is higher.
Detailed description of the invention
Fig. 1 is the circuit diagram of classical storage unit in BSIMIMG technology library；
Fig. 2 is the single-ended circuit diagram for reading storage unit of the full swing of the invention based on FinFET；
Fig. 3 is normal voltage (1v), and under the conditions of frequency 1G, the single-ended reading of the full swing of the invention based on FinFET is deposited
Simulation waveform of the storage unit under BSIMIMG standard technology.
Specific embodiment
The present invention will be described in further detail below with reference to the embodiments of the drawings.
Embodiment one: as shown in Fig. 2, a kind of single-ended reading storage unit of full swing based on FinFET, including write
Line WWL, write bit line WBL, reverse phase write bit line WBLb, readout word line RWL, sense bit line RBL, the first FinFET pipe B1, the 2nd FinFET
Pipe B2, the 3rd FinFET pipe B3, the 4th FinFET pipe B4, the 5th FinFET pipe B5, the 6th FinFET pipe B6, the 7th FinFET pipe
B7, the 8th FinFET pipe B8 and the 9th FinFET pipe B9, the first FinFET pipe B1, the 2nd FinFET pipe B2 and the 7th FinFET pipe
B7 is respectively the p-type FinFET pipe of Low threshold, the 3rd FinFET pipe B3, the 4th FinFET pipe B4, the 5th FinFET pipe B5, the 6th
FinFET pipe B6 and the 9th FinFET pipe B9 is the N-type FinFET pipe of Low threshold, and the 8th FinFET pipe B8 is high threshold
N-type FinFET pipe, source electrode, the source electrode of the 2nd FinFET pipe B2 and the source electrode of the 7th FinFET pipe B7 of the first FinFET pipe B1
Connection and its connecting pin are the single-ended power end for reading storage unit of full swing, and the single-ended power end for reading storage unit of full swing is used for
Access external power supply VDD, the leakage of the front gate, the backgate, the 2nd FinFET pipe B2 of the first FinFET pipe B1 of the first FinFET pipe B1
Drain electrode, the drain electrode of the 5th FinFET pipe B5, the 5th FinFET of pole, the front gate of the 3rd FinFET pipe B3, the 4th FinFET pipe B4
The front gate company of the backgate of pipe B5, the front gate of the 7th FinFET pipe B7, the backgate of the 7th FinFET pipe B7 and the 8th FinFET pipe B8
It connects and its connecting pin is the single-ended reversed-phase output for reading storage unit of full swing, the drain electrode of the first FinFET pipe B1, second
Before the front gate of FinFET pipe B2, the backgate of the 2nd FinFET pipe B2, the drain electrode of the 3rd FinFET pipe B3, the 4th FinFET pipe B4
Grid, the back-gate connection of the drain electrode of the 6th FinFET pipe B6 and the 6th FinFET pipe B6 and its connecting pin are the single-ended reading storage of full swing
The output end of unit, the source electrode of the 3rd FinFET pipe B3, the backgate of the 3rd FinFET pipe B3, the 4th FinFET pipe B4 source electrode,
The backgate of 4th FinFET pipe B4 is connected with the source electrode of the 8th FinFET pipe B8 and its connecting pin is that the single-ended reading storage of full swing is single
The ground terminal of member, the single-ended ground terminal for reading storage unit of full swing is for accessing the earth, the source electrode of the 5th FinFET pipe B5 and anti-
The WBLb connection of phase write bit line, the front gate of the 5th FinFET pipe B5, the front gate of the 6th FinFET pipe B6 are connected with write word line WWL, the
The source electrode of six FinFET pipe B6 is connected with write bit line WBL, the backgate of the 8th FinFET pipe B8, the front gate of the 9th FinFET pipe B9,
The backgate of 9th FinFET pipe B9 is connected with readout word line RWL, the drain electrode of the 7th FinFET pipe B7, the drain electrode of the 8th FinFET pipe B8
It is connected with the drain electrode of the 9th FinFET pipe B9, the source electrode of the 9th FinFET pipe B9 is connected with sense bit line RBL.
Embodiment two: as shown in Fig. 2, a kind of single-ended reading storage unit of full swing based on FinFET, including write
Line WWL, write bit line WBL, reverse phase write bit line WBLb, readout word line RWL, sense bit line RBL, the first FinFET pipe B1, the 2nd FinFET
Pipe B2, the 3rd FinFET pipe B3, the 4th FinFET pipe B4, the 5th FinFET pipe B5, the 6th FinFET pipe B6, the 7th FinFET pipe
B7, the 8th FinFET pipe B8 and the 9th FinFET pipe B9, the first FinFET pipe B1, the 2nd FinFET pipe B2 and the 7th FinFET pipe
B7 is respectively the p-type FinFET pipe of Low threshold, the 3rd FinFET pipe B3, the 4th FinFET pipe B4, the 5th FinFET pipe B5, the 6th
FinFET pipe B6 and the 9th FinFET pipe B9 is the N-type FinFET pipe of Low threshold, and the 8th FinFET pipe B8 is high threshold
N-type FinFET pipe, source electrode, the source electrode of the 2nd FinFET pipe B2 and the source electrode of the 7th FinFET pipe B7 of the first FinFET pipe B1
Connection and its connecting pin are the single-ended power end for reading storage unit of full swing, and the single-ended power end for reading storage unit of full swing is used for
Access external power supply VDD, the leakage of the front gate, the backgate, the 2nd FinFET pipe B2 of the first FinFET pipe B1 of the first FinFET pipe B1
Drain electrode, the drain electrode of the 5th FinFET pipe B5, the 5th FinFET of pole, the front gate of the 3rd FinFET pipe B3, the 4th FinFET pipe B4
The front gate company of the backgate of pipe B5, the front gate of the 7th FinFET pipe B7, the backgate of the 7th FinFET pipe B7 and the 8th FinFET pipe B8
It connects and its connecting pin is the single-ended reversed-phase output for reading storage unit of full swing, the drain electrode of the first FinFET pipe B1, second
Before the front gate of FinFET pipe B2, the backgate of the 2nd FinFET pipe B2, the drain electrode of the 3rd FinFET pipe B3, the 4th FinFET pipe B4
Grid, the back-gate connection of the drain electrode of the 6th FinFET pipe B6 and the 6th FinFET pipe B6 and its connecting pin are the single-ended reading storage of full swing
The output end of unit, the source electrode of the 3rd FinFET pipe B3, the backgate of the 3rd FinFET pipe B3, the 4th FinFET pipe B4 source electrode,
The backgate of 4th FinFET pipe B4 is connected with the source electrode of the 8th FinFET pipe B8 and its connecting pin is that the single-ended reading storage of full swing is single
The ground terminal of member, the single-ended ground terminal for reading storage unit of full swing is for accessing the earth, the source electrode of the 5th FinFET pipe B5 and anti-
The WBLb connection of phase write bit line, the front gate of the 5th FinFET pipe B5, the front gate of the 6th FinFET pipe B6 are connected with write word line WWL, the
The source electrode of six FinFET pipe B6 is connected with write bit line WBL, the backgate of the 8th FinFET pipe B8, the front gate of the 9th FinFET pipe B9,
The backgate of 9th FinFET pipe B9 is connected with readout word line RWL, the drain electrode of the 7th FinFET pipe B7, the drain electrode of the 8th FinFET pipe B8
It is connected with the drain electrode of the 9th FinFET pipe B9, the source electrode of the 9th FinFET pipe B9 is connected with sense bit line RBL.
In the present embodiment, the quantity of the fin of the first FinFET pipe B1 is 1, and the quantity of the fin of the 2nd FinFET pipe B2 is 1, the
The quantity of the fin of three FinFET pipe B3 is 1, and the quantity of the fin of the 4th FinFET pipe B4 is 1, the number of the fin of the 5th FinFET pipe B5
Amount is 1, and the quantity of the fin of the 6th FinFET pipe B6 is 1, and the quantity of the fin of the 7th FinFET pipe B7 is 1, the 8th FinFET pipe B8
The quantity of fin be 1, the quantity of the fin of the 9th FinFET pipe B9 is 1.
Embodiment three: as shown in Fig. 2, a kind of single-ended reading storage unit of full swing based on FinFET, including write
Line WWL, write bit line WBL, reverse phase write bit line WBLb, readout word line RWL, sense bit line RBL, the first FinFET pipe B1, the 2nd FinFET
Pipe B2, the 3rd FinFET pipe B3, the 4th FinFET pipe B4, the 5th FinFET pipe B5, the 6th FinFET pipe B6, the 7th FinFET pipe
B7, the 8th FinFET pipe B8 and the 9th FinFET pipe B9, the first FinFET pipe B1, the 2nd FinFET pipe B2 and the 7th FinFET pipe
B7 is respectively the p-type FinFET pipe of Low threshold, the 3rd FinFET pipe B3, the 4th FinFET pipe B4, the 5th FinFET pipe B5, the 6th
FinFET pipe B6 and the 9th FinFET pipe B9 is the N-type FinFET pipe of Low threshold, and the 8th FinFET pipe B8 is high threshold
N-type FinFET pipe, source electrode, the source electrode of the 2nd FinFET pipe B2 and the source electrode of the 7th FinFET pipe B7 of the first FinFET pipe B1
Connection and its connecting pin are the single-ended power end for reading storage unit of full swing, and the single-ended power end for reading storage unit of full swing is used for
Access external power supply VDD, the leakage of the front gate, the backgate, the 2nd FinFET pipe B2 of the first FinFET pipe B1 of the first FinFET pipe B1
Drain electrode, the drain electrode of the 5th FinFET pipe B5, the 5th FinFET of pole, the front gate of the 3rd FinFET pipe B3, the 4th FinFET pipe B4
The front gate company of the backgate of pipe B5, the front gate of the 7th FinFET pipe B7, the backgate of the 7th FinFET pipe B7 and the 8th FinFET pipe B8
It connects and its connecting pin is the single-ended reversed-phase output for reading storage unit of full swing, the drain electrode of the first FinFET pipe B1, second
Before the front gate of FinFET pipe B2, the backgate of the 2nd FinFET pipe B2, the drain electrode of the 3rd FinFET pipe B3, the 4th FinFET pipe B4
Grid, the back-gate connection of the drain electrode of the 6th FinFET pipe B6 and the 6th FinFET pipe B6 and its connecting pin are the single-ended reading storage of full swing
The output end of unit, the source electrode of the 3rd FinFET pipe B3, the backgate of the 3rd FinFET pipe B3, the 4th FinFET pipe B4 source electrode,
The backgate of 4th FinFET pipe B4 is connected with the source electrode of the 8th FinFET pipe B8 and its connecting pin is that the single-ended reading storage of full swing is single
The ground terminal of member, the single-ended ground terminal for reading storage unit of full swing is for accessing the earth, the source electrode of the 5th FinFET pipe B5 and anti-
The WBLb connection of phase write bit line, the front gate of the 5th FinFET pipe B5, the front gate of the 6th FinFET pipe B6 are connected with write word line WWL, the
The source electrode of six FinFET pipe B6 is connected with write bit line WBL, the backgate of the 8th FinFET pipe B8, the front gate of the 9th FinFET pipe B9,
The backgate of 9th FinFET pipe B9 is connected with readout word line RWL, the drain electrode of the 7th FinFET pipe B7, the drain electrode of the 8th FinFET pipe B8
It is connected with the drain electrode of the 9th FinFET pipe B9, the source electrode of the 9th FinFET pipe B9 is connected with sense bit line RBL.
In the present embodiment, the threshold voltage of the first FinFET pipe B1 is 0.3v, and the threshold voltage of the 2nd FinFET pipe B2 is
The threshold voltage of 0.3v, the 3rd FinFET pipe B3 are 0.3v, and the threshold voltage of the 4th FinFET pipe B4 is 0.3v, the 5th FinFET
The threshold voltage of pipe B5 is 0.3v, and the threshold voltage of the 6th FinFET pipe B6 is 0.3v, the threshold voltage of the 7th FinFET pipe B7
For 0.3v, the threshold voltage of the 8th FinFET pipe B8 is 0.6v, and the threshold voltage of the 9th FinFET pipe B9 is 0.3v.
Example IV: as shown in Fig. 2, a kind of single-ended reading storage unit of full swing based on FinFET, including write
Line WWL, write bit line WBL, reverse phase write bit line WBLb, readout word line RWL, sense bit line RBL, the first FinFET pipe B1, the 2nd FinFET
Pipe B2, the 3rd FinFET pipe B3, the 4th FinFET pipe B4, the 5th FinFET pipe B5, the 6th FinFET pipe B6, the 7th FinFET pipe
B7, the 8th FinFET pipe B8 and the 9th FinFET pipe B9, the first FinFET pipe B1, the 2nd FinFET pipe B2 and the 7th FinFET pipe
B7 is respectively the p-type FinFET pipe of Low threshold, the 3rd FinFET pipe B3, the 4th FinFET pipe B4, the 5th FinFET pipe B5, the 6th
FinFET pipe B6 and the 9th FinFET pipe B9 is the N-type FinFET pipe of Low threshold, and the 8th FinFET pipe B8 is high threshold
N-type FinFET pipe, source electrode, the source electrode of the 2nd FinFET pipe B2 and the source electrode of the 7th FinFET pipe B7 of the first FinFET pipe B1
Connection and its connecting pin are the single-ended power end for reading storage unit of full swing, and the single-ended power end for reading storage unit of full swing is used for
Access external power supply VDD, the leakage of the front gate, the backgate, the 2nd FinFET pipe B2 of the first FinFET pipe B1 of the first FinFET pipe B1
Drain electrode, the drain electrode of the 5th FinFET pipe B5, the 5th FinFET of pole, the front gate of the 3rd FinFET pipe B3, the 4th FinFET pipe B4
The front gate company of the backgate of pipe B5, the front gate of the 7th FinFET pipe B7, the backgate of the 7th FinFET pipe B7 and the 8th FinFET pipe B8
It connects and its connecting pin is the single-ended reversed-phase output for reading storage unit of full swing, the drain electrode of the first FinFET pipe B1, second
Before the front gate of FinFET pipe B2, the backgate of the 2nd FinFET pipe B2, the drain electrode of the 3rd FinFET pipe B3, the 4th FinFET pipe B4
Grid, the back-gate connection of the drain electrode of the 6th FinFET pipe B6 and the 6th FinFET pipe B6 and its connecting pin are the single-ended reading storage of full swing
The output end of unit, the source electrode of the 3rd FinFET pipe B3, the backgate of the 3rd FinFET pipe B3, the 4th FinFET pipe B4 source electrode,
The backgate of 4th FinFET pipe B4 is connected with the source electrode of the 8th FinFET pipe B8 and its connecting pin is that the single-ended reading storage of full swing is single
The ground terminal of member, the single-ended ground terminal for reading storage unit of full swing is for accessing the earth, the source electrode of the 5th FinFET pipe B5 and anti-
The WBLb connection of phase write bit line, the front gate of the 5th FinFET pipe B5, the front gate of the 6th FinFET pipe B6 are connected with write word line WWL, the
The source electrode of six FinFET pipe B6 is connected with write bit line WBL, the backgate of the 8th FinFET pipe B8, the front gate of the 9th FinFET pipe B9,
The backgate of 9th FinFET pipe B9 is connected with readout word line RWL, the drain electrode of the 7th FinFET pipe B7, the drain electrode of the 8th FinFET pipe B8
It is connected with the drain electrode of the 9th FinFET pipe B9, the source electrode of the 9th FinFET pipe B9 is connected with sense bit line RBL.
In the present embodiment, the quantity of the fin of the first FinFET pipe B1 is 1, and the quantity of the fin of the 2nd FinFET pipe B2 is 1, the
The quantity of the fin of three FinFET pipe B3 is 1, and the quantity of the fin of the 4th FinFET pipe B4 is 1, the number of the fin of the 5th FinFET pipe B5
Amount is 1, and the quantity of the fin of the 6th FinFET pipe B6 is 1, and the quantity of the fin of the 7th FinFET pipe B7 is 1, the 8th FinFET pipe B8
The quantity of fin be 1, the quantity of the fin of the 9th FinFET pipe B9 is 1.
In the present embodiment, the threshold voltage of the first FinFET pipe B1 is 0.3v, and the threshold voltage of the 2nd FinFET pipe B2 is
The threshold voltage of 0.3v, the 3rd FinFET pipe B3 are 0.3v, and the threshold voltage of the 4th FinFET pipe B4 is 0.3v, the 5th FinFET
The threshold voltage of pipe B5 is 0.3v, and the threshold voltage of the 6th FinFET pipe B6 is 0.3v, the threshold voltage of the 7th FinFET pipe B7
For 0.3v, the threshold voltage of the 8th FinFET pipe B8 is 0.6v, and the threshold voltage of the 9th FinFET pipe B9 is 0.3v.
In order to verify the single-ended excellent benefit for reading storage unit of the full swing of the invention based on FinFET,
Under BSIMIMG standard technology, under conditions of the input frequency of circuit is 1GHz, circuit is used under the conditions of supply voltage 1V, 0.7V
Emulation tool HSPICE is to the single-ended reading storage unit of the full swing of the invention based on FinFET and shown in FIG. 1
The performance of both circuits of classical storage unit carries out simulation comparison in BSIMIMG technology library, wherein BSIMIMG technology library pair
The standard mains voltage answered is 1V.Reading and writing gimp tolerance is compared simultaneously.Under normal voltage (1v), it is of the invention based on
The single-ended reading storage unit of the full swing of FinFET is based on BSIMIMG standard technology simulation waveform as shown in figure 3, analysis chart
3 it is found that the single-ended reading storage unit of the full swing of the invention based on FinFET has correct work-based logic.
Table 1 be under BSIMIMG standard technology, supply voltage 1V, input frequency be 1GHz when, it is of the invention based on
Two kinds of electricity of classical storage unit in the single-ended reading storage unit of the full swing of FinFET and BSIMIMG technology library shown in FIG. 1
The performance on road compares data.
Table 1
| Circuit types | Transistor size | It is delayed (ps) | Total power consumption (μ W) | Power-consumption design (fJ) |
| The present invention | 9 | 12.66 | 48.36 | 0.612 |
| Classical storage unit | 6 | 18.25 | 57.24 | 1.045 |
As can be drawn from Table 1: the single-ended reading storage unit of the full swing based on FinFET of the invention and and Fig. 1 institute
Classical storage unit is compared in the BSIMIMG technology library shown, and delay reduces 30.63%, and average total power consumption reduces
15.51%, power-consumption design reduces 41.44%.
Table 2 be under BSIMIMG standard technology, supply voltage 0.7V, input frequency be 1GHz when, it is of the invention based on
Two kinds of electricity of classical storage unit in the single-ended reading storage unit of the full swing of FinFET and BSIMIMG technology library shown in FIG. 1
The performance on road compares data.
Table 2
| Circuit types | Transistor size | It is delayed (ps) | Total power consumption (μ W) | Power-consumption design (fJ) |
| The present invention | 9 | 23.11 | 32.85 | 0.759 |
| Classical storage unit | 6 | 30.56 | 39.13 | 1.196 |
As can be drawn from Table 2: the single-ended reading storage unit of the full swing based on FinFET of the invention and and Fig. 1 institute
Classical storage unit is compared in the BSIMIMG technology library shown, and delay reduces 24.38%, and average total power consumption reduces
16.05%, power-consumption design reduces 36.54%.
Table 3 be under BSIMIMG standard technology, supply voltage 0.7V, input frequency be 1GHz when, it is of the invention based on
Two kinds of electricity of classical storage unit in the single-ended reading storage unit of the full swing of FinFET and BSIMIMG technology library shown in FIG. 1
The read operation on road/write operation noise margin compares data.
Table 3
As can be drawn from Table 3: the single-ended reading storage unit of the full swing based on FinFET of the invention and and Fig. 1 institute
Classical storage unit is compared in the BSIMIMG technology library shown, and read noise tolerance increases 221.74%, writes noise margin and increases
108.96%.
By above-mentioned comparison data as it can be seen that the single-ended reading storage unit of the full swing of the invention based on FinFET and figure
Classical storage unit compares in BSIMIMG technology library shown in 1, and the speed of service is improved, the power consumption and power consumption of circuit
Delay product is also optimized, and is solved after voltage divided, it is possible to it is compressed to out the problem for now reading out data inversion mistake,
Data will not malfunction when read operation, and circuit stability is higher.
Claims (3)
1. a kind of single-ended reading storage unit of full swing based on FinFET, it is characterised in that including write word line, write bit line, anti-
Phase write bit line, readout word line, sense bit line, the first FinFET pipe, the 2nd FinFET pipe, the 3rd FinFET pipe, the 4th FinFET pipe, the
Five FinFET pipe, the 6th FinFET pipe, the 7th FinFET pipe, the 8th FinFET pipe and the 9th FinFET pipe, described first
FinFET pipe, the 2nd FinFET pipe and the 7th FinFET pipe are respectively the p-type FinFET pipe of Low threshold, described
The 3rd FinFET pipe, described 4th FinFET pipe, the 5th FinFET pipe, the 6th FinFET pipe and described
The 9th FinFET pipe be respectively to be managed for the N-type FinFET of Low threshold, the described 8th FinFET pipe is the N-type of high threshold
FinFET pipe, the source electrode and the 7th FinFET of the source electrode of the first FinFET pipe, the 2nd FinFET pipe
The source electrode of pipe connects and its connecting pin is the single-ended power end for reading storage unit of the full swing, the single-ended reading of the full swing
The power end of storage unit is for accessing external power supply, the front gate of the first FinFET pipe, the first FinFET pipe
Backgate, the drain electrode of the 2nd FinFET pipe, the front gate of the 3rd FinFET pipe, the 4th FinFET pipe
Before drain electrode, the drain electrode of the 5th FinFET pipe, the backgate of the 5th FinFET pipe, the 7th FinFET pipe
Grid, the 7th FinFET pipe backgate connected with the front gate of the 8th FinFET pipe and its connecting pin is described complete
The amplitude of oscillation single-ended reversed-phase output for reading storage unit, the drain electrode of the first FinFET pipe, the 2nd FinFET pipe
Before front gate, the backgate of the 2nd FinFET pipe, the drain electrode of the 3rd FinFET pipe, the 4th FinFET pipe
Grid, the back-gate connection of the drain electrode of the 6th FinFET pipe and the 6th FinFET pipe and its connecting pin are described complete
The single-ended output end for reading storage unit of the amplitude of oscillation, the source electrode of the 3rd FinFET pipe, the 3rd FinFET pipe backgate,
The source electrode of the source electrode of the 4th FinFET pipe, the backgate of the 4th FinFET pipe and the 8th FinFET pipe connects
It connects and its connecting pin is the single-ended ground terminal for reading storage unit of the full swing, the single-ended reading storage unit of the full swing
Ground terminal is connected for accessing the earth, the source electrode of the 5th FinFET pipe with the reverse phase write bit line, and the described the 5th
The front gate of FinFET pipe, the front gate of the 6th FinFET pipe are connected with the write word line, the 6th FinFET pipe
Source electrode connected with the write bit line, the backgate of the 8th FinFET pipe, the front gate of the 9th FinFET pipe, institute
The backgate for the 9th FinFET pipe stated is connected with the readout word line, the drain electrode of the 7th FinFET pipe, the described the 8th
The drain electrode of FinFET pipe is connected with the drain electrode of the 9th FinFET pipe, the source electrode of the 9th FinFET pipe and described
Sense bit line connection.
2. the single-ended reading storage unit of a kind of full swing based on FinFET according to claim 1, it is characterised in that
The quantity of the fin of the first FinFET pipe is 1, and the quantity of the fin of the 2nd FinFET pipe is 1, the third
The quantity of the fin of FinFET pipe is 1, and the quantity of the fin of the 4th FinFET pipe is 1, the fin of the 5th FinFET pipe
Quantity be 1, the quantity of the fin of the 6th FinFET pipe is 1, and the quantity of the fin of the 7th FinFET pipe is 1, institute
The quantity of the fin for the 8th FinFET pipe stated is 1, and the quantity of the fin of the 9th FinFET pipe is 1.
3. the single-ended reading storage unit of a kind of full swing based on FinFET according to claim 1 or 2, feature exist
It is 0.3v in the threshold voltage of the first FinFET pipe, the threshold voltage of the 2nd FinFET pipe is 0.3v, described
The threshold voltage of the 3rd FinFET pipe be 0.3v, the threshold voltage of the 4th FinFET pipe is 0.3v, the described the 5th
The threshold voltage of FinFET pipe is 0.3v, and the threshold voltage of the 6th FinFET pipe is 0.3v, the 7th FinFET
The threshold voltage of pipe is 0.3v, and the threshold voltage of the 8th FinFET pipe is 0.6v, the threshold of the 9th FinFET pipe
Threshold voltage is 0.3v.
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| CN106448725A (en) * | 2016-09-21 | 2017-02-22 | 宁波大学 | Read/write splitting memory cell based on FinFET (fin field-effect transistor) devices |
| US9627043B1 (en) * | 2014-08-12 | 2017-04-18 | Skan Technologies Corporation | 9T, 8T, and 7T bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write |
| CN106601287A (en) * | 2015-10-15 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | SRAM unit, SRAM and electronic device |
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| US9627043B1 (en) * | 2014-08-12 | 2017-04-18 | Skan Technologies Corporation | 9T, 8T, and 7T bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write |
| CN106601287A (en) * | 2015-10-15 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | SRAM unit, SRAM and electronic device |
| CN105551518A (en) * | 2016-01-07 | 2016-05-04 | 中国科学院上海微系统与信息技术研究所 | SOI single-port SRAM (Static Random Access Memory) unit and a preparation method thereof |
| CN106448725A (en) * | 2016-09-21 | 2017-02-22 | 宁波大学 | Read/write splitting memory cell based on FinFET (fin field-effect transistor) devices |
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