CN103093809A - Static random access memory unit resisting single event upset - Google Patents
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- CN103093809A CN103093809A CN201310007970XA CN201310007970A CN103093809A CN 103093809 A CN103093809 A CN 103093809A CN 201310007970X A CN201310007970X A CN 201310007970XA CN 201310007970 A CN201310007970 A CN 201310007970A CN 103093809 A CN103093809 A CN 103093809A
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Abstract
The invention discloses a static random access memory unit resisting single event upset. The static random memory unit resisting the single event upset comprises a first differential series voltage switch logic unit, a second differential series voltage switch logic unit, a first PMOS (P-channel Metal Oxide Semiconductor) transistor resistor, a second PMOS transistor resistor, a first access NMOS (N-channel Metal Oxide Semiconductor) transistor and a second access NMOS transistor, wherein the first access NMOS transistor is connected with the first differential series voltage switch logic unit, the second access NMOS transistor is connected with the second differential series voltage switch logic unit, the first PMOS transistor resistor and the second PMOS transistor resistor are connected between the first differential series voltage switch logic unit and the second differential series voltage switch logic unit in parallel, and the first differential series voltage switch logic unit and the second differential series voltage switch logic unit constitute a cross-coupling latch.
Description
Technical field
The present invention relates to technical field of integrated circuits, relate more specifically to a kind of primary particle inversion resistant static ram cell.
Background technology
According to data storage method, semiconductor memory is divided into dynamic RAM (DRAM), non-volatility memorizer and static RAM (SRAM).Static RAM can realize operating speed fast in a kind of simple and mode low-power consumption, and, comparing with DRAM, SRAM does not need the periodic refresh canned data, so Design and manufacture is relatively easy.Static RAM thereby set up its unique advantage is used widely in field of data storage.But in the applications such as space, aerospace, the radiation effect that a large amount of high energy particles that exist, cosmic rays etc. produce, as single-particle inversion etc., will cause the loss of memory cell data, destroy thus the normal operation of static RAM, and along with constantly reducing of integration characteristic circuit size, radiation effect increases the weight of for the impact of static ram cell thereupon.Be the specific demand of the applications such as meeting spatial, aerospace, the radiation harden design of static ram cell is become extremely important.
traditional static ram cell is 6 pipe units, as shown in Figure 1, comprise: first, the second driving N MOS transistor 310, 320, first, the second load PMOS transistor 315, 325, wherein the first driving N MOS transistor 310 and the first load PMOS transistor 315 consist of the first phase inverter 31, the second driving N MOS transistor 320 and the second load PMOS transistor 325 consist of the second phase inverter 32, the first phase inverter output is connected with the second phase inverter input, the second phase inverter output is connected with the first phase inverter input, consist of thus cross-linked latch, this latch is connected between positive voltage (VCC) and power supply ground (GND), two access nmos pass transistors 340,341, its drain electrode are connected with first phase inverter output the 312, second phase inverter output 322 respectively, and its source electrode is connected with bit line 301, bit line anti-302 respectively, and its grid all is connected with word line 330.When 6 pipe units were carried out read/write operation, word line 330 was converted to high voltage, two pairs of paratope line read/write data.
Error in data due to the impact of radiation effect, especially when single event occurs, if when arbitrary memory node generation transient state of latch is overturn, all may cause the upset of latch data, thereby occurs in 6 pipe units of traditional structure under radiation environment.
The present invention just is being based on and is addressing the above problem, and has proposed a kind of primary particle inversion resistant static random deposit receipt unit, and this static random deposit receipt unit has 4 cross-linked nodes, and the storage unit of this structure is difficult for occuring single-particle inversion in radiation environment.
Summary of the invention
The technical matters that (one) will solve
In view of this, fundamental purpose of the present invention is to provide a kind of primary particle inversion resistant static ram cell, to reduce static ram cell, the possibility of Data flipping occuring when single event occurs, and then improves the static ram cell anti-radiation performance.
(2) technical scheme
for achieving the above object, the invention provides a kind of primary particle inversion resistant static ram cell, this primary particle inversion resistant static ram cell comprises the first differential series voltage switch logical block 1, the second differential series voltage switch logical block 2, the one PMOS transistor resistance 108, the 2nd PMOS transistor resistance 109, the first access nmos pass transistor 103 and the second access nmos pass transistor 203, wherein, the first access nmos pass transistor 103 is connected in the first differential series voltage switch logical block 1, the second access nmos pass transistor 203 is connected in the second differential series voltage switch logical block 2, the one PMOS transistor resistance 108 and the 2nd PMOS transistor resistance 109 are connected between the first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 concurrently, the first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 consist of cross-linked latch.
In such scheme, described the first differential series voltage switch logical block 1 comprises one first input NMOS transistor 104, one second input NMOS transistor 106, one first load PMOS transistor 105 and one second load PMOS transistor 107, wherein:
The source of the first input NMOS transistor 104 or drain terminal are connected with source or the drain terminal of the first load PMOS transistor 105, consist of the first output out10 of the first differential series voltage switch logical block;
The source of the second input NMOS transistor 106 or drain terminal are connected with source or the drain terminal of the second load PMOS transistor 107, consist of the second output out11 of the first differential series voltage switch logical block;
The grid end of the first input NMOS transistor 104 is the first input in10 of the first differential series voltage switch logical block;
The grid end of the second input NMOS transistor 106 is the second input in11 of the first differential series voltage switch logical block.
In such scheme, the second output out11 of the grid termination first differential series voltage switch logical block of described the first load PMOS transistor 105; The first output out10 of the grid termination first differential series voltage switch logical block of the second load PMOS transistor 107.
In such scheme, described the second differential series voltage switch logical block 2 comprises one the 3rd input PMOS transistor 204, one the 4th input PMOS transistor 206, one the 3rd load nmos pass transistor 205 and one the 4th load nmos pass transistor 207, wherein:
Source or the drain terminal of the 3rd input PMOS transistor 204 are connected with source or the drain terminal of the 3rd load nmos pass transistor 205, consist of the first output out20 of the second differential series voltage switch logical block;
Source or the drain terminal of the 4th input PMOS transistor 206 are connected with source or the drain terminal of the 4th load nmos pass transistor 207, consist of the second output out21 of the second differential series voltage switch logical block;
The grid end of the 3rd input PMOS transistor 204 is the first input in20 of the second differential series voltage switch logical block;
The grid end of the 4th input PMOS transistor 206 is the second input in21 of the second differential series voltage switch logical block.
In such scheme, the second output out21 of the grid termination second differential series voltage switch logical block of described the 3rd load nmos pass transistor 205; The first output out20 of the grid termination second differential series voltage switch logical block of the 4th load nmos pass transistor 207.
In such scheme, the first input in10 of described the first differential series voltage switch logical block is connected with the first output out20 of the second differential series voltage switch logical block; The second input in11 of the first differential series voltage switch logical block is connected with the second output out21 of the second differential series voltage switch logical block; The first output out10 of the first differential series voltage switch logical block is connected with the first input in20 of the second differential series voltage switch logical block through a PMOS transistor resistance 108 of conducting; The second output out11 of the first differential series voltage switch logical block is connected with the second input in21 of the second differential series voltage switch logical block through the 2nd PMOS transistor resistance 109 of conducting; The first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 consist of cross-linked latch thus.
In such scheme, the drain terminal of a described PMOS transistor resistance 108 or source are connected with the first output out10 of the first differential series voltage switch logical block, its grid end is connected with power supply ground, and its source or drain terminal are connected with the first input in20 of the second differential series voltage switch logical block; The drain terminal of described the 2nd PMOS transistor resistance 109 or source are connected with the second output out11 of the first differential series voltage switch logical block, its grid end is connected with power supply ground, and its source or drain terminal are connected with the second input in21 of the second differential series voltage switch logical block.
In such scheme, the drain terminal of described the first access nmos pass transistor 103 or source are connected with the first input in10 of the first differential series voltage switch logical block, and its grid end is connected with word line 102, and its source or drain terminal are connected with bit line 101.
In such scheme, the drain terminal of described the second access nmos pass transistor 203 or source are connected with the second input in11 of the first differential series voltage switch logical block, and its grid end is connected with word line 102, and its source or drain terminal are connected with bit line anti-201.
In such scheme, at this static ram cell and in comprising the array of a plurality of these static ram cells, described word line 102 is vertical with power ground, and described bit line 101 is parallel with power ground, and described bit line anti-201 is parallel with power ground.
(3) beneficial effect
Can find out from technique scheme, primary particle inversion resistant static ram cell provided by the invention, adopt 2 differential series voltage switch logical blocks to consist of latch structure, compare with 6 traditional pipe units and have 2 extra redundant storage nodes, i.e. 4 memory nodes (out10, out11, out20, out21) altogether, wherein any one memory node all is subjected to the control of other 2 memory nodes.Therefore, when wherein upset occurs in any one memory node in single event, the probability that upset occurs other memory nodes reduces greatly, reduce static ram cell the possibility of Data flipping has occured when single event occurs, and then greatly improved the static ram cell anti-radiation performance.In addition, 2 transistor resistances that insert between 2 differential series voltage switch logical blocks, the coupling time of transistor resistance two end nodes in the time of further increasing single event and occur, and then further improve the static ram cell anti-radiation performance.
Description of drawings
At length the foregoing invention content is described by the accompanying drawing image, so that the features and advantages of the invention become more clear, these accompanying drawings comprise:
Shown in Fig. 1 is the circuit diagram of traditional six pipe static ram cells;
Shown in Fig. 2 is circuit diagram according to the primary particle inversion resistant static ram cell of the embodiment of the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, hereinafter, by the reference accompanying drawing, one embodiment of the present of invention will be described in detail.But the present invention can be implemented in many different forms, should not be defined in example given here, this example to provide in order to make the disclosure be thoroughly with complete, and pass on all sidedly thought of the present invention to those skilled in the art.
as shown in Figure 2, shown in Fig. 2 is circuit diagram according to the primary particle inversion resistant static ram cell of the embodiment of the present invention, this primary particle inversion resistant static ram cell comprises the first differential series voltage switch logical block 1, the second differential series voltage switch logical block 2, the one PMOS transistor resistance 108, the 2nd PMOS transistor resistance 109, the first access nmos pass transistor 103 and the second access nmos pass transistor 203, wherein, the first access nmos pass transistor 103 is connected in the first differential series voltage switch logical block 1, the second access nmos pass transistor 203 is connected in the second differential series voltage switch logical block 2, the one PMOS transistor resistance 108 and the 2nd PMOS transistor resistance 109 are connected between the first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 concurrently, the first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 consist of cross-linked latch.
The first differential series voltage switch logical block 1 comprises one first input NMOS transistor 104, one second input NMOS transistor 106, one first load PMOS transistors 105 and one second load PMOS transistors 107; The source of the first input NMOS transistor 104 or drain terminal are connected with source or the drain terminal of the first load PMOS transistor 105, consist of the first output out10 of the first differential series voltage switch logical block; The source of the second input NMOS transistor 106 or drain terminal are connected with source or the drain terminal of the second load PMOS transistor 107, consist of the second output out11 of the first differential series voltage switch logical block; The grid end of the first input NMOS transistor 104 is the first input in10 of the first differential series voltage switch logical block; The grid end of the second input NMOS transistor 106 is the second input in11 of the first differential series voltage switch logical block; The second output out11 of the grid termination first differential series voltage switch logical block of the first load PMOS transistor 105; The first output out10 of the grid termination first differential series voltage switch logical block of the second load PMOS transistor 107.Wherein, source or drain terminal at the first input NMOS transistor 104 are connected with source or the drain terminal of the first load PMOS transistor 105, when consisting of the first output out10 of the first differential series voltage switch logical block, the source that can be both the first input NMOS transistor 104 is connected with source or the drain terminal of the first load PMOS transistor 105, can be also that the drain terminal of the first input NMOS transistor 104 is connected with source or the drain terminal of the first load PMOS transistor 105.Equally, source or drain terminal at the second input NMOS transistor 106 are connected with source or the drain terminal of the second load PMOS transistor 107, when consisting of the second output out11 of the first differential series voltage switch logical block, the source that can be both the second input NMOS transistor 106 is connected with source or the drain terminal of the second load PMOS transistor 107, can be also that the drain terminal of the second input NMOS transistor 106 is connected with source or the drain terminal of the second load PMOS transistor 107.
The second differential series voltage switch logical block 2 comprises one the 3rd input PMOS transistor 204, the 4th input PMOS transistor 206, the 3rd load nmos pass transistor 205 and one the 4th load nmos pass transistor 207; Source or the drain terminal of the 3rd input PMOS transistor 204 are connected with source or the drain terminal of the 3rd load nmos pass transistor 205, consist of the first output out20 of the second differential series voltage switch logical block; Source or the drain terminal of the 4th input PMOS transistor 206 are connected with source or the drain terminal of the 4th load nmos pass transistor 207, consist of the second output out21 of the second differential series voltage switch logical block; The grid end of the 3rd input PMOS transistor 204 is the first input in20 of the second differential series voltage switch logical block; The grid end of the 4th input PMOS transistor 206 is the second input in21 of the second differential series voltage switch logical block; The second output out21 of the grid termination second differential series voltage switch logical block of the 3rd load nmos pass transistor 205; The first output out20 of the grid termination second differential series voltage switch logical block of the 4th load nmos pass transistor 207.Wherein, source or drain terminal at above-mentioned the 3rd input PMOS transistor 204 are connected with source or the drain terminal of the 3rd load nmos pass transistor 205, when consisting of the first output out20 of the second differential series voltage switch logical block, the source that can be both the 3rd input PMOS transistor 204 is connected with source or the drain terminal of the 3rd load nmos pass transistor 205, can be also that the drain terminal of the 3rd input PMOS transistor 204 is connected with source or the drain terminal of the 3rd load nmos pass transistor 205.Equally, source or drain terminal at the 4th input PMOS transistor 206 are connected with source or the drain terminal of the 4th load nmos pass transistor 207, when consisting of the second output out21 of the second differential series voltage switch logical block, the source that can be both the 4th input PMOS transistor 206 is connected with source or the drain terminal of the 4th load nmos pass transistor 207, can be also that the drain terminal of the 4th input PMOS transistor 206 is connected with source or the drain terminal of the 4th load nmos pass transistor 207.
The drain terminal of the one PMOS transistor resistance 108 or source are connected with the first output out10 of the first differential series voltage switch logical block, its grid end is connected with power supply ground, and its source or drain terminal are connected with the first input in20 of the second differential series voltage switch logical block.
The drain terminal of the 2nd PMOS transistor resistance 109 or source are connected with the second output out11 of the first differential series voltage switch logical block, its grid end is connected with power supply ground, and its source or drain terminal are connected with the second input in21 of the second differential series voltage switch logical block.
The first input in10 of the first differential series voltage switch logical block is connected with the first output out20 of the second differential series voltage switch logical block; The second input in11 of the first differential series voltage switch logical block is connected with the second output out21 of the second differential series voltage switch logical block; The first output out10 of the first differential series voltage switch logical block is connected with the first input in20 of the second differential series voltage switch logical block through a PMOS transistor resistance 108 of conducting; The second output out11 of the first differential series voltage switch logical block is connected with the second input in21 of the second differential series voltage switch logical block through the 2nd PMOS transistor resistance 109 of conducting; Thus, the first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 consist of cross-linked latchs, and this latch is connected between positive voltage and power supply ground.
The drain terminal of the first access nmos pass transistor 103 or source are connected with the first input in10 of the first differential series voltage switch logical block, and its grid end is connected with word line 102, and its source or drain terminal are connected with bit line 101.
The drain terminal of the second access nmos pass transistor 203 or source are connected with the second input in11 of the first differential series voltage switch logical block, and its grid end is connected with word line 102, and its source or drain terminal are connected with bit line anti-201.
At this static ram cell and in comprising the array of a plurality of these static ram cells, described word line 102 is vertical with power ground, and described bit line 101 is parallel with power ground, and described bit line anti-201 is parallel with power ground.
When this static ram cell being carried out the one writing operation, bit line 101 is high level, bit line anti-201 is low level, word line 102 is high level, the first access nmos pass transistor 103 and the second access nmos pass transistor 203 are all opened, low level on high level on bit line 101 and bit line anti-201 will be linked into respectively on the first input in10 and the second input in11 of the first differential series voltage switch logical block, and the first output out10 of the first differential series voltage switch logical block goes out and the second output out11 will obtain respectively low level and high level; Annexation according to static ram cell, the first input in20 of the second differential series voltage switch logical block and the second input in21 will obtain respectively low level and high level, the first output out20 of the second differential series voltage switch logical block and the second output out21 will obtain respectively high level and low level, and with the first input in10 of the first differential series voltage switch logical block and high level and the low level coupling on the second input in11, static ram cell is completed the one writing operation respectively; When word line 102 was low level, the first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 consisted of latch structure, keep " 1 " data that write.
When this static ram cell being write " 0 " operation, bit line 101 is low level, bit line anti-201 is high level, word line 102 is high level, the first access nmos pass transistor 103 and the second access nmos pass transistor 203 are all opened, high level on low level on bit line 101 and bit line anti-201 will be linked into respectively on the first input in10 and the second input in11 of the first differential series voltage switch logical block, and the first output out10 of the first differential series voltage switch logical block goes out and the second output out11 will obtain respectively high level and low level; Annexation according to static ram cell, the first input in20 of the second differential series voltage switch logical block and the second input in21 will obtain respectively high level and low level, the first output out20 of the second differential series voltage switch logical block and the second output out21 will obtain respectively low level and high level, and respectively with the first input in10 of series voltage switching logic unit and the low level and high level coupling on the second input in11, static ram cell is completed and is write " 0 " and operate; When word line 102 was low level, the first differential series voltage switch logical block 1 and the second differential series voltage switch logical block 2 consisted of latch structure, keep " 0 " data that write;
when if the static ram cell latch data is " 1 ", namely the first output out20 of second of the first differential series voltage switch logical block the output out11 and the second differential series voltage switch logical block is high level, the second output out21 of the first output out10 of the first differential series voltage switch logical block and the second differential series voltage switch logical block is low level, when single event occurs in consideration in radiation environment, suppose that high energy particle acts on the first output out20 of the second differential series voltage switch logical block, the first output out20 is low level by the high level upset, because high level and the second low level of exporting on out11 on the first output out10 of the first differential series voltage switch logical block are not all overturn, it will act on the second differential series voltage switch logical block 2, the the first output out20 that recovers the second differential series voltage switch logical block is high level, suppose that high energy particle acts on the second output out11 of the first differential series voltage switch logical block, the second output out11 is low level by the high level upset, because high level and the second low level of exporting on out21 on the first output out20 of the second differential series voltage switch logical block are not all overturn, it will act on the first differential series voltage switch logical block 1, the the second output out11 that recovers the first differential series voltage switch logical block is high level, a PMOS transistor resistance 108 of introducing in addition, the 2nd PMOS transistor resistance 109 will suppress the single-ion transient state exporting change of the first differential series voltage switch logical block 1 for the impact of the second differential series voltage switch logical block 2, improve the stability of the output of the second differential series voltage switch logical block 2, and then the second output out11 that guarantees to recover the first differential series voltage switch logical block is high level.
This primary particle inversion resistant static ram cell based on 0.2 μ m technique realization, it is carried out the emulation testing of HSPICE single-particle, can get its single-particle inversion threshold value is 160MeV.cm2/mg, and six traditional pipe static ram cell single-particle inversion threshold values are only 3MeV.cm2/mg.Therefore, primary particle inversion resistant static ram cell provided by the invention can effectively improve the anti-radiation performance of static ram cell.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. primary particle inversion resistant static ram cell, it is characterized in that, this primary particle inversion resistant static ram cell comprises the first differential series voltage switch logical block (1), the second differential series voltage switch logical block (2), the one PMOS transistor resistance (108), the 2nd PMOS transistor resistance (109), the first access nmos pass transistor (103) and the second access nmos pass transistor (203), wherein, the first access nmos pass transistor (103) is connected in the first differential series voltage switch logical block (1), the second access nmos pass transistor (203) is connected in the second differential series voltage switch logical block (2), the one PMOS transistor resistance (108) and the 2nd PMOS transistor resistance (109) are connected between the first differential series voltage switch logical block (1) and the second differential series voltage switch logical block (2) concurrently, the first differential series voltage switch logical block (1) consists of cross-linked latch with the second differential series voltage switch logical block (2).
2. primary particle inversion resistant static ram cell according to claim 1, it is characterized in that, described the first differential series voltage switch logical block (1) comprises one first input NMOS transistor (104), one second input NMOS transistor (106), one first load PMOS transistor (105) and one second load PMOS transistor (107), wherein:
The source of the first input NMOS transistor (104) or drain terminal are connected with source or the drain terminal of the first load PMOS transistor (105), consist of the first output (out10) of the first differential series voltage switch logical block;
The source of the second input NMOS transistor (106) or drain terminal are connected with source or the drain terminal of the second load PMOS transistor (107), consist of the second output (out11) of the first differential series voltage switch logical block;
The grid end of the first input NMOS transistor (104) is the first input (in10) of the first differential series voltage switch logical block;
The grid end of the second input NMOS transistor (106) is the second input (in11) of the first differential series voltage switch logical block.
3. primary particle inversion resistant static ram cell according to claim 2, is characterized in that, the second output (out11) of the grid termination first differential series voltage switch logical block of described the first load PMOS transistor (105); The first output (out10) of the grid termination first differential series voltage switch logical block of the second load PMOS transistor (107).
4. primary particle inversion resistant static ram cell according to claim 1, it is characterized in that, described the second differential series voltage switch logical block (2) comprises one the 3rd input PMOS transistor (204), one the 4th input PMOS transistor (206), one the 3rd load nmos pass transistor (205) and one the 4th load nmos pass transistor (207), wherein:
Source or the drain terminal of the 3rd input PMOS transistor (204) are connected with source or the drain terminal of the 3rd load nmos pass transistor (205), consist of the first output (out20) of the second differential series voltage switch logical block;
Source or the drain terminal of the 4th input PMOS transistor (206) are connected with source or the drain terminal of the 4th load nmos pass transistor (207), consist of the second output (out21) of the second differential series voltage switch logical block;
The grid end of the 3rd input PMOS transistor (204) is the first input (in20) of the second differential series voltage switch logical block;
The grid end of the 4th input PMOS transistor (206) is the second input (in21) of the second differential series voltage switch logical block.
5. primary particle inversion resistant static ram cell according to claim 4, is characterized in that, the second output (out21) of the grid termination second differential series voltage switch logical block of described the 3rd load nmos pass transistor (205); The first output (out20) of the grid termination second differential series voltage switch logical block of the 4th load nmos pass transistor (207).
6. according to claim 2 or 4 described primary particle inversion resistant static ram cells, it is characterized in that, the first input (in10) of described the first differential series voltage switch logical block is connected with the first output (out20) of the second differential series voltage switch logical block; The second input (in11) of the first differential series voltage switch logical block is connected with the second output (out21) of the second differential series voltage switch logical block; The first output (out10) of the first differential series voltage switch logical block is connected with the first input (in20) of the second differential series voltage switch logical block through a PMOS transistor resistance (108) of conducting; The second output (out11) of the first differential series voltage switch logical block is connected with the second input (in21) of the second differential series voltage switch logical block through the PMOS transistor resistance (109) of conducting; The first differential series voltage switch logical block (1) consists of cross-linked latch with the second differential series voltage switch logical block (2) thus.
7. primary particle inversion resistant static ram cell according to claim 6, it is characterized in that, the drain terminal of a described PMOS transistor resistance (108) or source are connected with the first output (out10) of the first differential series voltage switch logical block, its grid end is connected with power supply ground, and its source or drain terminal are connected with the first input (in20) of the second differential series voltage switch logical block;
The drain terminal of described the 2nd PMOS transistor resistance (109) or source are connected with the second output (out11) of the first differential series voltage switch logical block, its grid end is connected with power supply ground, and its source or drain terminal are connected with the second input (in21) of the second differential series voltage switch logical block.
8. primary particle inversion resistant static ram cell according to claim 6, it is characterized in that, the drain terminal of described the first access nmos pass transistor (103) or source are connected with the first input (in10) of the first differential series voltage switch logical block, its grid end is connected with word line (102), and its source or drain terminal are connected with bit line (101).
9. primary particle inversion resistant static ram cell according to claim 6, it is characterized in that, the drain terminal of described the second access nmos pass transistor (203) or source are connected with the second input (in11) of the first differential series voltage switch logical block, its grid end is connected with word line (102), and its source or drain terminal are connected with bit line anti-(201).
10. primary particle inversion resistant static ram cell according to claim 1, it is characterized in that, at this static ram cell and in comprising the array of a plurality of these static ram cells, described word line (102) is vertical with power ground, described bit line (101) is parallel with power ground, and described bit line anti-(201) is parallel with power ground.
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| CN103366802A (en) * | 2013-06-26 | 2013-10-23 | 清华大学 | Static random storage unit |
| CN104409103A (en) * | 2014-09-22 | 2015-03-11 | 中国空间技术研究院 | Novel two-dimensional coding reinforcing method and circuit arrangement for aerospace memory |
| CN108766492A (en) * | 2017-12-28 | 2018-11-06 | 北京时代民芯科技有限公司 | A kind of anti-SEU storage unit circuits of low single-particle sensibility |
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