CN103366802B - A kind of static ram cell - Google Patents
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Abstract
Disclosure one static ram cell, including: trombone slide, first to fourth time trombone slide, first to fourth load pipe on first to fourth, and first to fourth pipe.The static ram cell of the present invention is on traditional DICE architecture basics, load pipe is increased, owing to the threshold voltage of load pipe is negative value, then when without soft error between the drain electrode of lower trombone slide and the drain electrode of upper trombone slide, load pipe is conducting state always, keeps storage information；When there being soft error, the feedback mechanism of load pipe and redundancy structure, can recover storage information.The present invention has that soft fault preventing ability is strong, the high and low power consumption of stability and the advantage with business logic process compatible.
Description
Technical field
The present invention relates to memory element, more specifically a kind of static ram cell.
Background technology
SRAM(StaticRandomAccessMemory), i.e. static RAM, SRAM, as the Major Members of semiconductor memory extended familys, is most widely used memorizer in the world, and it is indispensable parts in digital processing, information processing, automatic controlling device.
When deep submicron process, chip internal transmutability increases day by day, supply voltage VDD day by day reduces, SRAM memory cell stability is under some influence, and along with device size scaled down, chip integration raises, and packaging density rises, this a series of change all can cause some beyond thought problems so that the less reliable of semiconductor storage unit.Soft error (SoftError) problem that high energy charged particles incidence sram cell sensitive nodes causes just is increasingly subject to pay close attention to.Along with process node be gradually lowered, memory element power consumption become SRAM design great challenge.System on a ship designs in the urgent need to high reliability low-power consumption SRAM memory element.
Along with the fast development of space technology, increasing SRAM device is applied in the control system of all kinds of spacecraft and satellite.In space radiation environment, high energy particle (proton, neutron, alpha-particle and other heavy ions) can cause single particle effect (SingleEventEffect, SEE) when bombarding the sensitizing range of microelectronic circuit.High energy charged particles injects semiconductor device, by interacting with semi-conducting material, loses energy soon.The energy that charged particle loses, is that electronics jumps to conduction band from valence band.Then in conduction band, there is electronics, valence band has stayed hole, formed electron hole pair, introduced nonequilibrium carrier.When having electric field, electron hole pair moves in the opposite direction under the effect of electric field, is collected by different electrodes, forms transient current.Transient current can make node potential change, causes device logic state to overturn.Generally, it is considered that the space-charge region of blanking tube drain region reverse biased pn junction constitutes the sensitive volume of device, its electric field is enough to make electron hole pair separate, and is collected by electrode.This due to particle bombardment time the single particle effect that produces and change the phenomenon of the logic state of memory element, be called single-particle inversion (SingleEventUpset, SEU), be one of topmost integrity problem of facing of various spacecraft.
As it is shown in figure 1, tradition 6T-SRAM memory element, it is assumed that it stores state in the hold mode is ' 1 ', and namely Q=1, Qn=0, N1, P2 pipe end, and N2, P1 pipe turns on.So, the space-charge region of N1, P2 pipe drain region reverse biased pn junction is exactly the sensitive volume of device single-particle inversion.Assume now, have the drain region of a high-energy particle bombardment N1 pipe, N1 is managed, the transient current that charged particle causes, make drain potential reduce.When drain potential has high level to drop to low level, but when P1 pipe still turns on, the state of memory element is unstable.On the one hand, node Q is charged by power vd DI by P1 pipe so that it is current potential rises, and returns to original state；On the other hand, Q point current potential reduces, and is coupled to the grid of N2, P2 pipe, makes the cut-off of N2 pipe, P2 conducting, and the current potential of node Qn raises, and feeds back to the grid of N1, P1 pipe further, makes the conducting of N1 pipe, the cut-off of P1 pipe.Such a feedback procedure (ablation process of similar SRAM memory element) makes the state of memory element thoroughly be become " 0 " from " 1 ", and single-particle inversion occurs, and is all the focus studied to reinforcing for a long time of SEU.
The DICE(DualInterlockedstorageCell of 12 pipes) memory element is as in figure 2 it is shown, be common circuit design SEU reinforcement technique, due to its symmetrical configuration, uses number of transistors less, receives most commonly used concern.Assume in the hold mode, original state X0, X1, X2, X3 respectively 0,1,0,1.When particle bombardment N1 space-charge region, drain region, it is 0 that X1 will be pulled low, and X2 point also will be essentially pulled up to 1, N0 by P2, the cut-off of P3 pipe, P0, N3 pipe also can keep cut-off state constant, therefore X0, X3 point remains 0,1, the value of the two node can feed back to by bombardment node, gives by bombardment node supplemental current, after the electric charge of particle bombardment ionization generation has been collected, X1, X2 can be restored to 1,0, thus suppressing upset.But, when particle bombardment P2 space-charge region, drain region, it is 1 that X2 will be pulled up, and X1 point also will pulled down to 0, N0 by N1, the cut-off of P3 pipe, P0, N3 pipe also can keep cut-off state constant, therefore X0, X3 point remains 0,1, causes that N1, P1 pipe is both turned on, and X1 node voltage is uncertain, after the electric charge of particle bombardment ionization generation has been collected, there is bigger loss probability in DICE unit stored information.Meanwhile, in read mode, 2 pairs of nodes of the inside of DICE unit by reading and writing pipe connection, will destroy the self-recoverage mechanism of DICE unit, thus causing the lasting upset of unit.Particularly when particle bombardment stores the node of information 0, owing to bit line BL, BLn are high level by preliminary filling so that the pull-down NMOS pipe of cut-off is easier to open, and pull-down capability is relatively strong, destroys the self-recoverage mechanism of DICE unit, stores information dropout.Probability is overturn, thus causing allowing of no optimist based on working condition under the reinforcing sram chip heavy ion environment of DICE unit owing to tradition DICE unit exists stronger 0-1 under maintenance, reading mode.
The demand of defect and reply rapid technological growth in order to overcome above-mentioned prior art, needs a kind of Novel static random memory unit of offer badly.
Summary of the invention
It is contemplated that solve one of above-mentioned technical problem at least to a certain extent or provide at a kind of useful business selection.For this, it is an object of the invention to propose a kind of high stability, static ram cell to soft error immunity.
The static ram cell that the present invention proposes, including: trombone slide P0 to P3, first to fourth time trombone slide N0 to N3, first to fourth load pipe ND0 to ND3 on first to fourth, and first to fourth pipe NG0 to NG3, wherein, first pipe NG0, the 3rd pipe NG2 grid are controlled by wordline WL, drain electrode is connected with bit line BL, and first pipe NG0 source electrode and first time trombone slide N0 drain electrode are connected, and the 3rd pipe NG2 source electrode and the 3rd time trombone slide N2 drain electrode are connected；Second pipe NG1, the 4th pipe NG3 grid are controlled by wordline WL, and drain electrode is connected with bit line BLn, and second pipe NG1 source electrode and second time trombone slide N1 drain electrode are connected, and the 4th pipe NG3 source electrode and the 4th time trombone slide N3 drain electrode are connected；First time trombone slide N0, the 3rd time trombone slide N2 grid are respectively with trombone slide P2 on the 3rd, trombone slide P0 grid is connected on first, first time trombone slide N0 drain electrode is connected with the 4th time trombone slide N3 grid, 3rd time trombone slide N2 drain electrode is connected with second time trombone slide N1 grid, and source electrode is connected with VSS；Second time trombone slide N1, the 4th time trombone slide N3 grid are respectively with trombone slide P3 on the 4th, trombone slide P1 grid is connected on first, second time trombone slide N1 drain electrode is connected with first time trombone slide N0 grid, 4th time trombone slide N3 drain electrode is connected with the 3rd time trombone slide N2 grid, and source electrode is connected with VSS；Trombone slide P0 on first, trombone slide P2 grid is connected with the 3rd time trombone slide N2, first time trombone slide N0 grid respectively on the 3rd, on first, trombone slide P0 drain electrode is connected with the first load pipe ND0 drain electrode, on 3rd, trombone slide P2 drain electrode is connected with the 3rd load pipe ND2 drain electrode, and source electrode is controlled by supply voltage VDD；Trombone slide P1 on second, trombone slide P3 grid is connected with the 4th time trombone slide N3, second time trombone slide N1 grid respectively on the 4th, on second, trombone slide P1 drain electrode is connected with the second load pipe ND1 drain electrode, on 4th, trombone slide P3 drain electrode is connected with the 4th load pipe ND3 drain electrode, and source electrode is controlled by supply voltage VDD；First load pipe ND0 grid and the 3rd pipe NG2 source electrode are connected, and source electrode and first time trombone slide N0 drain electrode, the 4th time trombone slide N3 grid are connected, and drain and are connected with trombone slide P0 drain electrode on first；Second load pipe ND1 grid and the 4th pipe NG3 source electrode are connected, and source electrode and second time trombone slide N1 drain electrode, first time trombone slide N0 grid are connected, and drain and are connected with trombone slide P1 drain electrode on second；3rd load pipe ND2 grid and first pipe NG0 source electrode are connected, and source electrode and the 3rd time trombone slide N2 drain electrode, second time trombone slide N1 grid are connected, and drain and are connected with trombone slide P2 drain electrode on the 3rd；4th load pipe ND3 grid and second pipe NG1 source electrode are connected, and source electrode and the 4th time trombone slide N3 drain electrode, the 3rd time trombone slide N2 grid are connected, and drain and are connected with trombone slide P3 drain electrode on the 4th.
In sum, there is extremely strong immunocompetence in 0-1,1-0 soft error that single particle effect is caused by the static ram cell of the present invention under maintenance, reading mode.The high and low power consumption of stability of the present invention and with business logic process compatible, be hopeful to replace traditional DICE-SRAM memory element and become the optimized integration of SRAM to soft error immunity.
The additional aspect of the present invention and advantage will part provide in the following description, and part will become apparent from the description below, or is recognized by the practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or the additional aspect of the present invention and advantage are from conjunction with will be apparent from easy to understand the accompanying drawings below description to embodiment, wherein:
Fig. 1 is the circuit diagram of tradition 6T-SRAM memory element；
Fig. 2 is the circuit diagram of traditional 12T-DICE memory element；
Fig. 3 is the circuit diagram of the static ram cell of the embodiment of the present invention；
Fig. 4 is the reading precharging circuit figure of the static ram cell of the embodiment of the present invention under reading mode.
Detailed description of the invention
Being described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of same or like function from start to finish.The embodiment described below with reference to accompanying drawing is illustrative of, it is intended to is used for explaining the present invention, and is not considered as limiting the invention.
Shortcoming for the existing static random access memory cell mentioned in above-mentioned background, the present invention provides a kind of static random access memory cell, this structure is while realizing high stability, and the memory element soft error that there may exist under reading, maintenance state is thoroughly immune.
The static random access memory cell of the present invention is compared with DICE static random access memory cell, between original pull-up PMOS and pull-down NMOS pipe, increase threshold voltage is negative load NMOS tube, reduce leakage current, add the feedback network of storage information simultaneously.When any individual node overturns, it is possible to voluntarily by the Information recovering of redundant node.
The threshold voltage increased in invention unit structure is negative load NMOS tube, can adopt standard logic process manufacture.With common NMOS tube manufacturing process the difference is that, it is necessary to extra increase LVN and VTPH two-layer.
As it is shown on figure 3, the static ram cell of the embodiment of the present invention, including: trombone slide P0 to P3, first to fourth time trombone slide N0 to N3, first to fourth load pipe ND0 to ND3 on first to fourth, and first to fourth pipe NG0 to NG3.Wherein:
First pipe NG0, the 3rd pipe NG2 grid are controlled by wordline WL, and drain electrode is connected with bit line BL, and first pipe NG0 source electrode and first time trombone slide N0 drain electrode are connected, and the 3rd pipe NG2 source electrode and the 3rd time trombone slide N2 drain electrode are connected；
Second pipe NG1, the 4th pipe NG3 grid are controlled by wordline WL, and drain electrode is connected with bit line BLn, and second pipe NG1 source electrode and second time trombone slide N1 drain electrode are connected, and the 4th pipe NG3 source electrode and the 4th time trombone slide N3 drain electrode are connected；
First time trombone slide N0, the 3rd time trombone slide N2 grid are respectively with trombone slide P2 on the 3rd, trombone slide P0 grid is connected on first, first time trombone slide N0 drain electrode is connected with the 4th time trombone slide N3 grid, 3rd time trombone slide N2 drain electrode is connected with second time trombone slide N1 grid, and source electrode is connected with VSS；
Second time trombone slide N1, the 4th time trombone slide N3 grid are respectively with trombone slide P3 on the 4th, trombone slide P1 grid is connected on first, second time trombone slide N1 drain electrode is connected with first time trombone slide N0 grid, 4th time trombone slide N3 drain electrode is connected with the 3rd time trombone slide N2 grid, and source electrode is connected with VSS；
Trombone slide P0 on first, trombone slide P2 grid is connected with the 3rd time trombone slide N2, first time trombone slide N0 grid respectively on the 3rd, on first, trombone slide P0 drain electrode is connected with the first load pipe ND0 drain electrode, on 3rd, trombone slide P2 drain electrode is connected with the 3rd load pipe ND2 drain electrode, and source electrode is controlled by supply voltage VDD；
Trombone slide P1 on second, trombone slide P3 grid is connected with the 4th time trombone slide N3, second time trombone slide N1 grid respectively on the 4th, on second, trombone slide P1 drain electrode is connected with the second load pipe ND1 drain electrode, on 4th, trombone slide P3 drain electrode is connected with the 4th load pipe ND3 drain electrode, and source electrode is controlled by supply voltage VDD；
First load pipe ND0 grid and the 3rd pipe NG2 source electrode are connected, and source electrode and first time trombone slide N0 drain electrode, the 4th time trombone slide N3 grid are connected, and drain and are connected with trombone slide P0 drain electrode on first；
Second load pipe ND1 grid and the 4th pipe NG3 source electrode are connected, and source electrode and second time trombone slide N1 drain electrode, first time trombone slide N0 grid are connected, and drain and are connected with trombone slide P1 drain electrode on second；
3rd load pipe ND2 grid and first pipe NG0 source electrode are connected, and source electrode and the 3rd time trombone slide N2 drain electrode, second time trombone slide N1 grid are connected, and drain and are connected with trombone slide P2 drain electrode on the 3rd；
4th load pipe ND3 grid and second pipe NG1 source electrode are connected, and source electrode and the 4th time trombone slide N3 drain electrode, the 3rd time trombone slide N2 grid are connected, and drain and are connected with trombone slide P3 drain electrode on the 4th.
From the foregoing, it will be observed that on traditional DICE architecture basics, increase load pipe ND0, ND1, ND2, ND3 between lower trombone slide N0, N1, N2, N3 drain electrode and upper trombone slide P0, P1, P2, P3 drain electrode.Owing to the threshold voltage of load pipe ND0, ND1, ND2, ND3 is negative value, then when without soft error, load pipe ND0, ND1, ND2, ND3 are conducting state always, keep storage information.
In the hold mode, when a memory node (example, X0, X1, X2, X3 respectively 0,1,0,1) it is subject to soft error impact, such as high-energy particle bombardment sensitive nodes X1, lower trombone slide N1 drain region, produces single particle effect and changes memory node X1 when being become 0 by 1, will cause that N0 turns off, P2 turns on, and X2 node voltage rises.But, 1 is remained owing to X3 node voltage is not affected, upper trombone slide P0 ends, X0 node voltage is not affected and remains as 0, so when X2 node voltage rise between load pipe ND2 grid and source electrode voltage difference absolute value less than threshold voltage absolute value after, load pipe ND2 ends, and remains 1 owing to X3 node voltage is not affected, lower trombone slide N2 turns on, and X2 node voltage is by decline recovery 0.And now, the grid of load pipe ND1 is 1, the grid causing load pipe ND1 is produced bigger voltage difference with source electrode by this, and On current increases.After the pulse current produced when high-energy particle bombardment disappears, it is not affected by affecting or being affected recovering owing to X2, X3, X0 memory node stores information, upper trombone slide P1 turns on, and X1 node storage electric capacity is pulled up pipe P1 and load pipe ND1 write 1 again, and lost storage information is restored.
In read mode, reading precharging circuit structure of the present invention is as shown in Figure 4.Wherein N1, N2 are diode connected mode so that bit line BL, BLn voltage is not less than VDD-Vthn。
When a memory node (example, X0, X1, X2, X3 respectively 0,1,0,1) is subject to soft error impact, such as high-energy particle bombardment sensitive nodes X1, lower trombone slide N1 drain region, produce single particle effect and change memory node X1 when being become 0 by 1.Although in read mode, door pipe NG0, NG1, NG2, NG3 are both turned on, but due to the special precharging circuit structure of the present invention, it is ensured that bit line BL, BLn voltage is not less than VDD-Vthn.The single particle effect that sensitive nodes X1 produces is for sensitive nodes X3 almost without impact, and this structure is similar with keeping pattern recovery mechanism in the Restoration Mechanism of reading mode, does not repeat them here.
Under maintenance, reading mode, when a memory node (example, X0, X1, X2, X3 respectively 0,1,0,1) is subject to soft error impact, such as high-energy particle bombardment sensitive nodes X2', upper trombone slide P2 drain region, produces single particle effect and changes upper trombone slide P2 drain region when being become 1 by 0.Constantly on load pipe ND2 act as resistance, and the voltage greatly weakening the memory node X2 that single particle effect causes rises.Owing to memory node X0 voltage is constant, memory node X2 voltage rises, after grid and the source voltage difference of load pipe ND2 is less than ND2 pipe threshold voltage, load pipe ND2 turns off, memory node X2 voltage will no longer rise, after the pulse current produced when high-energy particle bombardment disappears, it is not affected by impact owing to X0, X1, X3 memory node stores information, X2 storage node voltage is unsatisfactory for lower trombone slide N1 conducting, upper trombone slide P2 turns off, X2 node storage electric capacity is pulled down pipe N2 electric discharge and re-writes 0, and stored information is not affected by single particle effect impact.
In sum, there is extremely strong immunocompetence in 0-1,1-0 soft error that single particle effect is caused by the static ram cell of the present invention under maintenance, reading mode.The high and low power consumption of stability of the present invention and with business logic process compatible, be hopeful to replace traditional DICE-SRAM memory element and become the optimized integration of SRAM to soft error immunity.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means in conjunction with this embodiment or example describe are contained at least one embodiment or the example of the present invention.In this manual, the schematic representation of above-mentioned term is not necessarily referring to identical embodiment or example.And, the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiments or example.
Although above it has been shown and described that embodiments of the invention, it is understandable that, above-described embodiment is illustrative of, being not considered as limiting the invention, above-described embodiment can be changed when without departing from principles of the invention and objective, revises, replace and modification by those of ordinary skill in the art within the scope of the invention.
Claims (1)
1. a static ram cell, it is characterised in that including:
Trombone slide P0 to P3, first to fourth time trombone slide N0 to N3, first to fourth load pipe ND0 to ND3 on first to fourth, and first to fourth pipe NG0 to NG3, wherein,
On first to fourth, trombone slide P0 to P3 is PMOS, and first to fourth time trombone slide N0 to N3 is NMOS tube, and first to fourth load pipe ND0 to ND3 is threshold voltage is negative NMOS tube；
First pipe NG0, the 3rd pipe NG2 grid are controlled by wordline WL, and drain electrode is connected with bit line BL, and first pipe NG0 source electrode and first time trombone slide N0 drain electrode are connected, and the 3rd pipe NG2 source electrode and the 3rd time trombone slide N2 drain electrode are connected；
Second pipe NG1, the 4th pipe NG3 grid are controlled by wordline WL, and drain electrode is connected with bit line BLn, and second pipe NG1 source electrode and second time trombone slide N1 drain electrode are connected, and the 4th pipe NG3 source electrode and the 4th time trombone slide N3 drain electrode are connected；
First time trombone slide N0, the 3rd time trombone slide N2 grid are respectively with trombone slide P2 on the 3rd, trombone slide P0 grid is connected on first, first time trombone slide N0 drain electrode is connected with the 4th time trombone slide N3 grid, 3rd time trombone slide N2 drain electrode is connected with second time trombone slide N1 grid, and source electrode is connected with VSS；
Second time trombone slide N1, the 4th time trombone slide N3 grid are respectively with trombone slide P3 on the 4th, trombone slide P1 grid is connected on first, second time trombone slide N1 drain electrode is connected with first time trombone slide N0 grid, 4th time trombone slide N3 drain electrode is connected with the 3rd time trombone slide N2 grid, and source electrode is connected with VSS；
Trombone slide P0 on first, trombone slide P2 grid is connected with the 3rd time trombone slide N2, first time trombone slide N0 grid respectively on the 3rd, on first, trombone slide P0 drain electrode is connected with the first load pipe ND0 drain electrode, on 3rd, trombone slide P2 drain electrode is connected with the 3rd load pipe ND2 drain electrode, and source electrode is controlled by supply voltage VDD；
Trombone slide P1 on second, trombone slide P3 grid is connected with the 4th time trombone slide N3, second time trombone slide N1 grid respectively on the 4th, on second, trombone slide P1 drain electrode is connected with the second load pipe ND1 drain electrode, on 4th, trombone slide P3 drain electrode is connected with the 4th load pipe ND3 drain electrode, and source electrode is controlled by supply voltage VDD；
First load pipe ND0 grid and the 3rd pipe NG2 source electrode are connected, and source electrode and first time trombone slide N0 drain electrode, the 4th time trombone slide N3 grid are connected, and drain and are connected with trombone slide P0 drain electrode on first；
Second load pipe ND1 grid and the 4th pipe NG3 source electrode are connected, and source electrode and second time trombone slide N1 drain electrode, first time trombone slide N0 grid are connected, and drain and are connected with trombone slide P1 drain electrode on second；
3rd load pipe ND2 grid and first pipe NG0 source electrode are connected, and source electrode and the 3rd time trombone slide N2 drain electrode, second time trombone slide N1 grid are connected, and drain and are connected with trombone slide P2 drain electrode on the 3rd；
4th load pipe ND3 grid and second pipe NG1 source electrode are connected, and source electrode and the 4th time trombone slide N3 drain electrode, the 3rd time trombone slide N2 grid are connected, and drain and are connected with trombone slide P3 drain electrode on the 4th.
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| CN103956184B (en) | 2014-05-16 | 2017-01-04 | 中国科学院微电子研究所 | A kind of improvement SRAM memory cell based on DICE structure |
| CN104409093B (en) * | 2014-12-09 | 2017-07-28 | 复旦大学 | The transistor memory unit of difference 10 of anti-single particle reversion |
| CN104700889B (en) * | 2015-03-27 | 2017-08-25 | 中国科学院自动化研究所 | The memory cell of static random-access memory based on DICE structures |
| CN108831515A (en) * | 2018-05-17 | 2018-11-16 | 上海华虹宏力半导体制造有限公司 | SRAM memory cell |
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