CN106847333B - A kind of novel anti-single particle SRAM bit cell - Google Patents
A kind of novel anti-single particle SRAM bit cell Download PDFInfo
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- CN106847333B CN106847333B CN201710024711.6A CN201710024711A CN106847333B CN 106847333 B CN106847333 B CN 106847333B CN 201710024711 A CN201710024711 A CN 201710024711A CN 106847333 B CN106847333 B CN 106847333B
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- nmos
- pmos
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
The invention discloses a kind of novel anti-single particle SRAM bit cells, by NMOS feedback arrangement, PMOS feedback arrangement, transferring structure, isolation structure and read-write structure composition.The novel anti-single particle SRAM bit cell of the present invention, which only uses 10 transistors, which to be built, can be realized: if only single storage point is overturn because of single-particle, no matter particle influence time, must can restore；If two second storage points are all overturn because of single-particle, can equally restore；Each storage point is at least connected with five points, and capacitor is larger, and turn threshold is big；At most connect PMOS and two NMOS between power supply and ground, and pressure drop is small, it is ensured that driving capability；Suitable for the identical read/write circuit of traditional 6T bit location, the original circuit of convenient substituting.
Description
Technical field
The invention belongs to technical field of integrated circuits, specifically, being to be related to a kind of novel primary particle inversion resistant SRAM
Bit location.
Background technique
In order to meet the needs of user is growing to computing capability, semiconductor technology node quickly reduces.Semiconductor device
Part size reduces, and leads to the reduction of transistor node capacitor, and at the same time, the supply voltage of circuit is also accordingly reducing, in
It is the quantity of electric charge stored on node is even more sharp-decay.In this case, single event (Single Event
Phenomena soft error caused by) (Soft Error) is not only considered in space application by emphasis, in Ground Application
Gradually it is taken seriously.On piece SRAM(Static RAM) on piece major part area generally is occupied, therefore, become generation single-particle
Overturn the severely afflicated area of (Single Event Upset) soft error.And equally because of the reduction of process node, caused by single-particle
Charge shares effect and parasitic bipolar transistor effect makes multiple node overturnings in circuit, causes higher soft error rate
(Soft Error Rate).
Because soft error caused by radiating particle has seriously affected the stability of system, in order to alleviate soft error, integrated circuit
System designer reinforces system from each level.
In terms of the Design of Reinforcement to SRAM bit cell (Bit Cell), T.Calin etc. is in IEEE Transactions
Article " the Upset hardened memory design for submicron CMOS of on Nuclear Science
Technology " gives a kind of reinforcing mode DICE structure (Dual Interlocked Storage Cell) of classics.If
For SRAM, this is 12 transistors (12T).The structure is using double feedback arrangements, so that any one storage section
When point is overturn, it can be corrected in time by another feedback arrangement.But in this configuration, if a memory node
It overturns, directly results in control its 2 node restored and lose driving, in a kind of highly unstable state, so once
Radiating particle influences any other any one memory node, and the storage information of the unit will overturn, can not correct.
Article " the A Soft in IEEE Transactions on Nuclear Science such as S.M.Jahinuzzaman
Error Tolerant 10T SRAM Bit-Cell with differential Read Capability " gives one kind
Equally more classical structure Quatro-10T.This structure increases the impedances that memory node influences its recovery nodes, so that
The structure to the lesser example of energy have preferable immunocompetence, once but particle effect duration is longer so that grain
Sub- effect is diffused into its recovery nodes, and the information of unit storage will be overturn, and can not correct.
There are also the improvement structure of the more design based on original 6T structure, these structures are not changing original bit location knot
In the case where structure, auxiliary transistor is added, so that particle influences diffusion velocity and reduces, or is increased based on certain existing ruggedized construction
Add its literacy etc., because these structures still are based on original 6T structure, is difficult the overturning in single-point last longer
Lower holding original information.
In terms of current existing technical solution, Design of Reinforcement is still the tradeoff of area, speed, stability and feasibility,
In the simple Design of Reinforcement for bit location, repaired almost without single-point overturning, the overturning of support section multiple spot is repaired, pressure drop is small,
Compatible 6T read/write circuit and the design less using transistor.
Summary of the invention
The present invention in view of the above shortcomings of the prior art, gives a kind of novel anti-single particle SRAM bit cell structure,
There is the structure single-point overturning to repair, the overturning of support section multiple spot is repaired, pressure drop is small, compatible 6T read/write circuit and only use 10
The advantages that transistor.
For achieving the above object, the present invention is mentioned adopting the following technical solutions and is achieved:
A kind of novel anti-single particle SRAM bit cell comprising
NMOS feedback arrangement, including the first NMOS and the 2nd NMOS, the source electrode of the first NMOS and the 2nd NMOS
Ground connection, the drain electrode of the first NMOS connect the grid of the 2nd NMOS, and the drain electrode of the 2nd NMOS meets the first NMOS
Grid, the drain electrode of the first NMOS is the first positive storage point Q, and the drain electrode of the 2nd NMOS is first instead to store point QN；
PMOS feedback arrangement, including the first PMOS and the 2nd PMOS, the source electrode of the first PMOS and the 2nd PMOS
Power supply is connect, the drain electrode of the first PMOS connects the grid of the 2nd PMOS, and the drain electrode of the 2nd PMOS connects described first
The grid of PMOS, the drain electrode of the first PMOS are the second positive storage point QU, and the drain electrode of the 2nd PMOS is the second anti-storage
Point QUN；
The source electrode of transferring structure, including the 3rd NMOS and the 4th NMOS, the 3rd NMOS and the 4th NMOS are grounded,
The grid of 3rd NMOS meets the described first positive storage point Q, and the drain electrode of the 3rd NMOS connects the described second anti-storage point
QUN, the grid of the 4th NMOS meet the described first anti-storage point QN, and the drain electrode of the 4th NMOS connects the described second positive storage
Point QU；
Isolation structure, including the 5th NMOS and the 6th NMOS, the source electrode of the 5th NMOS connect the described first positive storage point
Q, the drain and gate of the 5th NMOS meet the described second positive storage point QU, and it is anti-that the source electrode of the 6th NMOS connects described first
Point QN is stored, the drain and gate of the 6th NMOS meets the described second anti-storage point QUN；
Structure is read and write, including the grid of the 7th NMOS and the 8th NMOS, the 7th NMOS and the 8th NMOS connect word
Line WL, the source electrode of the 7th NMOS meet positive bit line BL, and the drain electrode of the 7th NMOS meets the described first positive storage point Q, described
The reversed bit line BLN of the source electrode of 8th NMOS, the drain electrode of the 8th NMOS meet the described first anti-storage point QN.
Compared with prior art, the advantages and positive effects of the present invention are: the novel anti-single particle SRAM bit cell of the present invention
Only using 10 transistors and building can be realized: if only single storage point is overturn because of single-particle, no matter particle influence time, must
Surely can restore；If two second storage points are all overturn because of single-particle, can equally restore；Each storage point is at least connected with five
A, capacitor is larger, and turn threshold is big；At most connect PMOS and two NMOS between power supply and ground, and pressure drop is small, it is ensured that
Driving capability；Suitable for the identical read/write circuit of traditional 6T bit location, the original circuit of convenient substituting.
After a specific embodiment of the invention is read in conjunction with the figure, the other features and advantages of the invention will become more clear
Chu.
Detailed description of the invention
Fig. 1 is the schematic diagram of the specific embodiment of the invention.
Specific embodiment
The technical scheme of the present invention will be explained in further detail with reference to the accompanying drawings and detailed description.
As shown in Figure 1, the novel anti-single particle SRAM bit cell of the present embodiment by NMOS feedback arrangement, PMOS feedback arrangement,
Transferring structure, isolation structure and read-write structure composition.
NMOS feedback arrangement includes the first NMOS(N1) and the 2nd NMOS(N2).First NMOS(N1) and the 2nd NMOS(N2)
Source electrode be grounded (GND), the first NMOS(N1) drain electrode meet the 2nd NMOS(N2) grid, the 2nd NMOS(N2) drain electrode connect the
One NMOS(N1) grid.Wherein, the first NMOS(N1) drain electrode be the first positive storage point (Q), the 2nd NMOS(N2) drain electrode
It is the first anti-storage point (QN).
PMOS feedback arrangement includes the first PMOS(P1) and the 2nd PMOS(P2).First PMOS(P1) and the 2nd PMOS(P2)
Source electrode meet power supply (VDD), the first PMOS(P1) drain electrode meet the 2nd PMOS(P2) grid, the 2nd PMOS(P2) drain electrode connect
First PMOS(P1) grid.Wherein, the first PMOS(P1) drain electrode be the second positive storage point (QU), the 2nd PMOS(P2) leakage
Pole is the second anti-storage point (QUN).
Transferring structure includes the 3rd NMOS(N3) and the 4th NMOS(N4).3rd NMOS(N3) and the 4th NMOS(N4) source
Pole is grounded (GND), the 3rd NMOS(N3) grid meet the first positive storage point (Q), the 3rd NMOS(N3) drain electrode connect second and counter deposit
Store up point (QUN), the 4th NMOS(N4) grid meet the first anti-storage point (QN), the 4th NMOS(N4) drain electrode connect the second positive storage
Point (QU).
Isolation structure includes the 5th NMOS(N5) and the 6th NMOS(N6).5th NMOS(N5) source electrode connect the first positive storage
Point (Q), the 5th NMOS(N5) drain and gate meet the second positive storage point (QU), the 6th NMOS(N6) source electrode connect first and counter deposit
Store up point (QN), the 6th NMOS(N6) drain and gate connect the second anti-storage point (QUN).
Reading and writing structure includes the 7th NMOS(N7) and the 8th NMOS(N8).7th NMOS(N7) and the 8th NMOS(N8) grid
Pole meets wordline (WL), the 7th NMOS(N7) source electrode connect positive bit line (BL), the 7th NMOS(N7) drain electrode connect the first positive storage point
(Q), the 8th NMOS(N8) the reversed bit line of source electrode (BLN), the 8th NMOS(N8) drain electrode connect the first anti-storage point (QN).
High level (indicating high level with 1) is stored with regard to the bit location below, is i.e. the case where Q=QU=1, QN=QUN=0, is discussed
The read-write and stability of the bit location.The case where the case where when bit location storage low level is with storage high level is identical, because should
Structure is full symmetric, so only illustrating a kind of situation.
Read operation
BL and BLN is precharged to high voltage, and WL, which is increased, starts read operation, and WL, which is increased, will open N7 and N8, because N2 also locates
In opening state, then the charge in BLN is discharged by N7 and N2, and N1 is in close state, so BL is in original level,
Sense amplifier obtains the state of storage unit according to the voltage difference between BL and BLN.In read operation, in the of short duration time
Interior, QN may be because read operation and increase voltage, be desirable to carefully tune transistor in read-write structure and NMOS feedback arrangement at this time
Size, to guarantee that read-write operation will not influence the storage state of unit, such case is identical as common 6T structure, solution
Also identical.
Write operation (write-in low level, change the value of bit location)
In original state, BL and BLN, in order to which low level is written, BL are discharged all in high level, then draw high WL opening
Read-write pipe.BL drags down Q level point by N7, declines N2 driving capability, QN voltage under the influence of the high level of BLN is caused to be higher than
The threshold voltage of N1, Q point accelerates electric discharge after opening N1, and forms positive feedback with QN.It changes in NMOS feedback arrangement level
While, PMOS feedback arrangement again changes.After QN voltage increases, N4 is opened, drags down QU, opens P2；And Q point voltage
It reduces so that N3 is closed, so the P2 opened draws high the level of QUN, then N6 is opened gradually, and the charge of QN is accumulative not at this time
External BLN is relied solely on, but is charged by P2 and N6 to QN, within the scope of maintaining QN voltage to be maintained at certain.
The voltage raising of QUN can close P1 simultaneously, drag down the voltage of QU completely under the driving of N4.So far entire unit, which is in, stablizes
State.It is worth noting that, peripheral circuit is i.e. it is believed that knot when the storage of NMOS feedback arrangement point voltage is overturn to when critical point
Beam write operation, at this point, NMOS feedback arrangement, which will drive PMOS feedback arrangement, carries out subsequent operation, until stabilization.
The analysis of single-point tipping stability
In QN 0 → 1:NMOS feedback arrangement, QN only connects the source electrode and drain electrode of NMOS, and the P type substrate of NMOS and p-well
Low-voltage is all connected, so, even if influencing by single-particle, also only the voltage of QN point can be made lower, Bu Huiying when QN is 0
Ring the state of storage.
Q 1 → 0: it is influenced when Q point is in high level state by single-particle, voltage can be reduced, it is possible to N2 can be closed
And N3 so that QN and QUN is in floating state, but all storage points all have biggish capacitor in the design, thus this two
Point keeps high level for a long time.The negative electrical charge that QUN controls recovery pipe P1, the Q point of Q point is discharged via N5 from P1,
Q point is set to restore former storage state.It should be noted that Q point can slightly drag down the electricity of QU point when P1 discharges negative electrical charge with more N5
Pressure, in order to guarantee stability, only two PMOS need biggish driving capability in the design.
QUN 0 → 1: because QUN is connected to P2, it is possible that because the drain electrode of P2 increases voltage because single-particle influences.QUN
P1 can be closed by increasing voltage, open N6.It is little to entire effect to close P1, opening N6 makes the positive charge of QUN only can be from N3
Release can also be discharged by N6 and N2, so the storage state of entire bit location will not change.It is worth noting that, if QUN
Positive charge is discharged by N6 and N2, it is possible to increase the voltage of QN, but the resistance of the higher N6 of QN voltage is bigger, and to N2
When being designed, if 6T design is identical, need N2 (N1) that there is biggish driving capability, to guarantee the stability of read operation, institute
Although can be increased in this case with QN voltage, storage state will not influence.
1 → 0:QU of QU is connected to N4 and N5, if the drain electrode of the two NMOS is influenced by single-particle, may reduce QU
Voltage.The reduction of QU voltage can open P2, close N5.Wherein N5 is substantially at closing due to the originally very little of the pressure difference between grid source
State reduces drain-to-gate voltage at this time, and N5 is still within closed state, will not generate other influences.And open P2 may be to QUN's
Voltage has an impact, but all in opening state, the voltage of QUN is not in large variation by N6 and N2 and N3 at this time.Finally
Negative electrical charge on QU can be discharged by P1, restore the state of script.
From above-mentioned analysis it is found that four storage points in the present embodiment, low level deposit is stored in NMOS feedback arrangement
Storage point because of its reasons in structure, will not be flipped under the influence of particle, and if other storage point there is single-point overturning, finally still
Original state can be restored to.
The analysis of multiple spot tipping stability
From analysis above as can be seen that the present invention is under stable storage state, it is ensured that a storage point affirmative is not
It can be influenced by single-particle, only there are three storage points to be influenced by single-particle, multiple spot overturning occurs with regard to this 3 points below and is stablized
Property analysis.
QU and QUN: if from previous analysis it is found that QU reduces voltage under the influence of single-particle, N5 and slightly may be closed
QUN is increased, if QUN is also affected simultaneously and increases voltage, also according to analysis above, QN can not be in the feelings opened in N2
The threshold voltage of N1 or N4 are increased under condition, so will not influence storage state.Even if then QU and QUN is simultaneously by single-particle shadow
It rings and changes voltage, the storage state of the bit location will not be influenced.
Q and QU or QU and QUN:Q point voltage reduces, and N2 can be closed, so that QN floating.If the voltage of QU/QUN at this time
It changes, the former can drive P2 to charge via N6 to QN, and the latter then passes through N6 and discharges charge, in these cases, QN to QN
Voltage can also change therewith, so in this case, which is only capable of receiving duration shorter situation, otherwise store
State can change correspondingly.
From multiple spot analysis as can be seen that the present embodiment can bear PMOS feedback arrangement be totally turned over (and NMOS feedback knot
The ability that structure itself is not totally turned over).If but all overturn in two feedback arrangements, be likely to not restore, but
This is also inevitable situation, and the reinforcing thought of all Redundancy Designs is the part being affected using the recovery of stomge of redundancy, if
All storage states are all affected, the ability that just do not restore naturally.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than is limited；Although referring to aforementioned reality
Applying example, invention is explained in detail, for those of ordinary skill in the art, still can be to aforementioned implementation
Technical solution documented by example is modified or equivalent replacement of some of the technical features；And these are modified or replace
It changes, the spirit and scope for claimed technical solution of the invention that it does not separate the essence of the corresponding technical solution.
Claims (1)
1. a kind of novel anti-single particle SRAM bit cell, which is characterized in that it includes
The source electrode of NMOS feedback arrangement, including the first NMOS and the 2nd NMOS, the first NMOS and the 2nd NMOS are grounded,
The drain electrode of first NMOS connects the grid of the 2nd NMOS, and the drain electrode of the 2nd NMOS connects the grid of the first NMOS
Pole, the drain electrode of the first NMOS are the first positive storage point Q, and the drain electrode of the 2nd NMOS is the first anti-storage point QN；
The source electrode of PMOS feedback arrangement, including the first PMOS and the 2nd PMOS, the first PMOS and the 2nd PMOS connect electricity
Source, the drain electrode of the first PMOS connect the grid of the 2nd PMOS, and the drain electrode of the 2nd PMOS connects the first PMOS's
Grid, the drain electrode of the first PMOS are the second positive storage point QU, and the drain electrode of the 2nd PMOS is the second anti-storage point QUN；
The source electrode of transferring structure, including the 3rd NMOS and the 4th NMOS, the 3rd NMOS and the 4th NMOS are grounded, described
The grid of 3rd NMOS meets the described first positive storage point Q, and the drain electrode of the 3rd NMOS meets the described second anti-storage point QUN, institute
The grid for stating the 4th NMOS meets the described first anti-storage point QN, and the drain electrode of the 4th NMOS meets the described second positive storage point QU；
Isolation structure, including the 5th NMOS and the 6th NMOS, the source electrode of the 5th NMOS meet the described first positive storage point Q, institute
The drain and gate for stating the 5th NMOS meets the described second positive storage point QU, and the source electrode of the 6th NMOS connects the described first anti-storage
Point QN, the drain and gate of the 6th NMOS meet the described second anti-storage point QUN；
Structure is read and write, including the grid of the 7th NMOS and the 8th NMOS, the 7th NMOS and the 8th NMOS meet wordline WL,
The source electrode of 7th NMOS meets positive bit line BL, and the drain electrode of the 7th NMOS meets the described first positive storage point Q, and the described 8th
The reversed bit line BLN of the source electrode of NMOS, the drain electrode of the 8th NMOS meet the described first anti-storage point QN.
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| CN108492843B (en) * | 2018-04-04 | 2021-09-14 | 安徽大学 | 14T radiation-resistant static storage unit |
| CN109872747A (en) * | 2019-01-10 | 2019-06-11 | 中国人民武装警察部队海警学院 | A kind of 10 transistor memory unit of subthreshold value for supporting column selection structure |
| CN110047535B (en) * | 2019-03-20 | 2021-01-22 | 上海华虹宏力半导体制造有限公司 | SRAM memory cell |
| CN112562756B (en) * | 2020-12-15 | 2024-03-08 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant sram cell and memory |
| CN112509622A (en) * | 2020-12-15 | 2021-03-16 | 安徽大学 | 10T TFET SRAM unit circuit with low power consumption and high write margin |
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