CN108133727A - The storage unit of anti-multiple node upset with stacked structure - Google Patents
The storage unit of anti-multiple node upset with stacked structure Download PDFInfo
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- CN108133727A CN108133727A CN201810049583.5A CN201810049583A CN108133727A CN 108133727 A CN108133727 A CN 108133727A CN 201810049583 A CN201810049583 A CN 201810049583A CN 108133727 A CN108133727 A CN 108133727A
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- nmos transistor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
Abstract
The present invention relates to a kind of storage unit of the anti-multiple node upset with stacked structure, which includes the first PMOS transistor, the second PMOS transistor, third PMOS transistor, the 4th PMOS transistor, access transistor, the first NMOS transistor, the second NMOS transistor, third NMOS transistor, the 4th NMOS transistor, the 5th NMOS transistor, the 6th NMOS transistor, the first bit line, the second bit line and wordline；The access transistor includes the 7th NMOS transistor and the 8th NMOS transistor.The present invention can single-particle binode upset carries out self- recoverage to single-particle single node upset and caused by charge is shared, and improves the reliability of system；Since storage unit belongs to latch, this storage unit is also the reinforcement elements of a radioresistance latch.
Description
Technical field
The present invention relates to technical field of integrated circuits, especially a kind of storage of the anti-multiple node upset with stacked structure
Unit.
Background technology
With the development of integrated circuit processing technique, storage unit becomes increasingly to be vulnerable to the influence of radiation, by radiating
Single-particle inversion caused by particle (single event upset, SEU) have become influence memory it is especially static with
One of an important factor for machine memory (static random access memory, SRAM) reliability.In space environment,
When radiating particle such as α particles or proton are when bombarding SRAM device sensitive nodes, it will generate additional charge, these charge meetings
Change the storage value of storage unit, generate SEU, it is this to cause device that permanent error occurs, but may result in electronics
The phenomenon that system fault also referred to as soft error.
6 transistor memory units of standard are usually used in the memory of contemporary electronic systems, traditional 6 transistor memory unit of standard with
And 6 transistor memory unit by radiating particle bombardment generate waveform diagram as depicted in figs. 1 and 2.6 transistor memory unit packet of standard
Include two PMOS transistors：101 and 102, four NMOS transistors：103rd, 104,105 and 106, wherein 105 He of NMOS transistor
NMOS transistor 106 is access transistor, and bit line BL and BLN connect 105 and 106 drain electrode respectively, and wordline WL connects 105 simultaneously
Grid with 106, and controls the on off state of access transistor 105 and 106.As shown in Fig. 2, when the value of node Q storages is
" 1 ", when the value of node QN storages is " 0 ", radiating particle bombardment memory node Q so that the storage value of node Q is turned to by " 1 "
" 0 ", due to PMOS transistor as shown in 101 in Fig. 1 and 102 and NMOS transistor is as shown in 103 in Fig. 1 and 104, structure
Into a positive feedback network, the storage value of node QN is caused to be turned to " 1 " by " 0 ", it is final so that 6 transistor memory units stored
Value is overturn, electronic system less reliable.
With the reduction of process, the reduction of supply voltage and the continuous reduction of node capacitor have caused memory
It is more sensitive to radiating particle, while density of memory cells is continuously increased so that primary particle radiation will be total to due to charge
It enjoys effect and the voltage of multiple nodes in storage unit is caused to overturn, further reduced the reliability of memory.
Invention content
It can be to single-particle single node upset and since charge shares caused list the purpose of the present invention is to provide one kind
Particle binode upset carries out self- recoverage, improves the storage list of the anti-multiple node upset with stacked structure of the reliability of system
Member.
To achieve the above object, present invention employs following technical schemes：A kind of anti-multinode with stacked structure turns over
The storage unit turned, the storage unit include the first PMOS transistor, the second PMOS transistor, third PMOS transistor, the 4th
PMOS transistor, access transistor, the first NMOS transistor, the second NMOS transistor, third NMOS transistor, the 4th NMOS are brilliant
Body pipe, the 5th NMOS transistor, the 6th NMOS transistor, the first bit line, the second bit line and wordline；
The access transistor includes the 7th NMOS transistor and the 8th NMOS transistor；8th NMOS transistor
Drain electrode is connected on the second bit line, and the source electrode of the 8th NMOS transistor connects the drain electrode of third NMOS transistor, the 6th simultaneously
The grid of NMOS transistor, the grid of the first NMOS transistor, the grid of the first PMOS transistor and the leakage of the 4th NMOS transistor
Pole, source electrode, the drain electrode of third NMOS transistor, the grid of the 6th NMOS transistor, the first NMOS of the 8th NMOS transistor are brilliant
Circuit node between the drain electrode of the grid of body pipe, the grid of the first PMOS transistor and the 4th NMOS transistor is Q；
The grid of the third NMOS transistor connects the grid of third PMOS transistor, the first NMOS transistor simultaneously
Drain electrode, the grid of the 5th NMOS transistor, the 7th NMOS transistor source electrode and the second NMOS transistor drain electrode, the 3rd NMOS
The grid of transistor, the grid of third PMOS transistor, the drain electrode of the first NMOS transistor and the 5th NMOS transistor grid,
Circuit node between the drain electrode of the source electrode and the second NMOS transistor of 7th NMOS transistor is QN；
The grid of 7th NMOS transistor and the grid of the 8th NMOS transistor are both connected in wordline, the 7th NMOS
The drain electrode of transistor is connected on the first bit line；
The source electrode of drain electrode the 4th NMOS transistor of connection of the third PMOS transistor；The drain electrode of first PMOS transistor
Connect the source electrode of the second NMOS transistor；
The grid of second NMOS transistor connects the grid of the second PMOS transistor, the 4th PMOS transistor simultaneously
Drain electrode and the drain electrode of the 6th NMOS transistor, the grid of the second NMOS transistor, the grid of the second PMOS transistor, the 4th PMOS
Circuit node between the drain electrode of transistor and the drain electrode of the 6th NMOS transistor is node S0；
The grid of 4th NMOS transistor connects the grid of the 4th PMOS transistor, the second PMOS transistor simultaneously
Drain electrode and the drain electrode of the 5th NMOS transistor, the grid of the 4th NMOS transistor, grid, the 2nd PMOS of the 4th PMOS transistor
Circuit node between the drain electrode of transistor and the drain electrode of the 5th NMOS transistor is node S1；
Supply voltage VDD connects the source electrode of third PMOS transistor, the source electrode of the 4th PMOS transistor, the 2nd PMOS simultaneously
The source electrode of the source electrode of transistor and the first PMOS transistor；Power supply simultaneously connect third NMOS transistor source electrode, the 6th
The source electrode of the source electrode of NMOS transistor, the source electrode of the 5th NMOS transistor and the first NMOS transistor.
When the level of node Q is " 1 ", the level of node QN is " 0 ", the level of node S0 is " 0 ", the level of node S1 is
When " 1 ", the storage unit, which is in, deposits the detailed process of mode of operation and is：
When wordline is low level " 0 ", the second PMOS transistor, third PMOS transistor, the first NMOS transistor, the 4th
NMOS transistor, the 6th NMOS transistor are in ON state, the first PMOS transistor, the 4th PMOS transistor, the 2nd NMOS crystal
Pipe, third NMOS transistor, the 5th NMOS transistor, the 7th NMOS transistor and the 8th NMOS transistor are in OFF state, complete
Operation is deposited into the storage unit.
When the level of node Q is " 1 ", the level of node QN is " 0 ", the level of node S0 is " 0 ", the level of node S1 is
When " 1 ", the detailed process that the storage unit carries out read operation state is：
First, the first bit line and the second bit line are precharged to power supply VDD, when wordline is high level " 1 ", No. seven
NMOS transistor and the 8th NMOS transistor are in ON state, and node Q keeps high level one state, and node QN keeps low level " 0 "
State, the first bit line are discharged by the 7th NMOS transistor and the first NMOS transistor；Then, it is sensitive in peripheral circuit
The storage state of the storage unit is exported according to the voltage difference between the first bit line and the second bit line, completed by amplifier
The read operation of storage unit.
When the level of node Q is " 1 ", the level of node QN is " 0 ", the level of node S0 is " 0 ", the level of node S1 is
When " 1 ", the detailed process that the storage unit carries out write operation state is：
Second bit line is pulled down into low level " 0 ", while the first bit line is pulled upward to high level " 1 ", when wordline is high electricity
When flat " 1 ", the 7th NMOS transistor and the 8th NMOS transistor are in ON state, and node Q pulled down to low level " 0 ", node QN
High level " 1 " is essentially pulled up to, at this point, the first PMOS transistor, the 4th PMOS transistor, the second NMOS transistor, the 3rd NMOS
Transistor and the 5th NMOS transistor are in ON state, the second PMOS transistor, third PMOS transistor, the first NMOS transistor,
4th NMOS transistor and the 6th NMOS transistor are in OFF state, when wordline falls back to low level " 0 ", the 7th NMOS transistor
OFF state is in the 8th NMOS transistor, the node Q, node QN, node S0 and node S1 are in stable state, complete institute
State the write operation of storage unit.
As shown from the above technical solution, the advantage of the invention is that：First, the present invention forms one using 12 transistors
The storage unit of anti-multiparticle overturning with stacked structure, wherein, PMOS transistor has 4, is the first PMOS crystal respectively
Pipe, the second PMOS transistor, third PMOS transistor and the 4th PMOS transistor；NMOS transistor has 8, is first respectively
NMOS transistor, the second NMOS transistor, third NMOS transistor, the 4th NMOS transistor, the 5th NMOS transistor, the 6th
NMOS transistor, the 7th NMOS transistor and the 8th NMOS transistor, the 7th NMOS transistor and the 8th NMOS transistor is deposit
Transistor is taken, is connected respectively on the first bit line and the second bit line, while they control switching manipulation by wordline；The second, the first
PMOS transistor, the second PMOS transistor, third PMOS transistor and the 4th PMOS transistor and the second NMOS transistor, the 4th
NMOS transistor constitutes pull-up network；First NMOS transistor, third NMOS transistor, the 5th NMOS transistor and the 6th
NMOS transistor constitutes pulldown network, wherein, the first NMOS transistor and the second NMOS transistor and the 3rd NMOS crystal
Pipe and the 4th NMOS transistor form NMOS stacked structure stacked structure, and stacked structure can effectively reduce storage
The power consumption of unit；Third, the memory node of storage unit of the present invention are Q and QN, node Q by the 8th NMOS transistor with
Second bit line is connected, and node QN is connected by the 7th NMOS transistor with the first bit line, and the present invention can be to single-particle single node
Overturning and the single-particle binode upset progress self- recoverage caused by charge is shared improve the reliability of system；4th, by
Belong to latch, therefore this storage unit is also the reinforcement elements of a radioresistance latch in storage unit.
Description of the drawings
Fig. 1 is 6 traditional transistor memory unit circuit diagrams；
Fig. 2 is the waveform diagram that SEU occurs for 6 traditional transistor memory units；
Fig. 3 is the circuit diagram of the present invention；
Fig. 4 is the reading and writing of the present invention, deposits operation waveform diagram；
Fig. 5 is the oscillogram when to S0-S1 SEU occurs for node Q, S0, S1 and node.
Specific embodiment
As shown in figure 3, a kind of storage unit of the anti-multiple node upset with stacked structure, which includes first
PMOS transistor 301, the second PMOS transistor 302, third PMOS transistor 303, the 4th PMOS transistor 304, access crystal
Pipe, the first NMOS transistor 305, the second NMOS transistor 306, third NMOS transistor 307, the 4th NMOS transistor 308,
Five NMOS transistors 309, the 6th NMOS transistor 310, the first bit line BLN, the second bit line BL and wordline WL；
The access transistor includes the 7th NMOS transistor 311 and the 8th NMOS transistor 312；8th NMOS is brilliant
The drain electrode of body pipe 312 is connected on the second bit line BL, and the source electrode of the 8th NMOS transistor 312 connects third NMOS transistor simultaneously
307 drain electrode, the grid of the 6th NMOS transistor 310, the grid of the first NMOS transistor 305, first PMOS transistor 301
Grid and the 4th NMOS transistor 308 drain, the drain electrode of the source electrode, third NMOS transistor 307 of the 8th NMOS transistor 312,
The grid of 6th NMOS transistor 310, the grid of the first NMOS transistor 305, the first PMOS transistor 301 grid and the 4th
Circuit node between the drain electrode of NMOS transistor 308 is Q；
It is brilliant that the grid of the third NMOS transistor 307 connects the grid of third PMOS transistor 303, the first NMOS simultaneously
The drain electrode of body pipe 305, the grid of the 5th NMOS transistor 309, the 7th NMOS transistor 311 source electrode and the second NMOS transistor
306 drain electrode, the grid of third NMOS transistor 307, the grid of third PMOS transistor 303, first NMOS transistor 305
Drain electrode and the leakage of the grid of the 5th NMOS transistor 309, the source electrode and the second NMOS transistor 306 of the 7th NMOS transistor 311
Circuit node between pole is QN；
The grid of 7th NMOS transistor 311 and the grid of the 8th NMOS transistor 312 are both connected on wordline WL,
The drain electrode of 7th NMOS transistor 311 is connected on the first bit line BLN；
The source electrode of drain electrode the 4th NMOS transistor 308 of connection of the third PMOS transistor 303；First PMOS transistor
The source electrode of 301 drain electrode the second NMOS transistor 306 of connection；
It is brilliant that the grid of second NMOS transistor 306 connects the grid of the second PMOS transistor 302, the 4th PMOS simultaneously
The drain electrode of body pipe 304 and the drain electrode of the 6th NMOS transistor 310, the grid of the second NMOS transistor 306, the second PMOS transistor
Circuit node between 302 grid, the drain electrode of the 4th PMOS transistor 304 and the drain electrode of the 6th NMOS transistor 310 is section
Point S0；
It is brilliant that the grid of 4th NMOS transistor 308 connects the grid of the 4th PMOS transistor 304, the 2nd PMOS simultaneously
The drain electrode of body pipe 302 and the drain electrode of the 5th NMOS transistor 309, the grid of the 4th NMOS transistor 308, the 4th PMOS transistor
Circuit node between 304 grid, the drain electrode of the second PMOS transistor 302 and the drain electrode of the 5th NMOS transistor 309 is section
Point S1；
Supply voltage VDD connects the source electrode of third PMOS transistor 303, the source electrode of the 4th PMOS transistor 304, simultaneously
The source electrode of the source electrode of two PMOS transistors 302 and the first PMOS transistor 301；Connect third NMOS transistor simultaneously to power supply
307 source electrode, the source electrode of the 6th NMOS transistor 310, the 5th NMOS transistor 309 source electrode and the first NMOS transistor 305
Source electrode.
As shown in figure 4, when the level of node Q is " 1 ", the level of node QN is " 0 ", the level of node S0 is " 0 ", node
When the level of S1 is " 1 ", the storage unit, which is in, deposits the detailed process of mode of operation and is：
When wordline WL is low level " 0 ", the second PMOS transistor 302, third PMOS transistor 303, the first NMOS are brilliant
Body pipe 305, the 4th NMOS transistor 308, the 6th NMOS transistor 310 are in ON state, the first PMOS transistor the 301, the 4th
PMOS transistor 304, the second NMOS transistor 306, third NMOS transistor 307, the 5th NMOS transistor 309, the 7th NMOS
311 and the 8th NMOS transistor 312 of transistor is in OFF state, and that completes the storage unit deposits operation.
As shown in figure 4, when the level of node Q is " 1 ", the level of node QN is " 0 ", the level of node S0 is " 0 ", node
When the level of S1 is " 1 ", the detailed process that the storage unit carries out read operation state is：
First, the first bit line BLN and the second bit line BL are precharged to power supply VDD, when wordline WL is high level " 1 "
When, No. seven 311 and the 8th NMOS transistors 312 of NMOS transistor are in ON state, and node Q keeps high level one state, node QN
Low level " 0 " state of holding, the first bit line BLN are put by the 7th NMOS transistor 311 and the first NMOS transistor 305
Electricity；Then, the sense amplifier in peripheral circuit is by according to the voltage difference between the first bit line BLN and the second bit line BL, by institute
The storage state output of storage unit is stated, completes the read operation of storage unit.
As shown in figure 4, when the level of node Q is " 1 ", the level of node QN is " 0 ", the level of node S0 is " 0 ", node
When the level of S1 is " 1 ", the detailed process that the storage unit carries out write operation state is：
Second bit line BL is pulled down into low level " 0 ", while the first bit line BLN is pulled upward to high level " 1 ", as wordline WL
During for high level " 1 ", the 7th NMOS transistor 311 and the 8th NMOS transistor 312 are in ON state, and node Q pulled down to low electricity
Flat " 0 ", node QN is essentially pulled up to high level " 1 ", at this point, the first PMOS transistor 301, the 4th PMOS transistor 304, second
NMOS transistor 306,307 and the 5th NMOS transistor 309 of third NMOS transistor are in ON state, the second PMOS transistor 302,
Third PMOS transistor 303, the first NMOS transistor 305, the 4th NMOS transistor 308 and the 6th NMOS transistor 310 are in
OFF state, when wordline WL falls back to low level " 0 ", the 7th NMOS transistor 311 and the 8th NMOS transistor 312 are in OFF state,
The node Q, node QN, node S0 and node S1 are in stable state, complete the write operation of the storage unit.
Based on SEU (single-particle inversion) generation mechanism, when a radiating particle bombards PMOS transistor, can only generate just
Transient pulse；When bombarding NMOS transistor, negative transient pulse can only be generated.Because node QN is " 0 " in the state,
And it with PMOS transistor without being connected；Therefore, the node QN invented in the storage unit is not sensitive nodes, is examined
Consider the node state that Fig. 3 is provided, sensitive nodes are Q, S0 and S1, in another storage state i.e. Q=0, QN=1, S0
During=1 and S1=0, sensitive nodes are QN, S0 and S1.
Design the radiation resistance analysis of storage unit：
1st, assume that node Q is turned to low level " 0 " state, it will the first NMOS transistor 305 of shutdown and the 6th NMOS
Transistor 310, temporarily opens the first PMOS transistor 301, and node QN and S0 will original low level " 0 " shapes of floating holding
State.Therefore the second PMOS transistor 302 keeps ON state, and node S1 can still maintain its high level one state.As a result, third
303 and the 4th NMOS transistor 308 of PMOS transistor is still opening, and then node Q will be pulled up back original height
Level one state；Fig. 5 shows the simulation waveform when SEU occurs for node Q.
2nd, assume that node S0 is turned to high level one state, the second NMOS transistor 306 and the second PMOS transistor
302 will be opened and closed respectively.But since the state of node Q, QN and S1 do not change, the 6th NMOS transistor 310
It will be always on.Then, node S0 is restored to its original low level " 0 " state；Fig. 5 is shown to be occurred in node S0
Simulation waveform during SEU.
3rd, assume that node S1 is turned to low level " 0 " state, the 4th NMOS transistor 308 is closed, and the 4th PMOS is brilliant
Body pipe 304 can be opened, and node S0 is changed to high level one state, but due to capacity effect, node Q is still original
High level one state, so to still maintain each original for the 6th NMOS transistor 310 and the first PMOS transistor 301
Opening and closing state, as a result, node S0 will be pulled down back original low level " 0 " state, at this time the state of node QN
Because the first NMOS transistor 305 is in ON state and does not also change, the 5th NMOS transistor 309 is in ON state, section
Point S1 is restored to original high level state " 1 ", and Fig. 5 shows the simulation waveform when SEU occurs for node S1.
4th, since charge shares the influence of effect, node may be reversed S0-S1.At this point, the second NMOS transistor 306
It is opened with the 4th PMOS transistor 304, the second PMOS transistor 302 and the 4th NMOS transistor 308 can close, to node
The analysis of the anti-raw overturnings of S1 learns that the node of overturning can be restored to S0-S1 respectively original state, if correspondingly, storage
Unit is in another storage state, that is, when Q=0, QN=1, S0=1 and S1=0, and life anti-at S0-S1 is turned in node
Turn also be resumed.Therefore, node is two fixed nodes pair that can restore from multiple node upset to S0-S1, and this
Two nodes are unrelated with the value that storage unit stores.Fig. 5 shows the simulation waveform when to S0-S1 SEU occurs for node.
5th, when node overturns S0-Q or S1-Q, the first PMOS transistor 301 and the 2nd NMOS crystal
Pipe 306 can be opened, and the state of node QN can change to state " 1 ", this process for writing low level " 0 " just as one leads to institute
The storage state for stating storage unit changes.
Therefore the possibility of multiple node upset occurs to minimize node to S0-Q or S1-Q, needs to set in domain grade
Rational domain topological structure is considered in meter.It therefore, can be by node Q and node S0 and S1 in version when layout drawing
That is drawn in the physical distance of figure is distant.
Point occurs between two transistors and shared effective distance is less than 1.5um, and N traps can effectively inhibit charge
It is shared.Therefore in the domain of drafting, node Q and node S1 are plotted in different N traps.It is opened up by a rational domain
Flutter structure so that the distance of node Q and node S0 or S1 are much larger than 1.5um.It is therefore contemplated that node to S0-Q or
S1-Q occurs the possibility that charge is shared and is not present.Since the distance between node S0 and node S1 are less than 1.5um, so
Charge may occur between the two nodes to share.But according to above analysis and the simulation waveform of Fig. 5, in node pair
Multiple node upset, which occurs, for S0-S1 to be resumed.Therefore, storage unit of the present invention can be effectively to single-particle
Single node upset turns and single-particle multiple node upset carries out self- recoverage protection, so as to improve the reliability of system.
Claims (4)
1. a kind of storage unit of the anti-multiple node upset with stacked structure, it is characterised in that：The storage unit includes first
PMOS transistor (301), the second PMOS transistor (302), third PMOS transistor (303), the 4th PMOS transistor (304),
Access transistor, the first NMOS transistor (305), the second NMOS transistor (306), third NMOS transistor (307), the 4th
NMOS transistor (308), the 5th NMOS transistor (309), the 6th NMOS transistor (310), the first bit line (BLN), second
Line (BL) and wordline (WL)；
The access transistor includes the 7th NMOS transistor (311) and the 8th NMOS transistor (312)；8th NMOS is brilliant
The drain electrode of body pipe (312) is connected on the second bit line (BL), and the source electrode of the 8th NMOS transistor (312) connects the 3rd NMOS simultaneously
The drain electrode of transistor (307), the grid of the 6th NMOS transistor (310), the grid of the first NMOS transistor (305), first
The grid of PMOS transistor (301) and the drain electrode of the 4th NMOS transistor (308), the source electrode of the 8th NMOS transistor (312), third
The drain electrode of NMOS transistor (307), the grid of the 6th NMOS transistor (310), the grid of the first NMOS transistor (305),
Circuit node between the drain electrode of the grid of one PMOS transistor (301) and the 4th NMOS transistor (308) is Q；
It is brilliant that the grid of the third NMOS transistor (307) connects the grid of third PMOS transistor (303), the first NMOS simultaneously
The drain electrode of body pipe (305), the grid of the 5th NMOS transistor (309), the 7th NMOS transistor (311) source electrode and the 2nd NMOS
The drain electrode of transistor (306), the grid of third NMOS transistor (307), the grid of third PMOS transistor (303), first
The grid of the drain electrode of NMOS transistor (305) and the 5th NMOS transistor (309), the 7th NMOS transistor (311) source electrode and
Circuit node between the drain electrode of second NMOS transistor (306) is QN；
The grid of 7th NMOS transistor (311) and the grid of the 8th NMOS transistor (312) are both connected to wordline (WL)
On, the drain electrode of the 7th NMOS transistor (311) is connected on the first bit line (BLN)；
The drain electrode of the third PMOS transistor (303) connects the source electrode of the 4th NMOS transistor (308)；First PMOS transistor
(301) drain electrode connects the source electrode of the second NMOS transistor (306)；
It is brilliant that the grid of second NMOS transistor (306) connects the grid of the second PMOS transistor (302), the 4th PMOS simultaneously
The drain electrode of body pipe (304) and the drain electrode of the 6th NMOS transistor (310), grid, the 2nd PMOS of the second NMOS transistor (306)
Between the grid of transistor (302), the drain electrode of the 4th PMOS transistor (304) and the drain electrode of the 6th NMOS transistor (310)
Circuit node is node S0；
It is brilliant that the grid of 4th NMOS transistor (308) connects the grid of the 4th PMOS transistor (304), the 2nd PMOS simultaneously
The drain electrode of body pipe (302) and the drain electrode of the 5th NMOS transistor (309), grid, the 4th PMOS of the 4th NMOS transistor (308)
Between the grid of transistor (304), the drain electrode of the second PMOS transistor (302) and the drain electrode of the 5th NMOS transistor (309)
Circuit node is node S1；
Supply voltage VDD connects the source electrode of third PMOS transistor (303), the source electrode of the 4th PMOS transistor (304), simultaneously
The source electrode of two PMOS transistors (302) and the source electrode of the first PMOS transistor (301)；Power supply the 3rd NMOS crystal is connected simultaneously
It is brilliant to manage the source electrode of (307), the source electrode of the 6th NMOS transistor (310), the source electrode of the 5th NMOS transistor (309) and the first NMOS
The source electrode of body pipe (305).
2. the storage unit of the anti-multiple node upset according to claim 1 with stacked structure, it is characterised in that：Work as section
It is described to deposit when the level of point Q is " 1 ", the level of node QN is " 0 ", the level of node S0 is " 0 ", the level of node S1 is " 1 "
Storage unit, which is in, to be deposited the detailed process of mode of operation and is：
When wordline (WL) is low level " 0 ", the second PMOS transistor (302), third PMOS transistor (303), the first NMOS
Transistor (305), the 4th NMOS transistor (308), the 6th NMOS transistor (310) are in ON state, the first PMOS transistor
(301), the 4th PMOS transistor (304), the second NMOS transistor (306), third NMOS transistor (307), the 5th NMOS are brilliant
Body pipe (309), the 7th NMOS transistor (311) and the 8th NMOS transistor (312) are in OFF state, complete the storage unit
Deposit operation.
3. the storage unit of the anti-multiple node upset according to claim 1 with stacked structure, it is characterised in that：Work as section
It is described to deposit when the level of point Q is " 1 ", the level of node QN is " 0 ", the level of node S0 is " 0 ", the level of node S1 is " 1 "
Storage unit carry out read operation state detailed process be：
First, the first bit line (BLN) and the second bit line (BL) are precharged to power supply VDD, when wordline (WL) is high level
When " 1 ", in ON state, node Q keeps high level " 1 " shape for No. seven NMOS transistors (311) and the 8th NMOS transistor (312)
State, node QN keep low level " 0 " state, and the first bit line (BLN) passes through the 7th NMOS transistor (311) and the first NMOS crystal
Pipe (305) discharges；Then, the sense amplifier in peripheral circuit will be according to the first bit line (BLN) and the second bit line (BL)
Between voltage difference, the storage state of the storage unit is exported, completes the read operation of storage unit.
4. the storage unit of the anti-multiple node upset according to claim 1 with stacked structure, it is characterised in that：Work as section
It is described to deposit when the level of point Q is " 1 ", the level of node QN is " 0 ", the level of node S0 is " 0 ", the level of node S1 is " 1 "
Storage unit carry out write operation state detailed process be：
Second bit line (BL) is pulled down into low level " 0 ", while the first bit line (BLN) is pulled upward to high level " 1 ", works as wordline
(WL) for high level " 1 " when, the 7th NMOS transistor (311) and the 8th NMOS transistor (312) are in ON state, and node Q is by under
Move low level " 0 " to, node QN is essentially pulled up to high level " 1 ", at this point, the first PMOS transistor (301), the 4th PMOS transistor
(304), the second NMOS transistor (306), third NMOS transistor (307) and the 5th NMOS transistor (309) are in ON state, and
Two PMOS transistors (302), third PMOS transistor (303), the first NMOS transistor (305), the 4th NMOS transistor (308)
With the 6th NMOS transistor (310) in OFF state, when wordline (WL) falls back to low level " 0 ", the 7th NMOS transistor (311)
With the 8th NMOS transistor (312) in OFF state, the node Q, node QN, node S0 and node S1 are in stable state,
Complete the write operation of the storage unit.
Priority Applications (1)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109547006A (en) * | 2018-11-26 | 2019-03-29 | 中北大学 | Flouride-resistani acid phesphatase D-latch |
| CN112562756A (en) * | 2020-12-15 | 2021-03-26 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant static random access memory cell and memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336362A (en) * | 2015-12-10 | 2016-02-17 | 中北大学 | Radiation hardened static random access memory |
| CN108766492A (en) * | 2017-12-28 | 2018-11-06 | 北京时代民芯科技有限公司 | A kind of anti-SEU storage unit circuits of low single-particle sensibility |
-
2018
- 2018-01-18 CN CN201810049583.5A patent/CN108133727A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336362A (en) * | 2015-12-10 | 2016-02-17 | 中北大学 | Radiation hardened static random access memory |
| CN108766492A (en) * | 2017-12-28 | 2018-11-06 | 北京时代民芯科技有限公司 | A kind of anti-SEU storage unit circuits of low single-particle sensibility |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109547006A (en) * | 2018-11-26 | 2019-03-29 | 中北大学 | Flouride-resistani acid phesphatase D-latch |
| CN112562756A (en) * | 2020-12-15 | 2021-03-26 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant static random access memory cell and memory |
| CN112562756B (en) * | 2020-12-15 | 2024-03-08 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant sram cell and memory |
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