CN106847324A - Radioresistance memory cell - Google Patents
Radioresistance memory cell Download PDFInfo
- Publication number
- CN106847324A CN106847324A CN201611218756.9A CN201611218756A CN106847324A CN 106847324 A CN106847324 A CN 106847324A CN 201611218756 A CN201611218756 A CN 201611218756A CN 106847324 A CN106847324 A CN 106847324A
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- CN
- China
- Prior art keywords
- pmos transistor
- node
- transistor
- nmos pass
- level
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
- H03K19/00338—In field effect transistor circuits
Abstract
Radioresistance memory cell, is related to IC design field.The present invention be in order to solve the problems, such as it is existing lack radiation tolerance design is carried out to memory.The present invention includes PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, nmos pass transistor N1, nmos pass transistor N2, nmos pass transistor N3 and nmos pass transistor N4；In electric charge shares the multiple node upset phenomenon for causing, it is that memory state will not be caused to occur effectively to change that the electric charge of unnecessary two nodes is shared, therefore, present invention confrontation multiple node upset is reinforced primary concern is that carrying out radiation hardening to two sensitive nodes.For carrying out radiation hardening to two sensitive nodes.
Description
Technical field
The present invention relates to IC design, the anti-single particle upset effect specially in integrated circuit field of radioresistance reinforcement
The memory cell answered is designed.
Background technology
With continuous advancement and China aerospace aerospace industry, the fast development of defense technology of integrated circuit, increasingly need
The protection of radiation tolerance design is carried out to memory.However, developed countries are carried out to related radiation hardening technology
Strict technology blockage.In order to break the technology blockage in the external radioresistance field to China, integrated circuit radioresistance is realized
The nationalization of change is, it is necessary to design a new radioresistance memory cell.
The content of the invention
The present invention be in order to solve the problems, such as it is existing lack radiation tolerance design is carried out to memory.Radioresistance is now provided
Memory cell.
Radioresistance memory cell, it includes PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS crystal
Pipe P4, PMOS transistor P5, PMOS transistor P6, nmos pass transistor N1, nmos pass transistor N2 and access transistor,
Access transistor includes nmos pass transistor N3 and nmos pass transistor N4,
Wordline WL simultaneously control bit line BLN and bit line BL switching manipulation,
The drain electrode of nmos pass transistor N4 is connected on bit line BL, and the grid of nmos pass transistor N4 is connected on wordline WL,
The source electrode of nmos pass transistor N4 as node A, while connect the drain electrode of PMOS transistor P4, the grid of PMOS transistor P6,
The drain electrode of the grid and nmos pass transistor N2 of nmos pass transistor N1,
The grid of PMOS transistor P4 is used as node D, while connecting the drain electrode of PMOS transistor P2, PMOS transistor P1
The source electrode of grid and PMOS transistor P5, the source electrode connection power supply of PMOS transistor P2,
The grid of PMOS transistor P2 is used as node C, while connecting the source electrode of PMOS transistor P6, PMOS transistor P1
Drain electrode and the grid of PMOS transistor P3, the source electrode connection power supply of PMOS transistor P1,
The source electrode of PMOS transistor P4 and the source electrode of PMOS transistor P3 are all connected with power supply,
The drain electrode of PMOS transistor P6, the source electrode of nmos pass transistor N2, the source electrode of nmos pass transistor N1 and PMOS transistor
The drain electrode of P5 is all connected with power supply ground,
The grid of nmos pass transistor N2 is used as node B, while connecting the drain electrode of nmos pass transistor N1, PMOS transistor P5
The source electrode of grid, the drain electrode of PMOS transistor P3 and nmos pass transistor N3,
The grid of nmos pass transistor N3 is connected on wordline WL, and the drain electrode of nmos pass transistor N3 is connected on bit line BLN.
According to radioresistance memory cell, when the level of node A be high level, the level of node B be low level, node C
Level be high level, node D level be low level, wordline WL be low level when, nmos pass transistor N1, PMOS transistor P4,
PMOS transistor P1 and PMOS transistor P5 be in ON state, nmos pass transistor N2, nmos pass transistor N3, nmos pass transistor N4,
PMOS transistor P2, PMOS transistor P3 and PMOS transistor P6 are in OFF state, and memory cell is in and deposits mode of operation.
According to radioresistance memory cell, when the level of node A be high level, the level of node B be low level, node C
Level is high level, the level of node D is low level, and bit line BLN and bit line BL is precharged to power supply, and wordline WL is
During high level, node B holding low level states are constant, and bit line BLN is put by nmos pass transistor N1 and nmos pass transistor N3
Electricity, then the sense amplifier in peripheral circuit by according to the voltage difference between bit line BLN and bit line BL by the shape of memory cell
State is exported, and completes read operation.
When the level of node A be high level, the level of node B be low level, the level of node C be high level, node D
Level is low level, and bit line BLN is essentially pulled up to high level, and bit line BL is essentially pulled up to low level, when wordline WL is high level, NMOS
Transistor N4, nmos pass transistor N3, PMOS transistor P2, PMOS transistor P3, PMOS transistor P6 and nmos pass transistor N2 quilts
Open, in ON state；Nmos pass transistor N1, PMOS transistor P4, PMOS transistor P1 and PMOS transistor P5 are closed simultaneously,
In OFF state, when wordline WL returns to low level, node A, node B, node C and node D write behaviour all in stable state, completion
Make.
Beneficial effects of the present invention are：
The physical mechanism that the present invention is produced based on single-particle inversion, when a radiating particle bombardment PMOS transistor
Wait, positive transient voltage pulses can only be produced；And when bombarding nmos pass transistor, negative transient voltage pulses can only be produced,
For node A be high level, node B be low level, node C be high level, node D be low level state, because node C does not have
Have and be connected with the gate/drain of nmos pass transistor, therefore node C is not sensitive nodes, sensitive nodes are node A, B and D；Together
Reason, the level for node A is low level, the level of node B is high level, the level of node C is low level, the electricity of node D
The state for high level is equalled, because node D is not connected with the gate/drain of nmos pass transistor, therefore node D is not sensitive
Node, sensitive nodes are node A, B and C；In electric charge shares the multiple node upset phenomenon for causing, the electric charge of unnecessary two nodes
Shared is that memory state will not be caused to occur effectively to change, therefore, carried out present invention primarily contemplates to two sensitive nodes
Radiation hardening.There is the possibility of multiple node upset, it is necessary in version to minimize node D-A (C-A) or D-B (C-B)
Reasonable contemplation domain topological structure in G- Design.Therefore, when layout drawing, can be by node D, node C and node
It is distant that A-B draws in the physical distance of domain.Memory cell of the invention is compared small with traditional memory cell area
10%, low in energy consumption 10%, the performance impact to the memory cell is small.
Brief description of the drawings
Fig. 1 is the circuit diagram of the radioresistance memory cell described in specific embodiment one.
Specific embodiment
Specific embodiment one：Reference picture 1 illustrates present embodiment, and the radioresistance storage described in present embodiment is single
Unit, it include PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5,
PMOS transistor P6, nmos pass transistor N1, nmos pass transistor N2 and access transistor,
Access transistor includes nmos pass transistor N3 and nmos pass transistor N4,
Wordline WL simultaneously control bit line BLN and bit line BL switching manipulation,
The drain electrode of nmos pass transistor N4 is connected on bit line BL, and the grid of nmos pass transistor N4 is connected on wordline WL,
The source electrode of nmos pass transistor N4 as node A, while connect the drain electrode of PMOS transistor P4, the grid of PMOS transistor P6,
The drain electrode of the grid and nmos pass transistor N2 of nmos pass transistor N1,
The grid of PMOS transistor P4 is used as node D, while connecting the drain electrode of PMOS transistor P2, PMOS transistor P1
The source electrode of grid and PMOS transistor P5, the source electrode connection power supply of PMOS transistor P2,
The grid of PMOS transistor P2 is used as node C, while connecting the source electrode of PMOS transistor P6, PMOS transistor P1
Drain electrode and the grid of PMOS transistor P3, the source electrode connection power supply of PMOS transistor P1,
The source electrode of PMOS transistor P4 and the source electrode of PMOS transistor P3 are all connected with power supply,
The drain electrode of PMOS transistor P6, the source electrode of nmos pass transistor N2, the source electrode of nmos pass transistor N1 and PMOS transistor
The drain electrode of P5 is all connected with power supply ground,
The grid of nmos pass transistor N2 is used as node B, while connecting the drain electrode of nmos pass transistor N1, PMOS transistor P5
The source electrode of grid, the drain electrode of PMOS transistor P3 and nmos pass transistor N3,
The grid of nmos pass transistor N3 is connected on wordline WL, and the drain electrode of nmos pass transistor N3 is connected on bit line BLN.
In present embodiment, based on the physical mechanism that single-particle inversion is produced, when a radiating particle bombardment PMOS crystal
When pipe, positive transient voltage pulses can only be produced；And when bombarding nmos pass transistor, negative transient voltage can only be produced
Pulse.Therefore, for the state, because C nodes are not connected with the gate/drain of nmos pass transistor, therefore it is not
It is sensitive nodes.Consider the state that Fig. 1 gives, sensitive nodes are node A, B and D.In another storage state, that is, A=
0th, B=1, C=0 and D=1 state, sensitive nodes are node A, B and C.
There is document to show, in electric charge shares the multiple node upset phenomenon for causing, the electric charge of unnecessary two nodes is shared to be
Memory state will not be caused to occur effectively to change, therefore, present invention confrontation multiple node upset is reinforced primary concern is that right
The radiation hardening that two sensitive nodes are carried out.
Design the radiation resistance analysis of memory cell：
1st, assume that node D is turned to one state, it will turn off PMOS transistor P1 and PMOS transistor P4, node A, B
Respective original state will be kept with C, therefore remaining transistor is still to maintain the state of original on or off, such as PMOS is brilliant
Body pipe P5 will keep it turned on.Therefore, node D will return to original " 0 " state.
2nd, when node B is turned to " 1 ", nmos pass transistor N2 and PMOS transistor P5 will be opened respectively
And closing.Node A will be affected, and its value will be " 0 ", while PMOS transistor P6 and nmos pass transistor N1 will be temporary transient
Be separately turned on and close.But, because the breadth length ratio of PMOS transistor P1 is more than No. six breadth length ratios of PMOS transistor P6, because
This, the value of node C will very quick return to original state " 1 ", and this will cause PMOS transistor P2 also to keep original closing shape
State, so, node D will keep constant, therefore PMOS transistor P4 will be always maintained at opening.Finally, impacted A
Node will quickly be pulled back to original high level；Then, nmos pass transistor N1 will return to opening, node B quilts
Return to its original " 0 " state.
3rd, when node A overturns, nmos pass transistor N1 is closed, and PMOS transistor P6 is unlocked.But, by
In the breadth length ratio of the breadth length ratio more than PMOS transistor P6 of PMOS transistor P1, therefore, the value of node C will keep original shape
State " 1 ", this will cause PMOS transistor P2 also to keep original closed mode, so, node D will keep constant, therefore PMOS
Transistor P4 will be always maintained at opening.Therefore, impacted A nodes will quickly be pulled back to original level.
4th, due to the influence of the shared effect of electric charge, node A and B are possible to be affected.Now, its state is with node B quilts
Upset is the same, therefore the analysis by being similar to, it can be found that node A and node B will be returned to original state.Correspondence
, if the memory of design is in another state, that is, A=0, B=1, C=0 and D=1 state, in node C and D
The multinode hair for locating to occur turns also be resumed.Therefore, node C and D are two fixed can recover from multiple node upset
Node, and the two nodes are unrelated with the value of memory storage.
5th, when node D-A or D-B occur multiple node upset, No. four PMOS transistor P4 will be closed, institute
Original state will not be returned to node A or B node.Now, the state of storage there occurs upset.
Therefore, in order to minimize node D-A (C-A) or D-B (C-B) there is the possibility of multiple node upset, it is necessary to
Reasonable contemplation domain topological structure in layout design.Therefore, when layout drawing, can be by node D, node C and section
It is distant that point A-B draws in the physical distance of domain.
Specific embodiment two：Present embodiment is that the radioresistance memory cell described in specific embodiment one is made into one
Step explanation, in present embodiment, when node A level for high level, node B level for low level, node C level for height
Level, the level of node D are low level, when wordline WL is low level, nmos pass transistor N1, PMOS transistor P4, PMOS crystal
Pipe P1 and PMOS transistor P5 is in ON state, nmos pass transistor N2, nmos pass transistor N3, nmos pass transistor N4, PMOS transistor
P2, PMOS transistor P3 and PMOS transistor P6 are in OFF state, and memory cell is in and deposits mode of operation.
Specific embodiment three：Present embodiment is that the radioresistance memory cell described in specific embodiment one is made into one
Step explanation, in present embodiment, when node A level for high level, node B level for low level, node C level for height
Level, the level of node D are low level, and bit line BLN and bit line BL is precharged to power supply, and wordline WL is high level
When, node B holding low level states are constant, and bit line BLN is discharged by nmos pass transistor N1 and nmos pass transistor N3, then
Sense amplifier in peripheral circuit by according to the voltage difference between bit line BLN and bit line BL by the State- output of memory cell,
Complete read operation.
Specific embodiment four：Present embodiment is that the radioresistance memory cell described in specific embodiment one is made into one
Step explanation, in present embodiment, when node A level for high level, node B level for low level, node C level for height
Level, the level of node D are low level, and bit line BLN is essentially pulled up to high level, and bit line BL is essentially pulled up to low level, and wordline WL is
During high level, nmos pass transistor N4, nmos pass transistor N3, PMOS transistor P2, PMOS transistor P3, PMOS transistor P6 and
Nmos pass transistor N2 is opened, in ON state；While nmos pass transistor N1, PMOS transistor P4, PMOS transistor P1 and PMOS
Transistor P5 is closed, and in OFF state, when wordline WL returns to low level, node A, node B, node C and node D are all in steady
Determine state, complete write operation.
In present embodiment, the state of memory cell includes two kinds, Yi Zhongwei：The level of node A is high level, node B
Level for low level, node C level for high level, node D level be low level；Another kind is：The level of node A is
Low level, the level of node B are high level, the level of node C is low level, the level of node D is high level.
The level of node A is low level, the level of node B is high level, the level of node C is low level, the electricity of node D
Put down under high level state deposit operation, read operation and write operation be respectively high level with the level of node A, the level of node B
Be the level of low level, node C for high level, node D level to deposit operation, read operation and write operation under low level state
Conversely.
Claims (4)
1. radioresistance memory cell, it is characterised in that it include PMOS transistor P1, PMOS transistor P2, PMOS transistor P3,
PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, nmos pass transistor N1, nmos pass transistor N2 and access transistor,
Access transistor includes nmos pass transistor N3 and nmos pass transistor N4,
Wordline WL simultaneously control bit line BLN and bit line BL switching manipulation,
The drain electrode of nmos pass transistor N4 is connected on bit line BL, and the grid of nmos pass transistor N4 is connected on wordline WL, and NMOS is brilliant
The source electrode of body pipe N4 is used as node A, while connecting drain electrode, the grid of PMOS transistor P6, the NMOS crystal of PMOS transistor P4
The drain electrode of the grid and nmos pass transistor N2 of pipe N1,
The grid of PMOS transistor P4 is used as node D, while connecting drain electrode, the grid of PMOS transistor P1 of PMOS transistor P2
With the source electrode of PMOS transistor P5, PMOS transistor P2 source electrode connection power supply,
The grid of PMOS transistor P2 is used as node C, while connecting source electrode, the drain electrode of PMOS transistor P1 of PMOS transistor P6
With the grid of PMOS transistor P3, PMOS transistor P1 source electrode connection power supply,
The source electrode of PMOS transistor P4 and the source electrode of PMOS transistor P3 are all connected with power supply,
The drain electrode of PMOS transistor P6, the source electrode of nmos pass transistor N2, the source electrode of nmos pass transistor N1 and PMOS transistor P5's
Drain electrode is all connected with power supply ground,
The grid of nmos pass transistor N2 is used as node B, while connecting drain electrode, the grid of PMOS transistor P5 of nmos pass transistor N1
The source electrode of pole, the drain electrode of PMOS transistor P3 and nmos pass transistor N3,
The grid of nmos pass transistor N3 is connected on wordline WL, and the drain electrode of nmos pass transistor N3 is connected on bit line BLN.
2. radioresistance memory cell according to claim 1, it is characterised in that when the level of node A is high level, node
The level of B is low level, the level of node C is high level, the level of node D is low level, when wordline WL is low level, NMOS
Transistor N1, PMOS transistor P4, PMOS transistor P1 and PMOS transistor P5 are in ON state, and nmos pass transistor N2, NMOS are brilliant
Body pipe N3, nmos pass transistor N4, PMOS transistor P2, PMOS transistor P3 and PMOS transistor P6 are in OFF state, and storage is single
Unit is in and deposits mode of operation.
3. radioresistance memory cell according to claim 1, it is characterised in that when the level of node A is high level, node
The level of B is low level, the level of node C is high level, the level of node D is low level, and bit line BLN and bit line BL are pre-
Power supply is charged to, when wordline WL is high level, node B keeps low level state constant, and bit line BLN passes through nmos pass transistor
N1 and nmos pass transistor N3 are discharged, and then the sense amplifier in peripheral circuit will be according between bit line BLN and bit line BL
Voltage difference by the State- output of memory cell, complete read operation.
4. radioresistance memory cell according to claim 1, it is characterised in that when the level of node A is high level, node
The level of B is low level, the level of node C is high level, the level of node D is low level, and bit line BLN is essentially pulled up to electricity high
Flat, bit line BL is essentially pulled up to low level, when wordline WL is high level, nmos pass transistor N4, nmos pass transistor N3, PMOS transistor
P2, PMOS transistor P3, PMOS transistor P6 and nmos pass transistor N2 are opened, in ON state；While nmos pass transistor N1,
PMOS transistor P4, PMOS transistor P1 and PMOS transistor P5 are closed, in OFF state, when wordline WL returns to low level,
Node A, node B, node C and node D complete write operation all in stable state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611218756.9A CN106847324A (en) | 2016-12-26 | 2016-12-26 | Radioresistance memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611218756.9A CN106847324A (en) | 2016-12-26 | 2016-12-26 | Radioresistance memory cell |
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| CN106847324A true CN106847324A (en) | 2017-06-13 |
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| CN201611218756.9A Pending CN106847324A (en) | 2016-12-26 | 2016-12-26 | Radioresistance memory cell |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108183706A (en) * | 2018-01-29 | 2018-06-19 | 中国人民解放军国防科技大学 | Single event upset resistant register file storage array write unit |
| CN112562756A (en) * | 2020-12-15 | 2021-03-26 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant static random access memory cell and memory |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6111780A (en) * | 1998-06-05 | 2000-08-29 | Lockheed Martin Corporation | Radiation hardened six transistor random access memory and memory device |
| US20120120704A1 (en) * | 2007-02-23 | 2012-05-17 | Lawson David C | Single event upset hardened static random access memory cell |
| CN103956183A (en) * | 2014-04-24 | 2014-07-30 | 中国科学院微电子研究所 | Anti-radiation static random access memory (SRAM) unit |
| CN103971734A (en) * | 2014-05-23 | 2014-08-06 | 中国科学院微电子研究所 | Anti-radiation SRAM (Static Random Access Memory) unit |
| CN104464795A (en) * | 2014-11-27 | 2015-03-25 | 西安交通大学 | Static random access memory unit with single-particle-upset resistance |
| CN105448327A (en) * | 2015-11-16 | 2016-03-30 | 哈尔滨工业大学 | Storage unit resistant to multi-node inversion |
-
2016
- 2016-12-26 CN CN201611218756.9A patent/CN106847324A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6111780A (en) * | 1998-06-05 | 2000-08-29 | Lockheed Martin Corporation | Radiation hardened six transistor random access memory and memory device |
| US20120120704A1 (en) * | 2007-02-23 | 2012-05-17 | Lawson David C | Single event upset hardened static random access memory cell |
| CN103956183A (en) * | 2014-04-24 | 2014-07-30 | 中国科学院微电子研究所 | Anti-radiation static random access memory (SRAM) unit |
| CN103971734A (en) * | 2014-05-23 | 2014-08-06 | 中国科学院微电子研究所 | Anti-radiation SRAM (Static Random Access Memory) unit |
| CN104464795A (en) * | 2014-11-27 | 2015-03-25 | 西安交通大学 | Static random access memory unit with single-particle-upset resistance |
| CN105448327A (en) * | 2015-11-16 | 2016-03-30 | 哈尔滨工业大学 | Storage unit resistant to multi-node inversion |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108183706A (en) * | 2018-01-29 | 2018-06-19 | 中国人民解放军国防科技大学 | Single event upset resistant register file storage array write unit |
| CN108183706B (en) * | 2018-01-29 | 2021-09-07 | 中国人民解放军国防科技大学 | Single event upset resistant register file storage array write unit |
| CN112562756A (en) * | 2020-12-15 | 2021-03-26 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant static random access memory cell and memory |
| CN112562756B (en) * | 2020-12-15 | 2024-03-08 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant sram cell and memory |
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Application publication date: 20170613 |