CN103971734A - Radiation-resistant SRAM cell - Google Patents
Radiation-resistant SRAM cell Download PDFInfo
- Publication number
- CN103971734A CN103971734A CN201410223064.8A CN201410223064A CN103971734A CN 103971734 A CN103971734 A CN 103971734A CN 201410223064 A CN201410223064 A CN 201410223064A CN 103971734 A CN103971734 A CN 103971734A
- Authority
- CN
- China
- Prior art keywords
- pipe
- pmos
- nmos pipe
- drain electrode
- nmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005855 radiation Effects 0.000 title abstract description 3
- 230000005540 biological transmission Effects 0.000 claims abstract description 11
- 210000004027 cell Anatomy 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000005055 memory storage Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Abstract
The invention provides an improved radiation-resistant SRAM memory cell, which comprises the following structures: the inverter structure comprises a first inverter structure, a second inverter structure, a third inverter structure and a fourth inverter structure, wherein the inverter structure is formed by connecting PMOS tubes and NMOS tubes in series, a storage node is arranged between the drain electrode of the PMOS tube and the drain electrode of the NMOS tube, and each storage node controls the gate voltage of one NMOS tube of the other inverter structure and the gate voltage of one PMOS tube of the other inverter structure; and the transmission structure consists of two NMOS tubes, and the source electrode, the grid electrode and the drain electrode of the transmission structure are respectively connected with the bit line j inverted phase line, the word line and the storage node. By adopting the improved SRAM storage unit, each node controls the other two nodes through one PMOS and one NMOS, and each node is controlled by one PMOS and one NMOS, so that closed-loop feedback control among the nodes is realized, and the high-level overturn resistance is effectively improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of improved radioresistance SRAM storage unit.
Background technology
Integrated circuit is the fastest electronic product of renewal speed on our times, and storer is the typical products that represents integrated circuit technique development level all the time.The raising of integrated circuit (IC) design, manufacturing technology level makes capacity, the performance of SRAM be able to continuous improvement.SRAM is because read or write speed piece becomes the volatile storage as the maximum of computer cache.In addition,, in aviation, communication, consumer electronics electronic product, SRAM also has a wide range of applications.
Along with the develop rapidly of Aero-Space cause and semiconductor technology, each class of electronic devices is applied in the space of environment very severe already, in space, be flooded with various radiating particles, and radiation effect can cause the Data flipping confusion of semiconductor memory storage cells, and cause the transmission error in data of whole logical circuit.Therefore, improve the capability of resistance to radiation of SRAM, become the problem that SRAM deviser must consider.
Traditional SRAM adopts six pipe units mostly, and its structure as shown in Figure 1, is added two transmission transistors (M3 and M4) with the phase inverter (M1 and M5 form a phase inverter, and M2 and M6 form second phase inverter) of two clampers and formed.Word line WL controls M3 and M4, in the time reading with write operation, and M3 and M4 conducting.While reading, two bit line BLB and BL are all precharged to high level.Write at 1 o'clock, BL=1, BLB=0; Write at 0 o'clock, BL=0, BLB=1.
Existing sram cell, in read operation, BL and BLB are precharged to Vdd/2.Due to transistorized voltage divider principle, cause storing 0 node voltage and rise, thereby static noise margin is reduced.As shown in Figure 1, in the time of read operation, two bit lines BL and BLB charge to respectively Vdd/2, if left side memory node Q storing value is 1, the right memory node QB storing value is 0, in the time of read operation, WL=1, M5 conducting, due to 1 of Q storage, M2 transistor gate voltage is always in opening, BLB reads 0 o'clock that in QB, stores, itself is charged to high level, and therefore M2 and M4 form a discharge path, and QB voltage rises from O.If QB voltage rises to a certain degree, can make M1 conducting, thus drop-down Q point current potential, whole sram memory storage data all can be overturn, and cause transmitting data and occur mistake.
Therefore carrying out when read operation, the node voltage of storage 0 rise to 0 to Vdd/2 between certain level, specifically depend on the conducting resistance between M2 and M4.At this moment,, if this node is subject to the disturbance of a noise voltage again, just more easily overturn, thereby static noise margin reduces.Equally, the problem that also exists storage node voltage to change in the time reading " 1 ".As shown in Figure 1, BL and BLB are precharged to Vdd/2 before data reading storage, if Q=1, QB=0, M3 and M5 form path, and Q point current potential certain level between Vdd/2 and Vdd specifically depends on the size of M3 and M5 conducting resistance.
Shown in Fig. 2 is 10 metal-oxide-semiconductor sram cells of prior art, forms 4 memory node A, B, C, D carry out storage information by 10 metal-oxide-semiconductors.Wherein, A node is controlled D node and B node respectively by nmos pass transistor M1 and M4, can say, only has in the time of A=1, and A is that effectively B node is also like this to the control of D and B node.Therefore, if A=1, B=0, and A saltus step is 0, and B remains 0, and A and B node lost efficacy to the control of redundant node C and D, were unfavorable for that whole SRAM keeps stable.In a word, if A and B node are because single-particle inversion is 0 simultaneously, may cause SRAM logic to be overturn.In like manner, C and D are also like this.C controls B and D respectively by PMOS transistor M6 and M7, and D controls A and C respectively by PMOS transistor M5 and M8.So C and D be also in 0 node to external world could effectively to control be 1, therefore, if C becomes at 1 o'clock with D also saltus step simultaneously, cannot feed back.If A=0, B=1.Known.C＝0，D＝1。A becomes 1, D and cannot control A, and A can control D by M1, may drop-down D be 0.Although the current potential that B=1 to a certain extent can drop-down A, A=1 also can impact B.
Owing to often can there is the upset from O to 1 in single particle effect, therefore, wish to propose a kind of novel sram cell, can there is good anti-high level upset ability.
Summary of the invention
The invention provides a kind of improved radioresistance SRAM storage unit, this unit comprises following structure:
Inverter structure, comprises the first inverter structure, the second inverter structure, the 3rd inverter structure, the 4th inverter structure, wherein,
The first inverter structure is formed by a PMOS pipe P1 and NMOS pipe N1 series connection, the source electrode of a described PMOS pipe P1 meets power vd D, the source ground of a described NMOS pipe N1, a described PMOS manages between P1 drain electrode and the drain electrode of NMOS pipe N1 as the first memory node A;
The second inverter structure is formed by the 2nd PMOS pipe P2 and the 2nd NMOS pipe N2 series connection, the source electrode of described the 2nd PMOS pipe P2 meets power vd D, the source ground of described the 2nd NMOS pipe N2, described the 2nd PMOS pipe drains between P2 and the drain electrode of the 2nd NMOS pipe N2 as the 3rd memory node C;
The 3rd inverter structure is formed by the 3rd PMOS pipe P3 and the 3rd NMOS pipe N3 series connection, the source electrode of described the 3rd PMOS pipe P3 meets power vd D, the source ground of described the 3rd NMOS pipe N3, described the 3rd PMOS pipe drains between P3 and the drain electrode of the 3rd NMOS pipe N3 as the 4th memory node D;
The 4th inverter structure is formed by the 4th PMOS pipe P4 and the 4th NMOS pipe N4 series connection, the source electrode of described the 4th PMOS pipe P4 meets power vd D, the source ground of described the 4th NMOS pipe N4, described the 4th PMOS pipe drains between P4 and the drain electrode of the 4th NMOS pipe N4 as the second memory node B;
Described the first memory node A, the gate electrode of connection the 2nd NMOS pipe N2 and the 4th PMOS pipe P4;
Described the second memory node B, the gate electrode of connection the 3rd NMOS pipe N3 and PMOS pipe P1;
Described the 3rd memory node C, the gate electrode of connection the one NMOS pipe N1 and the 3rd PMOS pipe P3;
Described the 4th memory node D, the gate electrode of connection the 4th NMOS pipe N4 and the 2nd PMOS pipe P2;
Transmission structure, for transmitting the logic level state of memory node and the information from bit line or anti-phase bit line of being stored in, is made up of the 5th NMOS pipe N5, the 6th NMOS pipe N6.
Compared with prior art, adopt technical scheme tool provided by the invention to have the following advantages: by adopting improved SRAM storage unit, make each node control two other node by a PMOS and a NMOS, each node is also subject to the control of a PMOS and NMOS simultaneously, so just realize internodal close-loop feedback control, effectively raised anti-high level upset ability.
Brief description of the drawings
By reading the detailed description that non-limiting example is done of doing with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become.
Fig. 1 is the sram cell structural drawing of six pipe unit structures of prior art;
Fig. 2 is the radioresistance sram cell structural drawing of prior art;
The improved according to an embodiment of the invention radioresistance SRAM memory cell structure of Fig. 3 figure.
Embodiment
Describe embodiments of the invention below in detail.
The example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, only for explaining the present invention, and can not be interpreted as limitation of the present invention.Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts to specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific device the invention provides and the example of structure, but those of ordinary skill in the art can recognize the use of the property of can be applicable to and/or other structures of other devices.
The invention provides a kind of improved radioresistance SRAM memory cell structure.Below, will the improved radioresistance SRAM storage unit shown in Fig. 3 be specifically described by one embodiment of the present of invention.As shown in Figure 3, improved radioresistance SRAM storage unit provided by the present invention comprises:
Inverter structure and transmission structure, wherein said inverter structure adopts two-tube phase inverter to form feedback loop, forms a latch structure.Adopt this structure, have four node logic states in each unit, wherein the state of each node is by two other node control, and this two other play control action node do not interknit, their state is also by the state control of other nodes; In the time carrying out read operation, be stored in the level state in memory node and cross transmission structure from the information exchange of bit line or anti-phase bit line and mutually transmit, below to respectively this two part-structure being specifically introduced.
Inverter structure, for latching logic status information, comprises the first inverter structure, the second inverter structure, the 3rd inverter structure, the 4th inverter structure, wherein,
The first inverter structure is formed by a PMOS pipe P1 and NMOS pipe N1 series connection, the source electrode of a described PMOS pipe P1 meets power vd D, the source ground of a described NMOS pipe N1, a described PMOS manages between P1 drain electrode and the drain electrode of NMOS pipe N1 as the first memory node A; The second inverter structure is formed by the 2nd PMOS pipe P2 and the 2nd NMOS pipe N2 series connection, the source electrode of described the 2nd PMOS pipe P2 meets power vd D, the source ground of described the 2nd NMOS pipe N2, described the 2nd PMOS pipe drains between P2 and the drain electrode of the 2nd NMOS pipe N2 as the 3rd memory node C; The 3rd inverter structure is formed by the 3rd PMOS pipe P3 and the 3rd NMOS pipe N3 series connection, the source electrode of described the 3rd PMOS pipe P3 meets power vd D, the source ground of described the 3rd NMOS pipe N3, described the 3rd PMOS pipe drains between P3 and the drain electrode of the 3rd NMOS pipe N3 as the 4th memory node D; The 4th inverter structure is formed by the 4th PMOS pipe P4 and the 4th NMOS pipe N4 series connection, the source electrode of described the 4th PMOS pipe P4 meets power vd D, the source ground of described the 4th NMOS pipe N4, the second memory node B between described the 4th PMOS pipe drain electrode P4 and the drain electrode of the 4th NMOS pipe N4.
Wherein said the first memory node A, the gate electrode of connection the 2nd NMOS pipe N2 and the 4th PMOS pipe P4; Described the second memory node B, the gate electrode of connection the 3rd NMOS pipe N3 and PMOS pipe P1; Described the 3rd memory node C, the gate electrode of connection the one NMOS pipe N1 and the 3rd PMOS pipe P3; Described the 4th memory node D, the gate electrode of connection the 4th NMOS pipe N4 and the 2nd PMOS pipe P2.By this connected mode, just realize the feedback closed loop control between memory node, concrete, the first memory node A realizes the control to the 3rd memory node C and the second memory node B by the 2nd NMOS pipe N2 and the 4th PMOS pipe P4; The second memory node B realizes the control to the 4th memory node D and the first memory node A by the 3rd NMOS pipe N3 and PMOS pipe P1; The 3rd memory node C realizes the control to the first memory node A and the 4th memory node D by a NMOS pipe N1 and the 3rd PMOS pipe P3; The 4th memory node D realizes the control to the second memory node B and the 3rd memory node C by the 4th NMOS pipe N4 and the 2nd PMOS pipe P2.
Just realize each internodal feedback closed loop control by above structure, wherein each node is controlled two other node by a PMOS and a NMOS, each node is also subject to the control of a PMOS and NMOS simultaneously, has so just ensured the stability of whole feedback control loop.Concrete, according to known to the analysis of existing ten pipe four memory node SRAM storage unit in background note, the 3rd memory node C and the 4th memory node D are 1 o'clock, C and D method are fed back A and B, and in structure of the present invention, structural representation of the present invention is as shown in Figure 3 known, if starting condition is A=0, B=1, now known C=1, D=0.Due to the effect of C, A is difficult to become 1, B also in like manner from 0.So just can eliminate the shortcoming of the pipe of ten shown in Fig. 2 four memory node SRAM, be conducive to improve the anti-high level upset ability of whole circuit.And in actual applications, from 0 to 1 upset is more common single particle effect,
Described transmission structure is stored in the logic level state of memory node and the information from bit line or anti-phase bit line for transmitting, and comprises the 5th NMOS pipe N5, the 6th NMOS pipe N6.Wherein, the drain electrode of the 5th NMOS pipe N5 meets the first memory node A, and source electrode meets bit line BL, and grid meets word line WL; The drain electrode of the 6th NMOS pipe N6 meets the second memory node B, and source electrode meets anti-phase bit line BLB, and grid meets word line WL.
In the time reading with write operation to this storage unit, transmission structure, i.e. the 5th NMOS pipe N5, the equal conducting of the 6th NMOS pipe N6; In the time reading, anti-phase bit line BLB and bit line BL are all precharged to high level, in the time carrying out write operation, to writing 1 node, BL=1, BLB=0; To writing 0 node, BL=0, BLB=1.
Compared with prior art, the present invention has the following advantages: by adopting improved SRAM storage unit, make each node control two other node by a PMOS and a NMOS, each node is also subject to the control of a PMOS and NMOS simultaneously, so just realize internodal close-loop feedback control, effectively raised anti-high level upset ability.
Although describe in detail about example embodiment and advantage thereof, be to be understood that the protection domain in the case of not departing from spirit of the present invention and claims restriction, can carry out various variations, substitutions and modifications to these embodiment.For other examples, those of ordinary skill in the art should easily understand in keeping in protection domain of the present invention, and the order of processing step can change.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacture, material composition, means, method and the step of the specific embodiment of describing in instructions.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for had or be about at present technique, mechanism, manufacture, material composition, means, method or the step developed later, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing with the present invention, can apply them according to the present invention.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection domain.
Claims (3)
1. an improved radioresistance SRAM storage unit, this unit comprises following structure:
Inverter structure, for latching logic level state, comprises the first inverter structure, the second inverter structure, the 3rd inverter structure, the 4th inverter structure, wherein,
The first inverter structure comprises a PMOS pipe (P1) and NMOS pipe (N1) cascaded structure, and a described PMOS manages between (P1) drain electrode and the drain electrode of NMOS pipe (N1) as the first memory node (A);
The second inverter structure comprises the 2nd PMOS pipe (P2) and the 2nd NMOS pipe (N2) cascaded structure, and described the 2nd PMOS manages between drain electrode (P2) and the drain electrode of the 2nd NMOS pipe (N2) as the 3rd memory node (C);
The 3rd inverter structure comprises the 3rd PMOS pipe (P3) and the 3rd NMOS pipe (N3) cascaded structure, and described the 3rd PMOS manages between drain electrode (P3) and the drain electrode of the 3rd NMOS pipe (N3) as the 4th memory node (D);
The 4th inverter structure is managed (P4) and the 4th NMOS pipe (N4) cascaded structure by the 4th PMOS, and described the 4th PMOS manages between drain electrode (P4) and the drain electrode of the 4th NMOS pipe (N4) as the second memory node (B);
Described the first memory node (A) connects the gate electrode of the 2nd NMOS pipe (N2) and the 4th PMOS pipe (P4);
Described the second memory node (B) connects the gate electrode of the 3rd NMOS pipe (N3) and PMOS pipe (P1);
Described the 3rd memory node (C) connects the gate electrode of a NMOS pipe (N1) and the 3rd PMOS pipe (P3);
Described the 4th memory node (D) connects the gate electrode of the 4th NMOS pipe (N4) and the 2nd PMOS pipe (P2);
Transmission structure, is stored in the logic level state of memory node and the information from bit line or anti-phase bit line for transmitting, and comprises the 5th NMOS pipe (N5) and the 6th NMOS pipe (N6).
2. SRAM storage unit according to claim 1, in described inverter structure:
The source electrode of a described PMOS pipe (P1) connects power supply (VDD), the source ground of a described NMOS pipe (N1), the drain electrode of a described PMOS pipe (P1) connects the drain electrode of a described NMOS pipe (N1);
The source electrode of described the 2nd PMOS pipe (P2) connects power supply (VDD), the source ground of described the 2nd NMOS pipe (N2), the drain electrode of described the 2nd PMOS pipe (P2) connects the drain electrode of described the 2nd NMOS pipe (N2);
The source electrode of described the 3rd PMOS pipe (P3) connects power supply (VDD), the source ground of described the 3rd NMOS pipe (N3), the drain electrode of described the 3rd PMOS pipe (P3) connects the drain electrode of described the 3rd NMOS pipe (N3);
The source electrode of described the 4th PMOS pipe (P4) connects power supply (VDD), the source ground of described the 4th NMOS pipe (N4), the drain electrode of described the 4th PMOS pipe (P4) connects the drain electrode of described the 4th NMOS pipe (N4).
3. SRAM storage unit according to claim 1, wherein, in described transmission structure:
The drain electrode of the 5th NMOS pipe (N5) connects the first memory node (A), and source electrode connects bit line (BL), and grid connects word line (WL);
The source electrode of the 6th NMOS pipe (N6) connects the second memory node (B), and drain electrode connects anti-phase bit line (BLB), and grid connects word line (WL).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410223064.8A CN103971734B (en) | 2014-05-23 | 2014-05-23 | Radiation-resistant SRAM cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410223064.8A CN103971734B (en) | 2014-05-23 | 2014-05-23 | Radiation-resistant SRAM cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103971734A true CN103971734A (en) | 2014-08-06 |
| CN103971734B CN103971734B (en) | 2017-02-15 |
Family
ID=51241135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410223064.8A Active CN103971734B (en) | 2014-05-23 | 2014-05-23 | Radiation-resistant SRAM cell |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103971734B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104318953A (en) * | 2014-10-29 | 2015-01-28 | 中国科学院微电子研究所 | Static random access memory unit |
| CN106328210A (en) * | 2015-06-17 | 2017-01-11 | 复旦大学 | Method for producing radiation-resistant fault-tolerant memory cell |
| CN106328189A (en) * | 2015-06-25 | 2017-01-11 | 中国科学院电子学研究所 | Reinforced SRAM circuit for resisting single event upset |
| CN106847324A (en) * | 2016-12-26 | 2017-06-13 | 齐齐哈尔大学 | Radioresistance memory cell |
| CN106847325A (en) * | 2016-12-26 | 2017-06-13 | 中北大学 | Primary particle inversion resistant memory cell |
| CN112562756A (en) * | 2020-12-15 | 2021-03-26 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant static random access memory cell and memory |
| CN112634956A (en) * | 2021-01-27 | 2021-04-09 | 复旦大学 | Storage unit of anti-multi-node upset SRAM |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7961499B2 (en) * | 2009-01-22 | 2011-06-14 | Qualcomm Incorporated | Low leakage high performance static random access memory cell using dual-technology transistors |
| CN102034533B (en) * | 2011-01-11 | 2012-09-26 | 中国科学院半导体研究所 | Static random storage unit with resetting function |
| CN103700398B (en) * | 2013-12-30 | 2018-06-22 | 上海集成电路研发中心有限公司 | A kind of static ram cell |
-
2014
- 2014-05-23 CN CN201410223064.8A patent/CN103971734B/en active Active
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104318953A (en) * | 2014-10-29 | 2015-01-28 | 中国科学院微电子研究所 | Static random access memory unit |
| CN104318953B (en) * | 2014-10-29 | 2017-03-29 | 中国科学院微电子研究所 | static random access memory unit |
| CN106328210A (en) * | 2015-06-17 | 2017-01-11 | 复旦大学 | Method for producing radiation-resistant fault-tolerant memory cell |
| CN106328189A (en) * | 2015-06-25 | 2017-01-11 | 中国科学院电子学研究所 | Reinforced SRAM circuit for resisting single event upset |
| CN106328189B (en) * | 2015-06-25 | 2019-07-05 | 中国科学院电子学研究所 | Primary particle inversion resistant reinforcing SRAM circuit |
| CN106847324A (en) * | 2016-12-26 | 2017-06-13 | 齐齐哈尔大学 | Radioresistance memory cell |
| CN106847325A (en) * | 2016-12-26 | 2017-06-13 | 中北大学 | Primary particle inversion resistant memory cell |
| CN112562756A (en) * | 2020-12-15 | 2021-03-26 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant static random access memory cell and memory |
| CN112562756B (en) * | 2020-12-15 | 2024-03-08 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant sram cell and memory |
| CN112634956A (en) * | 2021-01-27 | 2021-04-09 | 复旦大学 | Storage unit of anti-multi-node upset SRAM |
| CN112634956B (en) * | 2021-01-27 | 2023-08-01 | 复旦大学 | Memory cell of anti-multinode overturn SRAM |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103971734B (en) | 2017-02-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103956184A (en) | Improved SRAM (static random Access memory) storage unit based on DICE (digital imaging and instrumentation) structure | |
| CN103971734B (en) | Radiation-resistant SRAM cell | |
| CN103956183A (en) | Radiation-resistant SRAM cell | |
| US20110122709A1 (en) | Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit | |
| CN102097123A (en) | Anti-single event effect static random access memory unit | |
| CN103778954A (en) | Multi-node upset resistant memorizer | |
| US10818327B2 (en) | Memory circuit and method of operating same | |
| CN105049031A (en) | DICE structure latch unit resisting single-particle irradiation effect | |
| CN105336362A (en) | Radiation hardened static random access memory | |
| US9564209B1 (en) | Non-volatile static random access memory using a 7T1R cell with initialization and pulse overwrite | |
| CN103474092A (en) | Anti-radiation hardened storage cell circuit | |
| CN104464796A (en) | Ten-transistor anti-transient effect SRAM (static random Access memory) storage unit | |
| CN103337252A (en) | Static random access memory (SRAM) with redundant structure | |
| US10373663B2 (en) | Non-volatile memory circuit | |
| US20120243287A1 (en) | Semiconductor memory device capable of improving disturbability and writability | |
| Kumar et al. | Stability and performance analysis of low power 6T SRAM cell and memristor based SRAM cell using 45NM CMOS technology | |
| JP2018092695A (en) | Semiconductor memory | |
| Li et al. | A novel SEU hardened SRAM bit-cell design | |
| CN109658962B (en) | Single-particle multi-node upset resistant near-threshold SRAM (static random Access memory) storage unit | |
| CN111128271A (en) | RHPD-12T radiation-resistant SRAM memory cell circuit | |
| CN109841244A (en) | Primary particle inversion resistant SRAM cell | |
| Bhatnagar et al. | A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology | |
| CN103093809A (en) | Static random access memory unit resisting single event upset | |
| Qi et al. | A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications | |
| CN104318953A (en) | Static random access memory unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |