CN112634956B - Memory cell of anti-multinode overturn SRAM - Google Patents

Memory cell of anti-multinode overturn SRAM Download PDF

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Publication number
CN112634956B
CN112634956B CN202110106525.3A CN202110106525A CN112634956B CN 112634956 B CN112634956 B CN 112634956B CN 202110106525 A CN202110106525 A CN 202110106525A CN 112634956 B CN112634956 B CN 112634956B
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mos
node
stacking
electrodes
storage
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CN112634956A (en
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程旭
韩源源
韩军
曾晓洋
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Fudan University
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Fudan University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an SRAM (static random Access memory) storage unit capable of resisting multi-node overturning. The SRAM storage unit consists of two p-MOS stacked structures, two n-MOS stacked structures, two p-MOS, two n-MOS and two gate tubes. The storage unit forms a non-sensitive redundant storage node by using a stacking structure, and when other sensitive nodes generate logic inversion due to a single event effect, the non-sensitive redundant node cannot invert storage information, so that the storage information of the unit is unchanged. The invention has simple structure, can effectively prevent the storage state of the unit from being overturned by multi-node overturning, and can be effectively applied to a system on a chip in a radiation environment.

Description

Memory cell of anti-multinode overturn SRAM
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to an SRAM (static random Access memory) storage unit capable of resisting multi-node overturning.
Background
The memory cells are an integral part of a System on chip (soc). Among them, SRAM is a widely used memory. In a radiation environment, conventional memory cells are subject to single event effects. The conventional SRAM cell consists of a cross-coupled inverter and two gates. When the sensitive node is attacked by particles, the p-n junction which is reversely biased collects free charges, so that the voltage of the sensitive node is changed. If the voltage of the sensitive node cannot be restored to the initial state, the opposite stored information will be saved in the storage node, resulting in soft errors.
In 2014, jing Guo published "Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology" in the journal of "IEEE Transaction on Circuits and Systems-I: regular Paper", a 12-transistor (12T) radiation-resistant SRAM cell was proposed that is capable of multi-node flipping resistance. But this structure is resistant to specific multinode flipping only. If two sensitive nodes of the same well are flipped, the cell loses its radiation-resistant function. Chunyu Peng in 2019 published a "Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application" on "IEEE Transaction on Very Large Scale Integration (VLSI) Systems," which proposed a 14 transistor (14T) Radiation-resistant SRAM cell structure. The structure is modified on the basis of the Quattro-10T, and the defect of low writing speed of the Quattro-10T structure is overcome. But the structure is not resistant to multinode flipping.
Aiming at the problems, the invention provides a 12T memory cell of a radiation-resistant SRAM, and the sensitive node of the cell can resist the single event effect and has the characteristic of resisting multi-node overturn.
Disclosure of Invention
The invention aims to provide an SRAM memory cell resistant to multi-node overturn.
The invention provides an SRAM memory cell resisting multi-node overturn, which comprises: the device comprises two p-MOS stacking structures with source and drain connected, two n-MOS stacking structures with source and drain connected, two p-MOS, two n-MOS and a pair of gate tubes; the upper stacking pipes of the two p-MOS stacking structures are connected in a cross coupling mode, the source electrodes are connected with the VDD, the drain electrodes are respectively connected with the gates of the two p-MOS, the gate electrodes of the two lower stacking pipes are grounded, and the drain electrodes are respectively connected with the drain electrodes of the two n-MOS; the lower stacking tubes of the two n-MOS stacking structures are connected in a cross coupling way, the source electrodes are grounded, the drain electrodes are respectively connected with the gates of the two n-MOS, the gate electrodes of the two upper stacking tubes are controlled by a write enable signal, and the drain electrodes are respectively connected with the drain electrodes of the two p-MOS; the gate tube is connected with BLs and a storage node, wherein the storage node is an intermediate node of an n-MOS stacking structure, and the grid electrode of the gate tube is controlled by WL.
In the invention, the grid electrode of the upper stacking tube in the n-MOS stacking structure is controlled by the write-enabling signal so as to accelerate the writing speed of the memory unit.
In the invention, when all the sensitive nodes of the n-MOS or the sensitive nodes of the p-MOS are turned over due to the single event effect, the storage information of the non-sensitive nodes can not be affected, so that the storage unit is restored to the initial storage state, namely the storage unit of the SRAM has the performance of resisting the multi-node turning over effect.
The SRAM memory unit of the invention has 12 transistors in total, and the non-sensitive redundant memory node is formed by using the stacked structure, when other sensitive nodes generate logic inversion due to the single event effect, the non-sensitive redundant node can not generate storage information inversion, thereby ensuring that the unit storage information is unchanged. The invention has simple structure, can effectively prevent the storage state of the unit from being overturned by multi-node overturning, and can be effectively applied to a system on a chip in a radiation environment.
Drawings
FIG. 1 shows a 14T SRAM cell structure.
FIG. 2 is a graph of a sense node current injection simulation waveform of a 14T SRAM cell.
Detailed Description
The invention is further elucidated below in connection with the drawings and the embodiments.
Fig. 1 is a schematic diagram of a 12TSRAM memory cell of the present invention. Wherein, M1, M5, M2 and M6 form two p-MOS stacked structures, the upper stacked tubes M1 and M2 are connected in a cross coupling way, the source electrode is connected with VDD, the drain electrode respectively controls the grid electrodes of M3 and M4, the grid electrodes of the two lower stacked tubes M5 and M6 are grounded, and the drain electrodes are respectively connected with the drain electrodes of M9 and M10. M7, M11, M8 and M12 form two p-MOS stacking structures, the lower stacking tubes M11 and M12 are connected in a cross coupling mode, the sources are grounded, the drains respectively control the gates of M9 and M10, the gates of the upper stacking tubes M7 and M8 are controlled by a write enable signal WENB, and the drains are respectively connected with the drains of M3 and M4. Wherein the storage nodes are Q, QB, P, PB, S1, S2, S3 and S4, respectively. The gate tube M13 is connected with BL and the storage node Q, the gate tube M14 is connected with BLB and the storage node QB, and the grid electrodes of M13 and M14 are controlled by WL.
The memory cell has three states, namely a holding state, a writing state and a reading state, when in operation. When the state is maintained: WENB is "1", WL is "0", and transistors M7 and M8 are in an on state to form coupling feedback; the gate pipes M13 and M14 are closed, and the bit lines (BL, BLB) and the storage nodes are isolated; the final storage state can be kept stable. When writing state: WENB is 0, M7 and M8 are closed, a feedback path is cut off, and the information writing speed is increased; the word line WL is "1", and the gate is turned on to enable the voltages of BL and BLB to rewrite the stored information of the storage nodes Q and QB. When reading the state: WENB is "1", and transistors M7 and M8 are in an on state to form coupling feedback; the bit lines BL and BLB are precharged to 1, WL is 0 in the precharge state, the gate tubes M13 and M14 are in the closed state, WL is changed to 1 after the precharge is completed, the gate tubes M13 and M14 are opened, the storage information of the storage nodes Q and QB is transferred to BL and BLB, the potential between BL and BLB forms a potential difference, and finally the potential difference is read out through the sense amplifier.
In the state where the storage nodes Q and P are "0" and QB and PB are "1", a recovery mechanism of the storage unit for multi-node inversion is analyzed. In this state, the sensitive nodes S1 and S3 are "0", and the sensitive nodes S2 and S4 are "1". FIG. 2 is a waveform diagram of a memory cell when it encounters a multi-node flip.
As shown in figure 10ns, S1 and S3 are simultaneously flipped from "0" to "1": the n-MOS stack structure of M7 and M11 ensures that the Q point remains in a weak "0" state, thus placing M9 and M12 in an off state. The flipping of S3 to "1" also causes the information at point P to become "1", resulting in M1 and M4 being turned off, leaving PB and QB unchanged by "1". When the pulse is extinguished, the memory cell resumes its original memory state.
At 20ns as shown, S2 and S4 are flipped simultaneously from "1" to "0": the p-MOS stack structure of M1 and M5 ensures that the PB point remains in a weak "1" state, thus placing M2 and M3 in the off state. Flipping S2 to "0" also causes the information at QB point to become "0", resulting in M1 and M4 being turned off, leaving Q and P unchanged at "0". When the pulse is extinguished, the memory cell resumes its original memory state.

Claims (1)

1. An SRAM memory cell resistant to multi-node flipping, comprising: the device comprises two p-MOS stacking structures with source and drain connected, two n-MOS stacking structures with source and drain connected, two p-MOS, two n-MOS and a pair of gate tubes; the upper stacking pipes of the two p-MOS stacking structures are connected in a cross coupling mode, the source electrodes are connected with the VDD, the drain electrodes are respectively connected with the grid electrodes of the two p-MOS stacking structures, the grid electrodes of the two lower stacking pipes are grounded, and the drain electrodes are respectively connected with the drain electrodes of the two n-MOS stacking structures; the lower stacking tubes of the two n-MOS stacking structures are connected in a cross coupling way, the source electrodes are grounded, the drain electrodes are respectively connected with the grid electrodes of the two n-MOS stacking structures, the grid electrodes of the two upper stacking tubes are controlled by write enable signals, and the drain electrodes are respectively connected with the drain electrodes of the two p-MOS stacking structures; the gate tube is connected with BLs and a storage node, wherein the storage node is an intermediate node of an n-MOS stacking structure, and the grid electrode of the gate tube is controlled by WL; the sources of the two p-MOSs are connected with VDD, and the sources of the two n-MOSs are grounded.
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CN104392745A (en) * 2014-11-27 2015-03-04 西安交通大学 SRAM unit with high writing speed, low static power consumption and single-particle overturning resistance
CN105336362A (en) * 2015-12-10 2016-02-17 中北大学 Radiation hardened static random access memory
CN108766492A (en) * 2017-12-28 2018-11-06 北京时代民芯科技有限公司 A kind of anti-SEU storage unit circuits of low single-particle sensibility

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CN103337252A (en) * 2013-06-26 2013-10-02 清华大学 Static random access memory (SRAM) with redundant structure
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CN105336362A (en) * 2015-12-10 2016-02-17 中北大学 Radiation hardened static random access memory
CN108766492A (en) * 2017-12-28 2018-11-06 北京时代民芯科技有限公司 A kind of anti-SEU storage unit circuits of low single-particle sensibility

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