CN112634956A

CN112634956A - Storage unit of anti-multi-node upset SRAM

Info

Publication number: CN112634956A
Application number: CN202110106525.3A
Authority: CN
Inventors: 程旭; 韩源源; 韩军; 曾晓洋
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2021-01-27
Filing date: 2021-01-27
Publication date: 2021-04-09
Anticipated expiration: 2041-01-27
Also published as: CN112634956B

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an SRAM (static random access memory) storage unit resisting multi-node overturning. The SRAM memory unit consists of two p-MOS stacked structures, two n-MOS stacked structures, two p-MOS, two n-MOS and two gate tubes. The storage unit forms the non-sensitive redundant storage node by utilizing the stacking structure, and when other sensitive nodes generate logic inversion due to the single event effect, the non-sensitive redundant node cannot generate stored information inversion, so that the stored information of the unit is ensured to be unchanged. The invention has simple structure, can effectively prevent the storage state of the multi-node overturning initiating unit from overturning, and can be effectively applied to a system on chip in a radiation environment.

Description

Storage unit of anti-multi-node upset SRAM

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to an SRAM (static random access memory) storage unit resisting multi-node overturning.

Background

The memory unit is an indispensable part of a System on chip (System on chip). Among them, SRAM is a widely used memory. In a radiation environment, a conventional memory cell is affected by a single event effect. A conventional SRAM cell consists of a cross-coupled inverter and two gate tubes. When the sensitive node is attacked by particles, the reverse biased p-n junction will collect free charges, resulting in a change in the voltage of the sensitive node. If the voltage of the sensitive node cannot be restored to the original state, the opposite stored information will be stored in the storage node, resulting in a soft error.

In 2014, Jingguo published "Novel Low-Power and high reusable Radiation Hardened Memory Cell for 65 nm CMOS Technology" in "IEEE Transaction on Circuits and Systems-I: Regular Paper", and proposed a 12-transistor (12T) Radiation-resistant SRAM Cell, which is capable of resisting multi-node flip. But this structure can resist only a specific multi-node upset. If two sensitive nodes of the same trap are overturned, the unit loses the radiation-resistant function. In 2019, Chunyu Peng published a "Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application" on IEEE Transaction on Virtual Large Scale Integration (VLSI) Systems ", which proposed a Radiation-resistant SRAM cell structure of 14 transistors (14T). The structure is modified on the basis of Quatro-10T, and the defect of low writing speed of the Quatro-10T structure is overcome. But this structure is not resistant to multi-node upsets.

Aiming at the problems, the invention provides a 12T storage unit of a radiation-resistant SRAM, and sensitive nodes of the unit can resist single event effect and have the characteristic of resisting multi-node upset.

Disclosure of Invention

The invention aims to provide an SRAM memory cell resistant to multi-node upset.

The invention provides an SRAM memory cell resisting multi-node upset, which comprises: the semiconductor device comprises two source-drain interconnected p-MOS stacked structures, two source-drain interconnected n-MOS stacked structures, two p-MOS, two n-MOS and a pair of gate tubes; the upper stacked tubes of the two p-MOS stacked structures are in cross coupling connection, the source electrodes are connected with VDD, the drain electrodes are respectively connected with the grids of the two p-MOS stacked structures, the grid electrodes of the two lower stacked tubes are grounded, and the drain electrodes are respectively connected with the drain electrodes of the two n-MOS stacked structures; the lower stacked tubes of the two n-MOS stacked structures are in cross coupling connection, the source electrodes are grounded, the drain electrodes are respectively connected with the grids of the two n-MOS stacked tubes, the grid electrodes of the two upper stacked tubes are controlled by a write enable signal, and the drain electrodes are respectively connected with the drain electrodes of the two p-MOS stacked tubes; the gate tube connects BLs and a storage node, where the storage node is an intermediate node of the n-MOS stacked structure, and the gate of the gate tube is controlled by WL.

In the invention, the grid electrode of the upper stacked tube in the n-MOS stacked structure is controlled by the write enable signal so as to accelerate the write-in speed of the memory cell.

In the invention, when all the sensitive nodes of the n-MOS or the sensitive nodes of the p-MOS are overturned due to the single event effect, the storage information of the non-sensitive nodes can not be influenced, so that the storage unit can restore the initial storage state, namely the storage unit of the SRAM has the performance of resisting the multi-node overturning effect.

The SRAM storage unit of the invention has 12 transistors in total, a non-sensitive redundant storage node is formed by utilizing a stacked structure, and when other sensitive nodes generate logic inversion due to a single event effect, the non-sensitive redundant node can not generate stored information inversion, thereby ensuring that the stored information of the unit is unchanged. The invention has simple structure, can effectively prevent the storage state of the multi-node overturning initiating unit from overturning, and can be effectively applied to a system on chip in a radiation environment.

Drawings

FIG. 1 is a 14T SRAM cell structure.

FIG. 2 is a graph of a 14T SRAM cell sense node current injection simulation waveform.

Detailed Description

The invention is further illustrated below with reference to the figures and examples.

FIG. 1 is a schematic diagram of a 12TSRAM memory cell according to the present invention. The M1, the M5, the M2 and the M6 form two p-MOS stacked structures, the upper stacked tube M1 and the M2 are in cross-coupled connection, the source is connected with VDD, the drain controls the gates of the M3 and the M4 respectively, the gates of the two lower stacked tubes M5 and M6 are grounded, and the drain is connected with the drains of the M9 and the M10 respectively. M7, M11, M8 and M12 form two p-MOS stacked structures, a lower stacked tube M11 and M12 are in cross-coupling connection, the source is grounded, the drain controls the gates of M9 and M10 respectively, the gates of upper stacked tubes M7 and M8 are controlled by a write enable signal WENB, and the drain is connected with the drains of M3 and M4 respectively. Wherein the storage nodes are Q, QB, P, PB, S1, S2, S3 and S4, respectively. The gates of gate M13 connecting BL and storage node Q, gate M14 connecting BLB and storage nodes QB, M13 and M14 are controlled by WL.

The memory cell has three states, namely a hold state, a write state and a read state when in operation. When the state is maintained: WENB is 1, WL is 0, transistors M7, M8 are in on state, and coupling feedback is formed; gates M13 and M14 are closed, isolating the bit lines (BL, BLB) from the storage nodes; the final memory state can remain stable. In the writing state: WENB is '0', M7 and M8 are closed, a feedback path is cut off, and the information writing speed is accelerated; the word line WL is "1", and the gate line is turned on to allow the potentials of BL and BLB to rewrite the storage information of the storage nodes Q and QB. When in a reading state: WENB is 1, and the transistors M7 and M8 are in an open state to form coupling feedback; bit lines BL and BLB are precharged to '1', WL is '0' in the precharge state, gate tubes M13 and M14 are in the closed state, WL becomes '1' after precharge is finished, gate tubes M13 and M14 are opened, stored information of storage nodes Q and QB is transferred to BL and BLB, potential difference is formed between BL and BLB, and finally the potential difference is read out through a sensitive amplifier.

And analyzing a recovery mechanism of the storage unit for multi-node overturning in the state that the storage nodes Q and P are '0' and QB and PB are '1'. In this state, the sensitive nodes S1 and S3 are "0" and the sensitive nodes S2 and S4 are "1". FIG. 2 is a waveform diagram of a memory cell when it encounters a multi-node flip.

As shown in FIG. 10ns, S1 and S3 are simultaneously flipped from "0" to "1": the n-MOS stacked structure composed of M7 and M11 ensures that the Q point is maintained in a weak "0" state, thereby keeping M9 and M12 in an off state. The S3 flip to "1" also makes the information of P point become "1", resulting in M1 and M4 being turned off, keeping PB and QB unchanged at "1". When the pulse disappears, the memory cell restores to the original memory state.

As shown in fig. 20ns, S2 and S4 simultaneously flip from "1" to "0": the p-MOS stack structure composed of M1 and M5 ensures that the PB point is kept in a weak "1" state, so that M2 and M3 are in an off state. Flipping S2 to "0" also causes the information at QB point to become "0", causing M1 and M4 to be turned off, keeping Q and P unchanged at "0". When the pulse disappears, the memory cell restores to the original memory state.

Claims

1. An SRAM memory cell resistant to multi-node flipping, comprising: the semiconductor device comprises two source-drain interconnected p-MOS stacked structures, two source-drain interconnected n-MOS stacked structures, two p-MOS, two n-MOS and a pair of gate tubes; the upper stacked tubes of the two p-MOS stacked structures are in cross coupling connection, the source electrodes are connected with VDD, the drain electrodes are respectively connected with the grids of the two p-MOS stacked structures, the grid electrodes of the two lower stacked tubes are grounded, and the drain electrodes are respectively connected with the drain electrodes of the two n-MOS stacked structures; the lower stacked tubes of the two n-MOS stacked structures are in cross coupling connection, the source electrodes are grounded, the drain electrodes are respectively connected with the grids of the two n-MOS stacked tubes, the grid electrodes of the two upper stacked tubes are controlled by a write enable signal, and the drain electrodes are respectively connected with the drain electrodes of the two p-MOS stacked tubes; the gate tube connects BLs and a storage node, where the storage node is an intermediate node of the n-MOS stacked structure, and the gate of the gate tube is controlled by WL.

2. The SRAM memory cell of claim 1, wherein the gate of the upper stacked transistor in the n-MOS stacked structure is controlled by a write enable signal to increase the writing speed of the memory cell.

3. The storage unit of the SRAM of claim 1, wherein when all the sensitive nodes of the n-MOS or the sensitive nodes of the p-MOS are flipped due to the single event effect, the storage information of the non-sensitive nodes can be unaffected, so that the storage unit can recover the initial storage state, i.e. the storage unit of the SRAM has the performance of resisting the multi-node flipping effect.