JP2018092695A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of reading data more accurately.SOLUTION: A semiconductor memory includes: a bit line and a source line connected to a memory cell; a driver 31 for applying a first read voltage to the source line; a capacitor 30 connected to the bit line; a readout circuit 24 for finding a first time until a voltage of the bit line reaches the first voltage after the first readout voltage is applied to the source line; and a determination circuit 50 for determining a data of the memory cell by using the first time.SELECTED DRAWING: Figure 5

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  A processor used for a portable information terminal is required to have low power consumption. As one of the methods for reducing the power consumption of the processor, there is a method of replacing a cache memory composed of a static random access memory (SRAM) having a large standby power with a nonvolatile memory using a nonvolatile memory element. In SRAMs, with the miniaturization of transistors, leakage current increases both during operation and during standby. For this reason, by replacing the cache memory with a non-volatile memory, the cache memory can be powered off during standby, and power consumption during standby can be reduced.

  For example, an attempt to reduce the power consumption of a processor by using a magnetic random access memory (MRAM) as a cache memory has been studied. The MRAM is a memory that can simultaneously satisfy the three characteristics of high rewrite resistance, high-speed read / write operation performance, and high-integrable cell area among currently proposed non-volatile memories. When the MRAM is used as a cache memory, the operation speed is higher than that of other nonvolatile memories, the area efficiency is higher than that of other nonvolatile memories, and a large-capacity high-speed cache can be mounted on the processor. Expected.

  In the read operation of the MRAM, a current comparison read method using a reference cell is known. In this read method, it is an essential condition for performing an accurate read operation to realize a high MR (magnetoresistance) ratio, a low RA (resistance area product), and a low variation MTJ (magnetic tunnel junction) element. However, if the miniaturization of the MTJ element progresses or the RA becomes high, a certain cell current cannot be secured and a read error occurs.

US Patent Application Publication No. 2009/0323402

  Embodiments provide a semiconductor memory device capable of reading data more accurately.

  The semiconductor memory device according to the embodiment includes a memory cell including a variable resistance element, a bit line and a source line connected to the memory cell, and a first read voltage applied to the source line in a first read operation. One driver; a second driver for applying a second read voltage different from the first read voltage to the source line in a second read operation after the first read operation; a capacitor connected to the bit line; A read circuit for obtaining a first time from when the first read voltage is applied to the source line until the voltage of the bit line becomes the first voltage; and in the first read operation, the first time is And a determination circuit for determining data of the memory cell. When the data read by the first read operation is an error, the read circuit applies the second read voltage to the source line until the voltage of the bit line becomes the first voltage. The second time is calculated. The determination circuit determines data of the memory cell using the first time and the second time in the second read operation.

1 is a block diagram of a semiconductor memory device according to a first embodiment. FIG. 2 is a block diagram of the column control circuit shown in FIG. 1. FIG. 3 is a circuit diagram of the memory block shown in FIG. 2. FIG. 4 is a cross-sectional view of the MTJ element shown in FIG. 3. FIG. 6 is a circuit diagram of a reading circuit and a reading driver. The circuit diagram of a data determination circuit. The figure explaining resistance value distribution of an MTJ element. The figure explaining the relationship between the size of the MTJ element and the read current. FIG. 6 is a diagram illustrating a read current path flowing in a memory cell. The figure explaining the time constant RC on a read-out electric current path. The figure explaining the read-out electric current which flows into the MTJ element of a parallel state and an antiparallel state. The figure explaining the voltage of the capacitor charged by the reading current in the parallel state and the antiparallel state. 6 is a flowchart showing a read operation according to the first embodiment. FIG. 6 is a timing diagram of a read operation in a single end mode. The flowchart which shows the data determination operation | movement in single end mode. The figure explaining the relationship between the applied voltage and resistance value of an MTJ element. FIG. 6 is a timing diagram of a read operation in a self-reference mode. The flowchart which shows the data determination operation | movement in self-reference mode. The circuit diagram of the read-out circuit concerning a 2nd embodiment. The circuit diagram of the read-out circuit concerning a 3rd embodiment. The circuit diagram of the read-out circuit concerning a 4th embodiment. The circuit diagram of the read-out circuit concerning a 5th embodiment. FIG. 10 is a timing diagram of a read operation according to the fifth embodiment. 6A and 6B illustrate a method for setting a read voltage. The circuit diagram of the read-out circuit concerning a 6th embodiment. The circuit diagram of the read-out circuit concerning a 7th embodiment. FIG. 6 is a diagram for explaining how a global bit line is discharged in a read operation.

  Hereinafter, embodiments will be described with reference to the drawings. The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is specified by the shape, structure, arrangement, etc. of components. Is not to be done. Each functional block can be realized as hardware, software, or a combination of both. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

  In the present embodiment, an explanation will be given by taking an MRAM (Magnetic Random Access Memory) as an example of the semiconductor memory device.

[First Embodiment]
[1] Configuration of Semiconductor Memory Device FIG. 1 is a block diagram of a semiconductor memory device (MRAM) 10 according to the first embodiment. The semiconductor memory device 10 includes a memory cell array 11, a row decoder 12, a column decoder 13, a column control circuit 14, an ECC (Error Checking and Correcting) circuit 15, an input / output circuit (I / O circuit) 16, an address register 17, and a control circuit. (Controller) 18 and a voltage generation circuit 19 are provided.

  The memory cell array 11 includes a plurality of memory cells MC. Each memory cell MC includes an MTJ (magnetic tunnel junction) element as a storage element. A specific configuration of the memory cell MC will be described later.

  In the memory cell array 11, a plurality of word lines WL extending in the row direction, a plurality of local bit lines LBL extending in the column direction intersecting the row direction, and a plurality of local source lines LSL extending in the column direction are arranged. Memory cell MC is connected to one word line WL, one local bit line LBL, and one local source line LSL.

  The row decoder 12 is connected to a plurality of word lines WL. The row decoder 12 receives a row address from the address register 17. The row decoder 12 decodes a row address and selects a word line WL based on a decode signal (row selection signal). The row decoder 12 includes a driver (not shown) that drives the word line WL, for example.

  The column decoder 13 receives a column address from the address register 17. The column decoder 13 decodes the column address and sends a decode signal (column selection signal) to the column control circuit 14.

  The column control circuit 14 is connected to a plurality of local bit lines LBL and a plurality of local source lines LSL. The column control circuit 14 performs data reading, data writing, and data erasing with respect to the selected column. The column control circuit 14 includes a read circuit (sense amplifier), a write circuit (write driver), and the like. A specific configuration of the column control circuit 14 will be described later.

  The input / output circuit 16 is connected to an external device via an input / output terminal I / O. The input / output circuit 16 exchanges data with an external device. Data exchange between the input / output circuit 16 and the column control circuit 14 is performed via the bus 20. The bus 20 is a bidirectional data bus.

  The control circuit 18 controls the overall operation of the semiconductor memory device 10. The control circuit 18 sends various external control signals such as a chip enable signal / CE, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal / WE, and a read enable signal / RE to an external device (such as a host controller). ) The “/” appended to the signal name represents active low.

  The control circuit 18 identifies the address ADD and the command CMD supplied from the input / output terminal I / O based on these external control signals. Then, the control circuit 18 sends the address ADD to the row decoder 12 and the column decoder 13 via the address register 17. In addition, the control circuit 18 decodes the command CMD. The control circuit 18 performs sequence control regarding each of data reading, data writing, and data erasing in accordance with an external control signal and a command.

  The voltage generation circuit 19 generates an internal voltage (for example, including a voltage boosted from the power supply voltage) necessary for each operation. The voltage generation circuit 19 is controlled by the control circuit 18 and generates a necessary voltage.

[1-1] Configuration of Column Control Circuit 14 FIG. 2 is a block diagram of the column control circuit 14 shown in FIG. FIG. 2 shows a configuration example in which bit lines and source lines are hierarchized. However, the present invention is not limited to this, and the bit line and the source line may not be hierarchized. The correspondence between the memory cell array, the bit line, and the source line can be arbitrarily set.

  The memory cell array 11 includes a plurality of memory blocks MB0 to MBj. “J” is an integer of 1 or more. In the description of the present embodiment, when there is no need to particularly distinguish between the plurality of memory blocks MB0 to MBj, the branch numbers are omitted, and the description regarding the description without the branch numbers is given for the plurality of memory blocks MB0. Common to each of MBj. The other reference numbers with branch numbers are handled in the same manner. Each memory block MB includes a plurality of memory cells MC arranged in a matrix. In the memory block MB, a plurality of word lines WL (WL0 to WLn), a plurality of local bit lines LBL, and a plurality of local source lines LSL are arranged. “N” is an integer of 1 or more.

  The column control circuit 14 includes column selection circuits 21-0 to 21-j, column selection circuits 22-0 to 22-j, write circuits 23-0 to 23-j, read circuits 24-0 to 24-j, and read drivers. 25-0 to 25-j and data buffers 26-0 to 26-j.

  The column selection circuit 21 is connected to a plurality of local bit lines LBL arranged in the memory block MB. The column selection circuit 21 selects one local bit line LBL based on a column selection signal from the column decoder 13. The column selection circuit 21 connects the selected local bit line LBL to the global bit line GBL.

  The column selection circuit 22 is connected to a plurality of local source lines LSL arranged in the memory block MB. The column selection circuit 22 selects one local source line LSL based on the column selection signal from the column decoder 13. The column selection circuit 22 connects the selected local source line LSL to the global source line GSL.

  The write circuit 23 is connected to the global bit line GBL and the global source line GSL. In the write operation, the write circuit 23 writes data to the selected memory cell by, for example, passing a current through the selected memory cell.

  The read circuit 24 is connected to the global bit line GBL, and the read driver 25 is connected to the global source line GSL. In the read operation, the read driver 25 applies a read voltage to the global source line GSL. In the read operation, the read circuit 24 reads the data stored in the memory cell by detecting the current flowing through the selected memory cell. Details of the read circuit 24 and the read driver 25 will be described later.

  The data buffer 26 temporarily stores write data to be written to the memory cell in the write operation. The data buffer 26 temporarily stores read data read from the memory cell in the read operation.

[1-2] Configuration of Memory Block MB FIG. 3 is a circuit diagram of the memory block MB shown in FIG.

  The memory block MB includes a plurality of word lines WL (WL0 to WLn) extending in the row direction, a plurality of local bit lines LBL (LBL0 to LBLm) extending in the column direction, and a plurality of local source lines LSL (LSL0) extending in the column direction. To LSLm). “M” is an integer of 1 or more. The plurality of local bit lines LBL and the plurality of local source lines LSL are alternately arranged.

  The memory cell MC includes an MTJ (magnetic tunnel junction) element 27 as a storage element and a cell transistor (selection transistor) 28. The MTJ element 27 is a magnetoresistive element (magnetoresistance effect element) that stores data according to a change in resistance state and can rewrite the data with a current, for example. The cell transistor 28 is composed of, for example, an n-channel MOS (metal oxide semiconductor) transistor.

  One end of the MTJ element 27 is connected to the local bit line LBL, and the other end is connected to the drain of the cell transistor 28. The gate of the cell transistor 28 is connected to the word line WL, and its source is connected to the local source line LSL.

[1-3] Configuration of MTJ Element 27 Next, an example of the configuration of the MTJ element 27 will be described. FIG. 4 is a cross-sectional view of the MTJ element 27 shown in FIG.

  The MTJ element 27 is configured by laminating a lower electrode 27A, a storage layer (free layer) 27B, a nonmagnetic layer (tunnel barrier layer) 27C, a reference layer (fixed layer) 27D, and an upper electrode 27E in this order. For example, the lower electrode 27A is electrically connected to the cell transistor 28, and the upper electrode 27E is electrically connected to the local bit line LBL. Note that the stacking order of the memory layer 27B and the reference layer 27D may be reversed.

  The storage layer 27B and the reference layer 27D are each made of a ferromagnetic material. The tunnel barrier layer 27C is made of an insulating material such as MgO.

  Each of the storage layer 27B and the reference layer 27D has, for example, perpendicular magnetic anisotropy, and their easy magnetization direction is perpendicular. Here, the perpendicular magnetic anisotropy indicates that the magnetization direction is perpendicular or almost perpendicular to the film surface (upper surface or lower surface). The term “substantially perpendicular” includes that the direction of residual magnetization is within a range of 45 ° <θ ≦ 90 ° with respect to the film surface. Note that the magnetization directions of the storage layer 27B and the reference layer 27D may be in-plane directions.

  The memory layer 27B has a variable magnetization direction (inverts). “The magnetization direction is variable” means that the magnetization direction of the storage layer 27B can be changed when a predetermined write current is passed through the MTJ element 27. The reference layer 27D has an invariable magnetization direction (fixed). “The magnetization direction is unchanged” means that the magnetization direction of the reference layer 27 </ b> D does not change when a predetermined write current is passed through the MTJ element 27.

  The reference layer 27D is set to have a perpendicular magnetic anisotropy energy (or coercive force) sufficiently larger than that of the storage layer 27B. The magnetic anisotropy can be set by adjusting the material, area, and film thickness of the magnetic layer. In this way, the magnetization reversal current of the storage layer 27B is reduced, and the magnetization reversal current of the reference layer 27D is made larger than the magnetization reversal current of the storage layer 27B. Thereby, it is possible to realize the MTJ element 27 including the storage layer 27B having a variable magnetization direction and the reference layer 27D having a constant magnetization direction with respect to a predetermined write current.

  In this embodiment, a spin injection writing method is used in which a write current is directly supplied to the MTJ element 27 and the magnetization state of the MTJ element 27 is controlled by this write current. The MTJ element 27 can take either a low resistance state or a high resistance state depending on whether the relative relationship of magnetization between the storage layer 27B and the reference layer 27D is parallel or antiparallel. That is, the MTJ element 27 is a variable resistance element.

  When a write current from the storage layer 27B to the reference layer 27D is applied to the MTJ element 27, the relative relationship of magnetization between the storage layer 27B and the reference layer 27D becomes parallel. In the parallel state, the MTJ element 27 has the lowest resistance value, and the MTJ element 27 is set in the low resistance state. The low resistance state of the MTJ element 27 is defined as data “0”, for example.

  On the other hand, when a write current from the reference layer 27D to the storage layer 27B is applied to the MTJ element 27, the relative relationship of magnetization between the storage layer 27B and the reference layer 27D becomes antiparallel. In the antiparallel state, the MTJ element 27 has the highest resistance value, and the MTJ element 27 is set to the high resistance state. The high resistance state of the MTJ element 27 is defined as data “1”, for example.

  Thereby, the MTJ element 27 can be used as a storage element capable of storing 1-bit data (binary data). The assignment of the resistance state and data of the MTJ element 27 can be arbitrarily set.

[1-4] Configurations of Read Circuit 24 and Read Driver 25 Next, configurations of the read circuit 24 and the read driver 25 will be described. FIG. 5 is a circuit diagram of the read circuit 24 and the read driver 25. In FIG. 5, the read circuit 24 and the read driver 25 connected to one global bit line GBL and one global source line GSL are extracted and shown.

  In FIG. 5, one memory cell MC is extracted and shown. One end of the memory cell MC is connected to the global bit line GBL via a column selection switch 21A included in the column selection circuit 21. The other end of the memory cell MC is connected to the global source line GSL via a column selection switch 22A included in the column selection circuit 22. The column selection switches 21A and 22A are composed of, for example, transfer gates in which an n-channel MOS transistor and a p-channel MOS transistor are connected in parallel. The column selection switches 21A and 22A receive column selection signals CL and / CL from the column decoder 13, and are turned on when the column selection signal CL is at a high level (the column selection signal / CL is at a low level). The column selection signal / CL is an inverted signal of the column selection signal CL.

  A capacitor 30 is connected to the global bit line GBL. One electrode of the capacitor 30 is connected to the global bit line GBL, and the other electrode of the capacitor 30 is connected to the ground terminal VSS. Capacitor 30 integrates the charge due to the read current flowing through memory cell MC in the read operation.

  The read driver 25 includes switching elements 31 and 32 and power supply lines 33 and 34. The switching elements 31, 32 are composed of, for example, n-channel MOS transistors. The source of the MOS transistor 31 is connected to the global source line GSL, the drain thereof is connected to the power supply line 33, and a read signal (first read signal) RD 1 is input from the control circuit 18 to the gate. The source of the MOS transistor 32 is connected to the global source line GSL, the drain thereof is connected to the power supply line 34, and the read signal (second read signal) RD 2 is input from the control circuit 18 to the gate.

  As will be described later, in the present embodiment, two read operations of a single end mode and a self-reference mode can be executed. MOS transistor 31 is used in the single end mode, and MOS transistor 32 is used in the self-reference mode. A read voltage (first read voltage) VR1 for single end mode is applied to the power supply line 33 by the voltage generation circuit 19. A read voltage (second read voltage) VR2 for the self-reference mode is applied to the power supply line 34 by the voltage generation circuit 19.

  The global bit line GBL is connected to the read circuit 24 via the switching element 40. The switching element 40 is composed of, for example, an n-channel MOS transistor. The drain of the MOS transistor 40 is connected to the global bit line GBL, the source is connected to the wiring 41, and the read enable signal RE is input from the control circuit 18 to the gate.

  The readout circuit 24 is composed of a TDC (Time-to-Digital Converter). The read circuit 24 includes an n-channel MOS transistor (discharge element) 42, a p-channel MOS transistor 43, an inverter circuit 44, and a counter 46. An n-channel MOS transistor may be expressed as an NMOS transistor, and a p-channel MOS transistor may be expressed as a PMOS transistor.

  The drain of the MOS transistor 42 is connected to the wiring 41, the source is connected to the ground terminal VSS, and the pre-discharge signal PDE is input from the control circuit 18 to the gate.

  An input terminal of the inverter circuit 44 (corresponding to the node N1) is connected to the wiring 41. The inverter circuit 44 is configured by connecting a p-channel MOS transistor 44A and an n-channel MOS transistor 44B in series. The source of the MOS transistor 44A is connected to the power supply terminal VDD via the MOS transistor 43, the drain thereof is connected to the node N2 (corresponding to the output terminal of the inverter circuit 44), and the gate thereof is connected to the node N1. Connected to the wiring 41. A sense amplifier enable signal / SE is input from the control circuit 18 to the gate of the MOS transistor 43. The drain of the MOS transistor 44B is connected to the node N2, its source is connected to the ground terminal VSS, and its gate is connected to the wiring 41 via the node N1.

  The clock signal CLK is input from the control circuit 18 to the first input terminal of the AND gate 45, and the second input terminal is connected to the node N2.

  The counter 46 includes a plurality of D latch circuits 47-0 to 47-k and a plurality of inverter circuits 48-0 to 48-k. The counter 46 may be any circuit other than that shown in FIG.

  The D latch circuit 47 latches the data at the input terminal D at the falling edge of the clock signal, and outputs the latched data from the output terminal Q. The D latch circuit 47 receives the reset signal RST from the control circuit 18 and is reset when the reset signal RST is asserted as a high level.

  The clock terminal of the D latch circuit 47-0 is connected to the output terminal of the AND gate 45, its input terminal D is connected to the output terminal of the inverter circuit 48-0, and its output terminal Q is connected to the inverter circuit 48-0. And the clock terminal of the D latch circuit 47-1 at the next stage. The connection relationship between the D latch circuits 47-1 to 47-k and the inverter circuits 48-1 to 48-k is the same as the connection relationship between the D latch circuit 47-0 and the inverter circuit 48-0.

  The outputs of the D latch circuits 47-0 to 47-k are output from the read circuit 24 through the bus 49 as the (k + 1) -bit output signal OUT <k: 0>. The counter 46 configured in this manner counts up the clock signal CLK and outputs a (k + 1) -bit digital signal (digital data).

[1-5] Configuration of Data Determination Circuit 50 Next, the configuration of the data determination circuit 50 that receives the output signal OUT <k: 0> from the read circuit 24 will be described. FIG. 6 is a circuit diagram of the data determination circuit 50. The data determination circuit 50 is included in the column control circuit 14.

  The data determination circuit 50 determines the data stored in the memory cell MC using the digital signal sent from the read circuit 24. The data determination circuit 50 includes registers 51 to 54, a multiplier 55, comparators (Comp) 56 and 57, and a selector (multiplexer) 58.

  Register 51 stores output signal OUT <k: 0> in the single end mode. The register 51 stores the output signal OUT <k: 0> when the enable signal EN1 sent from the control circuit 18 is asserted as a high level. The register 52 stores the output signal OUT <k: 0> in the self-reference mode. The register 52 stores the output signal OUT <k: 0> when the enable signal EN2 sent from the control circuit 18 is asserted as a high level.

  The register 53 stores reference data (standard data) Dref composed of digital data. The reference data Dref is used to determine data “1” and data “0” of the memory cell MC.

  The register 54 stores a predetermined α value. The multiplier 55 multiplies the output of the register 52 by the α value of the register 54.

  The reference data Dref is input from the register 53 to the first input terminal of the comparator 56, and the output of the register 51 is input to the second input terminal. The comparator 56 outputs data “0” (indicating that the MTJ element is in a parallel state) when the output of the register 51 is smaller than the reference data Dref, and when the output of the register 51 is larger than the reference data Dref. Data “1” (indicating that the MTJ element is in an antiparallel state) is output.

  The output of the register 51 is input to the first input terminal of the comparator 57, and the output of the multiplier 55 is input to the second input terminal. The comparator 57 outputs data “0” when the output of the register 51 is smaller than the output of the multiplier 55, and outputs data “1” when the output of the register 51 is larger than the output of the multiplier 55. The α value of the multiplier 55 is set to a value with which the data in the memory cell MC can be more accurately determined in self-reference reading. Details of the data determination will be described later.

  The first input terminal of the selector 58 is connected to the output terminal of the comparator 56, the second input terminal is connected to the output terminal of the comparator 57, and the selection signal SEL is input from the control circuit 18 to the control terminal. The Based on the selection signal SEL, the selector 58 selects the output of the comparator 56 in the single-end mode, and selects the output of the comparator 57 in the self-reference mode.

[2] Operation Next, the operation of the semiconductor memory device 10 configured as described above will be described.

FIG. 7 is a diagram for explaining the resistance value distribution of the MTJ element. Figure 7 shows the resistance distribution R _P in the MTJ element in the parallel state, the resistance distribution R _AP in the MTJ element are antiparallel state. The horizontal axis of FIG. 7 is the voltage [Arbitrary unit] applied to the MTJ element, and the vertical axis of FIG. 7 is the number of MTJ elements (number of bits) [Arbitrary unit].

  The resistance value of the MTJ element in the parallel state is lower than the resistance value of the MTJ element in the antiparallel state. However, there are MTJ elements having a high resistance value in the parallel state, and such MTJ elements overlap with the distribution in the antiparallel state. The MTJ element included in the broken line in FIG. 7 cannot read data correctly, resulting in a read error.

  FIG. 8 is a diagram for explaining the relationship between the size (MTJ diameter) of the MTJ element and the read current. FIG. 8 indicates that the read current of the MTJ element decreases as the size of the MTJ element decreases. That is, as the size of the MTJ element decreases, the resistance value of the MTJ element increases. Since the storage capacity of the semiconductor memory device can be increased by reducing the size of the MTJ element, it is desirable to make the MTJ element finer.

  In the present embodiment, an effective read method is disclosed when the resistance value of the MTJ element increases and the read current decreases. For this purpose, the read operation is performed using a time constant based on the time for charging the capacitor 30 with the read current.

[2-1] Overview of Read Operation FIG. 9 is a diagram for explaining a read current path flowing in the memory cell MC. In FIG. 9, the hierarchical structure of the bit lines and the source lines is omitted, and the relationship between the plurality of memory cells MC connected to the bit lines BL and the source lines SL and the peripheral circuits is shown.

  The read driver 25 applies a read voltage VR to the source line SL. When a certain word line is selected, a read current flows through a path that passes through the read driver 25, the source line SL, the selected memory cell MC, the bit line BL, and the capacitor 30 in order. In the read operation, the bit line BL serves as an observation point, and the read circuit 24 connected to the bit line BL reads data.

  FIG. 10 is a diagram for explaining the time constant RC on the read current path. FIG. 10A is a diagram when the size of the MTJ element is relatively large, and FIG. 10B is a diagram when the size of the MTJ element is relatively small. In FIG. 10, in the MTJ element, the resistance value in the antiparallel state (AP state) is larger than the resistance value in the parallel state (P state). Therefore, the time constant RC in the antiparallel state is larger than the time constant RC in the parallel state.

  The time constant RC on the read current path is divided into an MTJ component (a portion with hatching in FIG. 10) and a parasitic component (a portion with no hatching in FIG. 10). The MTJ component is a time constant related to the resistance value of the MTJ element. The parasitic component is a time constant related to the wiring to which the MTJ element is connected. The time constant of the parasitic component is approximately constant as shown in FIG.

  In the case of FIG. 10A, in order to increase the difference between the time constant in the parallel state and the time constant in the antiparallel state, it is necessary to increase the magnetoresistance ratio (MR ratio) of the MTJ element. Since the MR ratio of the MTJ element largely depends on the material constituting the MTJ element, it is not easy to increase the MR ratio of the MTJ element.

  In the case of FIG. 10B, since the resistance value of the MTJ element is large, the difference between the time constant in the parallel state and the time constant in the antiparallel state is sufficiently large. Therefore, the data stored in the memory cell can be read more accurately by using the time constant for the read operation. Also, as the MTJ element size decreases, the difference between the time constant in the parallel state and the time constant in the antiparallel state increases, so that the data stored in the memory cell can be more accurately stored without increasing the MR ratio. Can be read.

  FIG. 11 is a diagram for explaining the read current flowing through the MTJ element in the parallel state and the anti-parallel state. The horizontal axis in FIG. 11 represents time, and the vertical axis in FIG. 11 represents the read current. FIG. 11 illustrates the timing at which the column selection signal CL, the word line WL, and the sense amplifier enable signal SE are asserted. As can be understood from FIG. 11, the read current flowing through the MTJ element in the parallel state is larger than the read current flowing through the MTJ element in the antiparallel state.

  FIG. 12 is a diagram illustrating the voltage of the capacitor 30 (that is, the voltage of the bit line BL) charged by the read current in the parallel state and the antiparallel state. The horizontal axis in FIG. 12 represents time, and the vertical axis in FIG. 12 represents the voltage of the capacitor 30. As can be understood from FIG. 12, the time for which the voltage of the capacitor 30 is a predetermined voltage (for example, the voltage of the broken line in the horizontal direction in FIG. 12) is slower in the antiparallel state than in the parallel state. By using this time difference for reading, the data stored in the memory cell can be read more accurately.

[2-2] Flow of Read Operation Next, the flow of the read operation will be described. FIG. 13 is a flowchart showing a read operation according to the first embodiment.

  The control circuit 18 performs a read operation in the single end mode (step S100). The single end mode is a mode in which a single read current is supplied to the memory cell MC and data stored in the memory cell MC is read based on the single read current.

  Subsequently, the ECC circuit 15 performs an error check on the multi-bit data read from the memory cell array 11 (step S101).

  When it is determined in step S101 that there is no error, the control circuit 18 outputs the data read from the memory cell array 11 to the external device (step S105).

  If it is determined in step S101 that there is an error, the ECC circuit 15 determines whether error correction is possible (step S102). The correction capability of the ECC circuit 15, that is, the number of error bits that can be corrected by the ECC circuit 15, can be arbitrarily set. When the correction capability of the ECC circuit 15 is increased, the processing time of the ECC circuit 15 tends to be long and the circuit scale tends to increase.

  If it is determined in step S102 that correction is possible, the ECC circuit 15 performs error correction (step S103). Subsequently, the control circuit 18 rewrites the corrected data into the memory cell array 11 (step S104). Thereafter, the process proceeds to step S105, and data output is performed.

  On the other hand, if it is determined in step S102 that correction is not possible, the control circuit 18 performs a read operation in the self-reference mode (step S106). The self-referencing mode is a mode in which two read currents are supplied to the memory cell MC while shifting the time, and data stored in the memory cell MC is read based on the two read currents. As described above, a method of executing reading twice with respect to the memory cell MC without using a reference current flowing in a reference cell having a fixed resistance value, and determining data using a comparison result of the two readings. Is referred to as self-referencing readout.

  Subsequently, the ECC circuit 15 performs an error check on the multi-bit data read from the memory cell array 11 (step S107).

  If it is determined in step S107 that there is no error, the control circuit 18 writes back the data read from the memory cell array 11 to the memory cell array 11 (step S108). When the self-reference mode is executed, data in the memory cell MC may be destroyed. Therefore, by performing write back in step S108, the memory cell MC can accurately store the data before reading. Thereafter, the process proceeds to step S105, and data output is performed.

  Note that the read current flows in a direction in which the MTJ element is set in a parallel state. Therefore, data may be rewritten when the MTJ element is in an antiparallel state. Therefore, in the write-back process, the write-back process may be performed only on the anti-parallel MTJ element, that is, the memory cell storing the data “1”.

  If it is determined in step S107 that there is an error, a read error occurs. Therefore, the control circuit 18 performs a recovery operation (step S109). In the recovery operation, the voltages of various wirings used in the read operation are reset. The control circuit 18 may output a signal indicating a read error to an external device.

[2-3] Details of Read Operation in Single End Mode Next, details of the read operation in the single end mode will be described. FIG. 14 is a timing chart of the read operation in the single end mode. The read operation will be described below with reference to the circuit diagram of FIG.

  At time t1, the column decoder 13 sets the selected column selection signal CL to high level, and the row decoder 12 sets the selected word line WL to high level. As a result, the column selection switches 21A and 22A are turned on, and the cell transistor 28 of the memory cell MC is turned on. In the example of FIG. 14, for simplification, the column selection signal CL and the word line WL are simultaneously set to the high level. However, the activation state in which both the column selection signal CL and the word line WL are at the high level is intended, and the column selection signal CL may be set to the high level earlier than the word line WL, or vice versa.

  At time t2, the control circuit 18 asserts the read enable signal RE as a high level. As a result, the MOS transistor 40 is turned on, and the global bit line GBL is connected to the wiring 41.

  At time t3, the control circuit 18 asserts the pre-discharge signal PDE as a high level. As a result, the MOS transistor 42 is turned on, and the wiring 41 and the global bit line GBL are substantially discharged to the ground voltage VSS. At time t3, the control circuit 18 asserts the reset signal RST as a high level. As a result, the counter 46 is reset.

  At time t4, both the pre-discharge signal PDE and the reset signal RST are set to the low level. Thereby, the MOS transistor 42 is turned off and the reset of the counter 46 is released.

  At time t5, the sense amplifier enable signal / SE is asserted as a low level. As a result, the MOS transistor 43 is turned on and the inverter circuit 44 is operable. At time t5, the read signal RD1 is asserted as a high level. As a result, the MOS transistor 31 is turned on, and the read voltage VR1 for single end mode is applied to the global source line GSL.

  After time t5, a read current flows through the memory cell MC, and the capacitor 30 is charged by this read current. As a result, the voltage of the wiring 41 increases. The inverter circuit 44 has a threshold voltage. The threshold voltage of the inverter circuit 44 is determined by the threshold voltage and the size of the MOS transistors 44A and 44B. The inverter circuit 44 outputs a high level from the node N2 when the voltage of the wiring 41 is lower than the threshold voltage, and outputs a low level from the node N2 when the voltage of the wiring 41 is equal to or higher than the threshold voltage. The threshold voltage of the inverter circuit 44 is set to a value higher than the ground voltage VSS (0 V) and lower than the read voltage VR1.

  The clock signal CLK is input from the control circuit 18 to the first input terminal of the AND gate 45. The clock signal CLK is a high frequency clock and has a frequency of about 1 GHz, for example. The AND gate 45 outputs the clock signal CLK while the output of the inverter circuit 44 is at a high level. Note that the read voltages VR1 and VR1 can be set as appropriate so that the charging time is consistent with the cycle of the clock signal CLK.

  The counter 46 counts the clock signal CLK output from the AND gate 45 and outputs the count value as the output signal OUT <k: 0>. The digital data output from the counter 46 corresponds to time. That is, the counter 46 measures the time from when charging of the capacitor 30 is started until the voltage of the wiring 41 reaches the threshold voltage of the inverter circuit 44.

  At time t6, the read signal RD1 is set to low level, and the sense amplifier enable signal / SE is set to high level. Thereby, the MOS transistors 31 and 43 are turned off. At time t7, the read enable signal RE is set to low level, and the MOS transistor 40 is turned off. At time t8, the column selection signal CL and the word line WL are set to the low level, and the column selection switches 21A and 22A and the cell transistor 28 are turned off.

(Data judgment operation)
Next, an example of the data determination operation in the single end mode will be described. FIG. 15 is a flowchart showing the data determination operation in the single end mode. The data determination operation is performed by the data determination circuit 50 shown in FIG.

  The control circuit 18 asserts the enable signal EN1. Thereby, the register 51 stores the output signal OUT <k: 0> of (k + 1) bits, that is, the data of the single end mode (step S200).

  Subsequently, the comparator 56 compares the single-end mode data sent from the register 51 with the reference data Dref sent from the register 53 (step S201). The reference data Dref is a time between a measurement time when the memory cell MC stores data “0” and a measurement time when the memory cell MC stores data “1” (for example, an intermediate Digital data corresponding to time). The comparator 56 outputs data “0” (that is, indicates that the MTJ element is in a parallel state) when the output of the register 51 is smaller than the reference data Dref, and when the output of the register 51 is larger than the reference data Dref. , Data “1” (that is, indicating that the MTJ element is in an antiparallel state) is output.

  Subsequently, the selector 58 outputs the comparison result of the comparator 56 as data stored in the memory cell (step S202).

[2-4] Details of Read Operation in Self-Reference Mode Next, details of the read operation in the self-reference mode will be described. As described with reference to FIG. 13, when the data read in the single end mode cannot be corrected, the self-reference mode is executed.

  FIG. 16 is a diagram for explaining the relationship between the applied voltage and the resistance value of the MTJ element. The relationship between the applied voltage and the resistance value of the MTJ element differs between the parallel state “P” and the antiparallel state “AP”. In the antiparallel state, the resistance value of the MTJ element greatly decreases as the applied voltage of the MTJ element increases. On the other hand, in the parallel state, the resistance value of the MTJ element slightly decreases as the applied voltage of the MTJ element increases, but the width of the decrease is small.

  Specifically, in the antiparallel state, the resistance value of the MTJ element at the applied voltage V1 is large, and the resistance value of the MTJ element at the applied voltage V2 (> V1) is small. On the other hand, in the parallel state, the resistance value of the MTJ element at the applied voltage V1 is not so different from the resistance value of the MTJ element at the applied voltage V2 (> V1).

  Therefore, the read voltage is changed and two read operations are executed, and the difference between the results of the two read operations is compared with the reference data. Thereby, it can be determined whether the data stored in the memory cell MC is “0” or “1”. Further, in the present embodiment, the first read operation uses the read result of the single end mode described above. The self-reference mode corresponds to the second read operation.

  FIG. 17 is a timing chart of the read operation in the self-reference mode. The read operation will be described below with reference to the circuit diagram of FIG.

  Except for the operation of the read driver 25, it is the same as the single-end mode described above. Specifically, at time t5, the read signal RD2 is asserted as a high level. As a result, the MOS transistor 32 is turned on, and the read voltage VR2 for the self-reference mode is applied to the global source line GSL. The read voltage VR2 for the self-reference mode is set larger than the read voltage VR1 for the single end mode. In the example of FIG. 16, the read voltage VR1 for the single end mode corresponds to the voltage V1, and the read voltage VR2 for the self-reference mode corresponds to the voltage V2.

  Thereafter, as in the single end mode, the counter 46 measures the time until the voltage of the wiring 41 reaches the threshold voltage of the inverter circuit 44.

(Data judgment operation)
Next, an example of the data determination operation in the self-reference mode will be described. FIG. 18 is a flowchart showing the data determination operation in the self-reference mode. The data determination operation is performed by the data determination circuit 50 shown in FIG.

  The control circuit 18 asserts the enable signal EN2. Thereby, the register 52 stores the output signal OUT <k: 0>, that is, the data in the self-reference mode (step S300).

  Subsequently, the multiplier 55 multiplies the data stored in the register 52 by the α value stored in the register 54 (step S301). As shown in FIG. 16, in the anti-parallel state, when the read voltage is changed as in the voltages V1 and V2 and the read is performed twice (first and second read), the second read is the first read. The resistance value is smaller. Therefore, since the read current is sufficiently larger in the second read than in the first read, the measurement time of the second read is sufficiently shorter than the measurement time of the first read. That is, the difference in measurement time by the counter 46 is sufficiently large between the first reading and the second reading.

  On the other hand, as shown in FIG. 16, in the parallel state, when the first and second readings are performed using the voltages V1 and V2, the difference between the reading currents in the first reading and the second reading is small (almost the same). The difference in measurement time by the counter 46 is small. Since “V1 <V2”, the measurement time is shorter in the second reading than in the first reading in each of the parallel state and the antiparallel state.

  In the present embodiment, when the first measurement time of the first reading is compared with the second measurement time obtained by multiplying the measurement time of the second reading by α (> 1), in the antiparallel state, “first measurement time> The “second measurement time”, that is, the relationship before α multiplication is maintained, and in the parallel state, the “first measurement time <second measurement time”, that is, the α value so that the relationship before α multiplication is reversed. Set. That is, the α value is (1) in the anti-parallel state, the second measurement time obtained by multiplying the measurement time of the first readout by α is smaller than the first measurement time of the first readout, and (2) in the parallel state A second measurement time obtained by multiplying the measurement time of the first reading by α is set to be longer than the first measurement time of the first reading. The α value is set to 2 to 3, for example. The first reading corresponds to the single end mode, and the second reading corresponds to the self-reference mode.

  Subsequently, the comparator 57 compares the single end mode data sent from the register 51 with the output data of the multiplier 55 (step S302). The comparator 57 outputs data “0” representing the parallel state of the MTJ element when the output of the register 51 is smaller than the output of the multiplier 55, and the output of the register 51 is larger than the output of the multiplier 55. , MTJ element outputs data “1” indicating the anti-parallel state.

  Subsequently, the selector 58 outputs the comparison result of the comparator 57 as data stored in the memory cell (step S303).

  Note that a method different from the above method may be used for the data determination in the self-reference mode. For example, when the time difference between the first reading and the second reading is larger than the reference value, it is determined that the data is “1”, and when the time difference between the first reading and the second reading is less than the reference value. The data may be determined as “0”.

[3] Effects of First Embodiment As described in detail above, in the first embodiment, when the first read operation is executed in the single end mode and the data read by the first read operation is an error, the self-reference mode Then, the second reading is executed. In the single end mode, a read current is supplied to the memory cell MC using the first read voltage VR1, and the capacitor 30 is charged. The readout circuit 24 measures (determines) a first time (digital data) until the voltage of the capacitor 30 (voltage of the wiring 41) becomes equal to or higher than the threshold voltage of the inverter circuit 44. The data determination circuit 50 determines the data of the memory cell MC by comparing the first time with the reference data.

  In the self-reference mode, a read current is supplied to the memory cell MC using the second read voltage VR2 higher than the first read voltage VR1, and the capacitor 30 is charged. The readout circuit 24 measures (determines) a second time (digital data) until the voltage of the capacitor 30 becomes equal to or higher than the threshold voltage of the inverter circuit 44. The data determination circuit 50 determines the data of the memory cell MC by comparing the first time in the single end mode and the second time in the self-reference mode.

  Therefore, according to the first embodiment, time information of the time constant (RC) can be read as digital information. Accordingly, since the resistance state of the MTJ element is determined based on the magnitude relationship of time information, it is possible to read out the MTJ element having a higher resistance. In addition, since the read margin increases as the resistance value of the MTJ element increases, data can be read more accurately.

  When the data read in the single end mode is an error, the mode is switched to the self-reference mode, and the resistance state of the MTJ element is determined using two pieces of time information. Thereby, data can be read more accurately, and the highly reliable semiconductor memory device 10 can be realized.

  In addition, this embodiment is particularly effective when the resistance value of the MTJ element increases and the read current decreases.

  Further, a reference cell for reading data is not necessary. Thereby, the area of the memory cell array can be reduced.

[Second Embodiment]
In the second embodiment, a comparator is used instead of the inverter circuit 44 of the first embodiment, and this comparator determines whether or not the voltage of the global bit line GBL is equal to or higher than a threshold voltage. FIG. 19 is a circuit diagram of the readout circuit 24 according to the second embodiment.

  The read circuit 24 includes a comparator 60. The negative input terminal of the comparator 60 is connected to the wiring 41, and the reference voltage Vref is input to the positive input terminal. The output terminal of the comparator 60 is connected to the second input terminal of the AND gate 45. The comparator 60 outputs a high level when the voltage of the wiring 41 is lower than the reference voltage Vref, and outputs a low level when the voltage of the wiring 41 is equal to or higher than the reference voltage Vref. The reference voltage Vref is set to a value higher than the ground voltage VSS (0 V) and lower than the read voltage VR1.

  The read circuit 24 measures the time from when charging of the capacitor 30 is started until the voltage of the wiring 41 becomes equal to or higher than the reference voltage Vref. At this time, the comparator 60 detects the voltage of the wiring 41. Operations other than the comparator 60 are the same as those in the first embodiment.

  In the second embodiment, the reference voltage Vref can be arbitrarily set. Furthermore, even after the semiconductor memory device 10 is manufactured, the reference voltage Vref can be set to a desired value. Other effects are the same as those of the first embodiment.

[Third Embodiment]
In the third embodiment, a plurality of inverter circuits having different threshold voltages are prepared, and the charging time of the wiring 41 is measured using these inverter circuits. FIG. 20 is a circuit diagram of the readout circuit 24 according to the third embodiment.

  The read circuit 24 includes a detection circuit 61. The detection circuit 61 includes a plurality of inverter circuits 62 (62-0 to 62-k). Inverter circuits 62-0 to 62-k include p-channel MOS transistors 63-0 to 63-k and n-channel MOS transistors 64-0 to 64-k, respectively.

  The sources of the MOS transistors 63-0 to 63-k are connected to the drain of the MOS transistor 43. The drains of the MOS transistors 63-0 to 63-k are connected to the drains of the MOS transistors 64-0 to 64-k, respectively. The sources of the MOS transistors 64-0 to 64-k are connected to the ground terminal VSS.

  The input terminals of the inverter circuits 62-0 to 62-k are connected to the wiring 41. That is, the gates of the p-channel MOS transistors 63-0 to 63-k and the gates of the n-channel MOS transistors 64-0 to 64-k are connected to the wiring 41. The output terminals of the inverter circuits 62-0 to 62-k are connected to the bus 49. That is, the drains of the n-channel MOS transistors 64-0 to 64-k are connected to the bus 49.

  The threshold voltages of the inverter circuits 62-0 to 62-k increase in this order. The threshold voltage of the inverter circuit 62-0 is the lowest, and the threshold voltage of the inverter circuit 62-k is the highest. In order to satisfy this relationship, the sizes of the p-channel MOS transistors 63-0 to 63-k increase in this order. The size of the p-channel MOS transistor 63-0 is the smallest, and the size of the p-channel MOS transistor 63-k is the largest. In other words, the current drivability of the p-channel MOS transistors 63-0 to 63-k increases in this order.

  The sizes of the n-channel MOS transistors 64-0 to 64-k decrease in this order. The n-channel MOS transistor 64-0 has the largest size, and the n-channel MOS transistor 64-k has the smallest size. In other words, the current drivability of the n-channel MOS transistors 64-0 to 64-k decreases in this order. The size of the MOS transistor corresponds to the gate width (channel width). The gate width is the length of the gate electrode in the direction in which the gate electrode extends, in other words, the length of the gate electrode in the direction (channel width direction) orthogonal to the channel direction (channel length direction).

  The sizing of this transistor can be adjusted only by the size of the p-channel MOS transistor 63-0 while fixing the size of the n-channel MOS transistors 64-0 to 64-k. Similarly, the size of the p-channel MOS transistor 63-0 can be fixed and adjusted only by the size of the n-channel MOS transistors 64-0 to 64-k.

  The timings of the signals RE, / SE, and PDE are the same as those in the first embodiment. In the readout circuit 24 configured as described above, when the voltage of the wiring 41 is the ground voltage VSS, the outputs of the inverter circuits 62-0 to 62-k are all at a high level (all data “1”). When the voltage of the wiring 41 rises continuously, the output of the inverter circuit 62-0 first becomes a low level (data “0”), and then the low level is output in order from the inverter circuits 62-1 to 62-k. . Thereby, the readout circuit 24 can measure the time from the start of charging of the capacitor 30 until the voltage of the wiring 41 reaches a predetermined voltage.

  The output signal / OUT <k: 0> becomes smaller as the measurement time elapses with “111...” As an initial value. Therefore, the output signal / OUT <k: 0> is inverted (that is, as the output signal OUT <k: 0>) and sent to the data determination circuit 50. The operation of the data determination circuit 50 may be changed according to the output signal / OUT <k: 0>.

  According to the third embodiment, the read circuit 24 can be configured using only a plurality of MOS transistors. Thereby, the read circuit 24 can be realized more easily. Other effects are the same as those of the first embodiment.

  Note that the p-channel MOS transistors 63-0 to 63-k are not limited to planar FETs (Field Effect Transistors), but may be configured by fin-type FETs (FinFETs) that are three-dimensional transistors. The FinFET includes a semiconductor fin provided on a substrate, a gate electrode provided on a top surface and both side surfaces of the semiconductor fin via a gate insulating film, and a source region and a drain provided on the semiconductor fin on both sides of the gate electrode, respectively. And an area. The current driving force of the FinFET can be increased by increasing the number of fins (multi-fin structure). That is, changing the size (gate width) of the planar FET corresponds to changing the number of fins of the FinFET. Similarly, the n-channel MOS transistors 64-0 to 64-k may be configured by FinFETs.

[Fourth Embodiment]
In the fourth embodiment, a plurality of reference voltages are generated using a plurality of resistance elements, and the reference voltage and the voltage of the wiring 41 are compared using a plurality of comparators. FIG. 21 is a circuit diagram of the readout circuit 24 according to the fourth embodiment.

  The detection circuit 61 includes a plurality of resistance elements 65 (65-0 to 65- (k + 1)) and a plurality of comparators 66 (66-0 to 66-k). Resistive elements 65-0 to 65- (k + 1) divide a voltage between reference voltage Vref1 and reference voltage Vref2. The reference voltage Vref2 is set to a value higher than the ground voltage VSS (0 V) and lower than the read voltage VR1. The reference voltage Vref1 is set higher than the ground voltage VSS (0 V) and lower than the reference voltage Vref2. The resistor elements 65-0 to 65- (k + 1) are connected in series, and a reference voltage Vref1 is supplied to one end of the resistor element 65-0, and a reference voltage Vref2 is supplied to one end of the resistor element 65- (k + 1). Is done.

  The positive side input terminals of the comparators 66-0 to 66-k are connected to the wiring 41. The negative side input terminal of the comparator 66-0 is connected to a connection node between the resistance element 65-0 and the resistance element 65-1. Similarly, the negative side input terminals of the comparators 66-1 to 65- (k + 1) are connected to the connection nodes of the resistance elements 65-1 to 65- (k + 1), respectively. Output terminals of the comparators 66-0 to 66-k are connected to the bus 49.

  The comparator 66 outputs a high level when the voltage of the wiring 41 is equal to or higher than the reference voltage. Therefore, the readout circuit 24 can measure the time until the voltage of the wiring 41 reaches a predetermined voltage. Other effects are the same as those of the first embodiment.

[Fifth Embodiment]
In the fifth embodiment, in the single end mode, the first read voltage is used to charge the first capacitor connected to the global bit line, and the voltage of the first capacitor is compared with the reference voltage to read data. In the self-reference mode, the first and second capacitors connected to the global bit line are charged using the first and second read voltages, respectively, and the voltages of the first and second capacitors are compared to read data. I have to.

[1] Configuration of Read Circuit 24 FIG. 22 is a circuit diagram of the read circuit 24 according to the fifth embodiment. In FIG. 22, the column selection switches 21A and 21B are not shown.

  Global bit line GBL is connected to wiring 71-1 through transfer gate 70-1. The transfer gate 70-1 is turned on when the read signal RD1 is at a high level (the read signal / RD1 is at a low level). The capacitor 30-1 is connected to the wiring 71-1. One electrode of the capacitor 30-1 is connected to the wiring 71-1, and the other electrode of the capacitor 30-1 is connected to the ground terminal VSS.

  The wiring 71-1 is connected to the wiring 41 through the n-channel MOS transistor 40-1. A read enable signal RE1 is input from the control circuit 18 to the gate of the MOS transistor 40-1. Wiring 41 is connected to ground terminal VSS via n-channel MOS transistor 42-1. A pre-discharge signal PDE1 is input from the control circuit 18 to the gate of the MOS transistor 42-1.

  The read circuit 24 includes a sense amplifier 72. Sense amplifier 72 includes p-channel MOS transistors 43-1, 43-2, 73-1, 73-2 and n-channel MOS transistors 74-1, 74-2.

  The source of the MOS transistor 43-1 is connected to the power supply terminal VDD, and the sense amplifier enable signal / SE is input from the control circuit 18 to the gate thereof. The source of the MOS transistor 43-2 is connected to the power supply terminal VDD, and the sense amplifier enable signal / SE is input to the gate thereof.

  MOS transistor 73-1 and MOS transistor 74-1 constitute an inverter circuit. The source of the MOS transistor 73-1 is connected to the drain of the MOS transistor 43-1, its drain is connected to the node N11, and its gate is connected to the node N12. The drain of the MOS transistor 74-1 is connected to the node N11, the source thereof is connected to the ground terminal VSS, and the gate thereof is connected to the node N12.

  MOS transistor 73-2 and MOS transistor 74-2 constitute an inverter circuit. The source of MOS transistor 73-2 is connected to the drain of MOS transistor 43-2, its drain is connected to node N12, and its gate is connected to node N11. The drain of the MOS transistor 74-2 is connected to the node N12, the source is connected to the ground terminal VSS, and the gate is connected to the node N11. The sense amplifier 72 outputs an output signal OUT from the node N11, and outputs an output signal / OUT from the node N12. The output signal / OUT is an inverted signal of the output signal OUT. Note that when the pre-discharge signal PDE1 is asserted, an equalizing N-channel MOS transistor that makes the node N11 and the node N12 have the same potential may be provided.

  Global bit line GBL is connected to wiring 71-2 via transfer gate 70-2. The transfer gate 70-2 is turned on when the read signal RD2 is at a high level (the read signal / RD2 is at a low level). Capacitor 30-2 is connected to wiring 71-2. One electrode of the capacitor 30-2 is connected to the wiring 71-2, and the other electrode of the capacitor 30-2 is connected to the ground terminal VSS. The capacity of the capacitor 30-2 is set to be approximately the same as the capacity of the capacitor 30-2.

  The wiring 71-2 is connected to the wiring 75 through the n-channel MOS transistor 40-2. The read enable signal RE2 is input from the control circuit 18 to the gate of the MOS transistor 40-2. Wiring 75 is connected to ground terminal VSS through n-channel MOS transistor 42-2. A pre-discharge signal PDE2 is input from the control circuit 18 to the gate of the MOS transistor 42-2.

  The first input terminal of the selector 76 is connected to the wiring 75, the reference voltage Vref is input to the second input terminal, and the selection signal SEL is input to the control terminal from the control circuit 18. Based on the selection signal SEL, the selector 76 outputs the reference voltage Vref in the single end mode, and outputs the voltage of the wiring 75 in the self reference mode.

[2] Operation Next, the operation of the semiconductor memory device 10 configured as described above will be described. FIG. 23 is a timing diagram of a read operation according to the fifth embodiment. As in the first embodiment, in the read operation, the single end mode is executed, and the self-reference mode is executed when the error cannot be corrected in the single end mode.

(Single-end mode)
First, the single end mode is executed. At time t1, the row decoder 12 sets the selected word line WL to the high level. Although not shown, the column decoder 13 sets the selected column selection signal CL to the high level as in the first embodiment.

  At time t2, the control circuit 18 asserts the read enable signal RE1 as a high level. Thereby, the MOS transistor 40-1 is turned on, and the capacitor 30-1 is connected to the wiring 41.

  At time t3, the control circuit 18 asserts the pre-discharge signal PDE1 as a high level. As a result, the MOS transistor 42-1 is turned on, and the wiring 41 and the capacitor 30-1 are almost discharged to the ground voltage VSS. At time t4, the pre-discharge signal PDE1 is set to the low level. Thereby, the MOS transistor 42-1 is turned off.

  At time t5, the read signal RD1 is asserted as a high level. As a result, the MOS transistor 31 is turned on, and the read voltage VR1 for single end mode is applied to the global source line GSL. At time t5, the transfer gate 70-1 is turned on and the global bit line GBL is connected to the wiring 41. As a result, a read current flows through the memory cell MC, and the capacitor 30-1 is charged by the read current.

  At time t6, the read signal RD1 and the read enable signal RE1 are set to low level. Thereby, the MOS transistors 31 and 40-1 and the transfer gate 70-1 are turned off.

  At time t7, the sense amplifier enable signal / SE is asserted as a low level. As a result, the MOS transistors 43-1 and 43-2 are turned on, and the sense amplifier 72 detects data based on the voltages at the nodes N11 and N12. At this time, the reference voltage Vref is input from the selector 76 to the node N12.

  At time t8, the sense amplifier enable signal / SE is set to the high level, and the MOS transistors 43-1 and 43-2 are turned off. Thereby, the sense amplifier 72 latches data based on the voltages of the nodes N11 and N12.

  The sense amplifier 72 outputs data “0” as the output signal / OUT when the voltage of the node N11 (that is, the voltage of the wiring 41) is higher than the reference voltage Vref, and when the voltage of the node N11 is lower than the reference voltage Vref, Data “1” is output as the output signal / OUT.

  The reference voltage Vref is the MTJ element in a parallel state (a state in which the memory cell stores data “0”), or the MTJ element is in a reverse state (a state in which the memory cell stores data “1”). Is used to determine whether or not That is, the reference voltage Vref is a voltage between the voltage of the wiring 41 charged by the read current flowing in the MTJ element in the parallel state and the voltage of the wiring 41 charged by the read current flowing in the MTJ element in the antiparallel state ( For example, an intermediate voltage is set.

  When the MTJ element is in a parallel state, the read current is large, and when the MTJ element is in an antiparallel state, the read current is small. Therefore, when the MTJ element is in a parallel state, the output signal / OUT becomes data “0”, and when the MTJ element is in an antiparallel state, the output signal / OUT becomes data “1”. Finally, the output signal / OUT is output to the outside as read data.

  At time t9, the word line WL is set to low level, and the cell transistor 28 is turned off.

(Self-referencing mode)
Next, the self reference mode will be described.

At time t10, the row decoder 12 sets the selected word line WL to high level.
At time t11, the control circuit 18 asserts the read enable signals RE1 and RE2 as high level. Thereby, the MOS transistor 40-1 is turned on, and the capacitor 30-1 is connected to the wiring 41. The capacitor 30-1 holds the charge in the single end mode described above. Therefore, the wiring 41 is charged to the voltage in the single end mode. Further, the MOS transistor 40-2 is turned on, and the capacitor 30-2 is connected to the wiring 75.

  At time t12, the control circuit 18 asserts the pre-discharge signal PDE2 as a high level. As a result, the MOS transistor 42-2 is turned on, and the wiring 75 and the capacitor 30-2 are substantially discharged to the ground voltage VSS. At time t13, the pre-discharge signal PDE2 is set to the low level. Thereby, the MOS transistor 42-2 is turned off.

  At time t14, the read signal RD2 is asserted as a high level. As a result, the MOS transistor 32 is turned on, and the read voltage VR2 for the self-reference mode is applied to the global source line GSL. At time t <b> 14, the transfer gate 70-2 is turned on and the global bit line GBL is connected to the wiring 75. As a result, a read current flows through the memory cell MC, and the capacitor 30-2 is charged by the read current.

  Similar to the first embodiment, the read voltage VR2 for the self-reference mode is set higher than the read voltage VR1 for the single end mode. Further, the pulse width of the read voltage VR2 is set smaller than the pulse width of the read voltage VR1. The pulse width of the read voltage VR1 can be controlled at the timing of negating the read signal RD1, and the pulse width of the read voltage VR2 can be controlled at the timing of negating the read signal RD2. The magnitudes of the read voltage VR1 and the read voltage VR2 and their pulse widths are optimally set so that the parallel state and antiparallel state of the MTJ element can be distinguished. A method for setting the read voltages VR1 and VR2 will be described later.

  At time t15, the read signal RD2 and the read enable signals RE1 and RE2 are set to low level. Thereby, the MOS transistors 32, 40-1, 40-2 and the transfer gate 70-2 are turned off.

  At time t16, the sense amplifier enable signal / SE is asserted as a low level. As a result, the MOS transistors 43-1 and 43-2 are turned on, and the sense amplifier 72 detects data based on the voltages at the nodes N11 and N12. At this time, the voltage of the wiring 75 (that is, the voltage of the capacitor 30-2) is applied from the selector 76 to the node N12.

  At time t17, the sense amplifier enable signal / SE is set to the high level, and the MOS transistors 43-1 and 43-2 are turned off. Thereby, the sense amplifier 72 latches data based on the voltages of the nodes N11 and N12.

  When the voltage at the node N11 (that is, the voltage at the wiring 41) is higher than the voltage at the node N12 (that is, the voltage at the wiring 75), the sense amplifier 72 outputs data “0” as the output signal / OUT. When the voltage is lower than the voltage of the node N12, data “1” is output as the output signal / OUT. Finally, the output signal / OUT is output to the outside as read data.

  At time t18, the word line WL is set to low level, and the cell transistor 28 is turned off.

[3] Read Voltages VR1 and VR2 Next, a method for setting the read voltages VR1 and VR2 will be described. FIG. 24 is a diagram illustrating a method for setting a read voltage. In FIG. 24A, the horizontal axis represents time, and the vertical axis represents the voltage of the capacitor 30-1. In FIG. 24B, the horizontal axis represents time, and the vertical axis represents the voltage of the capacitor 30-2. Time zero in FIG. 24 corresponds to the start of charging. FIG. 24 shows a curve when the capacitor is charged with a current flowing through the MTJ element in the parallel state (“P” in FIG. 24), and a curve when the capacitor is charged with the current flowing through the MTJ element in the antiparallel state (FIG. 24). "AP") and an average value of the curve "P" and the curve "AP"("Ref" in FIG. 24). Note that the voltage at time T1 and time T2 of the curve “Ref” is the reference voltage Vref.

  As described above, the read voltage VR2 in the self-reference mode is larger than the read voltage VR1 in the single end mode. As shown in FIG. 24A, when a read current is passed through the MTJ element in parallel using the read voltage VR1, and the capacitor 30-1 is charged by this read current, the voltage of the capacitor 30-1 at time T1. (Corresponding to the voltage of the wiring 41) is the voltage Vp1. When a read current is supplied to the MTJ element in the anti-parallel state using the read voltage VR1, and the capacitor 30-1 is charged by this read current, the voltage of the capacitor 30-1 is equal to the voltage Vap1 (<Vp1) at time T1. Become.

  As shown in FIG. 24B, when a read current is passed through the MTJ element in the parallel state using the read voltage VR2, and the capacitor 30-2 is charged by this read current, the voltage of the capacitor 30-2 at time T2. (Corresponding to the voltage of the wiring 75) is the voltage Vp2. When a read current is supplied to the MTJ element in the antiparallel state using the read voltage VR2, and the capacitor 30-2 is charged by this read current, the voltage of the capacitor 30-2 is equal to the voltage Vap2 (<Vp2) at time T2. Become.

  That is, when the MTJ element is in the parallel state, the voltage Vp1 in the single end mode is higher than the voltage Vp2 in the self-reference mode. On the other hand, when the MTJ element is in the antiparallel state, the voltage Vap1 in the single end mode is lower than the voltage Vap2 in the self-reference mode. Thus, when the MTJ element is in the parallel state, the output signal / OUT becomes data “0”, and when the MTJ element is in the anti-parallel state, the output signal / OUT becomes data “1”.

  Time T1 corresponds to the pulse width of the read voltage VR1, and time T2 corresponds to the pulse width of the read voltage VR2. By setting the magnitudes of the read voltage VR1 and the read voltage VR2 and their pulse widths as described above, it is possible to accurately determine the parallel state and antiparallel state of the MTJ element.

[4] Effects of Fifth Embodiment As described in detail above, in the fifth embodiment, when the first read operation is executed in the single end mode and the data read by the first read operation is an error, the self-reference mode Then, the second reading is executed. In the single end mode, a read current is supplied to the memory cell MC using the first read voltage VR1, and the capacitor 30-1 is charged. The read circuit 24 compares the voltage of the capacitor 30-1 (the voltage of the wiring 41) with the reference voltage Vref to determine the data of the memory cell MC.

  In the self-reference mode, a read current is supplied to the memory cell MC using the second read voltage VR2 higher than the first read voltage VR1, and the capacitor 30-2 is charged. The read circuit 24 compares the voltage of the capacitor 30-1 in the single end mode with the voltage of the capacitor 30-2 to determine data of the memory cell MC.

  Therefore, according to the fifth embodiment, data in the memory cell MC can be read out by one read operation (single end mode). Further, data can be read by comparing voltage levels.

  When the data read in the single end mode is an error, the mode is switched to the self-reference mode, and the resistance state of the MTJ element is determined using two voltage levels. Thereby, data can be read more accurately, and the highly reliable semiconductor memory device 10 can be realized.

[Sixth Embodiment]
The sixth embodiment is a modification of the first embodiment, and performs a precharge-type read operation. That is, after the global bit line GBL (and the capacitor 30) is charged to the power supply voltage VDD, for example, the time for discharging the global bit line GBL by the memory cell MC is measured.

[1] Configuration of Read Circuit 24 FIG. 25 is a circuit diagram of the read circuit 24 according to the sixth embodiment. Most of FIG. 25 is the same as FIG. 5 described in the first embodiment, and only portions different from FIG. 5 will be described below.

  The precharge circuit 80 is connected to the wiring 41. The precharge circuit 80 precharges the wiring 41 to a predetermined voltage (for example, the power supply voltage VDD). Precharge circuit 80 is formed of a p-channel MOS transistor. The source of the MOS transistor 80 is connected to the power supply terminal VDD, the drain thereof is connected to the wiring 41, and the precharge signal / PCE is input from the control circuit 18 to the gate thereof. The precharge signal / PCE is a signal obtained by inverting the logic of the predischarge signal PDE described in the first embodiment.

  An input terminal of the inverter circuit 81 is connected to the node N2 of the inverter circuit 44, and an output terminal thereof is connected to one input terminal of the AND gate 45.

  The discharge circuit 82 is connected to the global source line GBL. The discharge circuit 82 includes n-channel MOS transistors 31 and 32. The discharge circuit 82 has the same circuit configuration as the read driver 25 described in the first embodiment except that the levels of the read voltage VR1 and the read voltage VR2 are different.

  A read voltage VR1 for single end mode is applied to the power supply line 33 by the voltage generation circuit 19. A read voltage VR2 for the self-reference mode is applied to the power supply line 34 by the voltage generation circuit 19. The read voltage VR1 is set higher than the ground voltage VSS and lower than the power supply voltage VDD. The read voltage VR2 is set higher than the ground voltage VSS and lower than the read voltage VR1.

[2] Operation Next, the operation of the semiconductor memory device 10 configured as described above will be described. The timing chart of the read operation according to the sixth embodiment is the same as that of FIGS. 14 and 17 described in the first embodiment except that the pre-discharge signal PDE is replaced with the pre-charge signal / PCE. Below, only a different part from 1st Embodiment is demonstrated.

  First, the single end mode will be described. The control circuit 18 asserts the precharge signal / PCE as a low level. Thereby, the precharge circuit 80 charges the capacitor 30 to the approximate power supply voltage VDD.

  Subsequently, the sense amplifier enable signal / SE is asserted as a low level, and the read signal RD1 is asserted as a high level. As a result, the wiring 41 is discharged and the counter 46 counts the clock signal CLK.

  Subsequently, the inverter circuit 44 outputs a high level when the voltage of the wiring 41 becomes lower than its own threshold voltage. Thereby, the count operation of the counter 46 is completed. Thereafter, a data determination operation is performed as in the first embodiment.

  Next, the self reference mode will be described. In the self-reference mode, the read voltage VR2 (<VR1) is used during discharge. Other operations are the same as in the single-ended mode described above. Thereafter, a data determination operation is performed as in the first embodiment.

  According to the sixth embodiment, data in the memory cell MC can be read using the time for discharging the global bit line GBL from the power supply voltage VDD to the threshold voltage of the inverter circuit 44. The other effects are the same as in the first embodiment. The sixth embodiment can also be applied to the second to fourth embodiments.

[Seventh Embodiment]
The seventh embodiment is a modification of the fifth embodiment and performs a precharge-type read operation.

[1] Configuration of Read Circuit 24 FIG. 26 is a circuit diagram of the read circuit 24 according to the seventh embodiment. Most of FIG. 26 is the same as FIG. 22 described in the fifth embodiment, and only the parts different from FIG. 22 will be described below.

  The precharge circuit 80-1 is connected to the wiring 41. The precharge circuit 80-1 precharges the wiring 41 to a predetermined voltage (for example, the power supply voltage VDD). Precharge circuit 80-1 is composed of a p-channel MOS transistor. The source of the MOS transistor 80-1 is connected to the power supply terminal VDD, the drain is connected to the wiring 41, and the precharge signal / PCE 1 is input from the control circuit 18 to the gate. The precharge signal / PCE1 is a signal obtained by inverting the logic of the predischarge signal PDE1 described in the fifth embodiment.

  The precharge circuit 80-2 is connected to the wiring 75. The precharge circuit 80-2 precharges the wiring 75 to a predetermined voltage (for example, the power supply voltage VDD). Precharge circuit 80-2 is formed of a p-channel MOS transistor. The source of the MOS transistor 80-2 is connected to the power supply terminal VDD, the drain thereof is connected to the wiring 75, and the precharge signal / PCE2 is inputted from the control circuit 18 to the gate thereof. The precharge signal / PCE2 is a signal obtained by inverting the logic of the predischarge signal PDE2 described in the fifth embodiment.

  The discharge circuit 82 is connected to the global source line GBL. The configuration of the discharge circuit 82 is the same as that of the sixth embodiment.

[2] Operation Next, the operation of the semiconductor memory device 10 configured as described above will be described. The timing chart of the read operation according to the seventh embodiment is the same as FIG. 23 described in the fifth embodiment except that the pre-discharge signals PDE1 and PDE2 are replaced with the precharge signals / PCE1 and / PCE2. Below, only a different part from 5th Embodiment is demonstrated.

  First, the single end mode will be described. The control circuit 18 asserts the precharge signal / PCE1 as a low level. Thereby, precharge circuit 80-1 charges capacitor 30-1 to approximately power supply voltage VDD.

  Subsequently, the read signal RD1 is asserted as a high level. Thereby, the global bit line GBL is discharged according to the read voltage VR1 of the power supply line 33. Thereafter, the sense amplifier enable signal / SE is asserted as a low level, and the sense amplifier 72 detects data in the memory cell.

  When the MTJ element is in a parallel state, the read current is large, and when the MTJ element is in an antiparallel state, the read current is small. Therefore, when the MTJ element is in a parallel state, the output signal OUT is data “0”, and when the MTJ element is in an antiparallel state, the output signal OUT is data “1”. Finally, the output signal OUT is output to the outside as read data.

(Self-referencing mode)
Next, the self reference mode will be described. In the self-reference mode, the read voltage VR2 (<VR1) is used during discharge. The control circuit 18 asserts the precharge signal / PCE2 as a low level. As a result, the precharge circuit 80-2 charges the capacitor 30-2 to the approximate power supply voltage VDD.

  Subsequently, the read signal RD2 is asserted as a high level. As a result, the global bit line GBL is discharged according to the read voltage VR2 of the power supply line. Thereafter, the sense amplifier enable signal / SE is asserted as a low level, and the sense amplifier 72 detects data in the memory cell.

  FIG. 27 is a diagram for explaining how the global bit line GBL is discharged in the read operation. In FIG. 27A, the horizontal axis represents time, and the vertical axis represents the voltage of the capacitor 30-1. In FIG. 27B, the horizontal axis represents time, and the vertical axis represents the voltage of the capacitor 30-2.

  As shown in FIG. 27A, when a read current is supplied to the MTJ element in a parallel state using the read voltage VR1, and the capacitor 30-1 is discharged by this read current, the voltage of the capacitor 30-1 at time T1. (Corresponding to the voltage of the wiring 41) is the voltage Vp1. When a read current is supplied to the anti-parallel MTJ element using the read voltage VR1, and the capacitor 30-1 is discharged by this read current, the voltage of the capacitor 30-1 is the voltage Vap1 (> Vp1) at time T1. Become.

  As shown in FIG. 27B, when a read current is supplied to the MTJ element in parallel using the read voltage VR2, and the capacitor 30-2 is discharged by this read current, the voltage of the capacitor 30-2 at time T2. (Corresponding to the voltage of the wiring 75) is the voltage Vp2. When a read current is supplied to the MTJ element in the antiparallel state using the read voltage VR2, and the capacitor 30-2 is discharged by this read current, the voltage of the capacitor 30-2 is the voltage Vap2 (> Vp2) at time T2. Become.

  That is, when the MTJ element is in the parallel state, the voltage Vp1 in the single end mode is lower than the voltage Vp2 in the self-reference mode. On the other hand, when the MTJ element is in the antiparallel state, the voltage Vap1 in the single end mode is higher than the voltage Vap2 in the self-reference mode. Thus, when the MTJ element is in a parallel state, the output signal OUT becomes data “0”, and when the MTJ element is in an antiparallel state, the output signal OUT becomes data “1”. Finally, the output signal OUT is output to the outside as read data.

  Time T1 corresponds to the pulse width of the read voltage VR1, and time T2 corresponds to the pulse width of the read voltage VR2. By setting the magnitudes of the read voltage VR1 and the read voltage VR2 and their pulse widths as described above, it is possible to accurately determine the parallel state and antiparallel state of the MTJ element.

[3] Effects of Seventh Embodiment According to the seventh embodiment, data in the memory cell MC is read using a voltage after the global bit line GBL is discharged for a predetermined time (time T1, T2). it can. The other effects are the same as in the fifth embodiment.

  Note that the MRAM shown in each of the above embodiments may be an STT-MRAM (spin transfer torque type magnetoresistive random access memory).

  In each of the above embodiments, the MRAM using the magnetoresistive effect element is described as an example of the semiconductor memory device. However, the present invention is not limited to this, and a resistance change type memory similar to the MRAM, for example, The present invention is also applicable to ReRAM (Resistive Random Access Memory), PCRAM (Phase-Change Random Access Memory), and the like.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor memory device, 11 ... Memory cell array, 12 ... Row decoder, 13 ... Column decoder, 14 ... Column control circuit, 15 ... ECC circuit, 16 ... Input / output circuit, 17 ... Address register, 18 ... Control circuit, 19 ... Voltage generating circuit, 20 ... bus, 21, 22 ... column selection circuit, 23 ... write circuit, 24 ... read circuit, 25 ... read driver, 26 ... data buffer, 27 ... MTJ element, 28 ... cell transistor, 30 ... capacitor, 50: Data determination circuit.

Claims (14)

A memory cell including a variable resistance element;
A bit line and a source line connected to the memory cell;
A first driver for applying a first read voltage to the source line in a first read operation;
A second driver for applying a second read voltage different from the first read voltage to the source line in a second read operation after the first read operation;
A capacitor connected to the bit line;
A read circuit for obtaining a first time from when the first read voltage is applied to the source line until the voltage of the bit line becomes the first voltage;
A determination circuit for determining data of the memory cell using the first time in the first read operation;
When the data read by the first read operation is an error, the read circuit applies the second read voltage to the source line until the voltage of the bit line becomes the first voltage. For the second hour of
The determination circuit determines data of the memory cell by using the first time and the second time in the second read operation. The determination circuit includes:
During the first read operation, the first time is compared with reference data to determine data of the memory cell;
The semiconductor memory device according to claim 1, wherein during the second read operation, the data of the memory cell is determined by comparing the first time with the second time. A first register for storing the first time as data;
The semiconductor memory device according to claim 1, further comprising: a second register that stores the second time as data. In each of the first and second read operations, the counter further includes a counter that counts clock signals and outputs first and second count values,
The first count value corresponds to the first time,
The semiconductor memory device according to claim 1, wherein the second count value corresponds to the second time. A comparator for comparing the voltage of the bit line with a reference voltage;
The semiconductor memory device according to claim 4, wherein the counter stops a counting operation according to an output of the comparator. The readout circuit includes
A first comparator for comparing a second voltage with the voltage of the bit line;
A third comparator that compares a third voltage higher than the second voltage with the voltage of the bit line;
The outputs of the first and second comparators in the first read operation correspond to the first time,
The semiconductor memory device according to claim 1, wherein outputs of the first and second comparators in the second read operation correspond to the second time. A memory cell including a variable resistance element;
A bit line and a source line connected to the memory cell;
A first driver for applying a first read voltage to the source line in a first read operation;
A second driver for applying a second read voltage different from the first read voltage to the source line in a second read operation after the first read operation;
A capacitor connected to the bit line;
A first inverter circuit having an input terminal connected to the bit line and having a first PMOS transistor and a first NMOS transistor;
A second inverter circuit having an input terminal connected to the bit line and having a second PMOS transistor and a second NMOS transistor;
A determination circuit for determining data of the memory cell using output signals of the first and second inverter circuits;
The size of the second PMOS transistor is larger than the size of the first PMOS transistor. The semiconductor memory device according to claim 7, wherein a size of the second NMOS transistor is smaller than a size of the first NMOS transistor. A memory cell including a variable resistance element;
A bit line and a source line connected to the memory cell;
A first driver for applying a first read voltage to the source line in a first read operation;
A second driver for applying a second read voltage different from the first read voltage to the source line in a second read operation after the first read operation;
A capacitor connected to the bit line;
A first inverter circuit having an input terminal connected to the bit line and having a first PMOS transistor and a first NMOS transistor;
A second inverter circuit having an input terminal connected to the bit line and having a second PMOS transistor and a second NMOS transistor;
A determination circuit for determining data of the memory cell using output signals of the first and second inverter circuits;
The size of the second NMOS transistor is smaller than the size of the first NMOS transistor. The determination circuit includes:
During the first read operation, the output signal is compared with reference data to determine data of the memory cell;
The data of the memory cell is determined by comparing the first output signal in the first read operation and the second output signal in the second read operation during the second read operation. A semiconductor memory device according to claim 1. A memory cell including a variable resistance element;
A bit line and a source line connected to the memory cell;
A first driver for applying a first read voltage to the source line in a first read operation;
A second driver for applying a second read voltage different from the first read voltage to the source line in a second read operation after the first read operation;
A capacitor connected to the bit line;
An inverter circuit having an input terminal connected to the bit line, and outputting a first logic level when the voltage of the bit line becomes a first voltage;
An AND gate having a first input terminal connected to the output terminal of the inverter circuit and a second input terminal for receiving a clock signal;
A counter that counts the output of the AND gate;
A semiconductor memory device comprising: a determination circuit that determines data of the memory cell using a count value of the counter. The determination circuit includes:
During the first read operation, the count value and reference data are compared to determine data of the memory cell;
12. The semiconductor according to claim 11, wherein, during the second read operation, data of the memory cell is determined by comparing a first count value in the first read operation and a second count value in the second read operation. Storage device. The semiconductor memory device according to claim 1, wherein the second read voltage is higher than the first read voltage. The discharge element which discharges the capacitor before applying the first read voltage to the source line and applying the second read voltage to the source line is further provided. The semiconductor memory device described.