JP2012185870A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problems of an increase in a chip area due to a driver for writing data and an increase in data rewriting time due to serial execution of data 0 writing and data 1 writing.SOLUTION: In a semiconductor memory, a resistance change type memory cell with a resistance value changed by the application of voltage is connected to a bit line BL1 and a source line SL1, and switching elements S1-S4 are provided which can switch connection between a bit line driver BD1, and the bit line BL1 and source line SL1 and control the switch for each bit.

Description

  The present invention relates to a nonvolatile semiconductor memory device that can retain data even when power is not supplied, and more particularly to a data rewriting technique of a resistance change type memory that stores data by changing a resistance value.

  Semiconductor memory devices that store data by integrating elements on a semiconductor substrate can be roughly divided into a volatile memory that can hold data only while power is supplied, and data that can be held even when power is not supplied. There are two types of non-volatile memories, which are further classified according to the method and usage.

  Among the nonvolatile memories, the flash memory is most frequently used at present. However, in recent years, new nonvolatile memories that can be rewritten with high speed and low power consumption are actively developed. For example, a resistance change type memory (ReRAM: Resistive RAM) using a resistance change type element as a memory element (see Patent Document 1).

  The resistance change type memory can be rewritten at a high speed of nanosecond order. Further, the voltage required for rewriting requires 10 V or more for the flash memory, but the resistance change type memory can be rewritten at 1.8 V. It is possible to achieve low power consumption of the nonvolatile memory.

  FIG. 10 is a diagram showing a basic configuration of a conventional resistance change type memory when the resistance element R1 is used as a memory cell. The resistance element R1 has two connection nodes N1 and N2, and has a characteristic of changing its resistance value when a voltage is applied. The direction of the change varies depending on the direction of the voltage. That is, when a positive voltage pulse is applied to the node N1 side and the node N2 is kept at the ground potential, a positive voltage is applied to the resistance element R1 from the node N1 to the node N2, and the resistance value increases. Conversely, when a positive voltage pulse is applied to the node N2 side and the node N1 is kept at the ground potential, a negative voltage is applied to the resistance element R1 from the node N1 to the node N2, and the resistance value decreases. Since the change in the resistance value is maintained even when no voltage is applied, this characteristic can be used as a nonvolatile memory element. In the drawing, in order to clearly indicate that the direction of resistance change varies depending on the direction of voltage application, a black band is attached to the node N1 side, and thereafter a resistance value increases when a positive voltage is applied to the side where the black band is present. It shall be.

  A pair of the resistance element R1 and the transistor M1 constitutes a memory cell. The node N1 of the resistance element R1 is connected to the bit line BL1 through a transistor M1 (usually an NMOS transistor is also often used as an NMOS transistor), and the other node N2 is connected to the source line SL1. Yes. Further, the gate of the transistor M1 is connected to the word line WL1, the bit line BL1 is connected to the bit line driver BD1, and the source line SL1 is connected to the source line driver SD1.

  When writing data to the resistance element R1, the word line WL1 is set to high level to turn on the transistor M1, and a voltage pulse is applied to the resistance element R1. For example, it is assumed that a state in which the resistance of the resistance element R1 is high is assigned to data “0”, and a state in which the resistance element R1 is low is assigned to data “1”. In this case, in order to write data “0”, a positive voltage pulse generated in the bit line driver BD1 is applied to the resistance element R1 while the ground level is applied to the node N2 of the resistance element R1 by the source line driver SD1. Apply to node N1. On the other hand, in order to write data “1”, a positive voltage pulse generated in the source line driver SD1 is applied to the node of the resistance element R1 in a state where the ground level is applied to the node N1 of the resistance element R1 by the bit line driver BD1. Apply to N2.

JP 2009-230796 A

  In the above conventional example, since a high current capability is required, two of the bit line driver and the source line driver having a large area are necessary for writing into one memory cell, resulting in an increase in cost due to an increase in chip area. . In addition, since data “0” and data “1” cannot be simultaneously written into a plurality of memory cells, there are drivers that are not used during the writing period. In addition, if the data already written in the memory cell and the input write data are the same, there is no need to rewrite, but a write pulse is applied to such a cell, consuming extra power and time. In addition, it has an adverse effect on the reliability of disturbances. Further, it is necessary to provide two wirings of a source line and a bit line per memory cell in the vertical direction of the memory array, which causes an increase in chip area.

  These are important issues in the development of semiconductor memory devices that have strict performance and cost requirements.

  The present invention reduces the number of drivers required for writing, eliminates the presence of drivers that are not used during the writing operation, reduces the number of wirings required per cell, and reduces the chip area, thereby improving cost performance. An object of the present invention is to realize a semiconductor memory device which is excellent and has improved characteristics such as shortening of rewriting time and power consumption.

  In order to achieve the above-described object, a first semiconductor memory device of the present invention includes a resistance change type memory cell whose resistance value is changed by application of a voltage, a source line connected to the resistance change type memory cell, A bit line connected to the resistance change type memory cell, a driver for supplying a write potential to the resistance change type memory cell, a first switch element for connecting an output of the driver to the source line, and an output of the driver And a second switch element for connecting the first switch element and the second switch element based on write data input from the outside. To do.

  The second semiconductor memory device of the present invention includes a first resistance change type memory cell and a first resistance change type memory cell which are adjacent to each other and each change in resistance value by application of a voltage, and the first resistance change type memory cell. A first source line connected to the second resistance change type memory cell, a second source line connected to the second resistance change type memory cell, the first resistance change type memory cell, and the second resistance change type memory cell. And a bit line commonly connected to each other.

  According to the first semiconductor memory device of the present invention, only one bit line driver is required for writing to one memory cell, and data “0” and data “1” to a plurality of memory cells are provided. Simultaneous writing with can be easily realized. As a result, a semiconductor memory device with low cost and short rewrite time can be realized.

  According to the second semiconductor memory device of the present invention, the chip area can be reduced by sharing the bit line between two memory cells adjacent in the word line direction.

1 is a circuit diagram showing a basic configuration of a resistance change type memory that is a semiconductor memory device according to a first embodiment of the present invention; FIG. FIG. 2 is a block diagram of a resistance change type memory using the basic configuration of FIG. 1. 3 is a data flow diagram in a write operation of the resistance change type memory of FIG. 2. It is a block diagram of a resistance change type memory which is a semiconductor memory device concerning a 2nd embodiment of the present invention. 5 is a data flow diagram in a write operation of the resistance change type memory in FIG. 4. It is a circuit diagram which shows the basic composition of the resistance change memory which is a semiconductor memory device concerning the 3rd Embodiment of this invention. FIG. 7 is a detailed block diagram of a resistance change type memory using the basic configuration of FIG. 6. FIG. 7 is a schematic block diagram of a resistance change type memory using the basic configuration of FIG. 6. FIG. 9 is a data flow diagram in a write operation of the resistance change type memory of FIG. 8. It is a circuit diagram which shows the basic composition of the conventional resistance change memory.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<< First Embodiment >>
FIG. 1 is a diagram showing the most basic configuration of a resistance change type memory according to the present invention. When actually used as a semiconductor memory device, various other components are required. However, in order to facilitate the description of the present invention, the description is omitted. In addition, since components having the same reference numerals as those in FIG. 10 are the same components, description thereof will be omitted.

  As a difference from the conventional example described with reference to FIG. 10, the configuration of FIG. 1 includes a switch element S1 that connects the source line SL1 and the ground, a switch element S2 that connects the bit line BL1 and the ground, and a source line. The switch element S3 that connects SL1 and the bit line driver BD1 and the switch element S4 that connects the bit line BL1 and the bit line driver BD1, and the switch elements S1 to S4 can be controlled individually. To do. Further, the source line driver SD1 is deleted.

  In the initial state, the switch elements S1 to S4 are in an open state, and each node such as the word line WL1, the bit line BL1, and the source line SL1 is at the ground level.

  When writing data, a voltage pulse is applied to the resistance element R1 as follows. For example, to write data “0”, first, the switch element S4 is closed to connect the bit line BL1 and the bit line driver BD1, and the switch element S1 is closed to connect the source line SL1 to the ground. Next, a positive voltage pulse generated by the bit line driver BD1 is applied in a state where the word line WL1 is set to the high level, the transistor M1 is turned on, and the ground level is applied to the node N2 of the resistance element R1 through the source line SL1. The voltage is applied to the node N1 of the resistance element R1.

  To write data “1”, after returning to the initial state, the switch element S3 is closed to connect the source line SL1 and the bit line driver BD1, and the switch element S2 is closed to connect the bit line BL1 to the ground. To do. Next, the positive voltage pulse generated by the bit line driver BD1 is applied in a state where the word line WL1 is set to the high level, the transistor M1 is turned on, and the ground level is applied to the node N1 of the resistance element R1 through the bit line BL1. The voltage is applied to the node N2 of the resistance element R1.

  In this way, both data “0” writing and data “1” writing can be realized by one driver.

  Note that a required write potential may be supplied from the bit line driver BD1 while fixing the potential of one terminal of the switch elements S1 and S2 to a potential other than the ground level.

  FIG. 2 is a block diagram of a resistance change type memory according to the first embodiment of the present invention using the basic configuration of FIG. In actual use as a semiconductor memory device, there may be various components in addition to the components shown in FIG. 2, but the description thereof is omitted to facilitate the description of the present invention.

  The resistance change type memory 10 of FIG. 2 includes a memory array (ARY) 14 in which the memory cells of FIG. 1 are arranged in an array, a write driver (WD) 11 having the bit line driver BD1, and the switch elements S1 to S1. In addition to S4, a Y multiplexer (YMUX) 12 having switch elements SS1 and SS2 for switching the data flow, a Y decoder (YDEC) 13 for selecting a source line and a bit line of the memory array 14, and a memory array 14 An X decoder (XDEC) 15 for selecting a word line; a sense amplifier (SA) 16 for amplifying a signal representing read data; an output buffer (OUTBUF) 17 for storing data read using the sense amplifier 16; Input / output terminal (I / O) 18 for exchanging data with and from the outside Over a data input buffer (INBUF) 19 for storing a swap flag (SFLG) 20 to flag based on stored in the input buffer 19 data, and a control circuit (CONTROL) 21, which performs overall control.

  Note that one connection destination of the switch elements SS1 and SS2 is the sense amplifier 16, but when the read potential or current is generated only in the bit line and not generated in the source line, it is connected to the bit line. Only the switch element SS2 is connected to the sense amplifier 16, and the switch element SS1 to which the source line is connected is not necessarily connected to the sense amplifier 16. Further, a potential necessary for reading may be supplied from the write driver 11.

  FIG. 3 is a schematic diagram showing the flow of the data write operation of the semiconductor memory device of the present invention, and shows the relationship between the components described so far and the data flow. The case where the present invention is applied to an array will be described with reference to FIGS.

  In FIG. 2, the switch elements S1 to S4 switch the connection destination of the bit line BL1 and the source line SL1 according to the data to be written as described in FIG. 1, but the control is generated based on the data stored in the input buffer 19 Is performed based on the swap flag 20. The input buffer 19 and the swap flag 20 have a plurality of bits, and can hold a plurality of data and flags. Also, regarding the switch elements S1 to S4, only one group is shown in FIG. 2, but actually there are a plurality of groups of switch elements, each of which is controlled corresponding to each bit of the swap flag 20. The Here, for ease of explanation, the number of bits of the input buffer 19 and the swap flag 20 and the number of groups of switch elements are set to 4, and the write operation will be described with reference to FIG. Note that BD1 to BD4 are bit line drivers for 4 bits, and 101 to 104 are memory cells (MC) for 4 bits.

  First, it is assumed that write data “0110” is input to the input buffer 19. Based on the write data, 0 is set to the bit of the swap flag 20 corresponding to the bit for writing data “0”, and 1 is set to the bit of the swap flag 20 corresponding to the bit for writing data “1”. . In some cases, the input buffer 19 can be used as the swap flag 20. The output of the swap flag 20 is sent to each group of the switch elements S1 to S4 in the Y multiplexer 12, and the connection control according to the present invention described with reference to FIG. 1 is performed to execute the write operation.

  In this manner, in the memory array 14 in which the plurality of memory cells 101 to 104 are arranged, the switch elements S1 to S4 are individually controlled according to the write data, thereby writing the data “0” and the data “1”. Can be performed simultaneously.

<< Second Embodiment >>
FIG. 4 is a block diagram in which a part necessary for explanation is extracted from the entire configuration of the semiconductor memory device according to the second embodiment of the present invention. However, in order to facilitate the description of the present invention, the description is omitted. Also, since the components denoted by the same reference numerals as those in FIG. 2 are the same components, description thereof will be omitted.

  As a difference between FIG. 2 and FIG. 4, there is a write flag (HLFLG) 22 that compares the data stored in the input buffer 19 with the data stored in the output buffer 17 and sets a flag if they do not match. The write flag 22 also has a plurality of bits inside, and the number thereof is 4 as in the first embodiment. Each bit output of the write flag 22 is sent to the write driver 11 and used to control the bit line drivers BD1 to BD4.

  FIG. 5 is a schematic diagram showing the flow of data write operation of the semiconductor memory device of the present invention, and shows the relationship between the components described so far and the data flow. The case where the present invention is applied to an array will be described with reference to FIG. First, it is assumed that write data “0110” is input to the input buffer 19. Based on the write data, 0 is set to the bit of the swap flag 20 corresponding to the bit for writing data “0”, and 1 is set to the bit of the swap flag 20 corresponding to the bit for writing data “1”. . The process up to this point is the same as in the first embodiment. In the second embodiment, the data once stored in the memory cells 101 to 104 is read out to the output buffer 17 before applying the write pulse. The data is compared with the corresponding bit of the data stored in the input buffer 19, and “1” is set to the corresponding bit of the write flag 22 if they do not match, and “0” is set if they match. There are various methods such as temporarily resetting the write flag 22 (all “0”) and setting 1 only to the non-matching bits. Basically, a general comparison circuit and a latch circuit are used. A detailed description of the specific means for realizing this is omitted. The output of each bit of the write flag 22 is sent to the bit line drivers BD1 to BD4, respectively, and only the bit line driver corresponding to the bit for which “1” is set in the write flag 22 is controlled to output a pulse. To do. Other operations are the same as those in the first embodiment.

  By adopting such a configuration / control method, the data already written and the newly written data coincide with each other and need not be rewritten (bit 3 and bit 4 in FIG. 5). The generation and application of pulses can be stopped, and not only the power required for generating pulses can be reduced, but also the occurrence of disturbance due to the application of voltage pulses to the memory array 14 can be suppressed.

<< Third Embodiment >>
FIG. 6 is a diagram showing a basic configuration of a resistance change type memory which is a semiconductor memory device according to the third embodiment of the present invention. When actually used as a semiconductor memory device, various other components are required. However, in order to facilitate the description of the present invention, the description is omitted. Moreover, since what is attached | subjected with the same code | symbol as FIG. 1 is the same component, description is abbreviate | omitted.

  As a part different from FIG. 1, one node N3 of the other resistance element R2 adjacent to the resistance element R1 is connected to the bit line BL1 which is also the bit line of the resistance element R1 through the transistor M2, and the other resistance element R2 One node N4 is connected to the source line SL2, a switch element S5 connecting the source line SL2 and the ground, and a switch element S6 connecting the source line SL2 and the bit line driver BD1 are added. It is to be. Note that the added switch elements S5 to S6 can be individually controlled to open and close.

  In the initial state, the switch elements S1 to S6 are in an open state, and the nodes such as the word line WL1, the bit line BL1, and the source lines SL1 / SL2 are at the ground level.

  When writing data, voltage pulses are applied to the resistance elements R1 and R2 as follows. For example, in order to write data “0” to the resistance element R1, first, the switch elements S4 and S6 are closed, the bit line BL1 and the source line SL2 are connected to the bit line driver BD1, and the switch element S1 is closed and the source line Connect SL1 and ground. Next, the positive voltage generated by the bit line driver BD1 in a state where the word line WL1 is set to the high level, the transistors M1 and M2 are turned on, and the ground level is applied to the node N2 of the resistance element R1 through the source line SL1. A pulse is applied to the node N1 of the resistance element R1. At this time, the voltage pulse from the bit line driver BD1 is applied also to the node N3 of the resistance element R2 sharing the word line WL1, but at the same time, the node N4 of the resistance element R2 is also applied to the node N4 through the source line SL2. Since the voltage pulse from the bit line driver BD1 is applied, the potential difference generated in the resistance element R2 is maintained at 0, the resistance value of the resistance element R2 does not change, and no data is written to the resistance element R2. .

  In order to write data “1” to the resistance element R1, after returning to the initial state, the switch element S3 is closed to connect the source line SL1 and the bit line driver BD1, and the switch element S2 is closed to connect the bit line BL1. Connect to ground. At this time, the switch element S5 is left open and the source line SL2 is set to the Hi-z state, or the switch element S5 is closed and the source line SL2 is set to the ground state. There is no problem. Next, the positive voltage generated by the bit line driver BD1 in a state where the word line WL1 is set to the high level to turn on the transistors M1 and M2 and the ground level is applied to the node N1 of the resistance element R1 through the bit line BL1. A pulse is applied to the node N2 of the resistance element R1. At this time, since the potentials of the nodes N3 and N4 of the resistance element R2 sharing the word line WL1 are kept at the ground level, the resistance value of the resistance element R2 does not change, and data is written to the resistance element R2. Not done.

  In order to write data “0” to the resistance element R2, after returning to the initial state, the switch elements S4 and S3 are closed, the bit line BL1 and the source line SL1 are connected to the bit line driver BD1, and the switch element S5 is closed. The source line SL2 is connected to the ground. Next, the positive voltage generated by the bit line driver BD1 in the state where the word line WL1 is set to the high level to turn on the transistors M1 and M2 and the ground level is applied to the node N4 of the resistance element R2 through the source line SL2. A pulse is applied to the node N3 of the resistance element R2. At this time, the voltage pulse from the bit line driver BD1 is also applied to the node N1 of the resistance element R1 sharing the word line WL1, but at the same time, the node N2 of the resistance element R1 is also applied to the node N2 through the source line SL1. Since the voltage pulse from the bit line driver BD1 is applied, the potential difference generated in the resistance element R1 is maintained at 0, the resistance value of the resistance element R1 does not change, and no data is written to the resistance element R1. .

  In order to write data “1” to the resistance element R2, after returning to the initial state, the switch element S6 is closed, the source line SL2 and the bit line driver BD1 are connected, the switch element S2 is closed, and the bit line BL1 is connected. Connect to ground. At this time, the switch element S1 is left open and the source line SL1 is set to the Hi-z state, or the switch element S1 is closed and the source line SL1 is set to the ground state. There is no problem. Next, the positive voltage generated by the bit line driver BD1 in the state where the word line WL1 is set to the high level to turn on the transistors M1 and M2 and the ground level is applied to the node N3 of the resistance element R2 through the bit line BL1. A pulse is applied to the node N4 of the resistance element R2. At this time, since the potentials of the nodes N1 and N2 of the resistance element R1 sharing the word line WL1 are maintained at the ground level, the resistance value of the resistance element R1 does not change, and data is written to the resistance element R1. Not done.

  By doing so, writing can be performed even if the bit lines are shared by two adjacent memory cells, and the chip area can be reduced by reducing the number of bit lines by sharing the bit lines.

  Note that a required write potential may be supplied from the bit line driver BD1 while fixing the potential of one terminal of the switch elements S1, S2, and S5 to a potential other than the ground level.

  7 and 8 are obtained by adding elements constituting the memory array and its peripheral circuits to the basic configuration shown in FIG. 6 so as to be close to an actual semiconductor memory device. Memory cells 101 to 114, 201 to 214, 301 to 314 are arranged in an array, and word lines WL1, WL2, WL3, bit lines BL1, BL5, BL9, BL13, and source lines SL1, SL2, SL5, respectively. The memory array 14 is configured by being connected to SL6, SL9, SL10, SL13, and SL14. Among them, bit lines BL1, BL5, BL9, BL13. . . Are shared by memory cells (for example, 101 and 102) adjacent in the word line direction. For example, the bit line BL1 is shared by the memory cells 101 and 102.

  A Y decoder 13, a Y multiplexer 12, and a sense amplifier 16 exist between the memory array 14 and the write driver 11 or at a position aligned with the write driver 11. The Y decoder 13 receives the Y decode signals YD1 to YD4, turns on / off the selection transistors (usually NMOS transistors) MS1 to MS14 and MB1 to MB13, and connects the source line and bit connected to the sense amplifier 16 or the write driver 11 Select a line. The Y multiplexer 12 switches the connection destinations of the switch elements (usually composed of MOS transistors) SS1, SS2, and SS3 in accordance with an external control signal, so that the source line and the bit line are the sense amplifier 16 or the write driver 11. Connect to either. The Y decoder 13, the Y multiplexer 12, the sense amplifier 16, and the write driver 11 have components that are omitted in addition to the components described.

  In FIG. 7, the word line WL4 and later, the bit lines BL2 to BL4, BL6 to BL8, BL10 to BL12, and BL14 and the source lines SL3, SL4, SL7, SL8, SL10, SL12, and SL14 are described. However, they are omitted for convenience of explanation, and an actual semiconductor memory device includes memory cells connected to them.

  A plurality of bit lines and source lines are connected to the Y multiplexer 12 via the Y decoder 13, but the decoding method shown in this example is merely an example, and there are various other decoding methods. Description is omitted.

  In addition, one connection destination of the switch elements SS1, SS2, and SS3 in FIG. 8 is the sense amplifier 16, but the read potential and current are generated only in the bit line and not in the source line. Only the switch element SS2 connected to the bit line is connected to the sense amplifier 16, and the switch elements SS1 and SS3 connected to the source line are not necessarily connected to the sense amplifier 16. Further, a potential necessary for reading may be supplied from the write driver 11.

  FIG. 9 is a schematic diagram showing the flow of the data write operation of the semiconductor memory device of the present invention, and shows the relationship between the components described so far and the data flow. The case where the present invention is applied to an array will be described with reference to FIG. First, it is assumed that write data “0110” is input to the input buffer 19. Based on the write data, 0 is set in the bit of the swap flag 20 corresponding to the bit for writing data “0”, and 1 is set in the bit of the swap flag 20 corresponding to the bit for writing data “1”. The switch elements S1 to S6 are controlled according to the data of the swap flag 20. In addition, the data once stored in the memory cells 101 to 104 is read out to the output buffer 17 before the write pulse is applied. The data is compared with the corresponding bit of the data stored in the input buffer 19, and “1” is set in each bit of the write flag 22 when they do not match and “0” when they match. The process up to this point is the same as in the second embodiment.

  In the third embodiment, the output of each bit of the write flag 22 is sent to the bit line drivers BD1 and BD3, respectively, and writing to the memory cells 101 to 104 is performed in two steps. First, since the bit line driver BD1 writes to the memory cell 101 and the bit line driver BD3 writes to the memory cell 103, the output of the write flag 22 corresponding to the memory cell 101 corresponds to the bit line driver BD1 and the memory cell 103. The output of the write flag 22 to be transmitted is sent to the bit line driver BD3, and only the bit line driver corresponding to the bit for which “1” is set in the write flag 22 is controlled to output a pulse. Executed. Next, the output of the write flag 22 corresponding to the memory cell 102 is sent to the bit line driver BD1, and the output of the write flag 22 corresponding to the memory cell 104 is sent to the bit line driver BD3, and writing is executed.

  Also in the third embodiment, as in the second embodiment, by adopting such a configuration / control method, the already written data matches the newly written data, and there is no need to rewrite. For the bits (bit 3 and bit 4 in FIG. 9), the generation and application of the rewrite pulse can be stopped, and not only the power required for the pulse generation can be reduced, but also the disturbance caused by the voltage pulse application to the memory array 14 can be reduced. Occurrence can be suppressed.

<< Modification of Third Embodiment >>
A data write method different from the above in the resistance change type memory described with reference to FIG. 6 will be described with reference to FIG. In the initial state, the switch elements S1 to S6 are in an open state, and the nodes such as the word line WL1, the bit line BL1, and the source lines SL1 / SL2 are at the ground level.

  When writing data, first, the data states of the resistance elements R1 and R2 of the adjacent memory cells sharing the bit line BL1 and the word line WL1 are made the same. For example, in order to write data “0” to the two resistance elements R1 and R2, first, the switch element S4 is closed, the bit line BL1 is connected to the bit line driver BD1, the switch elements S1 and S5 are closed, and the source line SL1 and SL2 are connected to the ground. Next, the word line WL1 is set to the high level, the transistors M1 and M2 are turned on, and the ground level is applied to the node N2 of the resistance element R1 through the source line SL1, and simultaneously, the ground level is applied to the node N4 of the resistance element R2 through the source line SL2. With the level applied, a positive voltage pulse generated by the bit line driver BD1 is applied to the node N1 of the resistance element R1 and the node N3 of the resistance element R2. At this time, the data “0” is written to the resistance element R2 simultaneously with the data “0” being written to the resistance element R1.

  When the write data to the resistance elements R1 and R2 is “0”, it is not necessary to apply a new write pulse, and the write operation to these memory cells ends. On the other hand, when the write data to the resistor element R1 is “1”, the write data to the resistor element R2 is “1” by the same method as the method of writing the data “1” of the third embodiment to the resistor element R1. In this case, the same method as the method of writing the data “1” of the third embodiment to the resistance element R2 is performed. At this time, data is not written because the nodes at both ends of the resistance element not to be written are kept at the ground level.

  As described above, in the case of the writing method that performs the two-step writing operation in which the resistance elements R1 and R2 are once set in the data “0” state and then the data “1” is written to the desired resistance element, In the embodiment, by simultaneously applying a pulse to both ends of the resistance element, the method is more stable and easier to design and manufacture than the method of preventing data writing to the resistance element not to be written. That is, in the dynamic method of applying the same pulse as in the third embodiment, it is necessary to design / manufacture so that the pulse can be applied accurately in consideration of the influence of the additional capacitance / resistance of each node. However, there is no such restriction in the method of maintaining a static state as in this modification.

  Note that a method of applying the method described in this modification to the memory array is the same as in the first and second embodiments, and a description thereof will be omitted.

  According to the present invention, it is possible to realize a semiconductor memory device that eliminates waste of writing operation and consumes less power. Further, by further utilizing the technique of the present invention, a semiconductor memory device having a small chip area and a low cost can be realized. By realizing such a low-cost and easy-to-use nonvolatile memory, the performance of electronic devices using the nonvolatile memory can be improved, and better products can be sent to society.

  Specifically, the cost of the resistance change type nonvolatile memory is reduced, and the usability is improved. As a result, it is possible to provide nonvolatile memories that make use of high-speed rewriting / low power at a low price, especially in the field of portable devices that record and play back music and video, etc. Expansion is expected.

DESCRIPTION OF SYMBOLS 10 Resistance change type | mold memory 11 Write driver 12 Y multiplexer 13 Y decoder 14 Memory array 15 X decoder 16 Sense amplifier 17 Output buffer 18 Input / output terminal 19 Input buffer 20 Swap flag 21 Control circuit 22 Write flag 101-114 Memory cells 201-214 Memory cells 301-314 Memory cells BD1-BD4 Bit line drivers BL1-BL13 Bit lines M1-M2 NMOS transistors MB1-MB13 NMOS transistors MS1-MS14 NMOS transistors N1-N4 Connection nodes R1-R2 Resistance elements S1-S6 Switch element SD1 Source Line drivers SL1 to SL13 Source lines SS1 to SS3 Switch elements WL1 to WL3 Word lines YD1 to YD4 Y decode signal

Claims (17)

A resistance change type memory cell whose resistance value is changed by applying a voltage;
A source line connected to the resistance change type memory cell;
A bit line connected to the resistance change type memory cell;
A driver for supplying a write potential to the resistance change type memory cell;
A first switch element for connecting the output of the driver to the source line;
A second switching element for connecting the output of the driver to the bit line;
A semiconductor memory device, wherein the first switch element and the second switch element are switched on and off based on externally input write data. The semiconductor memory device according to claim 1.
A third switch element connecting the source line and a fixed potential;
A fourth switch element for connecting the bit line and the fixed potential;
A semiconductor memory device, wherein the third switch element and the fourth switch element are switched on and off based on the write data. The semiconductor memory device according to claim 2.
A semiconductor memory device using MOS transistors as the first to fourth switch elements. The semiconductor memory device according to claim 1.
A semiconductor memory device further comprising an input buffer for storing the write data. The semiconductor memory device according to claim 1.
A comparator for comparing the data read from the resistance change type memory cell with the write data;
A semiconductor memory device, wherein the driver is controlled based on a comparison result in the comparator. The semiconductor memory device according to claim 5.
A semiconductor memory device characterized by not writing data to the resistance-change memory cell when they match in the comparison, and writing data to the resistance-change memory cell when they do not match. The semiconductor memory device according to claim 5.
A semiconductor memory device further comprising an output buffer for storing the read data. The semiconductor memory device according to claim 5.
A semiconductor memory device further comprising a flag circuit for storing a comparison result in the comparator. First and second resistance change type memory cells that are adjacent to each other and each change in resistance value by application of a voltage;
A first source line connected to the first resistance change type memory cell;
A second source line connected to the second resistance change type memory cell;
A semiconductor memory device comprising: a bit line commonly connected to the first resistance change type memory cell and the second resistance change type memory cell. The semiconductor memory device according to claim 9.
A driver for supplying a write potential to the first resistance change type memory cell or the second resistance change type memory cell;
A first switch element for connecting the output of the driver to the first source line;
A second switch element for connecting the output of the driver to the second source line;
A third switch element for connecting the output of the driver to the bit line;
A semiconductor memory device, wherein on / off of the first switch element, the second switch element, and the third switch element is switched based on externally input write data. The semiconductor memory device according to claim 10.
A fourth switch element connecting the first source line and a fixed potential;
A fifth switch element connecting the second source line and the fixed potential;
A sixth switch element for connecting the bit line and the fixed potential;
A semiconductor memory device, wherein the fourth switch element, the fifth switch element, and the sixth switch element are switched on and off based on the write data. The semiconductor memory device according to claim 11.
A semiconductor memory device using MOS transistors as the first to sixth switch elements. The semiconductor memory device according to claim 10.
A semiconductor memory device further comprising an input buffer for storing the write data. The semiconductor memory device according to claim 10.
A comparator that compares the data read from the first resistance change type memory cell or the second resistance change type memory cell with the write data;
A semiconductor memory device, wherein the driver is controlled based on a comparison result in the comparator. The semiconductor memory device according to claim 14.
If they match in the comparison, data is not written to the first and second resistance change memory cells, and if they do not match, data is written to the first or second resistance change memory cell. A semiconductor memory device. The semiconductor memory device according to claim 14.
A semiconductor memory device further comprising an output buffer for storing the read data. The semiconductor memory device according to claim 14.
A semiconductor memory device further comprising a flag circuit for storing a comparison result in the comparator.

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