JP2011204358A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate a negative potential generating circuit, and to shorten a data read-out time, in a semiconductor memory device including a variable resistance type memory element.SOLUTION: At the time of standby, both ends of a variable resistance type memory element 403, that is, a bit line BL and a source line SL are set to a pre-charge potential Vp by each pre-charge circuit 402 of a bit line and a source line. At the time of setting, the bit line BL is set to a higher setting voltage Vd than the pre-charge potential Vp by a bit line write-in bias generating circuit 401, and the source line SL is grounded by the bit line write-in bias generating circuit. At the time of resetting, contrary to the time of setting, the bit line BL is grounded, the source line SL is set to the setting voltage Vd. During the time of read-out of data, for example, the source line SL is grounded by the read-out bias circuit 405 while keeping the bit line BL at the pre-charge potential Vp as it is.

Description

  The present invention relates to a semiconductor memory device, and more particularly to a technique effective when used for a nonvolatile semiconductor memory device using a resistance change device.

  In recent years, the technology of semiconductor integrated circuits has been miniaturized, and the gate oxide film has been made thinner or the gate electrode material has been modified. In addition, rewritable devices such as FLASH and EEPROM have been increased in scale and integration, and technical progress has been made. Even in the field of systems using semiconductor devices, the required device applications are changing, and there are cases where security applications, non-volatile memory elements such as IC TAG or OTP elements are mixedly mounted inside, and a large capacity that can be rewritten. There is also an increasing tendency to incorporate non-volatile memories. Recently, as an FG type non-volatile memory such as a normal FLASH or EEPROM, a new non-volatile memory has appeared and attracted attention as a further reduction in area. Typical examples include FeRAM using a ferroelectric, MRAM using magnetism, PRAM as a phase change memory, resistance change memory, and the like.

  Among the novel non-volatile memories, the memory element of the resistance change type memory uses a material having a perovskite structure or a binary transition metal oxide as its oxide film, and the resistance value of the memory element is reduced. Nonvolatile storage is performed by setting a high resistance value (when set) or a low resistance value (when erasing or resetting).

  Conventionally, a voltage of ± bipolarity is used as a voltage bias condition at the time of setting or resetting such a resistance change type memory. For example, as the bias voltage applied across the resistance of the resistance change type memory element, for example, a positive voltage of a predetermined value is used at the time of writing, and the positive voltage and the absolute value are the same value at the time of erasing, and a negative voltage of a predetermined value different only in sign used. Further, the voltage values of the above-mentioned ± bipolar range from 5V to about 1V. This type of technology is described in Patent Document 1, for example.

JP 2004-158119 A

  However, since the conventional resistance change type memory uses a voltage of ± bipolarity as the bias voltage, it has the following problems.

  FIG. 2 shows an applied state of a bias voltage when data is written (set, reset) in a conventional semiconductor memory device.

  In this figure, 203 is a resistance change memory element, 201 is one terminal of the resistance change memory element 203, 202 is the other terminal of the resistance change memory element 203, and 204 is the resistance change memory element 203. Reference numeral 205 denotes an application state in which a set bias voltage is applied at the time of setting, and reference numeral 205 denotes an application state in which a reset bias voltage is applied at the time of resetting the resistance change type memory element 203.

  As can be understood from the figure, it is assumed that the potential difference between the two terminals 201 and 202 of the memory element 203 necessary for setting or resetting the resistance change memory element 203 at the time of data writing is the set value Vd. Then, while the other terminal 202 is always at the ground potential GND, a positive set value + Vd is applied to one terminal 201 at the time of setting, and a negative set value −Vd is applied at the time of reset. The potential transitions between a positive voltage + Vd and a negative voltage −Vd. In this case, the voltage transition at the terminal 201 is 2 × Vd, which requires a high amplitude difference and a negative potential generation circuit that generates a negative set value −Vd. However, in an actual semiconductor device, in the case of a twin well or the like, generation of a negative potential is not allowed and it is difficult to employ this technique.

  Thus, as a configuration that does not require the negative potential generation circuit, for example, the voltage of the fixed potential terminal 202 may be set to the positive voltage + Vd. However, the voltage of one terminal 201 is a boosted voltage of 2 × Vd. There are two types, the ground voltage GND, and the voltage amplitude of the terminal 201 becomes a large amplitude of 2 × Vd as described above. In addition, even when the potential is generated internally, the current supply of the boosted potential generating circuit tends to have a small capacity, and there is a disadvantage that the number of bits at the time of writing is limited.

  The present invention has been made in view of such a point, and an object of the present invention is to set a potential difference between both terminals of a memory element necessary for data writing as a set value Vd in a semiconductor memory device having a resistance change type memory element. An object of the present invention is to allow data to be written to and read from the memory element at high speed while limiting the voltage amplitude of each terminal of the memory element to the set value Vd.

  In order to achieve the above object, in the present invention, a high potential such as a set voltage Vd and a low potential such as a ground potential are prepared, and only two types of the high potential and the low potential are used. While adopting a configuration in which a bias voltage of a predetermined value is applied to both terminals of the element in the forward direction and the reverse direction, data reading at the time of data reading is further performed at high speed.

  Specifically, the semiconductor memory device according to claim 1 is a resistance change type memory element having a first node and a second node, and a first selection line connected to the first node of the resistance change type memory element. And a second selection line connected to a second node of the resistance change type memory element, the resistance change type memory element having a forward and reverse bias voltage between the first and second nodes. Is a semiconductor memory device that sets and resets data, a sense amplifier that amplifies a potential difference between a set reference potential and a potential generated by a resistance value of the resistance change type memory element, and amplifies the sense amplifier Amplification control means to be operated and data setting or resetting operation to the resistance change type memory element are started, and the output signal of the sense amplifier is received and the received output signal is responded to. Characterized by comprising a writing means for stopping the set and reset operations of the data Te.

  According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the sense amplifier is also used as a data read sense amplifier used at the time of data read, and the set reference potential is set at the time of data write. And a reference potential generator for setting, resetting and data reading separately generated for a reference potential for setting, a reference potential for resetting, and a reference potential for data reading.

  According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, the writing unit stops the data setting and resetting operations in response to an output signal of the data read sense amplifier. Features.

  According to a fourth aspect of the present invention, in the semiconductor memory device according to the second aspect, the semiconductor memory device further includes a read data output circuit that outputs an output signal of the data read sense amplifier to the outside, and the writing means includes the data read The sense amplifier output signal is received via the read data output circuit, and the data read sense amplifier and the read data output circuit are activated at the same timing as the data read operation when data writing is set and reset. It is characterized by being.

  According to a fifth aspect of the present invention, in the semiconductor memory device according to the second aspect, the three reference potential generating means for setting, resetting, and reading data are set at the time of data writing. When resetting and reading data, it has the same current path as the current flowing through the resistance change type memory element to be written or read, and has a plurality of resistance elements for voltage division in the current path. The selection is based on a command, a reset command, and a read command.

  According to a sixth aspect of the present invention, in the semiconductor memory device according to the first aspect, the reference potential generating circuit generates the set reference potential, and the reference potential generating circuit has a source connected to a power supply used for data writing. A first P-channel transistor, a second P-channel transistor whose source is connected to a power source used for data reading, and a voltage dividing voltage commonly connected to the first and second P-channel transistors. A plurality of resistance elements and selection means for selecting one of the first and second P-channel transistors are provided.

  According to a seventh aspect of the invention, in the semiconductor memory device according to the first aspect, the amplification control means always amplifies the sense amplifier in the first state, and the writing means is in the second state. And starting the data setting or resetting operation to the resistance change type memory element, receiving the output signal of the sense amplifier, and stopping the data setting and resetting operation according to the received output signal. Features.

  According to an eighth aspect of the present invention, in the semiconductor memory device according to the seventh aspect, the first state is when data is written, and the second state is when data write is set or reset. It is characterized by being.

  As described above, in the first to eighth aspects of the invention, when the potential required for data writing is set to the set voltage Vd, the potential difference between the first and second nodes of the resistance change type memory element is set to + Vd or −Vd. When fixing, the voltage amplitude of each node is only the set voltage Vd applied to the bit line, so that it is not necessary to generate an extra write potential. In addition, during standby, the first and second nodes of the resistance change memory element are precharged to a predetermined potential, so that an inadvertent bias voltage is not applied, and the occurrence of resistance change due to Disturb or the like is effectively suppressed. In addition, when the transition from standby to data read is performed, the precharge potential becomes the data read potential as it is, so that the first and second potentials are different from the case where a potential different from the precharge potential is set as the data read potential. There is no need to apply an unnecessary bias voltage to the second node, the reading operation can be speeded up, and the control is simplified.

  In particular, according to the first aspect of the present invention, when data is written, the sense amplifier is always amplified, and based on the output change of the sense amplifier based on the resistance value change of the resistance change type memory element to which data is written. Since the data writing operation is stopped, the data writing operation can be stopped simultaneously with the completion of the data writing, and the data writing time can be shortened. In addition, when the resistance value after data erasure of the resistance change type memory element requires accuracy, such as multi-value, level control of the resistance value can be easily and automatically performed.

  According to the second aspect of the invention, there is no need to separately prepare a sense amplifier for detecting the completion of data writing, which contributes to a reduction in area. In addition, the reference potential of the sense amplifier corresponding to the set and reset commands can be supplied to the specific bit in the row direction among the active bits selected in the column direction.

  According to the third aspect of the present invention, since the stop control of the data writing operation is performed using the output signal of the data read sense amplifier, it is not necessary to generate a new signal for the stop control.

  In addition, in the invention described in claim 4, when the data read sense amplifier and read data output circuit which are already provided are used for detecting the completion of data write, the start timing at the time of data write is set as the read timing. Since the same timing is set, it is not necessary to add an extra circuit related to timing generation.

  In addition, according to the fifth aspect of the present invention, when data is written or read from the resistance change type memory element to be written or read, the reference potential of the sense amplifier is set corresponding to the fluctuation of the write or read voltage. Since it can be made variable, variations in the manufacturing process of the transistor located in the path of the current flowing through the resistance change type memory element can be absorbed.

  According to the sixth aspect of the present invention, since the reference potential of the sense amplifier is relatively changed according to the difference voltage between the write voltage and the read voltage, the reference potential of the sense amplifier can be generated with a simpler configuration. it can.

  As described above, according to the first to eighth aspects of the present invention, in the semiconductor memory device including the resistance change type memory element, the data writing operation can be stopped simultaneously with the completion of the data writing. Time can be shortened.

It is a figure which shows the resistance change memory element with which the semiconductor memory device of the 1st Embodiment of this invention is provided, and its bias potential. It is a figure which shows the bias electric potential to the conventional resistance change type memory element. It is a figure which shows the whole block structure of the semiconductor memory device of this invention. 1 is a configuration diagram around a sense amplifier of a semiconductor integrated circuit according to a first embodiment of the present invention; It is a block diagram around the sense amplifier of the semiconductor integrated circuit of the second embodiment of the present invention. It is a block diagram which shows the principal part structure of the semiconductor integrated circuit of the 3rd Embodiment of this invention. It is a figure which shows the structure of the reference electric potential generation circuit with which the semiconductor integrated circuit is equipped. It is a figure which shows the modification of the same reference potential generation circuit. It is a figure which shows the internal structure of the write / read circuit with which the same semiconductor integrated circuit is equipped. It is a figure which shows the various waveforms at the time of the reset command of the semiconductor integrated circuit of the 1st Embodiment of this invention. It is a figure which shows the various waveforms at the time of the set command of the semiconductor integrated circuit of the 1st Embodiment of this invention. It is a figure which shows the various waveforms at the time of the data reading of the semiconductor integrated circuit of the 1st Embodiment of this invention. It is a figure which shows the various waveforms at the time of the set command of the semiconductor integrated circuit of the 3rd Embodiment of this invention. It is a figure which shows the various waveforms at the time of the reset command of the semiconductor integrated circuit of the 3rd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  In order to simplify the explanation, the following items are defined. In the following description, “set” refers to an operation of increasing the resistance value of the resistance change type memory element and outputting a low level as an output of the nonvolatile semiconductor memory device, and “reset” means a resistance of the resistance change type memory element. It is defined as an operation of reducing the value and outputting a high level as the output of the semiconductor memory device. A case where the terminal connected to the bit line side of the resistance change memory element is set to a high potential is called a set, and a case where the terminal is set to a low potential is called a reset. Further, a potential used for data writing is described as a set value Vd, and a potential used for reading is described as a read potential Vp.

(First embodiment)
The semiconductor memory device according to the first embodiment of the present invention will be described below.

  In the present embodiment, first, a set operation and a reset operation will be described first when data is written to the resistance change type memory element.

  FIG. 1 shows a resistance change type memory element provided in the semiconductor memory device and a bias voltage application state during the write operation. In the figure, 103 is a resistance change type memory element, 101 is one terminal (first node) of the resistance change type memory element 103, 102 is the other terminal (second node) of the resistance change type memory element 103, Reference numeral 104 denotes an application state in which a forward bias voltage is applied when data writing to the memory element 103 is set, and reference numeral 105 denotes an application state in which a reverse bias voltage is applied when data writing to the memory element 103 is reset. Show.

  In the resistance change type memory element 103 of FIG. 1, assuming that the potential difference between both terminals 101 and 102 necessary for data writing is a set value + Vd, in standby mode (in this embodiment, a memory having a large number of resistance change type memory elements). In addition to the state where all of the resistance change type memory elements in the cell array are not selected, the resistance change type memory element is not selected but other resistance change type memory elements are selected. ), Both terminals 101 and 102 are precharged to a reference potential Vp smaller than the set value Vd. At the time of setting, the terminal 101 is set to the set value Vd and the other terminal 102 is set to the GND potential, whereby the forward bias voltage of the set voltage Vd is set between both terminals of the memory element 103 with the GND potential of the other terminal 102 as a reference. Apply. On the other hand, at the time of resetting, contrary to the setting, the terminal 101 is set to the GND potential, and the other terminal 102 is set to the set value Vd, whereby both terminals of the memory element 103 are set based on the set voltage Vd of the terminal 102. In the meantime, a bias voltage in the reverse direction of the negative set voltage -Vd is applied.

  FIG. 4 shows a main configuration of the semiconductor integrated circuit according to the present embodiment. In the figure, a resistance change type memory element 403 which is one memory cell includes a memory element body M whose resistance value changes in accordance with forward application or reverse application of a bias voltage, and a word line (row selection line). A selection transistor Ts composed of an Nch transistor whose gate potential is the potential of WL is connected. The resistance change type memory element 403 is connected to a bit line (column selection line) BL, and the source of the selection transistor Ts is coupled to a source line SL. Although only one resistance change type memory element 403 is shown in the figure, a large number of resistance change type memory elements 403 are arranged in a matrix in the word line WL and bit line BL directions.

  In FIG. 4, 401 is a bit line write bias generation circuit, 402 is a bit line precharge circuit, 407 is a source line write bias generation circuit, 406 is a source line precharge circuit, and 405 is a read bias generation circuit. A sense amplifier 404 amplifies the potential difference between the set reference potential Vref and the output potential of the resistance change memory element 403 by the sense amplifier activation signal SAE, and outputs an output signal IDO. The bit line precharge circuit 402 and the source line precharge circuit 406 constitute precharge means 420. The bit line write bias generating circuit 401 and the source line write bias generating circuit 407 constitute a bias applying means 421, and the bit line precharge circuit 402 and the read bias circuit 405 constitute a reading means 422.

  FIG. 10 shows a waveform diagram during the reset operation of the circuit of FIG. In the figure, at the time of Standby, the complementary signals ST and / ST are at the Low and High levels, respectively, and the other complementary signals RST and / RST are at the Low and High levels, respectively, and the bit line write bias circuit 401 and The source line write bias generation circuit 407 is stopped in the cut-off state. On the other hand, the two signals BLP and SLP are at the low level, and the bit line precharge circuit 402 and the source line precharge circuit 406 have their internal Pch transistors turned on to set the respective potentials of the bit line BL and the source line SL. It is precharged to the precharge potential Vp.

  Thereafter, at the reset time, in the complementary signals RST and / RST in FIG. 4, the signal RST goes to the high level and the inverted signal / RST goes to the low level. Further, the two signals BLP and SLP are at a high level. As a result, the two precharge circuits 402 and 406 are stopped. Then, the potential of the word line WL rises, the selection transistor Ts is turned on, and a state in which a bias voltage is applied to both terminals of the resistance change memory element 403 is formed. Since the signal RST becomes the high level, the bit line write bias generation circuit 401 sets the potential of the bit line BL to the low level (GND level). On the other hand, the source line write bias generation circuit 407 raises the potential of the source line SL to the set value Vd because the signal / RST becomes the Low level. Therefore, the resistance change memory element 403 has the GND level on the bit line BL side and the set potential Vd on the source line SL side, and the resistance value of the memory element body M of the resistance change memory element 403 becomes low. Thereafter, even if the bias state of the GND level on the bit line BL side and the set potential Vd on the source line SL side is released, the low resistance state of the memory element body M is maintained.

  FIG. 11 shows a waveform diagram during the set operation of the circuit of FIG. In the figure, contrary to the reset shown in FIG. 10, for the complementary signals ST and / ST, the signal ST becomes high level, the inverted signal / ST becomes low level, and the two signals BLP and SLP Both become High level. As a result, the two precharge circuits 402 and 406 are stopped. Then, the potential of the word line WL rises, and a state where a bias voltage is applied to both terminals of the resistance change memory element 403 is formed. The bit line write bias generation circuit 402 raises the potential of the bit line BL to the set value Vd because the signal / ST has become low level, while the source line write bias generation circuit 407 has the signal ST of High. Since the level is reached, the potential of the source line SL is lowered to the low level (GND level). The set voltage Vd of the bit line write bias generation circuit 401 is a potential necessary for writing data into the resistance change memory element 403. As a result, the bit line BL side of the resistance change type memory element 403 becomes the set potential Vd and the source line SL side becomes the GND level, and the resistance value of the memory element body M of the resistance change type memory element 403 becomes high. Thereafter, even if the bias state of the set potential Vd on the bit line BL side and the GND level on the source line SL side is released, the high resistance state of the memory element body M is maintained.

  Next, FIG. 12 shows a waveform diagram during the data read operation of the circuit of FIG. In the read operation shown in the figure, the complementary signals ST and / ST are set to Low and High levels, respectively, and the other complementary signals RST and / RST are also set to Low and High levels, respectively. Accordingly, the two bias generation circuits 401 and 407 are stopped. Further, the signal BLP is held at the low level as in the stanby state, and the potential of the bit line BL is set to the precharge potential Vp. In the present embodiment, the bit line precharge circuit 402 is also used at the time of reading. However, when a difference in speed of voltage change between the reading operation and the precharging is set, A read circuit having the same configuration as that of the line precharge circuit 402 may be added separately. The signal SLP shifts to a high level, and the source line precharge circuit 406 stops. Further, the read signal RD becomes High level, and the source line SL is lowered to Low level (GND level). At the same time, the word line WL shifts to a high level. As a result, the bit line side of the resistance change memory element 403 is lowered to the GND level on the source line side while the precharge potential Vp similar to that in the standby state is applied. Here, the precharge potential Vp is set lower than the set voltage Vd. Therefore, when the bias relationship at the time of data writing is set, that is, when the bit line side of the resistance change type memory element 403 is compared with the bias relationship of the set voltage Vd and the source line side is the GND potential, the bit line BL side is precharge potential Vp ( <Vd), so that a bias voltage higher than the bias voltage at the time of setting is not applied between both terminals of the resistance change memory element 403, so that the high resistance state of the resistance change memory element 403 can be maintained satisfactorily. Can be read out.

  Here, when the potential required for writing is set to the set voltage Vd, the voltage applied to each terminal of the resistance change memory element 403 is + Vd or GND regardless of whether the voltage is set or reset. The voltage change (amplitude) at each terminal is limited to + Vd and can be equal to the set voltage Vd applied to the bit line BL. Therefore, a negative potential generation circuit is not required as in the prior art, and an extra write voltage generation circuit is unnecessary, and this embodiment can be applied well to a semiconductor integrated circuit using a semiconductor device such as a twin well. It is.

  Further, when all the resistance change type memory elements 403 provided are not selected, when the standby state is narrow, when the resistance change type memory element 403 connected to one bit line BL is not selected, the resistance change type memory elements 403 are selected. Since both ends of the memory element 403 are precharged to a predetermined potential Vp (Vp <Vd) lower than the set voltage Vd, an inadvertent bias voltage is applied to both ends of the resistance change type memory element 403. Therefore, it is possible to suppress a change in resistance value caused by the Disturb or the like at both ends of the resistance change type memory element 403.

  Furthermore, at the time of reading from the stanby state or the non-selected state in a narrow sense, the precharge potential Vp in the stanby state or the non-selected state immediately becomes a read potential. Compared with the case where it does, it is not necessary to wait until the application of an unnecessary bias voltage is completed, and control becomes easy.

  In addition, in the present embodiment, at the time of reading, a precharge potential Vp is applied to the bit line BL and a GND potential is applied to the source line SL, and this voltage application state (application of a bias voltage to the resistance change memory element 403) is applied. (Condition) is a voltage application state similar to that in the set state in which the set potential Vd is applied to the bit line BL and the GND potential is applied to the source line SL. Therefore, even when the resistance change type memory element 403 is difficult to maintain when the resistance change type memory element 403 is set in reliability, and the high resistance value gradually decreases over time, the resistance change type memory element 403 is reduced. The voltage relationship between both ends can be maintained in the same manner as at the time of setting, and the high resistance value can be maintained well. If the resistance change memory element 103 in the reset state has a weak low resistance holding capability, the source line precharge circuit 406 is operated at the time of reading, contrary to the present embodiment. Is set to the precharge potential Vp and the read bias generation circuit 405 is arranged on the bit line BL side to operate, or the potential of the bit line BL is set to the precharge potential Vp and the source line SL is precharged. A potential higher than the potential Vp by a voltage necessary for data reading may be applied.

  Further, a semiconductor integrated circuit system having the semiconductor memory device includes a semiconductor device (internal circuit) that operates at a low voltage in the semiconductor integrated circuit system, and a low-voltage system core power source (operating these semiconductor devices). System low-voltage source) and a high-voltage data input / output high voltage source for external data input / output, the set voltage Vd of the semiconductor memory device of this embodiment is used as the data input / output If the precharge voltage Vp is supplied from the system core power supply while being supplied from the high voltage source, the internal voltage booster circuit for generating the set voltage Vd becomes unnecessary.

(Second Embodiment)
FIG. 5 is a diagram showing a main configuration of a semiconductor memory device according to the second embodiment of the present invention. Components common to those in FIG. 4 are denoted by the same reference numerals as in FIG.

  The semiconductor memory device of FIG. 5 differs from the semiconductor memory device of FIG. 4 in that a source line write bias generation circuit (second bias applying means) 407, a source line precharge circuit 406, and a read bias generation circuit 405 4 is arranged on the same side as the bit line write bias circuit (first bias applying means) 401 and the bit line precharge circuit 402 (one end side on the left side in FIG. 4) in the semiconductor integrated circuit of FIG. However, in this embodiment, the memory cell array 408 is arranged on the opposite side, that is, on the right side (the other end side) of the memory cell array 408 including the resistance change memory elements 403 arranged in the row and column directions. Since the control signal lines ST, / ST, RST, / RST are the same control signal that runs globally in the horizontal direction above the memory cell array 408, there is no problem even if such an arrangement is adopted. The applied waveforms of the signals at the time of setting, resetting and reading are the same as in the first embodiment.

  In general, as in the first embodiment, a bit line write bias circuit 401 and a source line write bias circuit 407 are arranged on one end side of the memory cell array 408, and a bit line precharge circuit 402 and a read bias circuit 405 are arranged. Are placed on the same side, when a current is passed through the series circuit of the bit line BL, the resistance change type memory element 403 and the source line SL at the time of setting, resetting or reading, the object of setting, resetting or reading The length of the current path changes according to the arrangement position of the resistance change type memory element 403, and the current change path is long in the resistance change type memory element 403 existing at a position far from the bias circuit 401 or the like. The current path in the resistance change type memory element 403 is shortened. As a result, the bias voltage value applied to each resistance change type memory element 403 varies depending on the resistance value of the metal wiring constituting the bit line BL and the source line SL.

  However, in this embodiment, regardless of the arrangement position of the resistance change type memory element 403 to be set, reset, or read, the voltage drop caused by the metal wiring resistance of the bit line BL and the source line SL is reduced. Therefore, the variation in the applied bias voltage value in the cell array is adjusted in a self-aligned manner.

  Therefore, in the present embodiment, the bias voltage to be applied to both ends of each resistance change type memory element 403 is held at a predetermined constant value regardless of the arrangement position of the resistance change type memory element 403 in the memory cell array 408. Thus, the resistance change memory elements 403 can be set, reset, and read out evenly between the resistance change memory elements 403.

(Third embodiment)
Next, a third embodiment of the present invention will be described.

  FIG. 6 is a diagram showing an overall configuration of a semiconductor memory device according to the third embodiment of the present invention. Components common to those in FIG. 4 are denoted by the same reference numerals as in FIG.

  In FIG. 6, reference numeral 602 denotes a write / read circuit including a write buffer therein, 603 denotes a memory cell array containing a large number of resistance change type memory elements 103 in the row and column directions, and 604 denotes a sense amplifier block. 4 includes a sense amplifier 404, bit line and source line precharge circuits 402 and 406, bit line and source line write bias generation circuits 401 and 407, and a read bias circuit 405 shown in FIG. A plurality of sense amplifier blocks 406 are provided in the direction of the word line WL to form a sense amplifier row 605. The circuit operation of the sense amplifier block 604 has already been described. Reference numeral 601 denotes a reference potential generation circuit that generates a reference potential Vref and supplies it to the sense amplifier block 604.

  Hereinafter, a block configuration for operating the sense amplifier block 604 will be described. In FIG. 6, a write / read circuit 602 receives a read control signal RD, a write control signal WT, and input data D from the outside, and an output signal IDO from a sense amplifier block 604. The write / read circuit 602 outputs output data DO and senses set signals (ST, / ST) and reset signals (RST, / RST) based on the input write control signal WT and input data DI. Output to amplifier block 604 and supply. Among these set signals and reset signals, the signals ST, RST and the read control signal RD are supplied to a reference potential generation circuit 601. The reference potential generation circuit 601 generates a reference potential Vref based on these input signals. And supplied to the sense amplifier block 604.

  The reference potential generation circuit 601 will be described with reference to FIG. This reference potential generation circuit 601 is configured to generate a reference potential Vref for each set, reset, and read operation. The set generation circuit (set reference potential generation means) 601s, the reset generation circuit (reset reference potential generation) Means) 601r and a read generation circuit (read reference potential generation means) 601R. These generation circuits 601s to 601R have substantially the same configuration as that for forming a current path that flows through the resistance change memory element 403 at the time of data write setting, resetting, and reading. . That is, in the set generation circuit 601s, the Pch transistor 705 corresponds to the Pch transistor of the bit line write bias generation circuit 401 in FIG. 4, the Nch transistor 702 corresponds to the selection transistor Ts in the resistance change type memory element 403, The Nch transistor 703 corresponds to the Nch transistor of the source line write bias generation circuit 407, and a set signal (set command) ST is adopted as the selection signal. Similarly, in the reset generation circuit 601r, the Pch transistor 711 corresponds to the Pch transistor of the source line write bias generation circuit 407 in FIG. 4, and the Nch transistor 710 corresponds to the selection transistor Ts in the resistance change type memory element 403. The Nch transistor 709 corresponds to the Nch transistor of the bit line write bias generation circuit 401, and a reset signal (reset command) RST is adopted as the selection signal. In the read generation circuit 601R, the Pch transistor 701 corresponds to the Pch transistor of the bit line precharge circuit 402 in FIG. 4, the Nch transistor 702 corresponds to the selection transistor Ts in the resistance change memory element 403, and the Nch transistor 703. Corresponds to the Nch transistor of the read bias circuit 405, and a read control signal (read command) RD is adopted as the selection signal.

  With this configuration, the reference potential Vref at the time of setting, resetting, and reading is set to two resistance elements (Rc, Rd), (Re, Rf) and (Ra, Rb) can be generated by resistance division.

  Further, the potential of the bit line BL corresponding to the resistance value of the resistance change type memory element 403 is uniquely fixed to the reference potential at the time of reading, and the relative change between the data reading voltage and the writing voltage is utilized. When data writing and reading are performed, it is possible to use a reference potential generation circuit 601 ′ shown in FIG.

  In the reference potential generation circuit 601 ′ of FIG. 8, when one of the control signals ST and RST is input, the first P-channel transistor 801 is turned on via the NOR circuit (selection means) 803, and its source Is supplied to two voltage-dividing resistors Rg and Rh connected in series, and a potential obtained by the resistance division is output as a reference potential Vref. On the other hand, when it is not at the time of setting or resetting, that is, at the time of reading, the other P-channel transistor 802 is turned on, and reference at the time of reading is performed by dividing the two resistors Rg and Rh based on the precharge potential Vp. A potential Vref is generated.

  The above reference potential generation circuits 601 and 601 ′ may be arranged one by one for each bit line BL according to one data input, or one is shared and a transfer gate is provided by a selection signal. A predetermined operation may be performed to select a predetermined one of the plurality of bit lines BL.

  Next, FIG. 9 shows an example of the internal configuration of the writing / reading circuit (writing means) 602, and FIG. 13 and FIG. 14 show signal waveforms during the operation. In brief, the write / read circuit 602 is configured to stop the data write operation based on a change in the output signal of the sense amplifier during the amplification operation during the data write operation. This will be specifically described below.

  In the write / read circuit 602 of FIG. 9, reference numeral 901 denotes a read amplifier (read data output circuit), which receives the output signal IDO from the sense amplifier block 604 shown in FIG. 6 and outputs the output signal DO to the outside. To do. The output signal DO of the read amplifier 901 has a predetermined phase difference relationship with the output signal IDO from the sense amplifier block 604.

  Here, at the time of data writing, the sense amplifier (see reference numeral 404 in FIG. 4) in sense amplifier block 604 shown in FIG. 6 is activated at the same activation timing as that at the time of data reading as in the case of data reading. Thus, the sense amplifier enable signal SAE is received from the amplification control circuit (amplification control means) 606, and the amplification operation is always controlled during the data writing.

  The read amplifier 901 is activated by receiving the output signal of the delay adjustment circuit 902 that delays the read command RD or the write command WT as a read amplifier enable signal RAEN. Therefore, the read amplifier 901 is started after being delayed by the set delay time by the common delay adjustment circuit 902 in the write operation based on the write command WT and the read operation based on the read command RD. The start timing during the write operation is the same as the start timing during the read operation.

  The read amplifier enable signal RAEN from the delay adjustment circuit 902 is delayed for a predetermined time by another delay adjustment circuit 903. This delay time corresponds to a period longer than the period until the value of the output signal of the read amplifier 901 is determined by the read amplifier enable signal RAEN. During the period until the output of the delay adjustment circuit 903 is determined, the node A and the node B are precharged to the set voltage Vdd by the precharge circuit 905. This state is a state waiting for input of the write command WT.

  In FIG. 9, the decode circuit 906 includes two NAND circuits 906a and 906b, and decodes the set state and the reset state according to the input data DI and the write command WT. The set / reset command generation circuit 907 includes two NAND circuits 907a and 907b, and inputs according to the decode signal from the decode circuit 906 and the high (Vdd) precharge state of the node A and the node B. A set command SC or a reset command RC corresponding to the data DI is determined. The set command SC or reset command RC is level-shifted at the same time as the potential is inverted by the level shift circuit 908, and then the two complementary signals (ST, / ST) based on the commands SC and RC, (RST, / RST) is generated. As described above, when the resistance value of the resistance variable memory element 403 in FIG. 4 is changed by the two types of complementary signals, the output value of the sense amplifier 404 is changed. When the read amplifier enable signal RAEN is activated and the output signal DO of the read amplifier 901 having received the output signal IDO of the sense amplifier 404 is determined, the transfer gate 904 sets the output signal DO of the read amplifier 901 to a set / reset command. The set command SC or reset command RC generated in the set / reset command generation circuit 907 is stopped by propagating to the generation circuit 907.

  In the following, a specific description will be given using the signal waveform diagram of FIG. 13 until a set command SC is generated and thereafter the set command SC is automatically stopped. When the write command WT transits to High and the input data DI is at the Low level, the decode circuit 906 operates the complementary signal ST and the NAND circuit 906b on the / ST side to operate as a set command for the High signal. Is output. Since the node A is precharged to High (Vdd), the set / reset command generation circuit 907 operates the complementary signal ST and the NAND circuit 907b on the / ST side to generate the set command SC for the High signal. , The signal ST transits to a high output, and the signal / ST transits to a low output. This state is maintained until the read amplifier enable signal RAEN is activated. Thereafter, when the read amplifier enable signal RAEN is activated, the output signal DO of the read amplifier 901 is initially at a high level when the resistance change memory element 403 to which data is to be written is in the reset state. However, when the resistance change type memory element 403 to which data is to be written changes to the set state, it becomes the Low level. The low level output signal DO is propagated to the node A via the transfer gate 904, and the potential of the node A becomes low level. Therefore, the set / reset command generation circuit 907 causes the complementary signals ST, / ST side The output of the NAND circuit 907b changes from the High level to the Low level, and the output of the set command SC is stopped. When the resistance change type memory element 403 to which data is to be written is in the initial state and the set state, the output of the read amplifier 901 immediately becomes Low level when the read amplifier 901 is activated, so that the node A becomes Low level. Thus, the set command SC of the set / reset command generation circuit 907 is automatically stopped immediately.

  Next, with reference to the signal waveform diagram of FIG. 14, a description will be given of a process until a reset command RC is generated and thereafter the reset command RC is automatically stopped. When the write command WT transits to a high level and the input data DI is at a high level, the decode circuit 906 outputs a complementary signal RST and a decode result that becomes a reset command for the high signal by operating the NAND circuit 906a on the / RST side. To do. Since node B is precharged high (Vdd), the set / reset command generation circuit 907 operates the complementary signal RST, the NAND circuit 907a on the / RST side, and generates a reset command RC for the high signal. RST transitions to High output and signal / RST transitions to Low output. This state is maintained until the read amplifier enable signal RAEN is activated. Thereafter, when the read amplifier enable signal RAEN is activated, the output signal DO of the read amplifier 901 is initially at a low level when the resistance change memory element 403 to be written with data is in the initial state. However, when the resistance change type memory element 403 to which data is to be written changes to the reset state, it becomes a high level. The high level output signal DO is propagated to the node B through the transfer gate 904, and the potential of the node B becomes low level. Therefore, the set / reset command generation circuit 907 causes the complementary signals RST and / RST to The High output from the NAND circuit 907a changes to the Low output, and the reset command RC is stopped. When the resistance change type memory element 403 to which data is written is in the initial state and in the reset state, the output of the read amplifier 901 immediately becomes High level when the read amplifier 901 is activated, so that the node B becomes Low level. Thus, the reset command RC of the set / reset command generation circuit 907 is automatically stopped immediately.

  On the other hand, at the time of data reading, since the write command WT is at the low level, the outputs of the two NAND circuits 906a and 906b are at the low level in the decode circuit 906, and the set / reset command generation circuit 907 has two outputs. The outputs of the NAND circuits 907a and 907b are at a low level, and the set command SC and the reset command RC are not output.

  As described above, in this embodiment, the set command SC or the reset command RC is generated according to the input data DI and the write command WT to control the resistance change memory element 403 to the set or reset state, and the input data DI In addition, the reference potential Vref of the sense amplifier 404 in the sense amplifier block 604 is variably set in response to the write command WT, and the output of the sense amplifier 404 accompanying the transition to the set or reset state of the resistance change memory element 403. Since the set SC or the reset command RC is automatically stopped based on the output signal IDO after waiting for the change of the signal IDO, a semiconductor memory device capable of accurately adjusting the resistance of the resistance change type memory element 403 is configured. However, the set or reset command SC, RC Using conventional sense amplifier 404 and read amplifier 901 for reading data of the stop, can the configuration of a semiconductor memory device without preparing a special circuit individually easily, it is more possible in more Roukosuto of.

  Next, FIG. 3 shows a block diagram when the series of circuits described above is configured as a core.

  In the figure, a data input / output circuit 301 that performs data input / output, command input, and address signal input transfers an address signal to an address generation circuit 307, and the address generation circuit 307 further transfers the address signal to a row decoder circuit 305. Then, a selection signal for the word line WL is generated. The command input to the data input / output circuit 301 is transferred to the command generation circuit 306. The command generation circuit 306 reads the transferred command into the row decoder 305, sense amplifier 303, reference potential generation circuit 308, write / read. Transfer to circuit 302. Data input to the data input / output circuit 301 is transferred to the write / read circuit 302, amplified by the sense amplifier 303, and written to the memory cell array 304 having a large number of resistance change memory elements 403.

  In this embodiment, the sense amplifier 404 for data reading is also used as a sense amplifier that is always amplified during data writing. However, a sense amplifier dedicated to data writing may be provided separately.

  In the first to third embodiments, as the resistance change type memory element 403, the memory element body M connected to the bit line (column selection line) BL and the word line (row selection line) WL serve as gates. Although a configuration comprising a series circuit with a connected select transistor Ts is employed, the present invention is not limited to this, and in addition, a memory element is provided between one column selection line and one row selection line. Of course, a resistance change type memory element in which the main body M is connected directly or via a diode may be adopted.

  As described above, according to the present invention, the bias amplitude voltage applied to each terminal of the resistance change memory element is suppressed to a small value, and the precharge voltage applied to both ends of the resistance change memory element during standby is used as the read voltage. The negative potential generating circuit can be eliminated and the data reading speed can be increased, which is practically useful as a semiconductor memory device using a resistance change type memory element.

103, 403 Resistance change type memory element (memory cell)
301 Data Input / Output Circuit 302 Write / Read Circuit 303 Sense Amplifier Row 304 Memory Cell Array 305 Row Decoder Circuit 306 Command Generation Circuit 307 Address Generation Circuit 308 Reference Potential Generation Circuit 401 Bit Line Write Bias Generation Circuit
(First bias applying means)
402 Bit line precharge circuit
Read bias generation circuit 404 Sense amplifier 405 Read bias generation circuit 406 Source line precharge circuit 407 Source line write bias generation circuit
(Second bias applying means)
408, 603 Memory cell array 420 Precharge means 421 Bias application means 422 Read means 601 Reference potential generation circuit 601s Set generation circuit (set reference potential generation means)
601r Reset generation circuit
(Reset reference potential generation means)
601R Read generation circuit
(Reading reference potential generating means)
602 Write / read circuit (write means)
604 Sense amplifier block 605 Sense amplifier row 606 Amplification control circuit (amplification control means)
803 NOR circuit (selection means)
901 Read amplifier (read data output circuit)
902, 903 Delay adjustment circuit 904 Transfer gate 905 Precharge circuit 906 Decode circuit 907 Set / reset command generation circuit 908 Level shift circuit

Claims (8)

A resistance change memory element having a first node and a second node;
A first selection line connected to a first node of the resistance change type memory element;
A second selection line connected to a second node of the resistance change type memory element;
The resistance change type memory element is a semiconductor memory device that sets and resets data by applying forward and reverse bias voltages between the first and second nodes.
A sense amplifier that amplifies a potential difference between a set reference potential and a potential generated by a resistance value of the resistance change type memory element;
Amplification control means for amplifying the sense amplifier;
Write means for starting data setting or resetting operation to the resistance change type memory element, receiving an output signal of the sense amplifier, and stopping the data setting and resetting operation according to the received output signal; A semiconductor memory device comprising: 2. The semiconductor memory device according to claim 1, wherein
The sense amplifier is also used as a data read sense amplifier for use in data read.
Further, the set reference potential for setting, resetting, and data reading are generated separately for the set reference potential for data writing, the reference potential for resetting, and the reference potential for data reading. A semiconductor memory device comprising a generation unit. 3. The semiconductor memory device according to claim 2, wherein
The writing means includes
The semiconductor memory device, wherein the data set and reset operations are stopped according to an output signal of the data read sense amplifier. 3. The semiconductor memory device according to claim 2, wherein
A read data output circuit for outputting an output signal of the data read sense amplifier to the outside;
The writing means receives an output signal of the data read sense amplifier via the read data output circuit,
The semiconductor memory device, wherein the data read sense amplifier and the read data output circuit are activated at the same timing as the data read operation at the time of data write setting and reset. 3. The semiconductor memory device according to claim 2, wherein
The three reference potential generation means for data write setting, resetting, and data reading are:
At the time of data writing set, at the time of resetting and at the time of data reading, the current path has the same current path as the current flowing through the resistance change type memory element to be written or read, and a plurality of voltage dividing voltages are provided in the current path. A semiconductor memory device comprising: a resistance element, and selected based on a set command, a reset command, and a read command. 2. The semiconductor memory device according to claim 1, wherein
A reference potential generating circuit for generating the set reference potential;
A first P-channel transistor having a source connected to a power supply used for data writing;
A second P-channel transistor having a source connected to a power supply used for data reading;
A plurality of voltage dividing resistor elements connected in common to the first and second P-channel transistors;
A semiconductor memory device comprising: selection means for selecting one of the first and second P-channel transistors. 2. The semiconductor memory device according to claim 1, wherein
The amplification control means always amplifies the sense amplifier in the first state,
In the second state, the writing means starts a data setting or resetting operation to the resistance change type memory element, receives an output signal of the sense amplifier, and receives the data according to the received output signal. A semiconductor memory device characterized by stopping the set and reset operations. 8. The semiconductor memory device according to claim 7, wherein
The semiconductor memory device, wherein the first state is when data is written, and the second state is when data writing is set or reset.

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