JP5267623B2 - Nonvolatile memory cell and nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory cell capable of performing storage and recalling between a volatile storage section and a nonvolatile storage section without damaging a static noise margin. <P>SOLUTION: A nonvolatile storage section 12 has an N channel transistor Tw1 and a resistance change type element R1 inserted in series between a node V1 of a volatile storage section 11 and a bias supply node NS, and an N channel transistor Tw2 and a resistance change type element R2 inserted in series between a node V2 of the volatile storage section 11 and the bias supply node NS. During storing, the N channel transistors Tw1 and Tw2 are turned on, and the resistance change type elements R1 and R2 are a high resistance when current flowing from the node V1(V2) toward the bias supply node NS is made to pass through, and are a low resistance when current in a reverse direction is made to pass through. During recalling, a power source voltage to a flip-flop of the volatile storage section 11 is started. <P>COPYRIGHT: (C)2013,JPO&amp;INPIT

Description

  The present invention relates to a nonvolatile memory cell using a resistance change element and a nonvolatile memory memory including the nonvolatile memory cell.

  In recent years, a resistance change type memory for storing data using a resistance change type element has attracted attention as a next-generation non-volatile memory in place of a flash memory or a DRAM that has become limited in miniaturization. Examples of the resistance change element include MRAM (Magnetoretic Random Access Memory), PRAM (Phase change Random Access Memory), ReRAM (Resistance Random Access Memory). The thing that is. A memory using such a resistance variable element does not require a complicated process like a flash memory, is compatible with a standard logic process, is suitable for miniaturization, and operates at a low voltage. The future is promising.

  The element configuration, characteristics, and array configuration of a memory using this type of variable resistance element are disclosed in Non-Patent Document 1, for example. This non-patent document 1 relates to an MRAM, but discloses a memory cell having a simple configuration including one transistor and one resistance variable element. According to Non-Patent Document 1, this memory cell can be written and read at a low voltage of 1.2 V, the write current is 49 μA, and the memory cell from the high resistance state in which data “1” is stored. The read current is 10 μA, and the read current from the memory cell in the low resistance state in which data “0” is stored is 15 μA. Thus, low power consumption can be realized. Further, according to FIG. 1 of Non-Patent Document 1, it is likely that the write voltage to the memory cell can be lowered to about ± 0.6V.

  FIGS. 21A and 21B are diagrams showing the configuration and operation of a memory cell using a typical MTJ (Magnetic Tunnel Junction) element as a resistance variable element. As shown in FIG. 21, the MTJ element is composed of a pinned layer having a constant magnetic direction, a tunnel barrier film, and a free layer whose magnetic direction changes. As shown in FIG. 21A, when a current in the direction from the free layer to the pinned layer is passed, the magnetization direction of the free layer becomes the same as that of the pinned layer, the MTJ element becomes low resistance, and data “0” is stored. It becomes a state. On the other hand, as shown in FIG. 21B, when a current in the direction from the pinned layer toward the free layer is passed, the magnetization direction of the free layer is opposite to that of the pinned layer, the MTJ element becomes high resistance, and data “1” "Is stored. When a memory cell is configured with such an MTJ element, a transistor Ts is connected in series with the MTJ element as a switch for selecting the MTJ element, as illustrated in FIGS. .

  FIG. 22 is a diagram illustrating a cross-sectional structure of a memory array including memory cells as shown in FIGS. 21 (a) and 21 (b). In the example shown in FIG. 22, the selection transistor Ts shown in FIGS. 21A and 21B is formed on the semiconductor substrate. A selection voltage WL is applied to the gate of each transistor Ts. The source of the transistor Ts is connected to the second layer metal wiring 2M for supplying the write voltage BL via the through hole and the first layer metal wiring 1M. The drain of the transistor Ts is connected to the pin layer of the MTJ element through a through hole, and the free layer of the MTJ element is connected to the second layer metal wiring 2M for supplying the source voltage SL through the through hole. Has been.

  Patent Document 1 discloses a rewritable nonvolatile RAM using a resistance variable element. In the nonvolatile RAM of Patent Document 1, a phase change memory element is used as a resistance change element.

  FIG. 23 is a circuit diagram showing a configuration of the memory cell of the nonvolatile RAM disclosed in FIG. In FIG. 23, a flip-flop is constituted by an inverter composed of a P-channel transistor P0 and an N-channel transistor N0 and an inverter composed of a P-channel transistor P1 and an N-channel transistor N1. An output node S0 of the inverter composed of the P channel transistor P0 and the N channel transistor N0 is connected to the bit line BL0 via the N channel transistor Na0. The output node S1 of the inverter composed of the P channel transistor P1 and the N channel transistor N1 is connected to the bit line BL1 via the N channel transistor Na1. The selection voltage WL is applied to the N channel transistors Na0 and Na1. The above circuit is a normal SRAM memory cell. In the memory cell shown in FIG. 23, phase change memory elements Rr and Rm and an N-channel transistor Ns are added to the SRAM memory cell. Here, phase change memory element Rr is interposed between the source of P channel transistor P0 and power supply line PWR, and phase change memory element Rm is interposed between the source of P channel transistor P1 and power supply line PWR. N-channel transistor Ns is interposed between the connection point of P-channel transistor P1 and phase change memory element Rm and store line STR, and the voltage of node S0 is applied to its gate.

  According to Patent Document 1, one of the phase change memory elements (Rr) is a reference (reference) resistance, and the other one of the phase change memory (logic storage resistance Rm) changes with a high resistance (logic value 1) and a low resistance. A resistance value between (logical value 0) is set in advance. The logic memory resistor Rm is applied with a current causing a phase change by the power supply line PWR, the switching element (transistor Ns), and the store line STR. At the time of reading, the SRAM circuit portion indicated by the dotted line is operated as a normal SRAM. The logical storage resistance Rm during this operation is set to a low resistance value. Then, before the power is turned off, the voltage of the store line STR is changed, and a current is passed through the logic storage resistor Rm by the transistor Ns, thereby transferring the logic value stored in the SRAM circuit portion (store). When the power is turned on, the stored contents transferred to the phase change memory element Rm are returned to the SRAM circuit section (recall). As described above, when the power is turned off (OFF) and turned on (ON), the memory contents are transferred and returned by the logical storage resistor Rm of the phase change memory and the SRAM circuit unit, thereby operating as a nonvolatile memory. (See paragraphs 0012 and 0013 of Patent Document 1).

Japanese Patent No. 3845734

IEICE IEICE technical report ICEC Technical Report ICD2010-7 p35-p40

The nonvolatile RAM of Patent Document 1 described above has several problems. First, in the nonvolatile RAM of Patent Document 1, a phase change memory element is used as a resistance change type element. This phase change memory element is a so-called monopolar type resistance change element, and data “1” is stored. It is necessary to pass current in the same direction when writing data or when writing data “0”. This complicates the control for writing data. In addition, the phase change memory element cannot be rewritten at high speed because the write characteristic and the erase characteristic are greatly different. Further, as shown in FIG. 23, in the nonvolatile RAM of Patent Document 1, phase change memory elements (Rr and Rm) whose resistance values change are inserted on the power supply current paths of two inverters constituting the flip-flop. Has been. For this reason, the flip-flop becomes unbalanced, and has a great adverse effect on the SNM (Static Noise Margin), which is the most important characteristic of the SRAM.
Hereinafter, this adverse effect on the SNM will be described.

  FIG. 24 is a circuit diagram showing a configuration of a general SRAM memory cell. In the illustrated example, one memory cell is constituted by P-channel transistors P1 and P2 and N-channel transistors N1, N2, Ta1, and Ta2.

  25A to 25D illustrate the SNM characteristics of the memory cell shown in FIG. In FIGS. 25A to 25D, the horizontal axis represents the voltage V0 at the common connection point of the transistors P1 and N1, and the vertical axis represents the voltage V1 at the common connection point of the transistors P2 and N2.

  In FIGS. 25A to 25D, the dashed curve and the solid curve are each called a butterfly curve. These two butterfly curves cross each other on the way, and the positional relationship between the top and bottom and the left and right is switched. In each of FIGS. 25A to 25D, two squares are drawn that fit in two regions sandwiched between a broken butterfly curve and a solid butterfly curve. The size of this square is the size of the SNM. More specifically, the square between the two butterfly curves in the region where the broken butterfly curve is at the upper right and the solid butterfly curve is at the lower left is a noise that increases the voltage V0 at the connection point of the drains of the transistors P1 and N1. When this occurs, it is an SNM (hereinafter referred to as a first SNM for convenience) indicating an allowable value of the noise level that does not invert the stored contents of the memory cell. The square between the two butterfly curves in the region where the solid butterfly curve is at the upper right and the broken butterfly curve is at the lower left is when noise that raises the voltage V1 at the connection point of the drains of the transistors P2 and N2 occurs. , An SNM (hereinafter referred to as a second SNM for convenience) indicating an allowable value of the noise level that does not invert the stored contents of the memory cell.

  FIGS. 25A and 25C illustrate SNM characteristics when the power supply voltage VDD of the SRAM is 1.0 V, respectively. In the example shown in FIG. 25 (a), the beta value β and the threshold voltage Vt of each transistor constituting the memory cell are balanced, the first SNM and the second SNM are approximately the same, and Is also large enough. Therefore, in this memory cell, stable write access and read access are possible.

  However, the butterfly curve depends on the balance of the beta values and the threshold voltage of each of the transistors P1, N1, P2, and N2. For example, in FIG. 25A, when the beta ratio βp / βn between the beta value βp of the transistor P2 and the beta value βn of the transistor N2 increases, the broken butterfly curve protrudes in the upper right direction. Conversely, when the beta ratio βp / βn decreases, the broken butterfly curve retreats in the lower left direction. Further, when the threshold voltage Vtn of the transistor N2 increases and the threshold voltage Vtp of the transistor P2 decreases, the voltage V0 at which the broken butterfly curve suddenly falls increases. Conversely, when the threshold voltage Vtn of the transistor N2 decreases and the threshold voltage Vtp of the transistor P2 increases, the voltage V0 at which the broken butterfly curve suddenly falls decreases.

  Further, in the process of increasing the voltage V0 from 0V to VDD, when the transistor N2 is turned on, a current flows into the transistor N2 via the transistor Ta2. Therefore, the voltage V1 does not fall down to the VSS level (0V), but the VSS level. Float from. If the current flowing through the transistor Ta2 is constant, the floating of the voltage V1 from the VSS level at this time increases as the threshold voltage Vtn of the transistor N2 is higher or the beta value βn of the transistor N2 is lower.

  Thus, the broken butterfly curve is affected by changes in threshold voltages and beta values of the transistors P2 and N2. On the other hand, the solid butterfly curve is mainly affected by changes in the balance of the beta values and the balance of the threshold voltages of the transistors P1 and N1. Thus, since the butterfly curve is affected by changes in the threshold voltage and beta value of each transistor, the first and second SNMs are also affected by changes in the threshold voltage and beta value of each transistor.

  In the example shown in FIG. 25C, an imbalance occurs between the threshold voltage Vt or the beta value of each transistor constituting the memory cell, and the first SNM is sufficiently large, but the second SNM Is slightly smaller.

  As described above, when the characteristics (specifically, the threshold voltage VT and the beta value) of the transistors constituting the memory cell vary, the sizes of the first and second SNMs vary.

  Further, when the power supply voltage VDD of the SRAM is reduced, the degree of influence on the first and second SNMs of the characteristic variation of each transistor constituting the memory cell is increased. FIGS. 25B and 25D show examples thereof. In the examples of FIGS. 25B and 25D, the power supply voltage VDD of the SRAM is 0.5V. In the example shown in FIG. 25B, since the power supply voltage VDD is 0.5 V, the first and second SNMs are considerably small, but the characteristics of the respective transistors constituting the memory cell are balanced. Therefore, the first and second SNMs are sized to enable normal write access and read access. However, in the example shown in FIG. 25 (d), there is a delicate imbalance in the characteristics of the transistors constituting the memory cell, and the second SNM is almost eliminated due to the influence. As described above, when the operation margin is insufficient, the write access and the read access are hindered.

  When an imbalance occurs in the characteristics of the transistors constituting the memory cell in this way, the SNM of the SRAM is adversely affected, particularly when the power supply voltage VDD is low.

  However, in the technique of Patent Document 1, phase change memory elements whose resistance values change are respectively inserted in power supply current paths of two inverters constituting such SRAM memory cells. When such a phase change memory element is inserted, an unbalance occurs in the bias condition between the transistors P0 and N0 constituting one inverter and the transistors P1 and N1 (see FIG. 23) constituting the other inverter. As a result, the characteristics of the transistors constituting each inverter are unbalanced, and the SNM of the memory cell is greatly deteriorated. The above is the analysis of the static operation of the SRAM. In addition, considering the dynamic operation, the gate capacitance of the transistor Ns is added to the node S0, and the capacitance is unbalanced between the node S0 and the node S1. This capacity imbalance reduces the dynamic operating margin.

  The present invention has been made in view of the circumstances described above, and a first object thereof is to rewrite the stored data in the volatile storage unit and to store the stored data in the nonvolatile storage unit without impairing the function as the SRAM. It is an object of the present invention to provide a non-volatile memory cell and a non-volatile memory that can easily perform a store operation for writing data and a recall operation for writing data from a non-volatile storage unit to a volatile storage unit. A second object of the present invention is to provide a non-volatile memory cell and a non-volatile memory that are resistant to variations in characteristics of elements constituting the cell. A third object of the present invention is to provide a nonvolatile memory cell and a nonvolatile memory that can operate at high speed with a small number of elements (small area).

  The present invention includes a volatile storage unit and a nonvolatile storage unit, and the volatile storage unit includes a flip-flop composed of first and second inverters each having an output signal of the other party as an input signal, When data is written to the flip-flop via the two bit lines inserted between the output nodes of the first and second inverters and the two bit lines, or the flip-flop First and second switches that are turned on when data is read from the two bit lines through the two bit lines, and the non-volatile storage unit includes an output node and a bias of the first inverter. A third switch and a first variable resistance element inserted in series with the supply node; and between an output node of the second inverter and the bias supply node. A fourth switch and a second variable resistance element interposed in a column, and each of the first and second variable resistance elements is connected to an output node of the first or second inverter. The resistance value changes in a first direction when a current directed to the bias supply node is passed, and when a current directed from the bias supply node to the output node of the first or second inverter is passed. A nonvolatile memory cell is provided that is a variable resistance element whose resistance value changes in a second direction opposite to the first direction.

  According to this invention, the first and second switches are turned OFF, the third and fourth switches are turned ON, and an intermediate between two kinds of voltages for expressing data “1” / “0” at the bias supply node. Is applied to the first and second resistance change-type elements, and currents corresponding to the data stored in the volatile storage section are supplied to the first and second resistance change-type elements. Each resistance value of the element can be changed in opposite directions (store operation). In this case, the magnitude relationship between the resistance values of the first and second variable resistance elements represents the data stored in the nonvolatile storage unit.

  Further, the first and second switches are turned OFF, the third and fourth switches are turned ON, and a predetermined voltage (for example, 0 V) is applied to the bias supply node to raise the power supply voltage for the flip-flop of the volatile memory portion. Between the current to the output node of the first inverter of the volatile storage unit and the current to the output node of the second inverter, the storage data of each of the first and second resistance change elements A difference in accordance with the magnitude relationship of the resistance value) is generated, and the storage data of the nonvolatile storage unit can be written into the volatile storage unit (recall operation).

  If the third and fourth switches are turned OFF, the first and second resistance change elements can be disconnected from the volatile storage unit, and the volatile storage unit can be operated as a normal SRAM memory cell. . In this case, a high SNM can be obtained because the volatile storage unit is not connected to any extra circuit or parasitic capacitance that impairs its function.

  Therefore, according to the present invention, the data stored in the volatile storage unit is rewritten, the stored data is written in the nonvolatile storage unit, and the data is transferred from the nonvolatile storage unit to the volatile storage unit without impairing the function as the SRAM. It is possible to realize a nonvolatile memory cell and a nonvolatile memory that can easily perform a recall operation for writing. In the present invention, in the nonvolatile memory unit, the magnitude relationship between the resistance values of the two resistance variable elements indicates stored data. At the time of storing, currents in opposite directions are passed through the first and second resistance variable elements, and the resistance values of the first and second resistance variable elements are changed in opposite directions. Therefore, even when the characteristic variation of the resistance variable element is large, the magnitude relationship between the resistance values of the first and second resistance variable elements at the time of storing is set to a magnitude relation corresponding to the storage data of the volatile storage unit. Can do. Therefore, according to the present invention, it is possible to realize a nonvolatile memory cell and a nonvolatile memory that are resistant to variations in characteristics of elements constituting the cell.

  In a preferred embodiment, an MTJ element or a resistance element that generates an electric field induced giant resistance change is used as the resistance change element. According to this aspect, store and recall can be performed at high speed.

  In another preferred aspect, the nonvolatile memory includes a booster circuit that boosts and outputs a power supply voltage. During a store operation, the output voltage of the booster circuit is supplied to the flip-flop power supply voltage, the third and fourth switches. Used as an activation voltage for turning on. Therefore, the power supply voltage for the non-volatile memory can be set to a minimum voltage at which the SRAM can be operated.

  In addition, according to the present invention, the number of elements of the nonvolatile memory portion provided in the nonvolatile memory cell is small, and the current flowing through the resistance variable element at the time of storing and recalling is small, so the area is small and inexpensive. A non-volatile memory chip can be realized.

1 is a circuit diagram showing a configuration of a nonvolatile memory cell according to a first embodiment of the present invention. FIG. FIG. 3 is a diagram showing a first operating condition of the nonvolatile memory cell. It is a figure which shows the 2nd operating condition of the non-volatile memory cell. It is a figure which shows the 3rd operating condition of the non-volatile memory cell. It is a block diagram which shows the structure of the non-volatile RAM which is 2nd Embodiment of this invention. It is a circuit diagram which shows the specific structural example of the non-volatile RAM. It is a block diagram which shows the structural example of the power supply control circuit of the non-volatile RAM. It is a time chart which shows operation | movement of the store of the non-volatile RAM. It is a time chart which shows the operation | movement of recall of the non-volatile RAM. It is a circuit diagram which shows the structural example of the row selection circuit suitable for the non-volatile RAM. It is a circuit diagram which shows the structure of the non-volatile memory cell which is 3rd Embodiment of this invention. It is a figure which shows the operating condition of the non-volatile memory cell. It is a circuit diagram which shows the structure of the non-volatile RAM which is 4th Embodiment of this invention. It is a time chart which shows the operation | movement at the time of recall of the non-volatile RAM. It is a circuit diagram which shows the structural example of the row selection circuit suitable for the non-volatile RAM. It is a circuit diagram which shows the structure of the non-volatile memory cell which is 5th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile RAM which is 6th Embodiment of this invention. It is a circuit diagram which shows the structural example of the row selection circuit suitable for the non-volatile RAM. It is a circuit diagram which shows the structure of the non-volatile memory cell which is 7th Embodiment of this invention. It is a circuit diagram which shows the structural example of the row selection circuit suitable for the non-volatile RAM which is 8th Embodiment of this invention. It is a figure which shows the structure and operation | movement of an MTJ element. It is a figure which illustrates the cross-sectional structure of the memory cell using an MTJ element. It is a circuit diagram which shows the structural example of the conventional non-volatile memory cell. 1 is a circuit diagram showing a configuration of a general SRAM memory cell; FIG. It is a figure which illustrates the static noise margin of the memory cell.

  Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the transistor refers to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor; field-effect transistor having a metal-oxide film-semiconductor structure).

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a nonvolatile memory cell 10 according to the first embodiment of the present invention. The nonvolatile memory cell 10 includes a volatile storage unit 11 and a nonvolatile storage unit 12. The volatile storage unit 11 has a configuration similar to that used as a memory cell in a normal SRAM. More specifically, the volatile storage unit 11 includes an inverter INV1 composed of a P-channel transistor P1 and an N-channel transistor N1, an inverter INV2 composed of a P-channel transistor P2 and an N-channel transistor N2, and an N-channel as a transfer gate. Transistors Ta1 and Ta2 are included. Here, the inverters INV1 and INV2 use the output signals of the other party as input signals for each other, and constitute a flip-flop. This flip-flop is interposed between a power supply line for supplying the high potential side power supply voltage VDC and a power supply line for supplying the low potential side power supply voltage VSS. The N channel transistor Ta1 is interposed between the output node V1 of the inverter INV1 and the bit line BL. The N-channel transistor Ta2 is interposed between the output node V2 of the inverter INV2 and the bit line BLB. These N-channel transistors Ta1 and Ta2 are turned on when the row selection voltage WL becomes an active level. As a result, data can be written to the flip-flop of the volatile storage unit 11 via the bit lines BL and BLB, and data can be read from the flip-flop of the volatile storage unit 11 to the bit lines BL and BLB.

  The nonvolatile memory unit 12 includes N-channel transistors Tw1 and Tw2 as switches and resistance change elements R1 and R2. Here, the drain of the N-channel transistor Tw1 is connected to the output node of the inverter INV1, and the source is connected to one end of the resistance variable element R1. The N-channel transistor Tw2 has a drain connected to the output node of the inverter INV2, and a source connected to one end of the resistance variable element R2. Activation signal WRE is applied to the gates of N channel transistors Tw1 and Tw2. The other ends of the variable resistance elements R1 and R2 are connected in common, and this common connection point is a bias supply node NS for supplying the source voltage SL.

  Each of the resistance variable elements R1 and R2 has a resistance value when the current from the output node of the inverter INV1 (INV2) to the bias supply node NS is passed while the N-channel transistors Tw1 and Tw2 are ON. 1 direction (for example, increasing direction), and a second direction (for example, decreasing direction) opposite to the first direction when current flowing from the bias supply node NS toward the output node of the inverter INV1 (INV2) is passed. ) Is a resistance change element whose resistance value changes. In the nonvolatile memory unit 12, the magnitude relationship between the resistance variable elements R1 and R2 represents “1” / “0” of the stored data.

  As an example, the resistance variable elements R1 and R2 are spin injection MTJ elements. Here, when the resistance variable elements R1 and R2 are spin injection MTJ elements, the pin layer of the spin injection MTJ element, which is the resistance variable element R1, is the source of the N-channel transistor Tw1, and the free layer is the bias supply node. The pin layer of the spin injection MTJ element, which is the resistance variable element R2, is connected to the source of the N-channel transistor Tw2, and the free layer is connected to the bias supply node. By doing so, the resistance change characteristics of the resistance change elements R1 and R2 as described above can be obtained.

  Alternatively, CER (Corrosive Electro-Resistance) resistance elements used in ReRAM memory cells may be used as the resistance change elements R1 and R2.

  In the present embodiment, a store for writing data stored in the volatile storage unit 11 to the nonvolatile storage unit 12 and a recall for writing the data stored in the nonvolatile storage unit 12 to the volatile storage unit 11 are possible. In this embodiment, in order to perform the store and recall, the N-channel transistors Tw1 and Tw2 are turned on by the activation signal WRE at an appropriate level, and the resistance variable elements R1 and R2 are connected to the inverter INV1 of the volatile storage unit 11. Output node V1 and inverter INV2 output node V2. At this time, the source voltage SL for the bias supply node NS is controlled to a level suitable for store and recall operations.

  FIG. 2 shows operating conditions when the nonvolatile memory cell 10 is operated with a power supply voltage of 1.2V. Hereinafter, the operation of the present embodiment will be described with reference to FIG. In the example shown in FIG. 2, the high potential side power supply voltage VDC is 1.2V, and the low potential side power supply voltage VSS is 0V. When the nonvolatile memory cell 10 is operated as a normal SRAM memory cell, the activation signal WRE is set to 0V. As a result, the N-channel transistors Tw1 and Tw2 are turned off, and the resistance variable elements R1 and R2 are disconnected from the volatile storage unit 11. In this state, the volatile storage unit 11 can be accessed via the bit lines BL and BLB.

  FIG. 2 shows operating conditions for reading data from the volatile storage unit 11. In order to read data from the volatile storage unit 11, the row selection voltage WL is set to 1.2 V, and the N-channel transistors Ta1 and Ta2 are turned on. When data “1” is stored in the volatile storage unit 11, the voltage 1.2V of the output node V1 of the inverter INV1 is the bit line BL, and the voltage of about 0V of the output node V2 of the inverter INV2 is the bit. Read to line BLB. When data “0” is stored in the volatile storage unit 11, the voltage of about 0 V at the output node V1 of the inverter INV1 is set to the bit line BL, and the voltage of 1.2 V at the output node V2 of the inverter INV2 is set to Read to line BLB. Although not shown, when data is written to the volatile storage unit 11, voltages corresponding to write data are applied from the bit lines BL and BLB to the output node V1 of the inverter INV1 and the output node V2 of the inverter INV2. Each is applied, and write data is held in a flip-flop formed of inverters INV1 and INV2.

  When the power of the nonvolatile memory cell 10 is turned off, a store for transferring the data stored in the volatile storage unit 11 to the nonvolatile storage unit 12 is performed prior to the power-off. In the example shown in FIG. 2, the row selection voltage WL is 0V, the activation signal WRE is 1.5V, and the source voltage SL is 0.6V. Here, the activation signal WRE of 1.5V is generated by boosting the power supply voltage of 1.2V, and the source voltage SL of 0.6V is generated by stepping down the power supply voltage.

  The reason why the activation signal WRE is set to 1.5 V is as follows. First, if the activation signal WRE is set to 1.2 V, which is the same as the power supply voltage, the maximum value of the voltage that can be applied from the volatile storage unit 11 to the resistance variable elements R1 and R2 is the activation signal WRE = 1.2V. To a voltage reduced by the threshold value of the N-channel transistors Tw1 and Tw2. Such a decrease in the voltage applied to the resistance variable elements R1 and R2 is not preferable because it prevents reliable data writing. In addition, it is necessary to reduce the resistances of the N-channel transistors Tw1 and Tw2 so that the current flowing through the resistance variable elements R1 and R2 has a sufficient current value that causes a change in the resistance value. Therefore, the activation signal WRE is set to 1.5V higher than the power supply voltage 1.2V.

  The source voltage SL is set to 0.6 V which is an intermediate voltage between two kinds of voltages (ie, 1.2 V and 0 V) used for expressing the data “1” / “0” in the volatile storage unit 11. ing. In a state where data “1” is stored in the volatile storage unit 11, the voltage of the output node V1 of the inverter INV1 is 1.2V, and the voltage of the output node V2 of the inverter INV2 is 0V. In this state, when the source voltage SL is 0.6 V, a voltage of 0.6 V in the direction from the output node V1 of the inverter INV1 to the bias supply node NS is applied to the resistance variable element R1, and a current in the same direction is It flows to the variable element R1. As a result, the resistance value of the resistance variable element R1 increases. Further, a voltage of 0.6 V in the direction from the bias supply node NS toward the output node V2 of the inverter INV2 is applied to the resistance variable element R2, and a current in the same direction flows through the resistance variable element R2. As a result, the resistance value of the resistance variable element R2 decreases. As described above, by storing the data “1”, the resistance variable element R1 of the nonvolatile memory unit 12 becomes high resistance and the resistance variable element R2 becomes low resistance.

  On the other hand, in a state where data “0” is stored in the volatile storage unit 11, the voltage of the output node V1 of the inverter INV1 is 0V, and the voltage of the output node V2 of the inverter INV2 is 1.2V. In this state, when the source voltage SL is 0.6 V, a voltage in the opposite direction to the case of storing data “1” is applied to the resistance variable elements R1 and R2. Therefore, storing the data “0” causes the resistance variable element R1 of the nonvolatile memory unit 12 to have a low resistance and the resistance variable element R2 to have a high resistance.

  When the MTJ element of Non-Patent Document 1 is used as the resistance variable elements R1 and R2, if the applied voltage to the resistance variable element can be secured to 0.6 V or more, the store can be performed, and the current flows to the resistance variable element at that time. The current is 49 μA.

  Next, a recall operation for writing data stored in the nonvolatile storage unit 12 to the volatile storage unit 11 will be described. In the recall operation, the row selection voltage WL is set to 0 V, and the bit lines BL and BLB are set to open (that is, the bit lines are disconnected from the flip-flops). Further, the activation signal WRE is set to 0.5 V, the N-channel transistors Tw1 and Tw2 are turned on, and the resistance variable elements R1 and R2 are connected to the output node V1 of the inverter INV1 and the output node V2 of the inverter INV2, respectively. Connect each one. In the recall operation, the source voltage SL is set to 0V. Here, the activation signal WRE is set to 0.5 V in order to limit the current flowing through the resistance variable elements R1 and R2 during the recall operation to reduce power consumption and to prevent erroneous writing. This is to prevent an excessive voltage from being applied to the mold elements R1 and R2.

  In the recall operation, the high-potential-side power supply voltage VDC for the nonvolatile memory cell 10 is increased from 0 V to 1.2 V while maintaining the activation signal WRE at 0.5 V and the source voltage SL at 0 V.

  When the nonvolatile storage unit 12 stores data “1”, the resistance variable element R1 has a high resistance and the resistance variable element R2 has a low resistance. In this state, when the high-potential-side power supply voltage VDC rises from 0 V to 1.2 V, the current flowing from the output node V1 of the inverter INV1 toward the bias supply node NS is changed from the output node V2 of the inverter INV2 to the bias supply node NS. Since the current flowing in the direction becomes larger, the voltage at the output node V1 becomes higher than the voltage at the output node V2. As a result, in the volatile storage unit 11, the output node V1 of the inverter INV1 is at the high level and the output node V2 of the inverter INV2 is at the low level, and this state is maintained. That is, the data “1” is stored in the volatile storage unit 11 and the recall of the data “1” is completed. At this time, if the MTJ element of Non-Patent Document 1 is used, the currents flowing through the resistance variable elements R1 and R2 are about 10 μA and 15 μA, respectively.

  On the other hand, when the nonvolatile storage unit 12 stores data “0”, the resistance variable element R1 has a low resistance and the resistance variable element R2 has a high resistance. In this case, if the high potential side power supply voltage VDC is raised from 0 V to 1.2 V in order to perform the recall, the output node V2 of the inverter INV2 is more than the current flowing from the output node V1 of the inverter INV1 toward the bias supply node NS. Since the current flowing from the first to the bias supply node NS becomes smaller, the voltage at the output node V2 becomes higher than the voltage at the output node V1. As a result, the volatile storage unit 11 maintains the state in which the output node V1 of the inverter INV1 is at the low level and the output node V2 of the inverter INV2 is at the high level. That is, the data “0” is stored in the volatile storage unit 11 and the recall of the data “0” is completed.

  When the recall is completed, the activation signal WRE is set to 0 V, and the resistance variable elements R1 and R2 are disconnected from the volatile storage unit 11. Thereby, the operation as the SRAM is started. In this state, the volatile storage unit 11 has the same configuration as that of a 6Tr configuration SRAM memory cell having complete symmetry, and thus a wide SNM can be obtained.

  FIG. 3 shows operating conditions when the nonvolatile memory cell 10 is operated at an extremely low power supply voltage of 0.5V. When the nonvolatile memory cell 10 is operated as a normal SRAM memory cell, the high-potential-side power supply voltage VDC for the nonvolatile memory cell 10 may be set to 0.5V. However, when storing, the high potential side power supply voltage VDC for the nonvolatile memory cell 10 is set to 1.2V, the activation signal WRE is set to 1.5V, and the source voltage SL is set to 0.6V. In this case, since the power supply voltage for the memory chip on which the nonvolatile memory cell 10 is mounted is 0.5 V, the high-potential-side power supply voltage VDC, the activation signal WRE, and the source voltage SL are generated by boosting this power supply voltage. To do. The store operation is the same as in FIG.

  Next, the recall operation will be described. In the recall operation, the source voltage SL is set to 0V, and the activation signal WRE is set to 0.3V. The activation signal WRE is set to 0.3 V because the power supply voltage of the memory chip is as low as 0.5 V and the target is ultra-low power consumption, so that the current consumption of the resistance variable elements R1 and R2 is reduced as much as possible. is there. However, there is no problem in operation even if the activation signal WRE at the time of recall is set to 0.5 V as shown in FIG.

  Next, in this state, the high potential side power supply voltage VDC is raised from 0V to 0.5V. Here, when the nonvolatile storage unit 12 stores data “1”, since the resistance variable element R1 has a high resistance and the resistance variable element R2 has a low resistance, the output is the same as in FIG. The node V1 becomes High, the output node V2 becomes Low, and the data “1” is held in the volatile storage unit 11. The operation in the case where the nonvolatile storage unit 12 stores data “0” at the time of recall is the same.

  When this recall is completed, the activation signal WRE is set to 0 V, and the resistance variable elements R1 and R2 are separated from the volatile storage unit 11. Thus, the volatile memory unit 11 operates as a normal SRAM memory cell in response to the supply of the power supply voltage VDC = 0.5V.

  FIG. 4 shows the operating conditions of the operation effective for reducing the current consumption during the recall. The difference from FIG. 2 is that the source voltage SL is raised from 0V to 0.3V at the time of recall. By raising the source voltage SL in this way, the current flowing through the resistance variable elements R1 and R2 during the recall can be suppressed, and the power consumption can be reduced.

Second Embodiment
FIG. 5 is a block diagram showing an overall configuration of a nonvolatile RAM according to the second embodiment of the present invention. In FIG. 5, a nonvolatile RAM cell array 100 is a cell array in which the nonvolatile memory cells 10 of the first embodiment are arranged in a matrix. In this example, the memory capacity of the nonvolatile RAM cell array 100 is 64M bits (4M × 16 bits).

  The control circuit 900 is a circuit that controls each part in the nonvolatile RAM in accordance with a chip enable signal CEB, a write permission signal WEB, an output permission signal OEB, and an activation instruction signal WRED given from the outside. Here, the chip enable signal CEB and the write enable signal WEB are control signals used in a normal SRAM. The activation instruction signal WRED is a control signal unique to the present embodiment, and is a control signal that is set to an active level (High level in this example) when storing or recalling the nonvolatile RAM.

  The address input circuit 950 is a circuit that receives and holds addresses A0 to A21 that designate access destinations in the nonvolatile RAM cell array 100 under the control of the control circuit 900. In the nonvolatile RAM cell array 100, the addresses A0 to A21 are divided into a row address that specifies the row to which the access destination belongs and a column address that specifies the column to which the access destination belongs.

  The row decoder 200 decodes the row address and selects one of the rows of the nonvolatile RAM cell array 100 according to the decoding result. In addition, the column decoder 300 decodes the column address and selects one of the columns of the nonvolatile RAM cell array 100 according to the decoding result. Column gate 400 connects write circuit 800 at the time of write access and sense amplifier 600 at the time of read access to the bit line of the column selected by column decoder 300. The sense amplifier 600 is a circuit that amplifies the voltage on the bit line supplied through the column gate 400 at the time of read access and outputs the amplified voltage to the input / output buffer 700. The write circuit 800 is a circuit that supplies the column gate 400 with a data voltage corresponding to write data supplied via the input / output buffer 700 during write access. Input / output buffer 700 receives 16-bit write data from the outside, supplies it to write circuit 800, and outputs 16-bit read data to the outside based on the output signal of sense amplifier 600. An output circuit is used.

  The row decoder 200 is provided with a function specific to the present embodiment in addition to the function of a normal SRAM row decoder. That is, the row decoder 200 in this embodiment selects a desired nonvolatile memory cell 10 in the nonvolatile RAM cell array 100 in units of rows, turns off the N-channel transistors Ta1 and Ta2 of the nonvolatile memory cell, and turns off the N-channel transistor Tw1. And Tw2 are turned ON, a predetermined source voltage SL is applied to the bias supply node NS of the nonvolatile memory cell 10, and a store for writing data from the volatile storage unit 11 to the nonvolatile storage unit 12 of the nonvolatile memory cell 10 is stored. The store control means to be performed and the desired nonvolatile memory cell M10 in the nonvolatile RAM cell array 100 are selected in units of rows, the N channel transistors Ta1 and Ta2 of the nonvolatile memory cell 10 are turned off, and the N channel transistors Tw1 and Tw2 are turned off. ON Then, by applying a predetermined source voltage SL to the bias supply node NS of the nonvolatile memory cell 10 and raising the power supply voltage for the flip-flop of the nonvolatile memory cell 10, nonvolatile storage of the nonvolatile memory cell 10 is performed. It has a function as a recall control means for performing a recall for writing data from the unit 12 to the volatile storage unit 11. The power supply control circuit 500 is a circuit that generates a reference source voltage VSL, a reference write voltage VDW, and a reference power supply voltage VDC that are used to generate various control signals for storing and recalling.

  FIG. 6 is a block diagram showing a specific configuration example of the nonvolatile RAM according to the present embodiment. In FIG. 6, only the configuration related to storage and input / output of 1-bit data is shown in order to prevent the drawing from becoming complicated. The actual nonvolatile RAM has a configuration in which the nonvolatile RAM cell array 100 and the column gate 400 shown in FIG.

  In FIG. 6, the nonvolatile RAM cell array 100 uses the nonvolatile memory cells 10 of the first embodiment (FIG. 1) as nonvolatile memory cells Mkj, and the nonvolatile memory cells Mkj are arranged in a matrix having m + 1 rows and n + 1 columns. It is an arrangement.

  A pair of bit lines BITj and BITjB are wired along each column j of the nonvolatile memory cell matrix Mkj (k = 0 to m, j = 0 to n). Here, the sources of the N-channel transistors Ta1 of m + 1 nonvolatile memory cells Mkj (k = 0 to m) belonging to the column j are connected to the bit line BITj, respectively, and the bit line BITjB belongs to the column j. The sources of N-channel transistors Ta2 of m + 1 nonvolatile memory cells Mkj (k = 0 to m) are connected to each other.

  Further, along each row k of the nonvolatile memory cell matrix Mkj (k = 0 to m, j = 0 to n), a signal line for supplying a row selection voltage WLk and a high potential side power supply voltage VDCk are supplied for each row. A power supply line for supplying power, a power supply line for supplying source voltage SLk for each row, and a signal line for supplying activation signal WREk are wired. Here, the high potential side power supply voltage VDCk is applied to the sources of P channel transistors P1 and P2 (see FIG. 1) of n + 1 nonvolatile memory cells Mkj (j = 0 to n) belonging to row k. The source voltage SLk is supplied to the bias supply node NS (see FIG. 1) of the nonvolatile memory cell Mkj (j = 0 to n). The activation signal WREk is supplied to the gates of the N-channel transistors Tw1 and Tw2 (see FIG. 1) of the nonvolatile memory cell Mkj (j = 0 to n).

  The low-potential-side power supply voltage VSS is applied to the connection node between the sources of the N-channel transistors N1 and N2 of each nonvolatile memory cell in the nonvolatile memory cell matrix Mkj (k = 0 to m, j = 0 to n). Supplied. In the present embodiment, the power supply line for supplying the low-potential-side power supply voltage VSS is wired in the column direction (direction across the row) for each column j.

  The column gate 400 includes n + 1 sets of N-channel column selection transistors CGj (j = 0 to n) and CGjB (j = 0 to 0) associated with the respective columns j (j = 0 to n) of the nonvolatile RAM cell array 100. n). The column selection transistors CGj and CGjB corresponding to the column j are turned on when the column selection voltage COLj becomes an active level, and connect the bit lines BITj and BITjB to the write circuit 800 and the sense amplifier 600.

  The column decoder 300 includes n + 1 column selection circuits 300-j (j = 0 to n) corresponding to the columns j (j = 0 to n) of the nonvolatile RAM cell array 100, respectively. Here, the column selection circuit 300-j corresponding to the column j includes a column address match detection unit 301 that outputs an L level signal when the column address indicates the column j, and an output of the column address match detection unit 301. When the signal is at the L level, the inverter 302 outputs an H level row selection voltage COLj and turns on the column gate transistors CGj and CGjB corresponding to the column j.

  The row decoder 200 includes m + 1 row selection circuits 200-k (k = 0 to m) corresponding to the rows k (k = 0 to m) of the nonvolatile RAM cell array 100, respectively. In an operation mode as a normal SRAM, the row selection circuit 200-k corresponding to each row k sets the row selection voltage WLk to an active level when the row address indicates the row k, and n + 1 pieces belonging to the row k. The N-channel transistors Ta1 and Ta2 (see FIG. 1) of the nonvolatile memory cell Mkj (j = 0 to n) are turned on. In addition, the row selection circuit 200-k corresponding to each row k includes a high-potential-side power supply voltage VDCk, a source voltage VSLk, and an active voltage supplied to n + 1 nonvolatile memory cells Mkj (j = 0 to n) belonging to the row k. The control signal WREk is controlled. More specifically, it is as follows.

a. In the normal operation mode in which the nonvolatile RAM is operated as an SRAM, when the row address indicates the row k, the row selection voltage WLk corresponding to the row k is set to an active level (High level), and the row address indicates the row k. If not, the accompanying selection voltage WLk is set to an inactive level (Low level).

b. In the operation mode for storing, when the row address indicates the row k, the level of the activation signal WREk corresponding to the row k is set to the reference write voltage VDW output from the power supply control circuit 500, and the row k corresponds to the row k. The high-potential-side power supply voltage VDCk is used as the reference power supply voltage VDC output from the power supply control circuit 500, the source voltage SLk corresponding to the row k is used as the reference source voltage VSL output from the power supply control circuit 500, and the row address is the row k. Is not set, the activation signal WREk and the source voltage SLk are set to 0V.

c. In the recall operation mode, when the nonvolatile RAM is powered on, the high potential side power supply voltage VDCk corresponding to the row k is initialized to 0 V, and after this initialization, the row address indicates the row k When a predetermined time further elapses, the high potential side power supply voltage VDCk corresponding to the row k is raised from 0 V to the reference power supply voltage VDC, and thereafter, the high potential side power supply voltage VDCk is maintained at the reference power supply voltage VDC. . When the row address indicates the row k, the level of the activation signal WREk corresponding to the row k is set to the reference write voltage VDW output from the power supply control circuit 500, and the source voltage SLk corresponding to the row k. Is the reference source voltage VSL output from the power supply control circuit 500. When the row address does not indicate the row k, the activation signal WREk and the source voltage SLk are set to 0V.

  As shown in FIG. 7, the power supply control circuit 500 includes a control circuit 501, a booster circuit 502, a step-down circuit 503, and an output adjustment circuit 504. The control circuit 501 is supplied with the activation instruction signal WRED and the power-on pulse PON described above. Here, the power-on pulse PON is a pulse generated when the power of the nonvolatile RAM is turned on. When the activation instruction signal WRED rises in a state where the power source of the nonvolatile RAM is ON (the power supply pulse PON is not generated, and only the rise of the activation instruction signal WRED is generated alone) ), A booster circuit 502 for outputting the reference source voltage VSL, the reference write voltage VDW, and the reference power supply voltage VDC necessary for causing the nonvolatile memory cell Mkj to perform the store operation. The step-down circuit 503 and the output adjustment circuit 504 are controlled. Further, when the rise of the activation instruction signal WRED and the power-on pulse PON are generated close to each other, the control circuit 501 interprets that a recall instruction has been issued, and causes the nonvolatile memory cell Mkj to perform a recall operation. The booster circuit 502, the step-down circuit 503, and the output adjustment circuit 504 for outputting the necessary reference source voltage VSL, reference write voltage VDW, and reference power supply voltage VDC are controlled.

  The booster circuit 502 boosts and outputs a power supply voltage for the nonvolatile RAM. The step-down circuit 503 steps down the power supply voltage and outputs it. The step-up circuit 502 and the step-down circuit 503 are provided, as shown in FIGS. 2 to 4, in order to perform store and recall operations, a voltage higher or lower than the power supply voltage for the nonvolatile RAM. This is because it is necessary to generate a voltage. The output adjustment circuit 504 selects a reference source voltage VSL, a reference write voltage VDW by selecting an output voltage of the booster circuit 502, an output voltage of the step-down circuit 503, or a power supply voltage for the nonvolatile RAM under the control of the control circuit 501. And the reference power supply voltage VDC is output.

  In the present embodiment, store and recall are performed in units of rows (that is, store and recall are performed in units of n + 1 nonvolatile memory cells Mkj (j = 0 to n) having the same row). The minimum unit of the nonvolatile RAM cell array is generally divided into 512 K bits, for example, as m + 1 = 1024 and n + 1 = 512, although depending on the high speed and the scale of the memory capacity. In this example, since the memory capacity is 64 Mbits, 128 nonvolatile RAM cell arrays of the minimum unit are provided.

  FIG. 8 is a time chart showing the operation during storage of the nonvolatile RAM according to the present embodiment. In this example, the nonvolatile RAM operates under the operating conditions shown in FIG. In the period t1, the nonvolatile RAM operates as a normal SRAM in response to the supply of the power supply voltage VDD of 0.5V. When the supply of the power supply voltage VDD to the nonvolatile RAM is cut off, the activation instruction signal WRED is raised prior to the operation, and the nonvolatile RAM performs the store operation as follows.

  First, the control circuit 501 outputs each voltage of 1.5 V to the booster circuit 502 and 0.6 V to the step-down circuit 503. Then, the control circuit 501 causes the output adjustment circuit 504 to output 1.2 V as the reference power supply voltage VDC, 1.5 V as the reference write voltage VDW, and 0.6 V as the reference source voltage VSL. As a result, the high-potential side power supply voltage VDCk (k = 0 to m) for the nonvolatile memory cell Mkj (k = 0 to m, j = 0 to n) rises from 0.5V to 1.2V.

  Next, during the period t2, storage from the volatile storage unit 11 to the nonvolatile storage unit 12 in each of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) is performed in units of rows. Specifically, first, the row address ADDX is set to the address AX0 corresponding to the first row k = 0. As a result, the row selection circuit 200-0 applies the activation signal WRE0 (= VDW) of 1.5 V to the N-channel transistors Tw1 and Tw2 of the nonvolatile memory cell M0j (j = 0 to n) in the 0th row for the time Δt1. Supply. In addition, the row selection circuit 200-0 supplies the source voltage SL0 (= VSL) of 0.6V to the bias supply node of the nonvolatile memory cell M0j (j = 0 to n) of the 0th row during the time Δt1. To do. As a result, the storage data of the volatile storage unit 11 is written to the nonvolatile storage unit 12 in each of the nonvolatile memory cells M0j (j = 0 to n) in the 0th row.

  Next, the row address ADDX is set to AX1 indicating the next row k = 1. Thereby, the row selection circuit 200-1 supplies the activation signal WRE1 of 1.5 V to the N-channel transistors Tw1 and Tw2 of the nonvolatile memory cells M1j (j = 0 to n) in the first row for a predetermined time. In addition, the row selection circuit 200-1 supplies the 0.6V source voltage SL1 to the bias supply node of the nonvolatile memory cell M1j (j = 0 to n) in the first row during this period. As a result, the storage data of the volatile storage unit 11 is written to the nonvolatile storage unit 12 in each of the nonvolatile memory cells M1j (j = 0 to n) in the first row.

  Similarly, the row address ADDX is sequentially advanced from AX2 to AXm, and the data writing in units of rows is advanced. When the data writing for all the rows is completed, the power supply voltage to the nonvolatile RAM is cut off in the subsequent period t3.

  In the above operation, if n + 1 = 512, the current required for storing per cell is 49 μA, the current consumption required to store one row (= 512) at once is 25 mA, which is within the allowable range. Current value.

  At present, further simultaneous storage is severe because the current consumption increases and the voltage drop of the resistance of the wiring for supplying the power supply voltage VDC and the source voltage SL becomes severe. If the above characteristics are improved and data can be written to the resistance variable element at a slightly lower current, for example, the number of cells to be stored at once can be increased to 1024.

  FIG. 9 is a time chart showing the operation at the time of recall of the nonvolatile RAM according to the present embodiment. In this example, the recall is performed in accordance with the operating conditions shown in FIG.

  First, when the power supply voltage VDD for the nonvolatile RAM rises to 0.5V and the activation instruction signal WRED rises, the control circuit 501 causes the voltage down converter 503 to output a voltage of 0.3V. Then, the control circuit 501 uses 0.5 V as the reference power supply voltage VDC (power supply voltage VDD of the nonvolatile RAM), 0.3 V as the reference write voltage VDW, and 0 V as the reference source voltage VSL (power supply voltage of the nonvolatile RAM). VSS) is output to the output adjustment circuit 504.

  In the nonvolatile RAM, the row address ADDX is set to the row address AX0 designating the first row, and the activation signal WRE is set to 0.3 V (= VDW). Thereafter, after a predetermined time Δt1, the high potential side power supply voltage VDC0 corresponding to the first row rises from 0V to 0.5V (= VDC). Thereafter, the row address AX0 is deselected (goes to the next address) after the time Δt2 has elapsed. As a result, the activation signal WRE0 becomes 0 V, and the data stored in the nonvolatile storage unit 12 (see FIG. 1) of the (n + 1) nonvolatile memory cells M0j (j = 0 to n) belonging to the first row is stored in the volatile memory. Held in the part 11.

  Thereafter, similarly, the row address is advanced to AX1, AX2,..., AXm, and the recall is performed in units of rows. When the recall is completed for all rows, the non-volatile RAM then starts the same operation as a normal SRAM.

  In this embodiment, the recall operation is very fast, and one cycle (one row) can be recalled in 10 ns or less (that is, Δt1 + Δt2 <10 ns). Therefore, if the size of the nonvolatile RAM cell array 100 is m + 1 = 1024 and n + 1 = 512, the time required to recall one nonvolatile RAM cell array 100 is 10 ns × 1024 rows = 10.2 μs. Further, when realizing a 64-Mbit SRAM, since 128 nonvolatile RAM cell arrays 100 are used, the time required for recalling the entire storage area is 10.2 μs × 128 = 1.3 ms.

  While the recall under the operating conditions of FIG. 3 has been described above, the recall operation under the operating conditions of FIG. 4 is the same. In FIG. 9, the waveforms of the source voltages SL0 to SLm during the recall operation under the operating conditions shown in FIG. 4 are indicated by broken lines. As shown in the figure, when a recall is performed under the operating conditions shown in FIG. 4, the source voltage SLk corresponding to the row k is increased to 0.3 during the period in which the activation signal WREk corresponding to the row k is increased. According to this aspect, the current consumption of the resistance variable element at the time of recall can be reduced. According to Non-Patent Document 1, the current that flows at the time of recall is about 10 μA, which is sufficiently smaller than 49 μA at the time of store, so that a plurality of rows can be selected simultaneously. In the case of a memory with a small capacity, it is possible to select all rows at once and shorten the recall time.

  FIG. 10 is a circuit diagram showing a configuration example of a row selection circuit 200-k suitable for the present embodiment. In FIG. 10, the address match detection unit 201 outputs a low level when the row address ADDX indicates the row k, and outputs a high level when the row address ADDX does not indicate the row k. The inverter 202 inverts the output signal of the address match detection unit 201 and outputs it as an address match detection signal ADTk.

  The latch L1 includes a P-channel transistor 203, N-channel transistors 204 and 206, and an inverter 205. The P-channel transistor 203 and the N-channel transistor 204 are interposed in series between the high potential side power supply VDD and the low potential side power supply VSS. Address match detection signal ADTk is applied to the gate of N channel transistor 204. Inverter 205 inverts and outputs a signal generated at a connection node between the drains of P-channel transistor 203 and N-channel transistor 204. The output signal of the inverter 205 becomes the output signal of the latch L1. The output signal of the inverter 205 is supplied to the gate of the P channel transistor 203. The N-channel transistor 206 is interposed between the output node of the inverter 205 and the low potential side power source VSS. A power-on pulse PON is applied to the gate of the N-channel transistor 206. The above is the configuration of the latch L1.

  The delay circuit 207 delays the output signal of the latch L1 by a predetermined time Δt1. The inverter 208 inverts the output signal of the delay circuit 207 and outputs it. The reference power supply voltage VDC output from the output adjustment circuit 504 of the power supply control circuit 500 is supplied to the level shifter 209 as a high potential side power supply voltage. The level shifter 209 inverts the output signal of the inverter 208. When the inverted result is “0”, the level shifter 209 uses 0V, and when the result is “1”, the reference power supply voltage VDC corresponds to the high-potential-side power supply voltage VDCk. Output as.

  The NAND gate 210 outputs a low level to the level shifters 211 and 212 when the address match detection signal ADTk is at a high level and the activation instruction signal WRED is at a high level, and otherwise the high level. A reference write voltage VDW output from the output adjustment circuit 504 of the power supply control circuit 500 is supplied to the level shifter 211 as a high potential side power supply voltage. The level shifter 212 is supplied with the reference source voltage VSL output from the output adjustment circuit 504 as a high potential side power supply voltage. The level shifter 211 inverts the output signal of the NAND gate 210. When the inverted result is “0”, the level shifter 211 sets the activation signal WREk corresponding to the row k to 0V, and when the result is “1”, the reference write voltage VDW is set. Output as. The level shifter 212 inverts the output signal of the NAND gate 210 and outputs 0 V when the inverted result is “0”, and outputs the reference source voltage VSL as the source voltage SLk corresponding to the row k when the result is “1”. To do.

  The NAND gate 214 receives an address match detection signal ADTk and a signal obtained by inverting the activation instruction signal WRED by the inverter 213. Inverter 215 inverts the output signal of NAND gate 214 and outputs the inverted signal as row selection voltage WLk corresponding to row k.

  Next, the operation of the row selection circuit 200-k will be described. First, the operation for the recall operation will be described. When the power supply voltage VDD rises to the nonvolatile RAM and the power-on pulse PON is generated, the N-channel transistor 206 is turned on, and the output signal of the latch L1 is reset to 0V (Low level). As a result, the high-potential-side power supply voltage VDCk for the row k output from the level shifter 209 is 0V. This is the initial state.

  Next, when the row address ADDX becomes a row address indicating the row k, the address match detection signal ADTk rises from the Low level to the High level. Here, since the activation instruction signal WRED is at the high level during the recall operation, the output signal of the NAND gate 210 is at the low level. Therefore, the level shifter 211 outputs the reference write voltage VDW as the activation signal WREk for the row k, and the level shifter 212 outputs the reference source voltage VSL as the source voltage SLk for the row k.

  Since activation instruction signal WRED is at a high level, the output signal of NAND gate 214 is at a high level, and row selection voltage WLk for row k output from inverter 215 is at a low level. Accordingly, the N channel transistors Ta1 and Ta2 of the nonvolatile memory cell 10 in the row k are turned off.

  When the address match detection signal ADTk rises, in the latch L1, the N-channel transistor 204 is turned on, and the output signal of the latch L1 rises to a high level. The rising edge of the output signal of the latch L1 is delayed by the time Δt1 by the delay circuit 207, inverted by the inverter 208, and transmitted to the level shifter 209. Therefore, the high-potential-side power supply voltage VDCk for the row k output from the level shifter 209 rises from 0 V to the reference power supply voltage VDC with the delay of the time Δt1 from the rise of the address match detection signal ADTk.

Once the output signal of the latch L1 is at a high level, the high level is maintained while the power supply voltage VDD is applied thereafter. Therefore, the high potential side power supply voltage VDCk for row k maintains the reference power supply voltage VDC.
As described above, the recall operation of FIG. 9 is realized.

  When the recall for all storage areas is completed, the activation instruction signal WRED becomes 0V. As a result, for all the rows k, the activation signal WREk and the source voltage SLk become 0V. As a result, in each nonvolatile memory cell 10, the resistance change elements R 1 and R 2 are disconnected from the volatile storage unit 11.

  In addition, since the output signal of the inverter 213 is at a high level, in the row selection circuit 200-k, the row selection voltage WLk is at a high level when the address match detection signal ADTk is at a high level. Therefore, the nonvolatile RAM operates as a normal SRAM.

  When storing, the activation instruction signal WRED becomes High level. The operation of the row selection circuit 200-k in this case is that the high potential side power supply voltage VDCk for the row k maintains the voltage VDC, the reference power supply voltage VDC, the reference write voltage VDW, and the reference source voltage VSL are stored. The operation is the same as that at the time of recall except that the voltage is set to a suitable voltage.

<Third Embodiment>
FIG. 11 is a circuit diagram showing a configuration of a nonvolatile memory cell 10A according to the third embodiment of the present invention. The non-volatile memory cell 10A includes a volatile memory unit 11A and a non-volatile memory unit 12 similar to that of the first embodiment. In the first embodiment, the low-potential-side power supply voltage VSS common to the memory chips and the high-potential-side power supply voltage VDC that is variably controlled in units of rows are supplied to the volatile storage unit 11. On the other hand, in the present embodiment, the reference power supply voltage VDC and the low-potential-side power supply voltage VSC that is variably controlled in units of rows are supplied to the volatile storage unit 11A.

  In the present embodiment, the nonvolatile memory cell 10A is operated according to the operating conditions shown in FIG. The operation of the nonvolatile memory cell 10A as a normal SRAM memory cell and the operation at the time of storage are the same as those in the first embodiment.

The operation at the time of recall of the nonvolatile memory cell 10A is as follows. In the initial state of the recall, the high-potential side power supply voltage VSC for the nonvolatile memory cell 10A is at a level substantially equal to the reference power supply voltage VDC, and is charged to 0.5 V in the illustrated example. In the recall operation, the activation signal WRE is set to 0.3 V, the source voltage SL is set to 0 V, and energization to the resistance variable elements R1 and R2 is started. Here, when the nonvolatile storage unit 12 stores data “1”, the resistance variable element R1 has a high resistance and the resistance variable element R2 has a low resistance, and the output node V1 of the inverter INV1. The level of the output node V2 of the inverter INV2 is slightly lower than the level of. In this state, when the low potential side power supply voltage VSC for the nonvolatile memory cell 10A is lowered from 0.5V to 0V, the data “1” is held in the volatile memory portion 11A. The same applies to the recall of data “0”.
Also in this embodiment, the same effect as the first embodiment can be obtained.

<Fourth embodiment>
FIG. 13 is a circuit diagram showing a partial configuration of a nonvolatile RAM according to the fourth embodiment of the present invention. FIG. 13 shows one row selection circuit 250-k in the nonvolatile RAM and one row of nonvolatile memory cells Mkj (j = 0 to n) controlled by the row selection circuit 250-k. ing. Here, each nonvolatile memory cell Mkj (j = 0 to n) is configured by the nonvolatile memory cell 10A of the third embodiment.

  FIG. 14 is a time chart showing the operation at the time of recall of the nonvolatile RAM according to the present embodiment. What is different from the operation of the second embodiment (FIG. 9) is the waveform of the low-potential-side power supply voltage VSCk (k = 0 to m).

  First, when the power supply voltage VDD for the nonvolatile RAM rises, the high-potential-side power supply voltage VDC for all the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) rises to 0.5V. . As a result, the low potential side power supply voltage VSCk (k = 0 to m) is charged to the level of the reference power supply voltage VDC.

  Next, the row address ADDX is input to the nonvolatile RAM. While the row address AX0 corresponding to the first row is given as the row address ADDX, the activation signal WRE0 corresponding to that row is set to the high level. As a result, in the nonvolatile memory cell M0j (j = 0 to n) in the first row, the resistance variable elements R1 and R2 are connected to the output node V1 of the inverter INV1 and the output node V2 of the inverter INV2. When a predetermined time Δt1 elapses after the activation signal WRE0 becomes High level, the low-potential-side power supply voltage VSC0 for the first row becomes 0V. Thereby, in the nonvolatile memory cell M0j (j = 0 to n) in the first row, the data stored in the nonvolatile storage unit 12 is held by the volatile storage unit 11A.

  Thereafter, after a predetermined time Δt2 has elapsed, the row address ADDX is switched to the row address AX1 corresponding to the next row, and the same operation as the first row is performed. Thereafter, the row address ADDX is sequentially switched to AX2,..., AXm, and recall for all rows is performed.

  FIG. 15 is a circuit diagram showing a configuration example of a row selection circuit 250-k suitable for the nonvolatile RAM according to the present embodiment. The difference from the circuit shown in FIG. 10 is that the inverter 208 is deleted and the level shifter 209 is replaced with an N-channel transistor 259. The N-channel transistor 259 has a source fixed at the low potential side power supply voltage VSS, a gate supplied with the output signal of the delay circuit 207, and a drain connected to the non-volatile memory cell Mkj (j = 0 to n) in the row k. Are connected to a power supply line for supplying the low potential side power supply voltage VSCk.

  In this configuration, as already described in the second embodiment, the output signal of the latch L1 is at the low level during the period from the generation of the power-on pulse PON until the address match detection signal ADTk rises, and the N-channel transistor 259. Becomes OFF. While the N-channel transistor 259 is OFF, the low potential side power supply voltage VSCk is in a floating state and is charged to the same level as the high potential side power supply voltage VDC of the nonvolatile RAM.

When the address coincidence detection signal ADTk rises, the output signal of the latch L1 becomes High level, and when a predetermined time Δt1 has elapsed from that time, the N-channel transistor 259 is turned ON and the low-potential power supply voltage VSCk becomes VSS = 0V. .
Therefore, the recall for row k can be performed.

  When it is not preferable to float the low potential side power supply voltage VSCk, a level shifter is used instead of the N-channel transistor 259, and a high reference power supply voltage VDC and a low potential side power supply voltage VSS are applied to the level shifter. Also good.

<Fifth Embodiment>
FIG. 16 is a circuit diagram showing a configuration of a nonvolatile memory cell 10B according to the fifth embodiment of the present invention. The nonvolatile memory cell 10B includes a volatile memory unit 11B and a nonvolatile memory unit 12 similar to that of the first embodiment. In the present embodiment, a P-channel transistor serving as a power switch between a common connection point between the sources of the P-channel transistors P1 and P2 of the volatile storage unit 11B and a power supply line for supplying the high-potential-side power supply voltage VDC. P3 is inserted. A selection signal SELD is applied to the gate of the P-channel transistor P3.

  When causing the nonvolatile memory cell 10B to perform an operation and store as a normal SRAM memory cell, the selection signal SELD is always at a low level, and the P-channel transistor P3 is turned on. The operation of the nonvolatile memory cell 10B in this case is the same as that in the first embodiment.

The operation when the nonvolatile memory cell 10B is recalled is different from that in the first embodiment. In the first embodiment, at the time of recall, the high-potential-side power supply voltage VDC is raised with the activation signal WRE being at a high level. On the other hand, in the present embodiment, at the start of the recall, the high potential side power supply voltage VDC for all the nonvolatile memory cells 10B is raised and the selection signal SELD for all the nonvolatile memory cells 10B is set to the high level. Thereafter, the rows to be recalled are sequentially selected, the selection signal SELD for the nonvolatile memory cell 10B in the selected row is lowered to the Low level, the P channel transistor P3 of the nonvolatile memory cell 10B is turned on, and the inverter The power supply voltage of the flip-flop composed of INV1 and INV2 is raised.
Also in this embodiment, the same effect as the first embodiment can be obtained.

<Sixth Embodiment>
FIG. 17 is a block diagram showing a partial configuration of a nonvolatile RAM according to the sixth embodiment of the present invention. FIG. 17 illustrates one row selection circuit 260-k in the nonvolatile RAM and one row of nonvolatile memory cells Mkj (j = 0 to n) controlled by the row selection circuit 260-k. ing. Here, each nonvolatile memory cell Mkj (j = 0 to n) is configured by the nonvolatile memory cell 10B of the fifth embodiment.

  The row selection circuit 260-k in this embodiment has a function of outputting the selection signal SELD-k described in the fifth embodiment for the nonvolatile memory cells Mkj (j = 0 to n).

  This embodiment has the following advantages. First, since the P-channel transistor P3 is individually provided in each nonvolatile memory cell Mkj, the power supply wiring of the high-potential-side power supply voltage VDC can be wired in the column direction (direction across the row) in the nonvolatile RAM cell array. Therefore, it is only necessary to consider the current for one bit as the current flowing in one power supply line at the time of store or recall, and voltage drop due to the power supply line resistance can be reduced.

  FIG. 18 is a circuit diagram showing a configuration example of a row selection circuit 260-k suitable for the nonvolatile RAM according to the present embodiment. This circuit is different from the circuit of FIG. 10 described above in that the inverter 208 is omitted and a level shifter 269 is provided instead of the level shifter 209. The level shifter 269 uses the reference power supply voltage VDC output by a circuit corresponding to the output adjustment circuit 504 (see FIG. 7) of the second embodiment as a high potential side power supply voltage. The level shifter 269 inverts the output signal of the delay circuit 207. When the inversion result is “1”, the level power supply voltage VDC is obtained. When the inversion result is “0”, the low potential side power supply voltage VSS (= 0 V) is obtained. The selection signal SELDk is output to the gate of the P-channel transistor P3 of each nonvolatile memory cell in the row k.

  According to this configuration, as in the second embodiment, when the power supply voltage VDD rises to the nonvolatile RAM and the recall operation is started, the output signal of the latch L is reset by the generation of the power-on pulse PON. As a result, the selection signal SELDk output from the level shifter 269 becomes the level of the reference power supply voltage VDC, and the P-channel transistor P3 of each nonvolatile memory cell in the row k is turned off.

  When the row address ADDX becomes an address indicating the row k and the address match detection signal ADTk becomes High level, the output signal of the latch L rises to High level. When a predetermined time Δt1 has elapsed from the rise of the output signal of the latch L, the selection signal SELDk output from the level shifter 269 becomes the level of the low potential side power supply voltage VSS, and the P-channel transistor of each nonvolatile memory cell in the row k P3 is turned ON. As a result, a recall operation is performed in each nonvolatile memory cell in row k.

<Seventh embodiment>
FIG. 19 is a circuit diagram showing a configuration of a nonvolatile memory cell 10C according to the seventh embodiment of the present invention. The nonvolatile memory cell 10C includes a volatile memory unit 11C and a nonvolatile memory unit 12 similar to that of the first embodiment. In the present embodiment, the N-channel transistor N3 is interposed between the common connection point between the sources of the N-channel transistors N1 and N2 of the volatile storage unit 11C and the power supply line for supplying the low-potential-side power supply voltage VSS. Has been. A selection signal SELS is applied to the gate of the N-channel transistor N3.

  When causing the nonvolatile memory cell 10C to perform an operation or store as a normal SRAM memory cell, the selection signal SELS is always at a high level, and the N-channel transistor N3 is turned on. The operation of the nonvolatile memory cell 10C in this case is the same as that in the first embodiment.

The operation when the nonvolatile memory cell 10C is recalled is similar to the third embodiment (FIG. 11), but is slightly different. In the third embodiment, at the time of recall, the low-potential-side power supply voltage VSC is raised with the activation signal WRE being at a high level. In contrast, in the present embodiment, at the start of the recall, the low-potential-side power supply voltage VSS for all the nonvolatile memory cells 10C is set to 0 V, and the selection signal SELS for all the nonvolatile memory cells 10C is set to the low level. . Thereafter, the rows to be recalled are sequentially selected, the selection signal SELS for the nonvolatile memory cell 10C in the selected row is raised to a high level, the N-channel transistor N3 of the nonvolatile memory cell 10C is turned on, and the inverter The power supply voltage of the flip-flop composed of INV1 and INV2 is set.
Also in this embodiment, the same effect as the third embodiment can be obtained.

<Eighth Embodiment>
Although not shown, in the present embodiment, the nonvolatile RAM cell array 100 (see FIG. 5) is configured using the nonvolatile memory cell 10C according to the seventh embodiment. According to this embodiment, the power supply line for supplying the high-potential-side power supply voltage VDC and the power supply line for supplying the low-potential-side power supply voltage VSS are arranged in the direction along the columns (rows) across the nonvolatile RAM cell array 100. Direction). Therefore, according to the present embodiment, as in the sixth embodiment, only one bit of current needs to be considered as the current flowing through one power supply line at the time of store or recall, and the voltage drop due to the power supply line resistance is reduced. Can be reduced.

  FIG. 20 is a circuit diagram showing a configuration example of a row selection circuit 270-k suitable for the nonvolatile RAM according to the present embodiment. This circuit is different from the circuit shown in FIG. 10 in that an inverter 279 is provided instead of the level shifter 209. The inverter 279 inverts the output signal of the delay circuit 207. When the inversion result is “1”, the high level is set, and when the result is “0”, the low level is set as the selection signal SELSk and each non-volatile in the row k. Output to the gate of the N-channel transistor N3 of the memory cell.

  In the present embodiment, it is only necessary to generate the selection signal SELSk that can perform ON / OFF switching of the N-channel transistor N3, and the High level of the selection signal SELSk has a degree of freedom. Therefore, a normal inverter that is not a level shifter is used as a means for generating the selection signal SELSk.

<Other embodiments>
Although the first to eighth embodiments of the present invention have been described above, other embodiments are conceivable for the present invention. For example:

(1) In the nonvolatile memory unit 12 of FIG. 1, the mutual positional relationship between the N-channel transistor Tw1 and the resistance variable element R1 and the mutual positional relationship between the N-channel transistor Tw2 and the resistance variable element R2 may be interchanged. .

(2) In each of the above embodiments, at the time of storing and recalling, a row address is given from the outside of the non-volatile RAM, and this row address is switched from the outside to store and recall in units of rows. However, instead of doing so, a row address generating means for outputting sequentially changing row addresses by a counter or the like is provided in the nonvolatile RAM, and store and recall are performed using the row address output by the row address generating means. May be performed.

(3) In each of the above embodiments, all the cells of the RAM cell array are configured by nonvolatile memory cells including a volatile storage unit and a nonvolatile storage unit. However, instead of doing so, a part of the RAM cell array may be constituted by nonvolatile memory cells, and the remaining area may be constituted by normal SRAM memory cells. That is, only a part of the entire memory space of the SRAM is made an area that can be stored and recalled.

10, 10A, 10B, 10C, Mkj... Nonvolatile memory cell, 11, 11A, 11B, 11C... Volatile memory unit, 12... Nonvolatile memory unit, P1, P2. , Ta1, Ta2, Tw1, Tw2... N channel transistor, R1, R2... Variable resistance element, INV1, INV2... Inverter, BL, BLB, BITj, BITjB... Bit line, NS. DESCRIPTION OF SYMBOLS 100 ... Nonvolatile RAM cell array, 200 ... Row decoder, 300 ... Column decoder, 400 ... Column gate, 500 ... Power supply control circuit, 600 ... Sense amplifier, 700 ... I / O buffer, 800 ... Writing Embedded circuit, 900... Control circuit, 200 -k, 250 -k, 260 -k, 270 -k... Row selection circuit, 201. Address coincidence detecting unit, L1 ...... latch, 207 ...... delay circuit, 209,211,212 ...... level shifter.

Claims (20)

A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
When data is written to the flip-flop via the two bit lines inserted between the output nodes of the first and second inverters and the two bit lines, or the flip-flop A first switch and a second switch that are turned on when data is read from the two bit lines via the two bit lines,
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between an output node of the first inverter and a bias supply node;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the bias supply node;
Each of the first and second variable resistance elements has a resistance value that changes in a first direction when passing a current from an output node of the first or second inverter to the bias supply node. The resistance change element whose resistance value changes in a second direction opposite to the first direction when a current from the bias supply node to the output node of the first or second inverter is passed. A non-volatile memory having a non-volatile memory cell array composed of non-volatile memory cells,
In the nonvolatile memory cell, when storing data from the volatile storage unit to the nonvolatile storage unit, the first and second switches are turned off, and the third and fourth switches are turned on. Supplying an intermediate voltage between two kinds of voltages used to express “1” / “0” in the volatile storage unit to the bias supply node;
When performing a recall to write data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell, the first and second switches are turned off, and the third and fourth switches are turned on. A nonvolatile memory, wherein a power supply voltage for a flip-flop of the volatile storage unit is raised in a state where a predetermined voltage is supplied to the bias supply node. Said first and second variable resistance element, a magnetic tunnel junction device or nonvolatile memory according to claim 1, characterized in that the resistive elements for generating the electric field-induced giant resistance change. The third and fourth switches are field effect transistors;
When the nonvolatile memory cell functions as an SRAM memory cell, a first voltage is applied as a power supply voltage to the flip-flop of the volatile memory cell,
3. The second voltage higher than the first voltage is applied as a power supply voltage to a flip-flop of the volatile memory cell when the nonvolatile memory cell performs the store. Non-volatile memory as described. 4. The nonvolatile memory according to claim 1, wherein a voltage applied to the bias supply node is set higher than 0 V when the nonvolatile memory cell performs the recall. 5. The third and fourth switches are field effect transistors, and when the nonvolatile memory cell performs the store, a voltage larger than a power supply voltage applied to a flip-flop of the nonvolatile memory unit is applied to the third and fourth switches. The nonvolatile memory according to any one of claims 1 to 4, wherein each field effect transistor is turned on by being applied to a gate of each field effect transistor which is a fourth switch. When causing the nonvolatile memory cell to perform the recall, a voltage lower than the power supply voltage after startup when the power supply voltage applied to the flip-flop of the nonvolatile memory unit for the recall is raised is set to the third and 6. The nonvolatile memory according to claim 5, wherein each field effect transistor is turned on by being applied to a gate of each field effect transistor which is a fourth switch. A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A power switch interposed between the flip-flop and a power line for supplying a low-potential power supply voltage to the flip-flop;
When the data is written to the flip-flop via the two bit lines inserted between the output nodes of the first and second inverters and the two bit lines, respectively, or from the flip-flop A first switch and a second switch that are turned on when reading data via the two bit lines;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between an output node of the first inverter and a bias supply node;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the bias supply node;
Each of the first and second variable resistance elements has a resistance value that changes in a first direction when passing a current from an output node of the first or second inverter to the bias supply node. The resistance change element whose resistance value changes in a second direction opposite to the first direction when a current from the bias supply node to the output node of the first or second inverter is passed. A non-volatile memory cell. A nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix;
Control means for controlling the operation of each nonvolatile memory cell in the nonvolatile memory cell array;
A booster circuit that boosts and outputs a power supply voltage for the nonvolatile memory, a step-down circuit that steps down and outputs a power supply voltage for the nonvolatile memory, an output voltage of the booster circuit, an output voltage of the step-down circuit, or the nonvolatile memory A power supply control circuit having an output adjustment circuit that selects and outputs a power supply voltage for the memory,
The non-volatile memory cell has a volatile memory unit and a non-volatile memory unit,
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
When the data is written to the flip-flop via the two bit lines inserted between the output nodes of the first and second inverters and the two bit lines, respectively, or from the flip-flop A first switch and a second switch that are turned on when reading data via the two bit lines;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between an output node of the first inverter and a bias supply node;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the bias supply node;
Each of the first and second variable resistance elements has a resistance value that changes in a first direction when passing a current from an output node of the first or second inverter to the bias supply node. The resistance change element whose resistance value changes in a second direction opposite to the first direction when a current from the bias supply node to the output node of the first or second inverter is passed. ,
The control means includes
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected, the first and second switches of the nonvolatile memory cell are turned off, the third and fourth switches are turned on, and the nonvolatile memory cell Store control means for applying a predetermined source voltage to the bias supply node, and performing a store for writing data from the volatile storage unit of the nonvolatile memory to the nonvolatile storage unit;
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected, the first and second switches of the nonvolatile memory cell are turned off, the third and fourth switches are turned on, and the nonvolatile memory cell Data is written from the nonvolatile memory unit of the nonvolatile memory cell to the volatile memory unit by applying a predetermined source voltage to the bias supply node and raising the power supply voltage for the flip-flop of the nonvolatile memory cell. And recall control means for performing the recall,
The store control means and the recall control means include an activation signal for turning on the third and fourth switches of a desired nonvolatile memory cell using an output voltage of the output adjustment circuit, and a desired nonvolatile memory A nonvolatile memory characterized by generating a source voltage supplied to a bias supply node of a cell and a power supply voltage for a flip-flop of a desired nonvolatile memory cell. A nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix;
A row decoder for selecting a row to which a nonvolatile memory cell to be controlled belongs in the nonvolatile memory cell array;
The non-volatile memory cell has a volatile memory unit and a non-volatile memory unit,
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
When the data is written to the flip-flop via the two bit lines inserted between the output nodes of the first and second inverters and the two bit lines, respectively, or from the flip-flop A first switch and a second switch that are turned on when reading data via the two bit lines;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between an output node of the first inverter and a bias supply node;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the bias supply node;
Each of the first and second variable resistance elements has a resistance value that changes in a first direction when passing a current from an output node of the first or second inverter to the bias supply node. The resistance change element whose resistance value changes in a second direction opposite to the first direction when a current from the bias supply node to the output node of the first or second inverter is passed. ,
The row decoder
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected in units of rows, the first and second switches of the nonvolatile memory cell are turned off, the third and fourth switches are turned on, and the nonvolatile memory cell is turned on. Store control means for applying a predetermined source voltage to the bias supply node of the non-volatile memory cell and performing a store for writing data from the volatile memory unit of the non-volatile memory cell to the non-volatile memory unit;
A desired nonvolatile memory cell in the nonvolatile memory cell array is selected in units of rows, the first and second switches of the nonvolatile memory cell are turned off, the third and fourth switches are turned on, and the nonvolatile memory cell is turned on. A predetermined source voltage is applied to the bias supply node of the non-volatile memory cell, and a power supply voltage for the flip-flop of the non-volatile memory cell is raised, so that the non-volatile memory unit of the non-volatile memory cell is changed to the volatile memory unit. A non-volatile memory comprising recall control means for performing a recall for writing data into the memory. The store control means sequentially switches the rows to which the nonvolatile memory cells to be stored belong, and performs the store for all the rows of the nonvolatile memory cell array, and the recall control means sets the recall targets. The nonvolatile memory according to claim 9, wherein the rows to which the nonvolatile memory cells belong are sequentially switched, and the recall is performed for all the rows of the nonvolatile memory cell array. A booster circuit that boosts and outputs a power supply voltage for the nonvolatile memory, a step-down circuit that steps down and outputs a power supply voltage for the nonvolatile memory, an output voltage of the booster circuit, an output voltage of the step-down circuit, or the nonvolatile memory A power supply control circuit having an output adjustment circuit that selects and outputs a power supply voltage for the memory,
The row decoder has a plurality of row selection circuits associated with each row of the nonvolatile memory cell array,
Each row selection circuit corresponding to each row
An address match detection circuit which sets an address match detection signal to an active level when the row address indicates the row;
A first level shifter for supplying an activation signal for turning on the third and fourth switches of the nonvolatile memory portion of each nonvolatile memory cell belonging to the row in response to the address match detection signal;
A second level shifter for supplying a source voltage to a bias supply node of a nonvolatile memory portion of each nonvolatile memory cell belonging to the row in response to the address match detection signal;
After a predetermined time has elapsed since the generation of the first address match detection signal after the power supply voltage for the nonvolatile memory rises, a high voltage is applied to the flip-flop of the volatile storage unit of each nonvolatile memory cell belonging to the row. A third level shifter for raising the potential side power supply voltage;
11. The nonvolatile memory according to claim 9, wherein an output voltage of the output adjustment circuit is supplied to the first to third level shifters as a high-potential side power supply voltage. 12. Each row selection circuit corresponding to each row sequentially switches the row to be stored in the nonvolatile memory cell array to perform the store for each row of the nonvolatile memory cell array. Nonvolatile memory as described in 1. 12. The row selection circuit corresponding to each row sequentially switches the row to be recalled in the nonvolatile memory cell array to perform the recall for each row of the nonvolatile memory cell array. Nonvolatile memory as described in 1. In the nonvolatile memory cell array, a power supply line for supplying a high-potential-side power supply voltage to the flip-flops of the nonvolatile memory cells in each column is wired in the column direction, and the low-potential side Power supply lines that supply power supply voltage are wired in the row direction,
The row decoder sets a level of a power supply line for supplying a low-potential-side power supply voltage to each nonvolatile memory cell belonging to the row in order to perform the recall for each nonvolatile memory cell belonging to the selected row. 10. The nonvolatile memory according to claim 9, wherein the power supply voltage for the flip-flop of the volatile storage unit is raised by lowering from the same level as the high-potential-side power supply voltage. A booster circuit that boosts and outputs a power supply voltage for the nonvolatile memory, a step-down circuit that steps down and outputs a power supply voltage for the nonvolatile memory, an output voltage of the booster circuit, an output voltage of the step-down circuit, or the nonvolatile memory A power supply control circuit having an output adjustment circuit that selects and outputs a power supply voltage for the memory,
The row decoder has a plurality of row selection circuits associated with each row of the nonvolatile memory cell array,
Each row selection circuit corresponding to each row
An address match detection circuit that outputs an address match detection signal when the row address indicates the row;
A first level shifter for outputting an activation signal for turning on the third and fourth switches of the nonvolatile memory portion of each nonvolatile memory cell belonging to the row in response to the address match detection signal;
A second level shifter for supplying a source voltage to a bias supply node of a nonvolatile memory portion of each nonvolatile memory cell belonging to the row in response to the address match detection signal;
A flip-flop of the volatile memory portion of each nonvolatile memory cell belonging to the row after a predetermined time has elapsed since the generation of the first address match detection signal after the power supply voltage for the nonvolatile memory rises A power switch for supplying a low-potential-side power supply voltage to the
15. The nonvolatile memory according to claim 14, wherein an output voltage of the output adjustment circuit is supplied to the first and second level shifters as a high-potential side power supply voltage. 16. The row selection circuit corresponding to each row sequentially switches the row to be recalled in the nonvolatile memory cell array to perform the recall for each row of the nonvolatile memory cell array. Nonvolatile memory as described in 1. Each volatile memory portion of each nonvolatile memory cell of the nonvolatile memory cell array has a power switch interposed between the flip-flop and a power supply line that supplies a high-potential-side power supply voltage to the flip-flop. And
In the nonvolatile memory cell array, each power supply line for supplying a high potential side power supply voltage and a low potential side power supply voltage to the flip-flops of the nonvolatile memory cells in each column is wired in the column direction,
The row decoder turns on the power switch of each volatile memory unit of each nonvolatile memory cell belonging to the row in order to perform the recall for each nonvolatile memory cell belonging to the selected row. The nonvolatile memory according to claim 9, wherein a power supply voltage for a flip-flop of the volatile storage unit is raised. A booster circuit that boosts and outputs a power supply voltage for the nonvolatile memory, a step-down circuit that steps down and outputs a power supply voltage for the nonvolatile memory, an output voltage of the booster circuit, an output voltage of the step-down circuit, or the nonvolatile memory A power supply control circuit having an output adjustment circuit that selects and outputs a power supply voltage for the memory,
The row decoder has a plurality of row selection circuits associated with each row of the nonvolatile memory cell array,
Each row selection circuit corresponding to each row
An address match detection circuit that outputs an address match detection signal when the row address indicates the row;
A first level shifter for outputting an activation signal for turning on the third and fourth switches of the nonvolatile memory portion of each nonvolatile memory cell belonging to the row in response to the address match detection signal;
A second level shifter for supplying a source voltage to a bias supply node of a nonvolatile memory portion of each nonvolatile memory cell belonging to the row in response to the address match detection signal;
After a predetermined time has elapsed since the first address match detection signal after the power supply voltage for the nonvolatile memory rises, turn on the power switch of the volatile storage unit of each nonvolatile memory cell belonging to the row A third level shifter for outputting a selection signal to be
18. The nonvolatile memory according to claim 17, wherein an output voltage of the output adjustment circuit is supplied to the first to third level shifters as a high-potential side power supply voltage. Each volatile memory portion of each nonvolatile memory cell of the nonvolatile memory cell array has a power switch interposed between the flip-flop and a power supply line that supplies a low-potential-side power supply voltage to the flip-flop. And
In the nonvolatile memory cell array, each power supply line for supplying a high potential side power supply voltage and a low potential side power supply voltage to the flip-flops of the nonvolatile memory cells in each column is wired in the column direction,
The row decoder turns on the power switch of each volatile memory unit of each nonvolatile memory cell belonging to the row in order to perform the recall for each nonvolatile memory cell belonging to the selected row. The nonvolatile memory according to claim 9, wherein a power supply voltage for a flip-flop of the volatile storage unit is raised. A booster circuit that boosts and outputs a power supply voltage for the nonvolatile memory, a step-down circuit that steps down and outputs a power supply voltage for the nonvolatile memory, an output voltage of the booster circuit, an output voltage of the step-down circuit, or the nonvolatile memory A power supply control circuit having an output adjustment circuit that selects and outputs a power supply voltage for the memory,
The row decoder has a plurality of row selection circuits associated with each row of the nonvolatile memory cell array,
Each row selection circuit corresponding to each row
An address match detection circuit that outputs an address match detection signal when the row address indicates the row;
A first level shifter for outputting an activation signal for turning on the third and fourth switches of the nonvolatile memory portion of each nonvolatile memory cell belonging to the row in response to the address match detection signal;
A second level shifter for supplying a source voltage to a bias supply node of a nonvolatile memory portion of each nonvolatile memory cell belonging to the row in response to the address match detection signal;
After a predetermined time has elapsed since the first address match detection signal after the power supply voltage for the nonvolatile memory rises, turn on the power switch of the volatile storage unit of each nonvolatile memory cell belonging to the row And a buffer for outputting a selection signal to be
The nonvolatile memory according to claim 19, wherein an output voltage of the output adjustment circuit is supplied to the first and second level shifters as a high-potential side power supply voltage.

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