JP5938887B2 - Nonvolatile memory cell and nonvolatile memory - Google Patents

Description

  The present invention relates to a nonvolatile memory cell using a resistance variable element and a nonvolatile memory including the nonvolatile memory cell.

  In recent years, a resistance change type memory for storing data using a resistance change type element has attracted attention as a next-generation non-volatile memory in place of a flash memory or a DRAM that has become limited in miniaturization. Examples of the resistance change element include MRAM (Magnetoretic Random Access Memory), PRAM (Phase change Random Access Memory), ReRAM (Resistance Random Access Memory). The thing that is. A memory using such a resistance variable element does not require a complicated process like a flash memory, is compatible with a standard logic process, is suitable for miniaturization, and operates at a low voltage. The future is promising.

  The element configuration, characteristics, and array configuration of a memory using this type of variable resistance element are disclosed in Non-Patent Document 1, for example. This non-patent document 1 relates to an MRAM, but discloses a memory cell having a simple configuration including one transistor and one resistance variable element. According to Non-Patent Document 1, this memory cell can be written and read at a low voltage of 1.2 V, the write current is 49 μA, and the memory cell from the high resistance state in which data “1” is stored. The read current is 10 μA, and the read current from the memory cell in the low resistance state in which data “0” is stored is 15 μA. Thus, low power consumption can be realized. Further, according to FIG. 1 of Non-Patent Document 1, it is likely that the write voltage to the memory cell can be lowered to about ± 0.6V.

  FIGS. 23A and 23B are diagrams showing the configuration and operation of a memory cell using a typical MTJ (Magnetic Tunnel Junction) element as a resistance variable element. As shown in FIG. 23, the MTJ element includes a pinned layer having a constant magnetic direction, a tunnel barrier film, and a free layer whose magnetic direction changes. As shown in FIG. 23A, when a current in a direction from the free layer to the pinned layer is passed, the magnetization direction of the free layer becomes the same as that of the pinned layer, the MTJ element has a low resistance, and data “0” is stored. It becomes a state. On the other hand, as shown in FIG. 23B, when a current in the direction from the pinned layer to the free layer is passed, the magnetization direction of the free layer is opposite to that of the pinned layer, the MTJ element becomes high resistance, and data “1” "Is stored. When a memory cell is configured with such an MTJ element, a transistor Ts is connected in series to the MTJ element as a switch for selecting the MTJ element, as illustrated in FIGS. .

  FIG. 24 is a diagram illustrating a cross-sectional structure of a memory array including memory cells as shown in FIGS. 23 (a) and 23 (b). In the example shown in FIG. 24, the selection transistor Ts shown in FIGS. 23A and 23B is formed on a semiconductor substrate. A selection voltage WL is applied to the gate of each transistor Ts. The source of the transistor Ts is connected to the second layer metal wiring 2M for supplying the write voltage BL via the through hole and the first layer metal wiring 1M. The drain of the transistor Ts is connected to the pin layer of the MTJ element through a through hole, and the free layer of the MTJ element is connected to the second layer metal wiring 2M for supplying the source voltage SL through the through hole. Has been.

  Patent Document 1 discloses a rewritable nonvolatile RAM using a resistance variable element. In the nonvolatile RAM of Patent Document 1, a phase change memory element is used as a resistance change element.

  FIG. 25 is a circuit diagram showing the configuration of the memory cell of the nonvolatile RAM disclosed in FIG. In FIG. 25, a flip-flop is constituted by an inverter composed of a P-channel transistor P0 and an N-channel transistor N0 and an inverter composed of a P-channel transistor P1 and an N-channel transistor N1. An output node S0 of the inverter composed of the P channel transistor P0 and the N channel transistor N0 is connected to the bit line BL0 via the N channel transistor Na0. The output node S1 of the inverter composed of the P channel transistor P1 and the N channel transistor N1 is connected to the bit line BL1 via the N channel transistor Na1. The selection voltage WL is applied to the N channel transistors Na0 and Na1. The above circuit is a normal SRAM memory cell. In the memory cell shown in FIG. 25, phase change memory elements Rr and Rm and an N-channel transistor Ns are added to the SRAM memory cell. Here, phase change memory element Rr is interposed between the source of P channel transistor P0 and power supply line PWR, and phase change memory element Rm is interposed between the source of P channel transistor P1 and power supply line PWR. N-channel transistor Ns is interposed between the connection point of P-channel transistor P1 and phase change memory element Rm and store line STR, and the voltage of node S0 is applied to its gate.

  According to Patent Document 1, one of the phase change memory elements (Rr) is a reference (reference) resistance, and the other one of the phase change memory (logic storage resistance Rm) changes with a high resistance (logic value 1) and a low resistance. A resistance value between (logical value 0) is set in advance. The logic memory resistor Rm is applied with a current causing a phase change by the power supply line PWR, the switching element (transistor Ns), and the store line STR. At the time of reading, the SRAM circuit portion indicated by the dotted line is operated as a normal SRAM. The logical storage resistance Rm during this operation is set to a low resistance value. Then, before the power is turned off, the voltage of the store line STR is changed, and a current is passed through the logic storage resistor Rm by the transistor Ns, thereby transferring the logic value stored in the SRAM circuit portion (store). When the power is turned on, the stored contents transferred to the phase change memory element Rm are returned to the SRAM circuit section (recall). As described above, when the power is turned off (OFF) and turned on (ON), the memory contents are transferred and returned by the logical storage resistor Rm of the phase change memory and the SRAM circuit unit, thereby operating as a nonvolatile memory. (See paragraphs 0012 and 0013 of Patent Document 1).

Japanese Patent No. 3845734

IEICE IEICE technical report ICEC Technical Report ICD2010-7 p35-p40

The nonvolatile RAM of Patent Document 1 described above has several problems. First, in the nonvolatile RAM of Patent Document 1, a phase change memory element is used as a resistance change type element. This phase change memory element is a so-called monopolar type resistance change element, and data “1” is stored. It is necessary to pass current in the same direction when writing data or when writing data “0”. This complicates the control for writing data. In addition, the phase change memory element cannot be rewritten at high speed because the write characteristic and the erase characteristic are greatly different. Also, as shown in FIG. 25, in the nonvolatile RAM of Patent Document 1, phase change memory elements (Rr and Rm) whose resistance values change are inserted on the power supply current paths of the two inverters constituting the flip-flop. Has been. For this reason, the flip-flop becomes unbalanced, and has a great adverse effect on the SNM (Static Noise Margin), which is the most important characteristic of the SRAM.
Hereinafter, this adverse effect on the SNM will be described.

  FIG. 26 is a circuit diagram showing a configuration of a general SRAM memory cell. In the illustrated example, one memory cell is constituted by P-channel transistors P1 and P2 and N-channel transistors N1, N2, Ta1, and Ta2.

  27A to 27D illustrate the SNM characteristics of the memory cell shown in FIG. 27A to 27D, the horizontal axis represents the voltage V0 at the common connection point of the transistors P1 and N1, and the vertical axis represents the voltage V1 at the common connection point of the transistors P2 and N2.

  In FIGS. 27A to 27D, the dashed curve and the solid curve are each called a butterfly curve. These two butterfly curves cross each other on the way, and the positional relationship between the top and bottom and the left and right is switched. In each of FIGS. 27A to 27D, two squares are drawn that fit in two regions sandwiched between a broken butterfly curve and a solid butterfly curve. The size of this square is the size of the SNM. More specifically, the square between the two butterfly curves in the region where the broken butterfly curve is at the upper right and the solid butterfly curve is at the lower left is a noise that increases the voltage V0 at the connection point of the drains of the transistors P1 and N1. When this occurs, it is an SNM (hereinafter referred to as a first SNM for convenience) indicating an allowable value of the noise level that does not invert the stored contents of the memory cell. The square between the two butterfly curves in the region where the solid butterfly curve is at the upper right and the broken butterfly curve is at the lower left is when noise that raises the voltage V1 at the connection point of the drains of the transistors P2 and N2 occurs. , An SNM (hereinafter referred to as a second SNM for convenience) indicating an allowable value of the noise level that does not invert the stored contents of the memory cell.

  FIGS. 27A and 27C illustrate the SNM characteristics when the power supply voltage VDD of the SRAM is 1.0 V, respectively. In the example shown in FIG. 27A, the beta value β and the threshold voltage Vt of each transistor constituting the memory cell are balanced, the first SNM and the second SNM are approximately the same, and Is also large enough. Therefore, in this memory cell, stable write access and read access are possible.

  However, the butterfly curve depends on the balance of the beta values and the threshold voltage of each of the transistors P1, N1, P2, and N2. For example, in FIG. 27A, when the beta ratio βp / βn between the beta value βp of the transistor P2 and the beta value βn of the transistor N2 becomes higher, the broken butterfly curve projects in the upper right direction. Conversely, when the beta ratio βp / βn decreases, the broken butterfly curve retreats in the lower left direction. Further, when the threshold voltage Vtn of the transistor N2 increases and the threshold voltage Vtp of the transistor P2 decreases, the voltage V0 at which the broken butterfly curve suddenly falls increases. Conversely, when the threshold voltage Vtn of the transistor N2 decreases and the threshold voltage Vtp of the transistor P2 increases, the voltage V0 at which the broken butterfly curve suddenly falls decreases.

  Further, in the process of increasing the voltage V0 from 0V to VDD, when the transistor N2 is turned on, a current flows into the transistor N2 via the transistor Ta2. Therefore, the voltage V1 does not fall down to the VSS level (0V), but the VSS level. Float from. If the current flowing through the transistor Ta2 is constant, the floating of the voltage V1 from the VSS level at this time increases as the threshold voltage Vtn of the transistor N2 is higher or the beta value βn of the transistor N2 is lower.

  Thus, the broken butterfly curve is affected by changes in threshold voltages and beta values of the transistors P2 and N2. On the other hand, the solid butterfly curve is mainly affected by changes in the balance of the beta values and the balance of the threshold voltages of the transistors P1 and N1. Thus, since the butterfly curve is affected by changes in the threshold voltage and beta value of each transistor, the first and second SNMs are also affected by changes in the threshold voltage and beta value of each transistor.

  In the example shown in FIG. 27C, an imbalance occurs between the threshold voltage Vt or the beta value of each transistor constituting the memory cell, and the first SNM is sufficiently large, but the second SNM Is slightly smaller.

  As described above, when the characteristics (specifically, the threshold voltage VT and the beta value) of the transistors constituting the memory cell vary, the sizes of the first and second SNMs vary.

  Further, when the power supply voltage VDD of the SRAM is reduced, the degree of influence on the first and second SNMs of the characteristic variation of each transistor constituting the memory cell is increased. FIGS. 27B and 27D show examples thereof. In the examples of FIGS. 27B and 27D, the power supply voltage VDD of the SRAM is 0.5V. In the example shown in FIG. 27B, since the power supply voltage VDD is 0.5 V, the first and second SNMs are considerably small. However, the characteristics of the transistors constituting the memory cell are balanced. Therefore, the first and second SNMs are sized to enable normal write access and read access. However, in the example shown in FIG. 27 (d), there is a delicate imbalance in the characteristics of the transistors constituting the memory cell, and the second SNM is almost eliminated due to the influence. As described above, when the operation margin is insufficient, the write access and the read access are hindered.

  When an imbalance occurs in the characteristics of the transistors constituting the memory cell in this way, the SNM of the SRAM is adversely affected, particularly when the power supply voltage VDD is low.

  However, in the technique of Patent Document 1, phase change memory elements whose resistance values change are respectively inserted in power supply current paths of two inverters constituting such SRAM memory cells. When such a phase change memory element is interposed, the transistors P0 and N0 constituting one inverter and the transistors P1 and N1 (see FIG. 25) constituting the other inverter are unbalanced in bias conditions. As a result, the characteristics of the transistors constituting each inverter are unbalanced, and the SNM of the memory cell is greatly deteriorated. The above is the analysis of the static operation of the SRAM. In addition, considering the dynamic operation, the gate capacitance of the transistor Ns is added to the node S0, and the capacitance is unbalanced between the node S0 and the node S1. This capacity imbalance reduces the dynamic operating margin.

  The present invention has been made in view of the circumstances described above, and a first object thereof is to rewrite the stored data in the volatile storage unit and to store the stored data in the nonvolatile storage unit without impairing the function as the SRAM. It is an object of the present invention to provide a non-volatile memory cell and a non-volatile memory that can easily perform a store operation for writing data and a recall operation for writing data from a non-volatile storage unit to a volatile storage unit. A second object of the present invention is to provide a non-volatile memory cell and a non-volatile memory that are resistant to variations in characteristics of elements constituting the cell. A third object of the present invention is to provide a nonvolatile memory cell and a nonvolatile memory that can operate at high speed with a small number of elements (small area).

  The present invention includes a volatile storage unit and a nonvolatile storage unit, and the volatile storage unit includes a flip-flop composed of first and second inverters each having an output signal of the other party as an input signal, A first switch interposed between an output node of the first inverter and a bit line; a second switch interposed between an output node of the second inverter and an inverted bit line; And the nonvolatile memory section includes a third switch and a first resistance variable element inserted in series between an output node of the first inverter and the bit line, and the second resistance element. A fourth switch and a second variable resistance element interposed in series between the output node of the inverter and the inverted bit line, wherein the first and second variable resistance elements are: The bit line and the inversion bit The third and fourth switches are respectively provided on the output node side of the first inverter and the output node side of the second inverter, and the first and second resistors are provided on the line side, respectively. Each of the variable elements has a resistance value that changes in a first direction when a current from an output node of the first or second inverter to the bit line or the inverted bit line is passed, and the bit line or A resistance change element whose resistance value changes in a second direction opposite to the first direction when a current from an inverted bit line to the output node of the first or second inverter is passed. A non-volatile memory cell is provided.

  According to this invention, the first and second switches are turned OFF, the third and fourth switches are turned ON, and two types of data for expressing data “1” / “0” on the bit line and the inverted bit line are provided. By applying a voltage intermediate between the voltages, currents corresponding to the data stored in the volatile storage unit and flowing in opposite directions to the first and second variable resistance elements are supplied to the first and second resistance change elements. Each resistance value of the resistance variable element can be changed in the opposite direction (store operation). In this case, the magnitude relationship between the resistance values of the first and second variable resistance elements represents the data stored in the nonvolatile storage unit.

  When the first and second switches are turned OFF, the third and fourth switches are turned ON, and 0 V is applied to the bit line and the inverted bit line to raise the power supply voltage to the flip-flop of the volatile memory portion, Between the current to the output node of the first inverter and the current to the output node of the second inverter, the storage data (the resistance values of the first and second resistance change elements) A difference in accordance with the magnitude relationship) is generated, and the storage data of the nonvolatile storage unit can be written into the volatile storage unit (recall operation).

  If the third and fourth switches are turned OFF, the first and second resistance change elements can be disconnected from the volatile storage unit, and the volatile storage unit can be operated as a normal SRAM memory cell. . In this case, a high SNM can be obtained because the volatile storage unit is not connected to any extra circuit or parasitic capacitance that impairs its function.

  Therefore, according to the present invention, the data stored in the volatile storage unit is rewritten, the stored data is written in the nonvolatile storage unit, and the data is transferred from the nonvolatile storage unit to the volatile storage unit without impairing the function as the SRAM. It is possible to realize a nonvolatile memory cell and a nonvolatile memory that can easily perform a recall operation for writing. In the present invention, in the nonvolatile memory unit, the magnitude relationship between the resistance values of the two resistance variable elements indicates stored data. At the time of storing, currents in opposite directions are passed through the first and second resistance variable elements, and the resistance values of the first and second resistance variable elements are changed in opposite directions. Therefore, even when the characteristic variation of the resistance variable element is large, the magnitude relationship between the resistance values of the first and second resistance variable elements at the time of storing is set to a magnitude relation corresponding to the storage data of the volatile storage unit. Can do. Therefore, according to the present invention, it is possible to realize a nonvolatile memory cell and a nonvolatile memory that are resistant to variations in characteristics of elements constituting the cell.

  In addition, according to the present invention, the number of elements of the nonvolatile memory portion provided in the nonvolatile memory cell is small, and the current flowing through the resistance variable element at the time of storing and recalling is small, so the area is small and inexpensive. A non-volatile memory chip can be realized.

  In a preferred embodiment, an MTJ element or a resistance element that generates an electric field induced giant resistance change is used as the resistance change element. According to this aspect, store and recall can be performed at high speed.

  The positional relationship between the first variable resistance element and the third switch and the positional relationship between the second variable resistance element and the fourth switch may be interchanged. Also in this case, a store operation similar to the above can be obtained. At the time of recall, the same recall operation as described above can be obtained by applying the higher one of the two kinds of voltages for expressing data “1” / “0” to the bit line and the inverted bit line. .

  In another preferred embodiment, a nonvolatile memory including a nonvolatile memory cell array composed of nonvolatile memory cells according to the present invention includes a booster circuit that boosts and outputs a power supply voltage. The output voltage of the booster circuit is used as a power supply voltage for the flip-flop and a write voltage for turning on the third and fourth switches. Therefore, the power supply voltage for the non-volatile memory can be set to a minimum voltage at which the SRAM can be operated.

1 is a circuit diagram showing a configuration of a nonvolatile memory cell according to a first embodiment of the present invention. FIG. FIG. 3 is a diagram showing a first operating condition of the nonvolatile memory cell. It is a figure which shows the 2nd operating condition of the non-volatile memory cell. It is a circuit diagram which shows the structure of the non-volatile memory cell which is 2nd Embodiment of this invention. It is a figure which shows the operating condition of the non-volatile memory cell. It is a circuit diagram which shows the structure of the non-volatile RAM which is 3rd Embodiment of this invention. It is a circuit diagram which shows the specific structural example of the non-volatile RAM. It is a circuit diagram which shows the structural example of the row selection circuit of the non-volatile RAM. It is a block diagram which shows the structural example of the control part of the non-volatile RAM. It is a time chart which shows the store operation | movement of the embodiment. It is a time chart which shows the recall operation | movement of the embodiment. It is a time chart which shows the division | segmentation store operation | movement performed in the non-volatile RAM which is 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile RAM which is 5th Embodiment of this invention. It is a circuit diagram which shows the structural example of the row selection circuit suitable for the non-volatile RAM. 3 is a circuit diagram showing a circuit for generating a signal WREB in the nonvolatile RAM. FIG. It is a time chart which shows the recall operation | movement of the embodiment. It is a circuit diagram which shows the structure of the non-volatile RAM which is 6th Embodiment of this invention. It is a circuit diagram which shows the structure of the non-volatile RAM which is 7th Embodiment of this invention. It is a circuit diagram which shows the structure of the row selection circuit and nonvolatile memory cell for one row in the nonvolatile RAM which is 8th Embodiment of this invention. It is a figure which shows the operating condition of the embodiment. It is a circuit diagram which shows the structure of the row selection circuit for one row and nonvolatile memory cell in the nonvolatile RAM which is 9th Embodiment of this invention. It is a circuit diagram which shows the structure of the row selection circuit and nonvolatile memory cell for one row in the nonvolatile RAM which is 10th Embodiment of this invention. It is a figure which shows the structure and operation | movement of an MTJ element. It is a figure which illustrates the cross-sectional structure of the memory cell using an MTJ element. It is a circuit diagram which shows the structural example of the conventional non-volatile memory cell. 1 is a circuit diagram showing a configuration of a general SRAM memory cell; FIG. It is a figure which illustrates the static noise margin of the memory cell.

  Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the transistor refers to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor; field-effect transistor having a metal-oxide film-semiconductor structure).

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a nonvolatile memory cell 10 according to the first embodiment of the present invention. The nonvolatile memory cell 10 includes a volatile storage unit 11 and a nonvolatile storage unit 12. The volatile storage unit 11 has a configuration similar to that used as a memory cell in a normal SRAM.

  More specifically, the volatile memory unit 11 includes an inverter INV1 composed of a P-channel transistor P1 and an N-channel transistor N1, an inverter INV2 composed of a P-channel transistor P2 and an N-channel transistor N2, and first and second switches. N-channel transistors Ta1 and Ta2. Here, the inverters INV1 and INV2 use the output signals of the other party as input signals for each other, and constitute a flip-flop. This flip-flop is interposed between a power supply line for supplying the high potential side power supply voltage VDC and a power supply line for supplying the low potential side power supply voltage VSS. The N channel transistor Ta1 is interposed between the output node V1 of the inverter INV1 and the bit line BL. The N channel transistor Ta2 is interposed between the output node V2 of the inverter INV2 and the inverted bit line BLB. These N-channel transistors Ta1 and Ta2 are turned on when the row selection voltage WL becomes an active level. As a result, data can be written to the flip-flop of the volatile memory unit 11 via the bit line BL and the inverted bit line BLB, and data can be read from the flip-flop of the volatile memory unit 11 to the bit line BL and the inverted bit line BLB. become.

  The nonvolatile memory unit 12 includes an N-channel transistor Tw1 and a resistance variable element R1 as a third switch inserted in series between the output node V1 of the inverter INV1 and the bit line BL, and an output node of the inverter INV2. It has an N-channel transistor Tw2 and a resistance variable element R2 as a fourth switch inserted in series between V2 and the inverted bit line BLB. Here, the N-channel transistor Tw1 has a source connected to the output node V1 of the inverter INV1, and a drain connected to one end of the resistance variable element R1. The other end of the resistance variable element R1 is connected to the bit line BL. The N-channel transistor Tw2 has a source connected to the output node V2 of the inverter INV2, and a drain connected to one end of the resistance variable element R2. The other end of the resistance variable element R2 is connected to the inverted bit line BLB. A write voltage WRE is applied to the gates of N-channel transistors Tw1 and Tw2.

  Each of resistance change elements R1 and R2 passes a reverse current from the output node of inverter INV1 (INV2) to bit line BL (inverted bit line BLB) while N-channel transistors Tw1 and Tw2 are ON. When the resistance value changes in a first direction (for example, an increasing direction), a forward current from the bit line BL (inverted bit line BLB) to the output node of the inverter INV1 (INV2) is passed. The resistance change element has a resistance value that changes in a second direction (for example, a decreasing direction) opposite to the first direction. In the nonvolatile memory unit 12, the magnitude relationship between the resistance variable elements R1 and R2 represents “1” / “0” of the stored data.

  As an example, the resistance variable elements R1 and R2 are spin injection MTJ elements. Here, when the resistance variable elements R1 and R2 are spin injection MTJ elements, the pin layer of the spin injection MTJ element, which is the resistance variable element R1, is the drain of the N-channel transistor Tw1, and the free layer is the bit line BL. The pin layer of the spin injection MTJ element, which is the resistance variable element R2, is connected to the drain of the N-channel transistor Tw2, and the free layer is connected to the inverted bit line BLB. By doing so, the resistance change characteristics of the resistance change elements R1 and R2 as described above can be obtained.

  Alternatively, CER (Corrosive Electro-Resistance) resistance elements used in ReRAM memory cells may be used as the resistance change elements R1 and R2.

  In the present embodiment, a store for writing data stored in the volatile storage unit 11 to the nonvolatile storage unit 12 and a recall for writing the data stored in the nonvolatile storage unit 12 to the volatile storage unit 11 are possible. In the present embodiment, in order to perform this store and recall, the N-channel transistors Tw1 and Tw2 are turned on by an appropriate level of the write voltage WRE, and the resistance variable elements R1 and R2 are connected to the inverter INV1 of the volatile storage unit 11. Output node V1 and inverter INV2 output node V2.

  FIG. 2 shows operating conditions when the nonvolatile memory cell 10 is operated with a power supply voltage of 1.2V. Hereinafter, the operation of the present embodiment will be described with reference to FIG. In the example shown in FIG. 2, the high potential side power supply voltage VDC is 1.2V, and the low potential side power supply voltage VSS is 0V. When the nonvolatile memory cell 10 is operated as a normal SRAM memory cell, the write voltage WRE is set to 0V. As a result, the N-channel transistors Tw1 and Tw2 are turned off, and the resistance variable elements R1 and R2 are disconnected from the volatile storage unit 11. In this state, the volatile storage unit 11 can be accessed via the bit lines BL and BLB.

  FIG. 2 shows operating conditions for reading data from the volatile storage unit 11. In order to read data from the volatile storage unit 11, the row selection voltage WL is set to 1.2 V, and the N-channel transistors Ta1 and Ta2 are turned on. When the data “1” is stored in the volatile storage unit 11, the voltage of about 1.2 V at the output node V1 of the inverter INV1 is applied to the bit line BL, and the voltage of about 0 V at the output node V2 of the inverter INV2 is applied. Read to the bit line BLB. Further, when data “0” is stored in the volatile storage unit 11, the voltage of about 0 V of the output node V1 of the inverter INV1 is applied to the bit line BL, and the voltage of about 1.2 V of the output node V2 of the inverter INV2 is applied. Read to the bit line BLB. Although not shown, when data is written to the volatile storage unit 11, voltages corresponding to write data are applied from the bit lines BL and BLB to the output node V1 of the inverter INV1 and the output node V2 of the inverter INV2. Each is applied, and write data is held in a flip-flop formed of inverters INV1 and INV2.

  When the power of the nonvolatile memory cell 10 is turned off, a store for transferring the data stored in the volatile storage unit 11 to the nonvolatile storage unit 12 is performed prior to the power-off. In the example shown in FIG. 2, the row selection voltage WL is 0V, the write voltage WRE is 1.5V, and the voltage for the bit line BL and the inverted bit line BLB is 0.6V. Here, the voltage of 1.5V is generated by boosting the power supply voltage of 1.2V, and the voltage of 0.6V is generated by stepping down the power supply voltage.

  The write voltage WRE is set to 1.5 V for the following reason. First, for example, assume that the voltage at the output node V1 of the inverter INV1 is 0V, and the voltage at the output node V2 of the inverter INV2 is 1.2V. In this case, if the write voltage WRE is set to 1.2 V, which is the same as the power supply voltage, the maximum value of the voltage that can be applied to the resistance variable element R2 is the write voltage WRE = 1.2 V and the inverted bit line BLB. The voltage is reduced by the threshold value of the N-channel transistor Tw2 from the difference of 0.6V from the voltage of 0.6V. Conversely, when the voltage at the output node V1 of the inverter INV1 is 1.2V and the voltage at the output node V2 of the inverter INV2 is 0V, the maximum value of the voltage that can be applied to the resistance variable element R1 is the write voltage. The voltage is reduced by the threshold value of the N-channel transistor Tw1 from the difference of 0.6V between WRE = 1.2V and the voltage of the bit line BL of 0.6V. Such a decrease in the voltage applied to the resistance variable elements R1 and R2 is not preferable because it prevents a reliable store operation.

  In addition, the resistances of the N-channel transistors Tw1 and Tw2 need to be reduced in order to cause a sufficient current that causes a change in the resistance value of the resistance variable elements R1 and R2 to flow through each resistance variable element. Therefore, the write voltage WRE is set to 1.5V which is higher than the power supply voltage 1.2V.

  When the 1.5V write voltage WRE is output and the N-channel transistors Tw1 and Tw2 are turned on, the nonvolatile memory unit 12 performs a store operation. Here, in a state where data “1” is stored in the volatile storage unit 11, the voltage of the output node V 1 of the inverter INV 1 is 1.2 V, and the voltage of the output node V 2 of the inverter INV 2 is 0 V. In this state, when the N-channel transistors Tw1 and Tw2 are turned on, a reverse current from the output node V1 (1.2V) of the inverter INV1 to the bit line BL (0.6V) flows to the resistance variable element R1. The resistance value of the variable element R1 increases. Further, a forward current from the bit line BLB (0.6 V) toward the output node V2 (0 V) of the inverter INV2 is applied to the resistance variable element R2, and the resistance value of the resistance variable element R2 decreases. As described above, by storing the data “1”, the resistance variable element R1 of the nonvolatile memory unit 12 becomes high resistance and the resistance variable element R2 becomes low resistance.

  On the other hand, in a state where data “0” is stored in the volatile storage unit 11, the voltage of the output node V1 of the inverter INV1 is 0V, and the voltage of the output node V2 of the inverter INV2 is 1.2V. In this state, when the N-channel transistors Tw1 and Tw2 are turned on, a forward current from the bit line BL (0.6 V) toward the output node V1 (0 V) of the inverter INV1 flows to the resistance variable element R1, and the resistance variable type The resistance value of the element R1 decreases. Further, a reverse current from the output node V2 (1.2V) of the inverter INV2 toward the inverted bit line BLB (0.6V) flows to the resistance variable element R2, and the resistance value of the resistance variable element R2 increases. Thus, by storing data “0”, the resistance variable element R1 of the nonvolatile memory unit 12 becomes low resistance, and the resistance variable element R2 becomes high resistance.

  When the MTJ element of Non-Patent Document 1 is used as the resistance variable elements R1 and R2, if the applied voltage to the resistance variable element can be secured to 0.6 V or more, the store can be performed, and the current flows to the resistance variable element at that time. The current is 49 μA.

  Next, a recall operation for writing data stored in the nonvolatile storage unit 12 to the volatile storage unit 11 will be described. In the recall operation, the row selection voltage WL is set to 0 V, and the N-channel transistors Ta1 and Ta2 are turned off. Further, the N-channel transistors Tw1 and Tw2 are turned on by setting the write voltage WRE to 0.5 V, and the resistance variable elements R1 and R2 are respectively connected to the output node V1 of the inverter INV1 and the output node V2 of the inverter INV2 Connecting. Here, the reason why the write voltage WRE is set to 0.5 V, which is lower than the power supply voltage for the volatile storage unit 11, is that the current flowing through the resistance variable elements R1 and R2 is limited during the recall operation to reduce power consumption. This is to prevent an excessive voltage from being applied to the resistance variable elements R1 and R2 in order to prevent erroneous writing.

  In the recall operation, the voltage for the bit lines BL and BLB is set to the lower one of the two voltages for expressing the data “1” / “0” in the volatile storage unit 11, specifically 0 V. The high-potential-side power supply voltage VDC for the nonvolatile memory cell 10 is increased from 0V to 1.2V while maintaining the write voltage WRE at 0.5V.

  When the nonvolatile storage unit 12 stores data “1”, the resistance variable element R1 has a high resistance and the resistance variable element R2 has a low resistance. In this state, when the high-potential-side power supply voltage VDC increases from 0 V to 1.2 V, the output node of the inverter INV2 is more than the current flowing from the output node V1 of the inverter INV1 to the bit line BL via the resistance variable element R1. Since the current flowing from V2 to the inverted bit line BLB via the resistance variable element R2 becomes larger, the voltage at the output node V1 becomes higher than the voltage at the output node V2. As a result, in the volatile storage unit 11, the output node V1 of the inverter INV1 is at the high level and the output node V2 of the inverter INV2 is at the low level, and this state is maintained. That is, the data “1” is stored in the volatile storage unit 11 and the recall of the data “1” is completed. At this time, if the MTJ element of Non-Patent Document 1 is used, the currents flowing through the resistance variable elements R1 and R2 are about 10 μA and 15 μA, respectively.

  On the other hand, when the nonvolatile storage unit 12 stores data “0”, the resistance variable element R1 has a low resistance and the resistance variable element R2 has a high resistance. In this case, when the high potential side power supply voltage VDC is raised from 0 V to 1.2 V in order to perform the recall, the current flowing from the output node V1 of the inverter INV1 toward the bit line BL via the resistance variable element R1 is increased. Since the current flowing from the output node V2 of the inverter INV2 toward the inverted bit line BLB via the resistance change element R2 is smaller, the voltage of the output node V2 is higher than the voltage of the output node V1. As a result, the volatile storage unit 11 maintains the state in which the output node V1 of the inverter INV1 is at the low level and the output node V2 of the inverter INV2 is at the high level. That is, the data “0” is stored in the volatile storage unit 11 and the recall of the data “0” is completed.

  When the recall is completed, the write voltage WRE is set to 0 V, and the resistance variable elements R1 and R2 are disconnected from the volatile storage unit 11. Thereby, the operation as the SRAM is started. In this state, the volatile storage unit 11 has the same configuration as that of a 6Tr configuration SRAM memory cell having complete symmetry, and thus a wide SNM can be obtained.

  FIG. 3 shows operating conditions when the nonvolatile memory cell 10 is operated at an extremely low power supply voltage of 0.6V. When the nonvolatile memory cell 10 is operated as a normal SRAM memory cell, the high-potential-side power supply voltage VDC for the nonvolatile memory cell 10 may be 0.6V. However, when storing, the high-potential-side power supply voltage VDC for the nonvolatile memory cell 10 is set to 1.2V, and the write voltage WRE is set to 1.5V. In this case, since the power supply voltage for the memory chip on which the nonvolatile memory cell 10 is mounted is 0.6 V, the high-potential-side power supply voltage VDC and the write voltage WRE are generated by boosting this power supply voltage. The store operation is the same as in FIG.

  Next, the recall operation will be described. In the recall operation, the write voltage WRE is set to 0.3V. The reason why the write voltage WRE is set to 0.3V is to reduce the current consumption of the resistance variable elements R1 and R2 as much as possible because the power supply voltage of the memory chip is as low as 0.6V and the ultra low power consumption is aimed at. is there. However, there is no problem in operation even when the write voltage WRE at the time of recall is set to 0.6 V as shown in FIG.

  Next, in this state, the high potential side power supply voltage VDC is raised from 0V to 0.6V. Here, when the nonvolatile storage unit 12 stores data “1”, since the resistance variable element R1 has a high resistance and the resistance variable element R2 has a low resistance, the output is the same as in FIG. The node V1 becomes High, the output node V2 becomes Low, and the data “1” is held in the volatile storage unit 11. The operation in the case where the nonvolatile storage unit 12 stores data “0” at the time of recall is the same.

  When the recall is completed, the write voltage WRE is set to 0 V, and the resistance variable elements R1 and R2 are separated from the volatile storage unit 11. Thus, the volatile memory unit 11 operates as a normal SRAM memory cell in response to the supply of the power supply voltage VDC = 0.6V.

Second Embodiment
FIG. 4 is a circuit diagram showing a configuration of a nonvolatile memory cell 10A according to the second embodiment of the present invention. The nonvolatile memory cell 10A includes a volatile storage unit 11 and a nonvolatile storage unit 12A similar to those of the first embodiment. Here, the nonvolatile memory unit 12A has a configuration in which the positional relationship between the N-channel transistor Tw1 and the resistance variable element R1 and the positional relationship between the N-channel transistor Tw2 and the resistance variable element R2 in the first embodiment are interchanged. It has become. More specifically, when the variable resistance elements R1 and R2 are, for example, spin injection type MTJ elements, in the nonvolatile memory unit 12A, the variable resistance element R1 (R2) is connected to the output node V1 (V2) of the inverter INV1 (INV2). ) Of the N channel transistor Tw1 (Tw2) is connected to the pin layer of the variable resistance element R1 (R2), and the source of the N channel transistor Tw1 (Tw2) is connected to the bit line BL (inverted). Bit line BLB).

  FIG. 5 is a diagram exemplifying operating conditions for operating the nonvolatile memory cell 10A in the present embodiment with a power supply voltage of 0.6V. In this embodiment, when writing to the resistance variable elements R1 and R2, a power supply voltage of 1.2V is required. Therefore, the power supply voltage VDD = 0.6V of the chip is boosted by a booster circuit and is nonvolatile. A power supply voltage VDC = 1.2V and a write voltage WRE = 1.5V are generated for the memory cell 10A. As shown in FIG. 2, when the power supply voltage VDD of the chip is 1.2V, the power supply voltage VDD may be used as the power supply voltage VDC for the nonvolatile memory cell 10A without boosting.

  In the store operation, the row selection voltage WL is set to 0V, the N-channel transistors Ta1 and Ta2 are turned OFF, the write voltage WRE is set to 1.5V, and the N-channel transistors Tw1 and Tw2 are turned ON. Further, the voltage for the bit line BL and the inverted bit line BLB is an intermediate between two kinds of voltages (that is, 1.2V and 0V) used for expressing the data “1” / “0” in the volatile memory unit 11. The voltage is 0.6V.

  When data “1” is stored in the volatile storage unit 11, the voltage of the output node V1 of the inverter INV1 is 1.2V, and the voltage of the output node V2 of the inverter INV2 is 0V. In this state, when the N-channel transistors Tw1 and Tw2 are turned on, a forward current from the output node V1 (1.2V) of the inverter INV1 toward the bit line BL (0.6V) flows to the resistance variable element R1, and the resistance The variable element R1 has a low resistance. Further, a reverse current from the inverted bit line BLB (0.6 V) toward the output node V2 (0 V) of the inverter INV2 flows through the resistance variable element R2, and the resistance variable element R2 becomes high resistance.

  On the other hand, when data “0” is stored in the volatile storage unit 11, the voltage of the output node V1 of the inverter INV1 is 0V, and the voltage of the output node V2 of the inverter INV2 is 1.2V. In this state, when the N-channel transistors Tw1 and Tw2 are turned on, a reverse current from the bit line BL (0.6V) toward the output node V1 (0V) of the inverter INV1 flows to the resistance variable element R1, and the resistance variable The element R1 has a high resistance. Further, a forward current from the output node V2 (1.2V) of the inverter INV2 toward the inverted bit line BLB (0.6V) flows to the resistance variable element R2, and the resistance variable element R2 has a low resistance.

  Next, the recall operation will be described. At the time of recall, the row selection voltage WL is set to 0 V, and the N-channel transistors Ta1 and Ta2 are turned off. The voltages for the bit line BL and the inverted bit line BLB are two kinds of voltages (that is, 0.6V) used for expressing the data “1” / “0” in the volatile memory unit 11 during normal operation. 0V), which is the higher voltage of 0.6V. Further, the write voltage WRE is set to 0.3 V, the N-channel transistors Tw1 and Tw2 are turned on, and the resistance variable elements R1 and R2 are connected to the output node V1 of the inverter INV1 and the output node V2 of the inverter INV2, respectively. In this state, the power supply voltage VDC for the nonvolatile memory cell 10A is raised from 0V to 0.6V which is the power supply voltage during normal operation.

  Here, since the voltage for the bit lines BL and BLB is 0.6 V and the write voltage WE is 0.3 V, the upper limit value of the voltage of the node V1 (V2) at which the N-channel transistor Tw1 (Tw2) is kept ON is The voltage obtained by subtracting the threshold voltage of the N-channel transistor Tw1 (Tw2) from the voltage value 0.3V of the write voltage WRE. Accordingly, in the process in which the power supply voltage VDC for the nonvolatile memory cell 10A rises from 0V to 0.6V, the period during which the voltage at the node V1 (V2) is less than or equal to this upper limit value is from A current can flow into the node V1 (V2) through the channel transistor Tw1 (Tw2). However, when the voltage at the node V1 exceeds the upper limit value, the N-channel transistor Tw1 is turned off. When the voltage at the node V2 exceeds the upper limit value, the N-channel transistor Tw2 is turned off. Hereinafter, based on this point, the operation of each part in the process in which the power supply voltage VDC for the nonvolatile memory cell 10A rises from 0V to 0.6V will be described.

  First, when data “1” is stored in the nonvolatile memory unit 10A, the resistance variable element R1 has a low resistance and the resistance variable element R2 has a high resistance. In this state, when the power supply voltage VDC for the nonvolatile memory cell 10A starts to increase from 0V, the voltage at the node V1 is set to 0.6V for the bit line BL, and the series resistance composed of the N-channel transistor Tw1 and the resistance variable element R1. And a voltage internally divided by the parallel resistance composed of the N-channel transistor N1 and the P-channel transistor P1. The voltage at the node V2 is divided internally from the voltage 0.6V with respect to the bit line BLB by a series resistance composed of the N-channel transistor Tw2 and the resistance variable element R2 and a parallel resistance composed of the N-channel transistor N2 and the P-channel transistor P2. Voltage.

  Here, since the resistance variable element R1 has a low resistance and the resistance variable element R2 has a high resistance, the former internal ratio is larger than the latter internal ratio. For this reason, in the process in which the power supply voltage VDC for the nonvolatile memory cell 10A increases from 0V, the voltage at the node V1 becomes higher than the voltage at the node V2. When the voltage at the node V1 increases, the ON resistance of the N channel transistor N2 decreases and the ON resistance of the P channel transistor P2 increases, so that current flows into the N channel transistor N2 via the resistance variable element R2. Even if there is, the voltage at the node V2 can be kept low.

  Then, as the power supply voltage VDC increases, the voltage at the node V1 increases, and when the above-described upper limit is exceeded, the N-channel transistor Tw1 is turned off. However, at this time, the volatile storage unit 11 including the inverters INV1 and INV2 has completed the operation of holding the data “1” (V1 = High level, V2 = Low level), so that the N-channel transistor Tw1 is turned off. Does not affect the recall operation. In this way, the recall of data “1” is completed.

  On the other hand, when data “0” is stored in the nonvolatile memory unit 10A, the resistance variable element R1 has a high resistance and the resistance variable element R2 has a low resistance. In this case, the N channel transistor Tw2 and the resistance variable element are compared with the internal ratio of the series resistance composed of the N channel transistor Tw1 and the resistance variable element R1 and the parallel resistance composed of the N channel transistor N1 and the P channel transistor P1. The internal division ratio between the series resistance composed of R2 and the parallel resistance composed of the N-channel transistor N2 and the P-channel transistor P2 becomes larger. Therefore, in the process in which the power supply voltage VDC to the nonvolatile memory cell 10A increases from 0V, the voltage at the node V2 becomes higher than the voltage at the node V1, and the volatile storage unit 11 stores data “0” (V1 = Low level, (V2 = High level) holding operation is performed.

  When the recall operation is completed as described above, the write voltage WRE is then set to 0 V, and the resistance variable elements R1 and R2 are separated from the volatile storage unit 11. Then, the power supply voltage VDC for the nonvolatile memory cell 10A is set to 0.6V, and the read operation and write operation of the volatile storage unit 10A similar to those of a normal SRAM are performed.

<Third Embodiment>
FIG. 6 is a block diagram showing an overall configuration of a nonvolatile RAM according to the third embodiment of the present invention. In FIG. 6, a nonvolatile RAM cell array 100 is a cell array in which the nonvolatile memory cells 10 of the first embodiment are arranged in a matrix. In this example, the memory capacity of the nonvolatile RAM cell array 100 is 64M bits (4M × 16 bits).

  The control unit 500 includes a control circuit 501 and a power supply control circuit 510. Here, the control circuit 501 includes a power supply control circuit 510, an address input circuit 550, a row decoder 200, and the like according to a chip enable signal CEB, an output permission signal OEB, a store instruction signal STR, a recall instruction signal RCL, and the like given from the outside. This circuit controls the column decoder 300, the write circuit 800, and the input / output buffer 700. Here, the chip enable signal CEB and the output permission signal OEB are control signals used in a normal SRAM. The store instruction signal STR and the recall instruction signal RCL are control signals peculiar to the present embodiment, and are control signals that are set to active levels when the nonvolatile RAM is to store and to be recalled, respectively. The power supply control circuit 510 is a circuit that generates voltages for operating the row decoder 200, the column decoder 300, and the write circuit 800 under the control of the control circuit 501.

  The address input circuit 550 is a circuit that receives and holds addresses A0 to A21 that specify access destinations in the nonvolatile RAM cell array 100 under the control of the control circuit 501. In the nonvolatile RAM cell array 100, the addresses A0 to A21 are divided into a row address that specifies the row to which the access destination belongs and a column address that specifies the column to which the access destination belongs.

  The row decoder 200 decodes the row address and selects one of the rows of the nonvolatile RAM cell array 100 according to the decoding result. In addition, the column decoder 300 decodes the column address and selects one of the columns of the nonvolatile RAM cell array 100 according to the decoding result. Column gate 400 connects write circuit 800 at the time of write access and sense amplifier 600 at the time of read access to the bit line and the inverted bit line of the column selected by column decoder 300. The sense amplifier 600 is a circuit that differentially amplifies the voltage on the bit line and the inverted bit line supplied via the column gate 400 during read access and outputs the amplified voltage to the input / output buffer 700. The write circuit 800 is a circuit that supplies the column gate 400 with a data voltage corresponding to write data supplied via the input / output buffer 700 during write access. Input / output buffer 700 receives 16-bit write data from the outside, supplies it to write circuit 800, and outputs 16-bit read data to the outside based on the output signal of sense amplifier 600. An output circuit is used.

  The row decoder 200 in the present embodiment turns off the N-channel transistors Ta1 and Ta2 of all the nonvolatile memory cells of the nonvolatile RAM cell array 100 at the time of storing and recalling, and each nonvolatile memory of the nonvolatile RAM cell array 100 at the time of storing. ON / OFF control of the N channel transistors Tw1 and Tw2 is performed in cell row units, and ON / OFF control of the N channel transistors Tw1 and Tw2 of each nonvolatile memory cell of the nonvolatile RAM cell array 100 is performed at the time of recall. Further, the column decoder 300 in the present embodiment is a column for selecting each bit line and each inverted bit line to which each nonvolatile memory cell of all the columns of the nonvolatile RAM cell array 100 is connected at the time of storing and recalling. The gate 400 is controlled.

  FIG. 7 is a block diagram showing a specific configuration example of the nonvolatile RAM according to the present embodiment. In FIG. 7, only the configuration related to storage and input / output of 1-bit data is shown in order to prevent the drawing from becoming complicated. The actual non-volatile RAM has a configuration in which the non-volatile RAM cell array 100 and the column gate 400 shown in FIG.

  In FIG. 7, the nonvolatile RAM cell array 100 uses the nonvolatile memory cells 10 of the first embodiment (FIG. 1) as nonvolatile memory cells Mkj, and the nonvolatile memory cells Mkj are arranged in a matrix of m + 1 rows and n + 1 columns. It is an arrangement. The minimum unit of the nonvolatile RAM cell array 100 is generally divided into 512K bits, for example, m = 1024 and n = 512, although depending on the high speed and the scale of the memory capacity. In this example, since the memory capacity is 64 Mbits, 128 nonvolatile RAM cell arrays 100 as the minimum memory array are provided.

  A paired bit line BITj and inverted bit line BITjB are wired along each column j of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) forming the matrix. Here, the source of the N-channel transistor Ta1 of m + 1 nonvolatile memory cells Mkj (k = 0 to m) belonging to the column j is connected to the bit line BITj, respectively, and the inverted bit line BITjB is connected to the column j. The sources of the N channel transistors Ta2 of the m + 1 nonvolatile memory cells Mkj (k = 0 to m) to which it belongs belong to each other. Further, one end of each of the resistance change elements R1 of the m + 1 nonvolatile memory cells Mkj (k = 0 to m) belonging to the column j is connected to the bit line BITj, and the inverted bit line BITjB is connected to the column j. One end of the resistance change element R2 of each of the m + 1 nonvolatile memory cells Mkj (k = 0 to m) to which it belongs is connected.

  A signal line for supplying a row selection voltage WLk and a signal line for supplying a write voltage WREk are provided along each row k of the nonvolatile memory cell Mkj (k = 0 to m, j = 0 to n). Wired. Here, the row selection voltage WLk corresponding to the row k is supplied to the gates of the N-channel transistors Ta1 and Ta2 (see FIG. 1) of the nonvolatile memory cells Mkj (j = 0 to n) of the row k. The write voltage WREk corresponding to the row k is supplied to the gates of the N-channel transistors Tw1 and Tw2 (see FIG. 1) of the non-volatile memory cell Mkj (j = 0 to n) of the row k (FIG. 1). reference).

  The low-potential-side power supply voltage VSS is supplied to the sources of the N-channel transistors N1 and N2 of all the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) of the nonvolatile RAM cell array 100. The In addition, each source of P channel transistors P1 and P2 (see FIG. 1) of all the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) of the nonvolatile RAM cell array 100 has a reference power supply voltage. A certain high potential side power supply voltage VDC is supplied. In the present embodiment, at the time of recall, a reference power supply voltage VDC common to all nonvolatile memory cells is generated in order to recall all nonvolatile memory cells simultaneously. This reference power supply voltage VDC is controlled by a power supply control circuit 510.

  The column gate 400 includes n + 1 sets of N-channel column selection transistors CGj (j = 0 to n) and CGjB (j = 0 to 0) associated with the respective columns j (j = 0 to n) of the nonvolatile RAM cell array 100. n). The column selection transistors CGj and CGjB corresponding to the column j are turned on when the column selection voltage COLj becomes an active level, and connect the bit line BITj and the inverted bit line BITjB to the data line DL and the inverted data line DLB, respectively. Data line DL and inverted data line DLB are connected to write circuit 800 and sense amplifier 600.

  The column decoder 300 includes n + 1 column selection circuits 300-j (j = 0 to n) corresponding to the columns j (j = 0 to n) of the nonvolatile RAM cell array 100, respectively. Here, the column selection circuit 300-j corresponding to the column j includes a column address match detection unit 301, an AND gate 302, and a level shifter 303.

  The column address match detection unit 301 outputs an L level signal when the column address indicates the column j. The AND gate 302 receives the output signal of the column address match detection unit 301 and the collective selection signal ASELB. Here, the collective selection signal ASELB is a signal output by the control circuit 501, and is set to an inactive level (High level) during an operation as a normal SRAM, and to an active level (Low level) during a store operation and a recall operation. Level).

  The AND gate 302 supplies the output signal of the column address match detection unit 301 to the level shifter 303 when the collective selection signal ASELB is at the inactive level, and supplies the low level signal to the level shifter 303 when it is at the active level.

  The level shifter 303 outputs the row selection voltage COLj at the H level when the output signal of the AND gate 302 is at the Low level, and turns on the column gate transistors CGj and CGjB corresponding to the column j. A reference column selection voltage VCOL is applied to the high potential side power supply terminal of each level shifter 303 of the column selection circuit 300-j (j = 0 to n). The reference column selection voltage VCOL is a voltage output from the power supply control circuit 510.

  The row decoder 200 includes m + 1 row selection circuits 200-k (k = 0 to m) corresponding to the rows k (k = 0 to m) of the nonvolatile RAM cell array 100, respectively. A row selection circuit 200-k corresponding to each row k includes N channel transistors Ta1 and Ta2 and N channel transistors Tw1 and Tw2 of n + 1 nonvolatile memory cells Mkj (j = 0 to n) belonging to the row k (FIG. 1). Control).

  FIG. 8 is a circuit diagram showing a configuration example of a row selection circuit 200-k corresponding to row k. In FIG. 8, a signal STRB and a signal RCLB are signals obtained by inverting the logic of the store instruction signal STR and the recall instruction signal RCL, and are generated by the control circuit 501. ADDX is a row address held in the address input circuit 550.

  The address match detection unit 201 is a circuit that outputs a high level when the row address ADDX indicates the row, and outputs a low level otherwise. NAND gate 202 inverts the output signal of address match detection unit 201 when both signals STRB and RCLB are at a high level, that is, both store instruction signal STR and recall instruction signal RCL are at an inactive level (low level). If not, a high level is output. The inverter 203 inverts the output signal of the NAND gate 202 and outputs it as a row selection voltage WLk for the row k.

  Therefore, when both the store instruction signal STR and the recall instruction signal RCL are in the inactive level (Low level) (that is, in the operation mode as the SRAM), the row selection is performed when the row address ADDX indicates the row k. When the voltage WLk is at a high level and the row address ADDX does not indicate the row k, the row selection voltage WLk is at a low level. When one of the store instruction signal STR and the recall instruction signal RCL is at an active level (High level), the row selection voltage WLk is at a Low level.

  The NAND gate 206 receives an output signal from the address match detection unit 201 and a signal obtained by inverting the signal STRB by the inverter 204. A P-channel transistor 206P is inserted between the high-potential side power supply terminal and the high-potential side power supply VDD of the NAND gate 206. A signal obtained by inverting the signal RCLB by the inverter 205 is connected to the gate of the P-channel transistor 206P. Is entered. An N-channel transistor 206N is interposed between the output node of the NAND gate 206 and the low-potential-side power supply VSS. A signal obtained by inverting the signal RCLB by the inverter 205 is input to the gate of the N-channel transistor 206N. Is done.

  Therefore, at the time of recall, when the recall instruction signal RCL is at the active level (High level), the output signal of the inverter 205 becomes High level, the P-channel transistor 206P is turned off, and the N-channel transistor 206N is turned on. Accordingly, the NAND gate 206 forcibly outputs a Low level.

  When the store instruction signal STR is at the active level during the store, the recall instruction signal RCL is at the inactive level, so that the P-channel transistor 206P is turned on and the N-channel transistor 206N is turned off. Here, when the row address ADDX indicates the row k and the address match detection unit 201 outputs a high level, the NAND gate 206 outputs a low level.

  On the other hand, when the row address does not indicate the row k and the address match detection unit 201 outputs a low level, the output signal of the NAND gate 206 becomes a high level.

  The level shifter 207 inverts the output signal of the NAND gate 206 and outputs it as the write voltage WREk. Here, the reference write voltage VWR output from the power supply control circuit 510 is applied to the level shifter 207 as a high potential side power supply voltage. Therefore, when the level shifter 207 outputs the high level write voltage WREk, the level shifter 207 outputs the write voltage WREk having the same level as the reference write voltage VWR.

  Write circuit 800 outputs a bit voltage and an inverted bit voltage corresponding to write data Din from the outside of the nonvolatile RAM to data line DL and inverted data line DLB during a write access. In write access, one bit line selected by the column gate 400 among the bit lines BITj (j = 0 to n) is connected to the data line DL, and the inverted data line DLB is connected to the inverted bit line. One inverted bit line selected by the column gate 400 among BITjB (j = 0 to n) is connected.

  On the other hand, the reference bit line voltage VWD is applied to the write circuit 800 from the power supply control circuit 510. Write circuit 800 outputs reference bit line voltage VWD to both data line DL and inverted data line DLB during a store operation and a recall operation.

  During the store operation and the recall operation, the collective selection signal ASELB is set to the active level (Low level), and all the column selection circuits 300-j (j = 0 to n) are set to the high level (= VCOL) column selection voltage. COLj (j = 0 to n) is output. Therefore, all of the bit lines BITj (j = 0 to n) are connected to the data line DL via the column gate 400, and the inverted bit line BITjB (j = 0 to n) is connected to the inverted data line DLB. All are connected via the column gate 400. Accordingly, the reference bit line voltage VWD is applied to all the bit lines BITj (j = 0 to n) and the inverted bit lines BITjB (j = 0 to n).

  FIG. 9 is a block diagram illustrating a configuration of the control unit 500. In the control unit 500, the power supply control circuit 510 includes a booster circuit 502, a step-down circuit 503, an output adjustment circuit 504, and a voltage detection circuit 505. The control circuit 501 controls the booster circuit 502, the step-down circuit 503, and the output adjustment circuit 504 based on the store instruction signal STR and the recall instruction signal RCL. The voltage detection circuit 505 is a circuit that outputs a power-on pulse PON when the power supply VDD of the nonvolatile RAM is turned on.

  The booster circuit 502 boosts and outputs the power supply voltage VDD for the nonvolatile RAM. The step-down circuit 503 steps down the power supply voltage and outputs it. The step-up circuit 502 and the step-down circuit 503 are provided, as shown in FIGS. 2, 4, and 5, which are higher than the power supply voltage for the nonvolatile RAM in order to perform store and recall operations. This is because it is necessary to generate a voltage or a low voltage. The output adjustment circuit 504 selects a reference column selection voltage VCOL and a reference write voltage by selecting an output voltage of the booster circuit 502, an output voltage of the step-down circuit 503, or a power supply voltage for the nonvolatile RAM under the control of the control circuit 501. VWR, reference bit line voltage VWD, and cell power supply voltage VDC for nonvolatile RAM cell array 100 are output.

  FIG. 10 is a time chart showing the operation during storage of the nonvolatile RAM according to the present embodiment. In this example, the nonvolatile RAM operates under the operating conditions shown in FIG. Then, the control circuit 501 causes the booster circuit 502 to output a voltage of 1.2V and a voltage of 1.5V.

  In the period t1, the nonvolatile RAM operates as a normal SRAM in response to the supply of the power supply voltage VDD of 0.6V. The output adjustment circuit 504 outputs the power supply voltage VDD as the power supply voltage VDC to the nonvolatile RAM cell array 100 under the control of the control circuit 501.

  When the supply of the power supply voltage VDD to the nonvolatile RAM is cut off, the store instruction signal STR is raised prior to that. As a result, the control circuit 501 causes the output adjustment circuit 501 to select the voltage of 1.2 V output from the booster circuit 502, and outputs the voltage as the reference column selection voltage VCOL and the power supply voltage VDC to the nonvolatile RAM cell array 100. In addition, the control circuit 501 causes the output adjustment circuit 501 to select the voltage of 1.5 V output from the booster circuit 502 and outputs the selected voltage as the reference write voltage VWR.

  When the store instruction signal STR rises, the row selection circuit 200-k (k = 0 to m) sets the row selection voltage WLk (k = 0 to m) to 0 V because the signal STRB becomes a low level. . As a result, the N-channel transistors Ta and Tb of all the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) are turned off. The row selection circuit 200-k corresponding to the row k indicated by the row address ADDX outputs the reference write voltage VWR as the write voltage WREk corresponding to the row k. Further, the control circuit 501 sets the collective selection signal ASELB to the active level (Low level). Accordingly, the column selection circuit 300-j (j = 0 to n) turns on all the column selection transistors CGj (j = 0 to n) and CGjB (j = 0 to n), and all the bit lines BITj (j = 0 to n) are connected to the data line DL, and all the inverted bit lines BITjB (j = 0 to n) are connected to the inverted data line DLB.

  Then, the control circuit 501 causes the output adjustment circuit 504 to output the power supply voltage VDD = 0.6 V as the reference bit line voltage VWD over the period t2 after the rise of the store instruction signal STR, and causes the write circuit 800 to Reference bit line voltage VWD = 0.6 V is output to data line DL and inverted data line DLB. In the nonvolatile RAM, the store operation is performed using the period t2.

  First, the address input circuit 550 outputs the first address AX0 as the row address ADDX, and causes the row selection circuit 200-0 to output the 1.5V write voltage WRE0 over time Δt1. As a result, the N-channel transistors Tw1 and Tw2 of all the nonvolatile memory cells M0j (j = 0 to n) in the 0th row are turned on. At this time, the 0.6V reference bit line is used for the bit line BITj (j = 0 to n) and the inverted bit line BITjB (j = 0 to n) sandwiching each nonvolatile memory cell M0j (j = 0 to n). A voltage VWD is applied. Therefore, the data stored in the volatile storage unit 11 is written into the nonvolatile storage unit 12 in all the nonvolatile memory cells M0j (j = 0 to n) in the 0th row.

  Next, the address input circuit 550 outputs the second address AX1 as the row address ADDX, and causes the row selection circuit 200-1 to output the write voltage WRE1 of 1.5 V over the time Δt1. As a result, the data stored in the volatile storage unit 11 is written into the nonvolatile storage unit 12 in all the nonvolatile memory cells M1j (j = 0 to n) in the first row.

  The same applies to the following, and the row address ADDX is repeatedly advanced from AX2 to AXm, and the store operation of all the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) is performed.

  When the store operation for the last row is completed, the store instruction signal STR is set to the Low level. In the subsequent period t3, the power supply voltage VDD is set to 0 V, and the power supply is shut off.

  For sudden power off due to an unexpected power failure, etc., a voltage drop detection circuit (not shown) detects a voltage drop, performs a store operation with the charge stored in a capacitor (storage battery), etc., and shuts off the power A function for terminating the store operation may be added.

  FIG. 11 is a time chart showing the operation at the time of recall of the nonvolatile RAM according to the present embodiment. In this example, the nonvolatile RAM operates under the operating conditions shown in FIG. First, when power is supplied to the nonvolatile RAM, the power supply voltage VDD rises to 0.6V. The voltage detection circuit 505 detects the rise of the power supply voltage VDD and outputs a power-on pulse PON. The internal circuit is reset (initialized) by the power-on pulse PON. This period is the power-on period t1.

  Next, when the recall instruction signal RCL becomes high level, the nonvolatile RAM performs a recall operation using the subsequent period t2. First, the control circuit 501 outputs the reference bit line voltage VWD of 0V to the output adjustment circuit 504, and causes the write circuit 800 to output the reference bit line voltage VWD = 0V to the data line DL and the inverted data line DLB. As a result, the reference bit line voltage VWD = 0 V is applied to all the bit lines BITj (j = 0 to n) and all the inverted bit lines BITjB (j = 0 to n). In addition, the control circuit 501 causes the output adjustment circuit 504 to output a reference write voltage VWR of 0.3V and a reference column selection voltage VCOL of 0.6V.

  Further, when the recall instruction signal RCL becomes High level, the signal RCLB becomes Low level in the row selection circuit 200-k (k = 0 to m), so that the row selection voltage WLk (k = 0 to m) is 0V. It is said. As a result, the N-channel transistors Ta and Tb of all the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) are turned off.

  In the row selection circuit 200-k (k = 0 to m), the P-channel transistor 206P is turned OFF and the N-channel transistor 206N is turned ON, so that all the write voltages WREk (k = 0 to m) are the reference write voltages. VWR = 0.3V.

  Further, the control circuit 501 sets the collective selection signal ASELB to High level. Accordingly, the column selection circuit 300-j (j = 0 to n) turns on all the column selection transistors CGj (j = 0 to n) and CGjB (j = 0 to n), and all the bit lines BITj (j = 0 to n) are connected to the data line DL, and all the inverted bit lines BITjB (j = 0 to n) are connected to the inverted data line DLB. As a result, the reference bit line voltage VWD = 0 V is applied to all the bit lines BITj (j = 0 to n) and all the inverted bit lines BITjB (j = 0 to n).

  Then, the control circuit 501 causes the output adjustment circuit 501 to raise the power supply voltage VDC for the nonvolatile memory cell Mkj (k = 0 to m, j = 0 to n) from 0V to 0.6V with a predetermined time gradient. . As a result, in the nonvolatile memory cell Mkj (k = 0 to m, j = 0 to n), a recall operation for writing the data stored in the nonvolatile storage unit 12 to the volatile storage unit 11 is performed.

  Thereafter, when the recall instruction signal RCL falls, the period t2 for the recall operation ends, and the period t3 during which the operation as the SRAM is performed. In this period t3, since the recall instruction signal RCL and the store instruction signal STR are at the low level, the row selection circuit 200-k (k = 0 to m) sets the write voltage WREk (k = 0 to m) to 0V. And Therefore, in the nonvolatile memory cell Mkj (k = 0 to m, j = 0 to n), the N-channel transistors Tw1 and Tw2 are turned off, and the nonvolatile RAM operates as a normal SRAM.

<Fourth embodiment>
In the third embodiment, all the columns are selected by the column decoder 300, and all the nonvolatile memory cells belonging to the row are stored in units of rows. However, if the number of nonvolatile memory cells that simultaneously perform a store operation is large, the store current increases. Therefore, in the present embodiment, a divided store is used in which all nonvolatile memory cells belonging to one row are divided into a plurality of groups, and each group is sequentially selected to perform a store operation. Here, when the store current required for writing data to one resistance variable element is 49 μA, one row of nonvolatile memory cells is divided into a plurality of groups each consisting of 16 bits of nonvolatile memory cells. Assuming that the store current per group is 49 μA × 16 × 2 (R1 and R2) = 1.6 mA. Further, if a store operation is performed in units of 1 group = 128 bit pages, the store current per group is 49 μA × 128 × 2 = 12.5 mA.

  FIG. 12 is a time chart showing the store operation in the present embodiment. Hereinafter, the operation of the present embodiment will be described focusing on differences from the store operation (FIG. 10) of the third embodiment.

  In the example shown in FIG. 12, the nonvolatile memory cells Mkj (j = 0 to n) in each row are divided into a first group Mkj (j = 0 to h) and a second group Mkj (j = h + 1 to n). Store operation is performed in group units.

  Specifically, when the row selection circuit 200-0 sets the write voltage WRE0 corresponding to the 0th row to 1.5V, first, the column decoders 300-0 to 300-h corresponding to the first group. Outputs high level column selection voltages COL0 to COLh and COL0B to COLhB, and column decoders 300- (h + 1) to 300-n corresponding to the second group have low level column selection voltages COLh + 1 to COLn and COL (h + 1). ) B to COLnB are output.

  As a result, the voltage of the bit line BITj (j = 0 to h) corresponding to the first group and the inverted bit line BITjB (j = 0 to h) becomes 0.6 V, and the bit line BITj corresponding to the second group. (J = h + 1 to n), the inverted bit line BITjB (j = h + 1 to n) is opened. Therefore, the data stored in the volatile storage unit 11 in the first group of nonvolatile memory cells M0j (j = 0 to h) is written into the nonvolatile storage unit 12.

  Next, column decoders 300-0 to 300-h corresponding to the first group output low level column selection voltages COL0 to COLh and COL0B to COLhB, and column decoders 300- (h + 1) corresponding to the second group. ) To 300-n output high level column selection voltages COLh + 1 to COLn and COL (h + 1) B to COLnB.

  As a result, the bit line BITj (j = 0 to h) corresponding to the first group and the inverted bit line BITjB (j = 0 to h) are opened, and the bit line BITj (j = h + 1) corresponding to the second group. N), the voltage of the inverted bit line BITjB (j = h + 1 to n) becomes 0.6V. Therefore, the data stored in the volatile storage unit 11 in the second group of nonvolatile memory cells M0j (j = h + 1 to n) is written into the nonvolatile storage unit 12. Thereafter, the write voltage WRE0 becomes 0V, and the storage of the nonvolatile memory cells M0j (j = 0 to n) connected to the row selection circuit 200-0 is completed.

  Next, the row selection circuit 200-1 sets the write voltage WRE1 corresponding to the first row to 1.5 V, and the same operation is performed. Thereafter, the same operation is repeated from the second row to the m-th row, and the store operation of all the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) is completed.

  In order to realize the divided store operation as described above, for example, the column selection circuit 300-j (j = 0 to h) and the second column selection circuit 300-j (j = h + 1 to 1) corresponding to the first group. n) are supplied with separate batch selection signals ASELB-1 and ASELB-2. In the first half of the period for selecting one row, the collective selection signal ASELB-1 is set to the active level and the collective selection signal ASELB-2 is set to the inactive level, and in the second half, the collective selection signal ASELB-1 is set to the inactive level and the collective selection signal ASELB- What is necessary is just to repeat the control which makes 2 active level. In the above description, the nonvolatile memory cells Mkj (j = 0 to n) in each row are divided into two groups, but the number of groups to be divided depends on the nonvolatile memory cells Mkj (j in one row). = 0 to n), the allowable limit of the total value of the store current, and the like may be determined appropriately.

<Fifth Embodiment>
FIG. 13 is a block diagram showing a configuration of a nonvolatile RAM according to the fifth embodiment of the present invention. In the present embodiment, a modification for performing a recall operation in units of rows is added to the third embodiment.

  In the present embodiment, the nonvolatile RAM cell array 100 and the row selection circuit 200-k (k = 0 to m) in the third embodiment are replaced with the nonvolatile RAM cell array 110 and the row selection circuit 220-k (k = 0 to m). Has been replaced.

  Here, like the nonvolatile RAM cell array 100, the nonvolatile RAM cell array 110 is configured by arranging the nonvolatile memory cells 10 of the first embodiment in a matrix. However, in the nonvolatile RAM cell array 110, the high-potential-side power supply voltage VDCk (k = 0 to m) is independently applied to each row k of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) forming a matrix. ) Is provided. A power supply line for supplying the high-potential-side power supply voltage VDCk (k = 0 to m) for each row k of the nonvolatile memory cell Mkj (k = 0 to m, j = 0 to n) is the row selection circuit 220. -K (k = 0 to m) are connected to each other.

  In addition to the function of the row selection circuit 220-k of the third embodiment, the row selection circuit 220-k corresponding to each row k has the row k when the row address ADDX indicates the row k during the recall operation. The high potential side power supply voltage VDCk supplied to the non-volatile memory cell Mkj (j = 0 to n) belonging to is raised from 0 V to the reference power supply voltage VDC output from the power supply control circuit 510.

  FIG. 14 is a circuit diagram showing a specific configuration example of the row selection circuit 220-k. In FIG. 14, the address match detection unit 221 outputs a high level when the row address ADDX indicates the row k, and outputs a low level when the row address ADDX does not indicate the row k.

  The latch L1 is composed of a P-channel transistor 222, N-channel transistors 223 and 225, and an inverter 224. The P-channel transistor 222 and the N-channel transistor 223 are inserted in series between the high potential side power supply VDD and the low potential side power supply VSS. The output signal N1 of the address match detection unit 221 is given to the gate of the N-channel transistor 223. Inverter 224 inverts and outputs a signal generated at a connection node between the drains of P channel transistor 222 and N channel transistor 223. The output signal of the inverter 224 becomes the output signal N2 of the latch L1. This signal N 2 is supplied to the gate of the P-channel transistor 222. The N-channel transistor 225 is interposed between the output node of the inverter 224 and the low potential side power source VSS. A power-on pulse PON generated when the power supply voltage VDD for the nonvolatile RAM rises is applied to the gate of the N-channel transistor 225. The above is the configuration of the latch L1.

  The delay circuit 226 delays the output signal N2 of the latch L1 by a predetermined time Δt1. The inverter 227 inverts the output signal of the delay circuit 226 and outputs it. The level shifter 228 is supplied with the reference power supply voltage VDC output from the output adjustment circuit 504 (see FIG. 9) of the power supply control circuit 510 as the high potential side power supply voltage. The level shifter 228 inverts the output signal of the inverter 227, and when the inverted result is “0”, the level shifter 228 sets the reference power supply voltage VDC to the high potential side power supply voltage VDCk corresponding to the row k. Output as.

  The NAND gate 229 receives the output signal N1 of the address match detection unit 221 and the signal WREB. This signal WREB is a signal generated by the NOR gate of FIG. 15 built in the control circuit 501, and becomes Low level when the store instruction signal STR or the recall instruction signal RCL is at the active level, and the store instruction signal STR and the recall instruction When both signals RCL are at an inactive level, they are at a high level. The output signal of the NAND gate 229 is inverted by the inverter 230 and is output as the row selection voltage WLk corresponding to the row k. The row selection voltage WLk is at a high level only when both the store instruction signal STR and the recall instruction signal RCL are at an inactive level and the output signal N1 of the address match detection unit 221 is at a high level. Becomes Low level.

  The NAND gate 232 receives a signal obtained by inverting the signal WREB by the inverter 231 and the output signal N1 of the address match detection unit 221. The level shifter 233 is supplied with the reference write voltage VWR output from the output adjustment circuit 504 (see FIG. 9) of the power supply control circuit 510 as the high potential side power supply voltage. The level shifter 233 inverts the output signal of the NAND gate 232, and outputs 0V when the inversion result is “0”, and outputs the reference write voltage VWR as the write voltage WREk when it is “1”.

  Therefore, when both store instruction signal STR and recall instruction signal RCL are at the inactive level, write voltage WREk is 0V. Further, when one of the store instruction signal STR or the recall instruction signal RCL is at the active level and the output signal N1 of the address match detection unit 221 is at the high level, the write voltage WREk is the same voltage as the reference write voltage VWR. become.

  FIG. 16 is a time chart showing a recall operation in the present embodiment. When the power supply voltage VDD rises to the nonvolatile RAM and the power-on pulse PON is generated, in each row selection circuit 220-k (k = 0 to m) (see FIG. 14), the N-channel transistor 225 is turned on and the output of the latch L1 The signal N2 is reset to 0V (Low level). As a result, the high-potential side power supply voltage VDCk (k = 0 to m) output from the level shifter 228 of each row selection circuit 220-k (k = 0 to m) becomes 0V. This is the initial state.

  Next, when the recall instruction signal RCL rises, the non-volatile RAM performs a recall operation as follows using the subsequent period t2. First, the control circuit 501 sets the collective selection signal ASELB to an active level, causes the output adjustment circuit 504 of the power supply control circuit 510 to output a reference bit line voltage VWD of 0 V, and causes the writing circuit 800 to output this reference bit line voltage VWD. = 0V is output to the data line DL and the inverted data line DLB. As a result, the reference bit line voltage VWD = 0 V is applied to all the bit lines BITj (j = 0 to n) and all the bit lines BITjB (j = 0 to n).

  Thereafter, when the row address ADDX becomes the row address AX0 indicating the 0th row, the output signal N1 of the address coincidence detection unit 221 of the row selection circuit 220-0 rises from the Low level to the High level. Here, since the signal WREB is at the low level during the recall operation, the row selection voltage WLk (k = 0 to m) output from each row selection circuit 220-k (k = 0 to m) is 0V. As a result, the N channel transistors Ta1 and Ta2 of all the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) are turned off.

  On the other hand, when the signal WREB is at the low level, the row selection circuit 220-0 causes the level shifter 233 to write the same voltage as the reference write voltage VWR because the output signal N1 of the address match detection unit 221 is at the high level. Output voltage WRE0. As a result, the N-channel transistors Tw1 and Tw2 of the nonvolatile memory cell M0j (j = 0 to n) in the 0th row are turned on.

  In the row selection circuit 220-0, when the output signal N1 of the address match detection unit 221 rises from the low level to the high level, the output signal N2 of the latch L1 rises to the high level. The power supply voltage VDC0 that the level shifter 228 supplies to the non-volatile memory cells M0j (j = 0 to n) in the 0th row is delayed from this rising timing by the delay time Δt1 of the delay circuit 226 from 0V to the reference power supply voltage. It rises to VDC = 0.6V. Here, once the output signal N2 of the latch L1 becomes the high level, the high level is maintained while the power supply voltage VDD is applied thereafter. Therefore, the high-potential side power supply voltage VDC0 for the 0th row thereafter maintains the reference power supply voltage VDC = 0.6V.

  When the high-potential side power supply voltage VDC0 for the 0th row rises in this way, the data stored in the nonvolatile storage unit 12 is volatilized in the nonvolatile memory cells M0j (j = 0 to n) in the 0th row. Held in the sex storage unit 11.

  Next, when a predetermined time Δt2 has elapsed since the rising of the high potential side power supply voltage VDC0 for the 0th row, the row address ADDX is switched to the row address AX1 indicating the first row. As a result, the output signal N1 of the address match detection unit 221 of the row selection circuit 220-0 falls from the High level to the Low level. Then, the write voltage WRE0 that the row selection circuit 220-0 supplies to the nonvolatile memory cell M0j (j = 0 to n) in the 0th row becomes 0V. As a result, the variable resistance elements R1 and R2 of the nonvolatile memory cell M0j (j = 0 to n) in the 0th row are transferred from the bit line BITj (j = 0 to n) and the inverted bit line BITjB (j = 0 to n). Disconnected.

  On the other hand, when the row address ADDX becomes the row address AX1 indicating the first row, the output signal N1 of the address match detection unit 221 of the row selection circuit 220-1 rises from the Low level to the High level. As a result, the write voltage WRE1 supplied to the non-volatile memory cell M1j (j = 0 to n) in the first row by the row selection circuit 220-1 becomes 0.3V. Then, the row selection circuit 220-1 is delayed by a time Δt1 from the rising timing of the output signal N1 of the address coincidence detection unit 221 of the row selection circuit 220-1, and the row selection circuit 220-1 receives the nonvolatile memory cell M1j (j = 0 to 0) in the first row. The high potential side power supply voltage VDC1 supplied to n) rises.

  When the high potential side power supply voltage VDC1 for the first row rises in this way, the data stored in the nonvolatile storage unit 12 is volatilized in the nonvolatile memory cells M1j (j = 0 to n) in the first row. Held in the sex storage unit 11.

  Thereafter, the row address ADDX is sequentially switched from the row address AX2 indicating the second row to the row address AXm indicating the m-th row, and the same operation is repeated. As a result, the recall operation of all the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) is completed.

  Thereafter, when the recall instruction signal RCL falls, the period t2 for the recall operation ends, and the period t3 during which the operation as the SRAM is performed. In this period t3, since the recall instruction signal RCL and the store instruction signal STR are at the low level, the row selection circuit 220-k (k = 0 to m) sets the write voltage WREk (k = 0 to m) to 0V. And Therefore, in the nonvolatile memory cell Mkj (k = 0 to m, j = 0 to n), the N-channel transistors Tw1 and Tw2 are turned off, and the nonvolatile RAM operates as a normal SRAM.

  In each nonvolatile memory cell Mkj (k = 0 to m, j = 0 to n), the operation of holding the data stored in the nonvolatile storage unit 12 in the volatile storage unit 11 is very fast, and is 10 ns or less. Cycle. That is, in FIG. 16, Δt1 + Δt2 <10 ns.

  Therefore, if the nonvolatile RAM cell array 110 is a memory array with m = 1024 and n = 512, the time required to complete the recall of one memory array is 10 ns × 1024 rows = 10.2 μs. In the case of a 64-Mbit memory, since there are 128 memory arrays, the recall of all memories can be completed in a time of 10.2 μs × 128 blocks = 1.3 ms.

  Note that the store operation in the present embodiment is the same as that in the third embodiment, and a description thereof will be omitted.

<Sixth Embodiment>
FIG. 17 is a block diagram showing a configuration of a nonvolatile RAM according to the sixth embodiment of the present invention. The present embodiment is a modification of the fifth embodiment. In the present embodiment, the nonvolatile RAM cell array 110 and the column selection circuit 300-j (j = 0 to n) and the column gate 400 in the fifth embodiment are the nonvolatile RAM cell array 120 and the column selection circuit 320-j (j = 0-n), replaced by column gate 420.

  The non-volatile AM cell array 120 is formed by arranging the non-volatile memory cells 10A of the second embodiment (FIG. 4) in a matrix. As in the fifth embodiment, the high-potential-side power supply voltage VDCk (k = 0 to m) is independently applied to each row k of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) forming a matrix. A power line is provided for supplying. A power supply line for supplying the high-potential-side power supply voltage VDCk (k = 0 to m) for each row k of the nonvolatile memory cell Mkj (k = 0 to m, j = 0 to n) is the row selection circuit 220. -K (k = 0 to m) are connected to each other.

  The column gate 420 includes a CMOS transfer gate TGj (j = 0 to n) composed of a P channel transistor CGpj and an N channel transistor CGnj, and a CMOS transfer gate TGjB (j = 0) composed of a P channel transistor CGpjB and an N channel transistor CGnjB, respectively. To n). Here, the CMOS transfer gate TGj (j = 0 to n) is interposed between the data line DL and the bit line BITj (j = 0 to n). The CMOS transfer gate TGjB (j = 0 to n) is interposed between the inverted data line DLB and the inverted bit line BITjB (j = 0 to n).

  Along with the switch constituting the column gate 420 being a CMOS transfer gate, the column selection circuit 320-j (j = 0 to n) in the column selection circuit 320-j (j = 0 to n) of the fifth embodiment. The level shifter 303 is replaced with two level shifters 304 and 305. These level shifters 304 and 305 are supplied with a reference bit line voltage VWD lower than the reference column selection voltage VCOL of the fifth embodiment as a high potential side power supply voltage. As described above, in this embodiment, the power supply voltage for generating the column selection voltage for turning on the switch of the column gate 400 is changed from the reference column selection voltage VCOL to the reference bit line voltage VWD.

  In each column selection circuit 300-j (j = 0 to n), the level shifter 304 inverts the output signal of the AND gate 302. When the inversion result is “0”, 0V is set, and “1”. Supplies reference bit line voltage VWD to the gates of N-channel transistors CGnj and CGnjB corresponding to each column j in column gate 420. In each column selection circuit 300-j (j = 0 to n), the level shifter 305 inverts the output signal of the level shifter 304, and when the inversion result is “0”, 0V is set to “1”. In this case, reference bit line voltage VWD is supplied to each gate of P channel transistors CGpj and CGnjB corresponding to each column j in column gate 420.

  The store operation in this embodiment is the same as that in the fifth embodiment, but the recall operation in this embodiment is slightly different from that in the fifth embodiment. In this embodiment, when a recall is performed, the power supply voltage VDD is set to the reference bit line voltage VWD, and this reference bit line voltage VWD is set to all the bit lines BITj (j = 0 to n) and all the inverted bit lines BITjB (j = 0 to n). As a result, each nonvolatile memory cell Mkj can be recalled under the operating conditions shown in FIG. 5 and the data stored in the nonvolatile storage unit 12 can be held in the volatile storage unit 11.

  According to the present embodiment, since the switch constituting the column gate 400 is a CMOS transfer gate, the layout area is somewhat increased. However, when the switch constituting the column gate 400 is a CMOS transfer gate, the voltage of the data lines DL and DLB can be raised to the level of the column selection voltage, so that it is necessary to output the column selection voltage VCOLj to the booster circuit. Disappear. Therefore, the power consumption of the nonvolatile RAM can be reduced.

<Seventh embodiment>
FIG. 18 is a circuit diagram showing a configuration of a nonvolatile RAM according to the seventh embodiment of the present invention. This embodiment is a modification of the fifth embodiment (FIG. 13). In this embodiment, the column selection circuit 300-j (j = 0 to n) in the fifth embodiment is replaced with a column selection circuit 330-j (j = 0 to n), and the bit line BITj (j = 0). ˜n) and the inverted bit line BITjB (j = 0 to n) are connected to a bias circuit 900 dedicated for storing and recalling.

  The column selection circuit 330-j (j = 0 to n) replaces the level shifter 303 of the column selection circuit 300-j (j = 0 to n) in the fifth embodiment (FIG. 13) with a normal inverter having no level shift function. The configuration is replaced with 306. The inverter 306 is supplied with a power supply voltage VDD for the nonvolatile RAM.

  Bias circuit 900 includes inverter 901, NOR gate 903, level shifters 902 and 904, and N-channel transistors SRGj (j = 0 to n) and SRGjB (j = 0 to n).

  Inverter 901 inverts store instruction signal STR and outputs the inverted signal. The level shifter 902 is supplied with the reference bit line voltage VWD output from the power supply control circuit 510 as a high potential side power supply voltage. The level shifter 902 inverts the output signal of the inverter 901, and outputs 0 V when the inversion result is “0”, and outputs the reference bit line voltage VWD to the common source line COM when it is “1”.

  N-channel bit line selection transistors SRGj (j = 0 to n) are interposed between the common source line COM and the bit lines BITj (j = 0 to n). An N-channel inverted bit line selection transistor SRGjB (j = 0 to n) is interposed between the common source line COM and the inverted bit line BITjB (j = 0 to n). The gates of the bit line selection transistor SRGj (j = 0 to n) and the inverted bit line selection transistor SRGjB (j = 0 to n) are connected to the common gate line SR.

  The NOR gate 903 is supplied with a store instruction signal STR and a recall instruction signal RCL. A reference power supply voltage VDC output from the power supply control circuit 510 is applied to the level shifter 904 as a high potential side power supply voltage. The level shifter 904 inverts the output signal of the NOR gate 903, and outputs 0 V when the inversion result is “0”, and outputs the reference power supply voltage VDC to the common gate line SR when the inversion result is “1”.

  Next, the store operation of the present embodiment will be described. When the store instruction signal STR becomes High level, the control circuit 501 supplies the power supply control circuit 510 with a reference power supply voltage VDC of 1.2V, a reference write voltage VWR of 1.5V, and a reference bit line voltage VWD of 0.6V. Output.

  Further, since the store instruction signal STR is at a high level, the bias circuit 900 outputs the reference bit line voltage VWD = 0.6V to the common source line COM, and supplies the reference power supply voltage VDC = 1.2V to the common gate line SR. Output to. As a result, the bit line selection transistor SRGj (j = 0 to n) and the inverted bit line selection transistor SRGjB (j = 0 to n) are turned on, and the reference bit line voltage VWD = 0.6 V is set to the bit line BITj (j = 0). To n) and the inverted bit line BITjB (j = 0 to n).

  In this state, the row indicated by the row address ADDX is sequentially switched from the 0th row to the mth row. Then, the row selection circuit 220-k (see FIG. 14) corresponding to the row k indicated by the row address ADDX outputs the reference write voltage VWR = 1.5V as the write voltage WREk. As a result, the store operation is performed in the nonvolatile memory cells Mkj (j = 0 to n) corresponding to the row k.

  Next, the operation at the time of recall of this embodiment will be described. When the recall instruction signal RCL becomes High level, the control circuit 501 causes the power supply control circuit 510 to output the 0.6V reference power supply voltage VDC, the 0.3V reference write voltage VWR, and the 0V reference bit line voltage VWD. .

  The bias circuit 900 outputs the reference bit line voltage VWD = 0V to the common source line COM and outputs the reference power supply voltage VDC = 0.6V to the common gate line SR because the recall instruction signal RCL is at the high level. To do. As a result, the bit line selection transistor SRGj (j = 0 to n) and the inverted bit line selection transistor SRGjB (j = 0 to n) are turned on, and the reference bit line voltage VWD = 0 V is set to the bit line BITj (j = 0 to n). ) And the inverted bit line BITjB (j = 0 to n).

  In this state, the row indicated by the row address ADDX is sequentially switched from the 0th row to the mth row. The row selection circuit 220-k corresponding to the row k indicated by the row address ADDX outputs the reference write voltage VWR = 1.5V as the write voltage WREk, and corresponds to the row k with a delay of time Δt1 from this timing. The raised power supply voltage VDCk is raised (see FIG. 16). As a result, the recall operation is performed in the nonvolatile memory cells Mkj (j = 0 to n) corresponding to the row k.

  In the present embodiment, the common gate line SR is connected to all the gates of the bit line selection transistor SRGj (j = 0 to n) and the inverted bit line selection transistor SRGjB (j = 0 to n). The address may be divided into a plurality of groups, and the common gate line SR may be divided accordingly. For example, the gates of the bit line selection transistor and the inverted bit line selection transistor corresponding to each column address of the 0th group are connected to the 0th common gate line SR0, and the bit line corresponding to each column address of the first group Each gate of the selection transistor and the inverted bit line selection transistor is connected to the first common gate line SR0, and so on, and the common gate line SR is divided. Then, a plurality of groups are sequentially selected, and the reference power supply voltage VDC = 0.6 V is applied to the common gate line of the selected group, and the store operation of the nonvolatile memory cells of the group is performed. According to this aspect, the store current that flows in one store operation can be reduced.

<Eighth Embodiment>
FIG. 19 is a circuit diagram showing configurations of a row selection circuit 230-k and nonvolatile memory cells Mkj (j = 0 to n) for one row of the nonvolatile RAM according to the eighth embodiment of the present invention. This embodiment is a modification of the fifth embodiment (FIG. 13).

  The difference of the present embodiment from the fifth embodiment is that the sources of the P-channel transistors P1 and P2 of all the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) are connected in common to the reference power supply. A power supply line that applies a voltage VDC and supplies a low-potential-side power supply voltage to the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) is divided into rows, and a row selection circuit 230-corresponding to each row The low-potential-side power supply voltage VSCk (k = 0 to m) is supplied for each row from k.

  FIG. 20 is a diagram showing operating conditions of the present embodiment. As shown in FIG. 20, the recall operation differs between the operation of the present embodiment and the operation of the fifth embodiment (see FIGS. 5 and 16).

  After powering on the nonvolatile RAM, the row selection circuit 230-k supplies the low-potential-side power supply voltage VSCk to the nonvolatile memory cells Mkj (j = 0 to n) in the row k during a period when the row address ADDX does not indicate the row k. VDC = 0.6V and the write voltage WREk is 0V.

  However, when the row address ADDX indicating the row k is given, the row selection circuit 230-k first sets the write voltage WREk for the nonvolatile memory cells Mkj (j = 0 to n) in the row k to 0.3 V, Next, the low potential side power supply voltage VSCk is decreased from 0.6V to 0V. As a result, the data stored in the nonvolatile storage unit 12 in the nonvolatile memory cell Mkj (j = 0 to n) in the row k is held in the volatile storage unit 11. Once the low-potential-side power supply voltage VSCk reaches 0V, it is maintained at 0V unless a reset is applied thereafter.

Then, the row address ADDX is sequentially switched from the address indicating the 0th row to the address indicating the mth row, this recall operation is repeated, and the recall operation for all the nonvolatile memory cells is completed. Thereafter, the nonvolatile RAM operates as a normal SRAM.
Since the store operation in the present embodiment is the same as that in the fifth embodiment, description thereof is omitted.

<Ninth Embodiment>
FIG. 21 is a circuit diagram showing configurations of a row selection circuit 240-k and nonvolatile memory cells Mkj (j = 0 to n) for one row of the nonvolatile RAM according to the ninth embodiment of the present invention. This embodiment is a modification of the fifth embodiment (FIG. 13). The difference of the present embodiment from the fifth embodiment is that each power line supplying the power supply voltages VDC and VSS is arranged along each column of nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n). Connection between the power supply line for supplying the power supply voltage VDC of each column and the sources of the P channel transistors P1 and P2 in each column of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) A P-channel source selection transistor Tw3 is interposed between the point and each of the source selection transistors Tw3 of the nonvolatile memory cells Mkj (j = 0 to n) in the row k from the row selection circuit 240-k corresponding to each row. The source selection control voltage RCSBk is supplied to the gate.

  In the fifth embodiment, the row selection circuit 220-k (see FIG. 14) raises the power supply voltage VDCk supplied to the nonvolatile memory cells Mkj (j = 0 to n) in the row k, thereby causing the nonvolatile in the row k. The memory cell Mkj (j = 0 to n) was caused to perform a recall operation.

On the other hand, in this embodiment, the row selection circuit 240-k outputs the source selection control voltage RCSBk that turns on the P-channel transistor Tw3 of the nonvolatile memory cell Mkj (j = 0 to n) of the row k. The recall operation is performed on the k nonvolatile memory cells Mkj (j = 0 to n).
Since the store operation in the present embodiment is the same as that in the fifth embodiment, description thereof is omitted.

  According to the present embodiment, the power supply line for supplying the high potential side power supply voltage VDC and the power supply line for supplying the low potential side power supply voltage VSS are connected to the nonvolatile memory cells Mkj (k = 0 to m, j = Wiring can be performed in the direction crossing each row along each column of 0-n). Accordingly, when the store operation and the recall operation of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) are performed in units of rows, one power supply line for supplying the high potential side power supply voltage VDC. In addition, only a current consumption corresponding to one nonvolatile memory cell flows through one power supply line for supplying the low potential side power supply voltage VSS. Therefore, in determining the line width of each power supply line, only the current consumption for one bit (one nonvolatile memory cell) needs to be considered, and the voltage drop due to the wiring resistance of each power supply line is reduced. Can do.

<Tenth Embodiment>
FIG. 22 is a circuit diagram showing configurations of a row selection circuit 250-k and nonvolatile memory cells Mkj (j = 0 to n) for one row of the nonvolatile RAM according to the tenth embodiment of the present invention. This embodiment is a modification of the eighth embodiment (FIG. 19). The difference of this embodiment from the eighth embodiment is that each power supply line for supplying power supply voltages VDC and VSS is arranged along each column of nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n). Connection between the power supply line for supplying the power supply voltage VSS of each column and the sources of the N channel transistors N1 and N2 in each column of the nonvolatile memory cells Mkj (k = 0 to m, j = 0 to n) An N-channel source selection transistor Tw4 is interposed between the point and each of the source selection transistors Tw4 of the nonvolatile memory cell Mkj (j = 0 to n) in the row k from the row selection circuit 250-k corresponding to each row. The source selection control voltage RCSK is supplied to the gate.

  In the eighth embodiment, the row selection circuit 230-k (see FIG. 19) raises the low-potential-side power supply voltage VSCk supplied to the nonvolatile memory cells Mkj (j = 0 to n) in the row k, thereby causing the row k. The non-volatile memory cell Mkj (j = 0 to n) was subjected to a recall operation.

On the other hand, in this embodiment, the row selection circuit 250-k outputs the source selection control voltage RCSK that turns on the source selection transistor Tw4 of the nonvolatile memory cell Mkj (j = 0 to n) of the row k. The recall operation is performed on the k nonvolatile memory cells Mkj (j = 0 to n).
Also in this embodiment, the same effect as the ninth embodiment can be obtained.

<Other embodiments>
Although the first to tenth embodiments of the present invention have been described above, other embodiments are conceivable for the present invention. For example:

(1) In each of the above embodiments, at the time of storing and recalling, a row address is given from outside the non-volatile RAM, and this row address is switched from outside to perform storing and recall in units of rows. However, instead of doing so, a row address generating means for outputting sequentially changing row addresses by a counter or the like is provided in the nonvolatile RAM, and store and recall are performed using the row address output by the row address generating means. May be performed.

(2) In each of the above embodiments, all the cells of the RAM cell array are configured by nonvolatile memory cells including a volatile storage unit and a nonvolatile storage unit. However, instead of doing so, a part of the RAM cell array may be constituted by nonvolatile memory cells, and the remaining area may be constituted by normal SRAM memory cells. That is, only a part of the entire memory space of the SRAM is made an area that can be stored and recalled.

(3) In the third to fifth and seventh to tenth embodiments, the nonvolatile RAM cell array is configured using the nonvolatile memory cell 10 of the first embodiment. In the sixth embodiment, the nonvolatile RAM cell array is configured using the nonvolatile memory cell 10A of the second embodiment. However, in the third to fifth and seventh to tenth embodiments, the nonvolatile RAM cell array may be configured using the nonvolatile memory cell 10A of the second embodiment. In the sixth embodiment, a nonvolatile RAM cell array may be configured using the nonvolatile memory cell 10 of the first embodiment.

  When a nonvolatile RAM cell array is configured using the nonvolatile memory cell 10 of the first embodiment, it is used for expressing “1” / “0” in the volatile storage unit 11 of the nonvolatile memory cell at the time of storing. An intermediate voltage between the two types of voltages may be applied to each bit line and each inverted bit line as a reference bit line voltage. At the time of recall, the lower voltage (for example, 0 V) of the two kinds of voltages used to express “1” / “0” in the volatile memory unit 11 of the nonvolatile memory cell is used as the reference bit line voltage. What is necessary is just to give to each bit line and each inversion bit line.

  Further, when the nonvolatile RAM cell array is configured using the nonvolatile memory cell 10A of the second embodiment, “1” / “0” is expressed in the volatile storage unit 11 of the nonvolatile memory cell at the time of storing. An intermediate voltage between the two types of voltages used in the above may be applied to each bit line and each inverted bit line as a reference bit line voltage. Further, at the time of recall, the higher voltage (for example, the volatile storage unit during normal operation) of the two types of voltages used to express “1” / “0” in the volatile storage unit 11 of the nonvolatile memory cell. 11 is applied to each bit line and each inverted bit line as a reference bit line voltage.

(4) Various operating voltages disclosed in the above embodiments are based on the resistance element characteristics described in Non-Patent Document 1. However, development in this field is progressing, and in the future, a variable resistance element that can store, recall, or read out sufficiently even at a low power supply voltage of 0.6 V or lower and does not require a boosted voltage. Is expected to be realized. The present invention does not preclude changing the operating voltage value in accordance with a new variable resistance element in such a case. A mode in which the operating voltage value is changed in accordance with the characteristics of such a new variable resistance element also belongs to the scope of the present invention.

10, 10A, Mkj: Non-volatile memory cell, 11: Volatile memory unit, 12, 12A: Non-volatile memory unit, P1, P2, Tw3: P channel transistor, N1, N2, Ta1, Ta2, Tw1 , Tw2, Tw4... N channel transistor, R1, R2... Variable resistance element, INV1, INV2... Inverter, BL, BLB, BITj, BITjB... Bit line, 100, 110, 120. , 200 ... row decoder, 300 ... column decoder, 400, 420 ... column gate, 600 ... sense amplifier, 700 ... input / output buffer, 800 ... write circuit, 500 ... control unit, 501 ... Control circuit, 510... Power supply control circuit, 200-k, 220-k, 230-k, 240-k, 250-k, row selection circuit 300-j, 320-j, 330-j... Column selection circuit, 201, 221 and 301... Address match detection unit, L1... Latch, 226 ... delay circuit, 207, 228, 233, 303, 304, 305, 902, 904... Level shifter.

Claims (32)

A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are respectively provided on the bit line and the inverted bit line side,
The third and fourth switches are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. A non-volatile memory having a non-volatile memory cell array composed of non-volatile memory cells, which is a variable resistance element
The third and fourth switches of the nonvolatile memory cell are formed of field effect transistors;
When performing storage for writing data from the volatile storage unit to the nonvolatile storage unit in the nonvolatile memory cell, the first and second switches are turned off, and the volatile storage unit is operated during normal operation. An intermediate voltage between two kinds of voltages used to express “1” / “0” in the volatile memory unit by applying a gate voltage higher than the power supply voltage to turn on the third and fourth switches. To the bit line and the inverted bit line,
When performing a recall to write data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell, the first and second switches are turned OFF, and the volatile memory unit during normal operation is turned off. Two types of voltages used to express “1” / “0” in the volatile memory unit during normal operation by applying a gate voltage lower than the power supply voltage to turn on the third and fourth switches. A non-volatile memory, wherein a power supply voltage for the volatile memory portion is raised from 0 V to a power supply voltage during normal operation in a state where the lower voltage is supplied to the bit line and the inverted bit line . A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are respectively provided on the bit line and the inverted bit line side,
The third and fourth switches are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. A non-volatile memory having a non-volatile memory cell array composed of non-volatile memory cells, which is a variable resistance element
The third and fourth switches of the nonvolatile memory cell are formed of field effect transistors;
When performing storage for writing data from the volatile storage unit to the nonvolatile storage unit in the nonvolatile memory cell, the first and second switches are turned off, and the volatile storage unit is operated during normal operation. A power supply voltage higher than the power supply voltage is applied to the volatile storage unit, a gate voltage higher than the power supply voltage for the volatile storage unit at the time of storage is applied to turn on the third and fourth switches, and the store Supplying an intermediate voltage between two kinds of voltages used to express “1” / “0” in the volatile memory unit to the bit line and the inverted bit line;
When performing a recall to write data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell, the first and second switches are turned OFF, and the volatile memory unit during normal operation is turned off. Two types of voltages used to express “1” / “0” in the volatile memory unit during normal operation by applying a gate voltage lower than the power supply voltage to turn on the third and fourth switches. A non-volatile memory, wherein a power supply voltage for the volatile memory portion is raised from 0 V to a power supply voltage during normal operation in a state where the lower voltage is supplied to the bit line and the inverted bit line. In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are respectively provided on the bit line and the inverted bit line side,
The third and fourth switches are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
Means for outputting a voltage corresponding to write data to the data line and the inverted data line during normal operation, and in the nonvolatile memory cell array, when storing data from the volatile storage unit to the nonvolatile storage unit In the volatile memory portion of the nonvolatile memory cell, an intermediate voltage between two kinds of voltages used to express “1” / “0” is output to the data line and the inverted data line as a reference bit line voltage. At the time of recall for writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, it is used to express “1” / “0” in the volatile memory unit during normal operation. A write circuit that outputs the lower of the two types of voltages to the data line and the inverted data line as a reference bit line voltage;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the nonvolatile memory cell is at the store and the recall time. The first and second switches of all the nonvolatile memory cells in the memory cell array are turned OFF, and the third and fourth switches in the row unit of each nonvolatile memory cell in the nonvolatile memory cell array are stored during the storage. A row decoder that performs ON / OFF control and performs ON / OFF control of the third and fourth switches of each nonvolatile memory cell of the nonvolatile memory cell array at the time of recall;
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for connection to each line;
A non-volatile memory comprising: The row decoder outputs a write voltage for turning on the third and fourth switches of each nonvolatile memory cell belonging to the row indicated by the row address at the time of the store, and at the time of the recall, the row decoder 4. The non-volatile memory according to claim 3, wherein a write voltage for turning on the third and fourth switches of each non-volatile memory cell in all rows is output. A power supply control circuit including a booster circuit that boosts a power supply voltage for the nonvolatile memory;
The row decoder outputs a first voltage boosted by the booster circuit as a power supply voltage for each nonvolatile memory cell of the nonvolatile memory cell array during the store, and is a voltage boosted by the booster circuit. 5. The nonvolatile memory according to claim 4, wherein a second voltage higher than the first voltage is supplied to each nonvolatile memory cell in a row indicated by the row address as the write voltage. In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are respectively provided on the bit line and the inverted bit line side,
The third and fourth switches are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
Means for outputting a voltage corresponding to write data to the data line and the inverted data line during normal operation, and in the nonvolatile memory cell array, when storing data from the volatile storage unit to the nonvolatile storage unit In the volatile memory portion of the nonvolatile memory cell, an intermediate voltage between two kinds of voltages used to express “1” / “0” is output to the data line and the inverted data line as a reference bit line voltage. At the time of recall for writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, it is used to express “1” / “0” in the volatile memory unit during normal operation. A write circuit that outputs the lower of the two types of voltages to the data line and the inverted data line as a reference bit line voltage;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the nonvolatile memory cell is at the store and the recall time. The first and second switches of all the nonvolatile memory cells in the memory cell array are turned OFF, and the third and fourth switches in the row unit of each nonvolatile memory cell in the nonvolatile memory cell array are stored during the storage. ON / OFF control is performed, and at the time of the recall, ON / OFF control of the third and fourth switches in units of rows of the nonvolatile memory cells of the nonvolatile memory cell array, and the third and fourth switches are controlled. A row decoder for controlling the rise of the power supply voltage for each non-volatile memory cell that is turned ON;
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for connection to each line;
A non-volatile memory comprising: The row decoder outputs a write voltage for turning on the third and fourth switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array at the time of storing, and at the time of the recall, After the power supply voltage for the nonvolatile memory is raised, a write voltage for turning on the third and fourth switches of each nonvolatile memory cell belonging to the row indicated by the row address in the nonvolatile memory cell array is output. 7. The nonvolatile memory according to claim 6, wherein a power supply voltage for each nonvolatile memory cell belonging to the row is raised, and the raised power supply voltage is maintained. The column decoder outputs the write voltage for turning on the third and fourth switches of the nonvolatile memory cells belonging to one row during the store, while the row decoder outputs the write voltage. Each column is divided into a plurality of groups, each group is sequentially selected, and each bit line and each inverted bit line to which each nonvolatile memory cell of each column of the selected group is connected in the nonvolatile memory cell array The nonvolatile memory according to claim 3, wherein the column gate for connecting to the data line and the inverted data line is sequentially controlled. In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are respectively provided on the bit line and the inverted bit line side,
The third and fourth switches are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
A write circuit for outputting a voltage corresponding to write data during normal operation to the data line and the inverted data line;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the volatile storage unit in the nonvolatile memory cell array When storing data from the nonvolatile memory cell array and when recalling writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, all nonvolatile memory cells in the nonvolatile memory cell array The first and second switches are turned off, the third and fourth switches are turned on and off in units of rows of the nonvolatile memory cells of the nonvolatile memory cell array at the time of storing, and at the time of the recall A row of each nonvolatile memory cell in the nonvolatile memory cell array A row decoder for raising control of the power supply voltage to the third and fourth switches ON / OFF control, and the third and fourth of each nonvolatile memory cell is turned ON the switch in position,
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for separation from the line;
At the time of storing, “1” / “0” in the volatile memory portion of the nonvolatile memory cell for each bit line and each inverted bit line to which the nonvolatile memory cells of each column of the nonvolatile memory cell array are connected. An intermediate voltage between two kinds of voltages used to express the signal is output as a reference bit line voltage, and at the time of the recall, the volatile memory unit during normal operation expresses “1” / “0”. A bias circuit for outputting a lower one of the two kinds of voltages used as the reference bit line voltage;
A non-volatile memory comprising: The bias circuit includes a common source line for supplying the reference bit line voltage, and a plurality of bit line selection switches interposed between the common source line, the bit lines, and the inverted bit lines, respectively. The nonvolatile memory according to claim 9, wherein the plurality of bit line selection switches are turned on at the time of storing and at the time of recall. The bias circuit outputs the write voltage for turning on the third and fourth switches of the nonvolatile memory cells belonging to one row during the store while the row decoder outputs the write voltage. Each column is divided into a plurality of groups, each group is sequentially selected, and each bit line and each inverted bit line to which each nonvolatile memory cell in each column of the selected group is connected in the nonvolatile memory cell array The nonvolatile memory according to claim 9, wherein the control for outputting the reference bit voltage is sequentially performed. In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are respectively provided on the bit line and the inverted bit line side,
The third and fourth switches are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
Means for outputting a voltage corresponding to write data to the data line and the inverted data line during normal operation, and in the nonvolatile memory cell array, when storing data from the volatile storage unit to the nonvolatile storage unit In the volatile memory portion of the nonvolatile memory cell, an intermediate voltage between two kinds of voltages used to express “1” / “0” is output to the data line and the inverted data line as a reference bit line voltage. At the time of recall for writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, it is used to express “1” / “0” in the volatile memory unit during normal operation. A write circuit that outputs the lower of the two types of voltages to the data line and the inverted data line as a reference bit line voltage;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the nonvolatile memory cell is at the store and the recall time. The first and second switches of all the nonvolatile memory cells in the memory cell array are turned OFF, and the third and fourth switches in the row unit of each nonvolatile memory cell in the nonvolatile memory cell array are stored during the storage. ON / OFF control is performed, and at the time of the recall, the ON / OFF control of the third and fourth switches and the third and fourth switches are turned ON for each nonvolatile memory cell of the nonvolatile memory cell array. By reducing the low-potential-side power supply voltage for each nonvolatile memory cell A row decoder for controlling turning on the power voltage on sexual memory cell,
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for connection to each line;
  A non-volatile memory comprising: In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile storage unit, a nonvolatile storage unit, a power line for supplying a high-potential-side power supply voltage, and a high-potential-side power switch interposed between the high-potential-side power supply node in the volatile storage unit, Have
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are respectively provided on the bit line and the inverted bit line side,
The third and fourth switches are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
Means for outputting a voltage corresponding to write data to the data line and the inverted data line during normal operation, and in the nonvolatile memory cell array, when storing data from the volatile storage unit to the nonvolatile storage unit In the volatile memory portion of the nonvolatile memory cell, an intermediate voltage between two kinds of voltages used to express “1” / “0” is output to the data line and the inverted data line as a reference bit line voltage. At the time of recall for writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, it is used to express “1” / “0” in the volatile memory unit during normal operation. A write circuit that outputs the lower of the two types of voltages to the data line and the inverted data line as a reference bit line voltage;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the nonvolatile memory cell at the time of storing and recalling The first and second switches of all the nonvolatile memory cells in the nonvolatile memory cell array are turned OFF, and the third and fourth switches in the row unit of each nonvolatile memory cell in the nonvolatile memory cell array at the time of storing ON / OFF control of the third and fourth switches in the row unit of each nonvolatile memory cell of the nonvolatile memory cell array, and the third and fourth switches at the time of the recall. By turning on the high potential side power switch of each nonvolatile memory cell whose switch is turned on, A row decoder for the control of turning on the power voltage for the nonvolatile memory cell,
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for connection to each line;
A non-volatile memory comprising: Each power line for supplying a high-potential-side power supply voltage and a low-potential-side power supply line to each volatile memory portion of each nonvolatile memory cell is in a direction crossing each row along each column of the nonvolatile memory cell array. The nonvolatile memory according to claim 13, wherein the nonvolatile memory is wired. In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile memory unit; a nonvolatile memory unit; a power line for supplying a low-potential-side power supply voltage; and a low-potential-side power switch interposed between the low-potential-side power node in the volatile memory unit; Have
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are respectively provided on the bit line and the inverted bit line side,
The third and fourth switches are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
Means for outputting a voltage corresponding to write data to the data line and the inverted data line during normal operation, and in the nonvolatile memory cell array, when storing data from the volatile storage unit to the nonvolatile storage unit In the volatile memory portion of the nonvolatile memory cell, an intermediate voltage between two kinds of voltages used to express “1” / “0” is output to the data line and the inverted data line as a reference bit line voltage. At the time of recall for writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, it is used to express “1” / “0” in the volatile memory unit during normal operation. A write circuit that outputs the lower of the two types of voltages to the data line and the inverted data line as a reference bit line voltage;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the nonvolatile memory cell is at the store and the recall time. The first and second switches of all the nonvolatile memory cells in the memory cell array are turned OFF, and the third and fourth switches in the row unit of each nonvolatile memory cell in the nonvolatile memory cell array are stored during the storage. ON / OFF control is performed, and at the time of the recall, the ON / OFF control of the third and fourth switches and the third and fourth switches are turned ON for each nonvolatile memory cell of the nonvolatile memory cell array. Each non-volatile memory cell is turned on by turning on the low potential side power switch. A row decoder for controlling turning on the power voltage for the nonvolatile memory cell,
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for connection to each line;
A non-volatile memory comprising: Each power line for supplying a high-potential-side power supply voltage and a low-potential-side power supply line to each volatile memory portion of each nonvolatile memory cell is in a direction crossing each row along each column of the nonvolatile memory cell array. The nonvolatile memory according to claim 15, wherein the nonvolatile memory is wired. A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
The third and fourth switches are provided on the bit line and the inverted bit line side, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. A non-volatile memory having a non-volatile memory cell array composed of non-volatile memory cells, which is a variable resistance element
The third and fourth switches of the nonvolatile memory cell are formed of field effect transistors;
When performing storage for writing data from the volatile storage unit to the nonvolatile storage unit in the nonvolatile memory cell, the first and second switches are turned off, and the volatile storage unit is operated during normal operation. An intermediate voltage between two kinds of voltages used to express “1” / “0” in the volatile memory unit by applying a gate voltage higher than the power supply voltage to turn on the third and fourth switches. To the bit line and the inverted bit line,
When performing a recall to write data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell, the first and second switches are turned OFF, and the volatile memory unit during normal operation is turned off. Two types of voltages used to express “1” / “0” in the volatile memory unit during normal operation by applying a gate voltage lower than the power supply voltage to turn on the third and fourth switches. A non-volatile memory, wherein a power supply voltage for the volatile memory portion is raised from 0 V to a power supply voltage during normal operation in a state where a higher voltage is supplied to the bit line and the inverted bit line. A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
The third and fourth switches are provided on the bit line and the inverted bit line side, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. A non-volatile memory having a non-volatile memory cell array composed of non-volatile memory cells, which is a variable resistance element
The third and fourth switches of the nonvolatile memory cell are formed of field effect transistors;
When performing storage for writing data from the volatile storage unit to the nonvolatile storage unit in the nonvolatile memory cell, the first and second switches are turned off, and the volatile storage unit is operated during normal operation. A power supply voltage higher than the power supply voltage is applied to the volatile storage unit, a gate voltage higher than the power supply voltage for the volatile storage unit at the time of storage is applied to turn on the third and fourth switches, and the store Supplying an intermediate voltage between two kinds of voltages used to express “1” / “0” in the volatile memory unit to the bit line and the inverted bit line;
When performing a recall to write data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell, the first and second switches are turned OFF, and the volatile memory unit during normal operation is turned off. Two types of voltages used to express “1” / “0” in the volatile memory unit during normal operation by applying a gate voltage lower than the power supply voltage to turn on the third and fourth switches. A non-volatile memory, wherein a power supply voltage for the volatile memory portion is raised from 0 V to a power supply voltage during normal operation in a state where a higher voltage is supplied to the bit line and the inverted bit line. In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
The third and fourth switches are provided on the bit line and the inverted bit line side, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
Means for outputting a voltage corresponding to write data to the data line and the inverted data line during normal operation, and in the nonvolatile memory cell array, when storing data from the volatile storage unit to the nonvolatile storage unit In the volatile memory portion of the nonvolatile memory cell, an intermediate voltage between two kinds of voltages used to express “1” / “0” is output to the data line and the inverted data line as a reference bit line voltage. At the time of recall for writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, it is used to express “1” / “0” in the volatile memory unit during normal operation. A write circuit that outputs the higher of the two types of voltages to the data line and the inverted data line as a reference bit line voltage;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the nonvolatile memory cell is at the store and the recall time. The first and second switches of all the nonvolatile memory cells in the memory cell array are turned OFF, and the third and fourth switches in the row unit of each nonvolatile memory cell in the nonvolatile memory cell array are stored during the storage. A row decoder that performs ON / OFF control and performs ON / OFF control of the third and fourth switches of each nonvolatile memory cell of the nonvolatile memory cell array at the time of recall;
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for connection to each line;
A non-volatile memory comprising: The row decoder outputs a write voltage for turning on the third and fourth switches of each nonvolatile memory cell belonging to the row indicated by the row address at the time of the store, and at the time of the recall, the row decoder The nonvolatile memory according to claim 19, wherein a write voltage for turning on the third and fourth switches of each nonvolatile memory cell in all rows is output. A power supply control circuit including a booster circuit that boosts a power supply voltage for the nonvolatile memory;
The row decoder outputs a first voltage boosted by the booster circuit as a power supply voltage for each nonvolatile memory cell of the nonvolatile memory cell array during the store, and is a voltage boosted by the booster circuit. 21. The nonvolatile memory according to claim 20, wherein a second voltage higher than the first voltage is supplied to each nonvolatile memory cell in a row indicated by the row address as the write voltage. In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
The third and fourth switches are provided on the bit line and the inverted bit line side, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
Means for outputting a voltage corresponding to write data to the data line and the inverted data line during normal operation, and in the nonvolatile memory cell array, when storing data from the volatile storage unit to the nonvolatile storage unit In the volatile memory portion of the nonvolatile memory cell, an intermediate voltage between two kinds of voltages used to express “1” / “0” is output to the data line and the inverted data line as a reference bit line voltage. At the time of recall for writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, it is used to express “1” / “0” in the volatile memory unit during normal operation. A write circuit that outputs the higher of the two types of voltages to the data line and the inverted data line as a reference bit line voltage;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the nonvolatile memory cell is at the store and the recall time. The first and second switches of all the nonvolatile memory cells in the memory cell array are turned OFF, and the third and fourth switches in the row unit of each nonvolatile memory cell in the nonvolatile memory cell array are stored during the storage. ON / OFF control is performed, and at the time of the recall, ON / OFF control of the third and fourth switches in units of rows of the nonvolatile memory cells of the nonvolatile memory cell array, and the third and fourth switches are controlled. A row decoder for controlling the rise of the power supply voltage for each non-volatile memory cell that is turned ON;
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for connection to each line;
  A non-volatile memory comprising: The row decoder outputs a write voltage for turning on the third and fourth switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array at the time of storing, and at the time of the recall, After the power supply voltage for the nonvolatile memory is raised, a write voltage for turning on the third and fourth switches of each nonvolatile memory cell belonging to the row indicated by the row address in the nonvolatile memory cell array is output. 23. The nonvolatile memory according to claim 22, wherein a power supply voltage for each nonvolatile memory cell belonging to the row is raised, and the raised power supply voltage is maintained. The column decoder outputs the write voltage for turning on the third and fourth switches of the nonvolatile memory cells belonging to one row during the store, while the row decoder outputs the write voltage. Each column is divided into a plurality of groups, each group is sequentially selected, and each bit line and each inverted bit line to which each nonvolatile memory cell of each column of the selected group is connected in the nonvolatile memory cell array 23. The nonvolatile memory according to claim 19, wherein the column gate for connecting to the data line and the inverted data line is sequentially controlled. In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
The third and fourth switches are provided on the bit line and the inverted bit line side, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
A write circuit for outputting a voltage corresponding to write data during normal operation to the data line and the inverted data line;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the volatile storage unit in the nonvolatile memory cell array When storing data from the nonvolatile memory cell array and when recalling writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, all nonvolatile memory cells in the nonvolatile memory cell array The first and second switches are turned off, the third and fourth switches are turned on and off in units of rows of the nonvolatile memory cells of the nonvolatile memory cell array at the time of storing, and at the time of the recall A row of each nonvolatile memory cell in the nonvolatile memory cell array A row decoder for raising control of the power supply voltage to the third and fourth switches ON / OFF control, and the third and fourth of each nonvolatile memory cell is turned ON the switch in position,
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for separation from the line;
At the time of storing, “1” / “0” in the volatile memory portion of the nonvolatile memory cell for each bit line and each inverted bit line to which the nonvolatile memory cells of each column of the nonvolatile memory cell array are connected. An intermediate voltage between two kinds of voltages used to express the signal is output as a reference bit line voltage, and at the time of the recall, the volatile memory unit during normal operation expresses “1” / “0”. A bias circuit for outputting a higher one of the two kinds of voltages used as the reference bit line voltage;
A non-volatile memory comprising: The bias circuit includes a common source line for supplying the reference bit line voltage, and a plurality of bit line selection switches interposed between the common source line, the bit lines, and the inverted bit lines, respectively. 26. The nonvolatile memory according to claim 25, wherein the plurality of bit line selection switches are turned on at the time of storing and at the time of recall. The bias circuit outputs the write voltage for turning on the third and fourth switches of the nonvolatile memory cells belonging to one row during the store while the row decoder outputs the write voltage. Each column is divided into a plurality of groups, each group is sequentially selected, and each bit line and each inverted bit line to which each nonvolatile memory cell in each column of the selected group is connected in the nonvolatile memory cell array 26. The nonvolatile memory according to claim 25, wherein control for outputting the reference bit voltage is sequentially performed. In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile storage unit and a non-volatile storage unit;
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
The third and fourth switches are provided on the bit line and the inverted bit line side, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
Means for outputting a voltage corresponding to write data to the data line and the inverted data line during normal operation, and in the nonvolatile memory cell array, when storing data from the volatile storage unit to the nonvolatile storage unit In the volatile memory portion of the nonvolatile memory cell, an intermediate voltage between two kinds of voltages used to express “1” / “0” is output to the data line and the inverted data line as a reference bit line voltage. At the time of recall for writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, it is used to express “1” / “0” in the volatile memory unit during normal operation. A write circuit that outputs the higher of the two types of voltages to the data line and the inverted data line as a reference bit line voltage;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the nonvolatile memory cell is at the store and the recall time. The first and second switches of all the nonvolatile memory cells in the memory cell array are turned OFF, and the third and fourth switches in the row unit of each nonvolatile memory cell in the nonvolatile memory cell array are stored during the storage. ON / OFF control is performed, and at the time of the recall, the ON / OFF control of the third and fourth switches and the third and fourth switches are turned ON for each nonvolatile memory cell of the nonvolatile memory cell array. By reducing the low-potential-side power supply voltage for each nonvolatile memory cell A row decoder for controlling turning on the power voltage on sexual memory cell,
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for connection to each line;
A non-volatile memory comprising: In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile storage unit, a nonvolatile storage unit, a power line for supplying a high-potential-side power supply voltage, and a high-potential-side power switch interposed between the high-potential-side power supply node in the volatile storage unit, Have
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
The third and fourth switches are provided on the bit line and the inverted bit line side, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
Means for outputting a voltage corresponding to write data to the data line and the inverted data line during normal operation, and in the nonvolatile memory cell array, when storing data from the volatile storage unit to the nonvolatile storage unit In the volatile memory portion of the nonvolatile memory cell, an intermediate voltage between two kinds of voltages used to express “1” / “0” is output to the data line and the inverted data line as a reference bit line voltage. At the time of recall for writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, it is used to express “1” / “0” in the volatile memory unit during normal operation. A write circuit that outputs the higher of the two types of voltages to the data line and the inverted data line as a reference bit line voltage;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the nonvolatile memory cell is at the store and the recall time. The first and second switches of all the nonvolatile memory cells in the memory cell array are turned OFF, and the third and fourth switches in the row unit of each nonvolatile memory cell in the nonvolatile memory cell array are stored during the storage. ON / OFF control is performed, and at the time of the recall, ON / OFF control of the third and fourth switches in units of rows of the nonvolatile memory cells of the nonvolatile memory cell array, and the third and fourth switches By turning on the high-potential-side power switch of each nonvolatile memory cell in which A row decoder for the control of turning on the power voltage for the nonvolatile memory cell,
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for connection to each line;
A non-volatile memory comprising: Each power line for supplying a high-potential-side power supply voltage and a low-potential-side power supply line to each volatile memory portion of each nonvolatile memory cell is in a direction crossing each row along each column of the nonvolatile memory cell array. The nonvolatile memory according to claim 29, wherein the nonvolatile memory is wired. In a nonvolatile memory having a nonvolatile memory cell array in which nonvolatile memory cells are arranged in a matrix,
The nonvolatile memory cell is
A volatile memory unit; a nonvolatile memory unit; a power line for supplying a low-potential-side power supply voltage; and a low-potential-side power switch interposed between the low-potential-side power node in the volatile memory unit; Have
The volatile storage unit is
A flip-flop composed of first and second inverters each having the other's output signal as an input signal;
A first switch interposed between an output node of the first inverter and a bit line;
A second switch interposed between the output node of the second inverter and the inverted bit line;
The nonvolatile storage unit is
A third switch and a first variable resistance element inserted in series between the output node of the first inverter and the bit line;
A fourth switch and a second variable resistance element inserted in series between the output node of the second inverter and the inverted bit line;
The first and second variable resistance elements are provided on the output node side of the first inverter and the output node side of the second inverter, respectively.
The third and fourth switches are provided on the bit line and the inverted bit line side, respectively.
Each of the first and second variable resistance elements has a resistance value in a first direction when current flowing from the output node of the first or second inverter to the bit line or the inverted bit line is passed. Changes and the resistance value changes in a second direction opposite to the first direction when a current from the bit line or the inverted bit line to the output node of the first or second inverter is passed. It is a variable resistance element that
The nonvolatile memory is
Data lines and inverted data lines;
Each switch interposed between the bit line and each data line of each column of the nonvolatile memory cell of the nonvolatile memory cell array, and each interposed between the inverted bit line and each inverted data line of each column. A column gate having each switch;
Means for outputting a voltage corresponding to write data to the data line and the inverted data line during normal operation, and in the nonvolatile memory cell array, when storing data from the volatile storage unit to the nonvolatile storage unit In the volatile memory portion of the nonvolatile memory cell, an intermediate voltage between two kinds of voltages used to express “1” / “0” is output to the data line and the inverted data line as a reference bit line voltage. At the time of recall for writing data from the nonvolatile memory unit to the volatile memory unit in the nonvolatile memory cell array, it is used to express “1” / “0” in the volatile memory unit during normal operation. A write circuit that outputs the higher of the two types of voltages to the data line and the inverted data line as a reference bit line voltage;
Means for turning on the first and second switches of each nonvolatile memory cell belonging to a row indicated by a row address in the nonvolatile memory cell array during normal operation, wherein the nonvolatile memory cell is at the store and the recall time. The first and second switches of all the nonvolatile memory cells in the memory cell array are turned OFF, and the third and fourth switches in the row unit of each nonvolatile memory cell in the nonvolatile memory cell array are stored during the storage. ON / OFF control is performed, and at the time of the recall, the ON / OFF control of the third and fourth switches and the third and fourth switches are turned ON for each nonvolatile memory cell of the nonvolatile memory cell array. Each non-volatile memory cell is turned on by turning on the low potential side power switch. A row decoder for controlling turning on the power voltage for the nonvolatile memory cell,
Control of the column gate for connecting a bit line and an inverted bit line to which each nonvolatile memory cell of a column indicated by a column address is connected to the data line and the inverted data line in the nonvolatile memory cell array during normal operation And at the time of storing and at the time of recall, each bit line and each inverted bit line to which each nonvolatile memory cell of all columns of the nonvolatile memory cell array is connected are connected to the data line and the inverted data. A column decoder for controlling the column gate for connection to each line;
A non-volatile memory comprising: Each power line for supplying a high-potential-side power supply voltage and a low-potential-side power supply line to each volatile memory portion of each nonvolatile memory cell is in a direction crossing each row along each column of the nonvolatile memory cell array. 32. The nonvolatile memory according to claim 31, wherein the nonvolatile memory is wired.

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