CN102097123A - Anti-single event effect static random access memory unit - Google Patents

Anti-single event effect static random access memory unit Download PDF

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CN102097123A
CN102097123A CN 201010599030 CN201010599030A CN102097123A CN 102097123 A CN102097123 A CN 102097123A CN 201010599030 CN201010599030 CN 201010599030 CN 201010599030 A CN201010599030 A CN 201010599030A CN 102097123 A CN102097123 A CN 102097123A
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unit
sram
transistors
memory
single
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CN 201010599030
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Chinese (zh)
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乔宁
李振涛
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中国科学院半导体研究所
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Abstract

The invention discloses an anti-single event effect static random access memory unit, which can effectively improve the single event upset resistance of a static random access memory (SRAM) unit and remarkably increase an upset threshold of an SRAM. The SRAM unit is a 14-transistor memory unit, and comprises two access N-channel metal oxide semiconductor (NMOS) transistors and two phase inverters, wherein each phase inverter consists of six metal oxide semiconductor (MOS) transistors. Different from the phase inverters forming the most basic six-transistor unit, the inverter structure of the anti-single event effect SRAM unit regulates a level by the two NMOS transistors as drive transistors, two P-channel metal oxide semiconductor (PMOS) transistors as load transistors and a transmission gate consisting of the PMOS transistor and the NMOS transistor so as to realize the anti-single event upset of the memory unit. The SRAM unit has a relatively simpler structure, and is easy to realize in the designing of a radiation resistant SRAM chip.

Description

一种抗单粒子效应的静态随机存储器单元 An anti-single event effects of static random access memory cells

技术领域 FIELD

[0001] 本发明涉及静态随机存储器(SRAM)技术领域,更具体地,涉及一种具有抗单粒子翻转效应的CMOS SRAM单元。 [0001] Technical Field The present invention relates to static random access memory (SRAM), and more particularly, to a CMOS SRAM cell having an anti-SEU effects.

背景技术 Background technique

[0002] 按照数据存储方式,半导体存储器分为动态随机存取存储器(DRAM),非挥发性存储器和静态随机存取存储器(SRAM)。 [0002] The data storage mode, a semiconductor memory is divided into dynamic random access memory (DRAM), non-volatile memory and static random access memory (SRAM). SRAM能够以一种简单而且低功耗的方式实现快速的操作速度,因而建立起其独特的优势。 SRAM can be a simple way to achieve low power consumption and fast operation speed, thus establishing its unique advantages. 而且,与DRAM相比,因为SRAM不需要周期性刷新存储的信息,所以设计和制造相对容易。 Moreover, compared with a DRAM, SRAM does not require periodic refresh information as stored, so the design and relatively easy to manufacture.

[0003] 通常,SRAM单元由两个驱动晶体管、两个负载器件和两个存取晶体管组成。 [0003] Generally, SRAM cell consists of two driving transistors and two load devices and two access transistors. 根据所含负载器件的类型,SRAM本身又可以分为完全CM0SSRAM,高负载电阻(High Load Resistor) SRAM 和薄膜晶体管(Thin FilmTransistor) SRAM。 Depending on the type of device included in the load, SRAM can be divided into itself completely CM0SSRAM, high load resistance (High Load Resistor) SRAM and a thin film transistor (Thin FilmTransistor) SRAM. 完全CMOS SRAM 使用PMOS 管作为负载器件,HLRSRAM使用高负载电阻作为负载器件,而TFT SRAM使用多晶硅TFT作为负载器件。 Full CMOS SRAM using PMOS transistors as load devices, HLRSRAM a high resistance load as the load device, while the SRAM TFT using a polysilicon TFT as a load device.

[0004] 一个传统的完全CMOS SRAM的电路在图1中示出。 [0004] A traditional full CMOS SRAM circuit shown in FIG. 如图1所示,第一反相器INVl 和第二反相器INV2构成锁存器,INVl和INV2分别受存取晶体管TAl和TA2有选择地驱动。 1, a first inverter and a second inverter INV2 INVL latch configuration, INVL and INV2 respectively TAl access transistors TA2 and selectively driven by.

[0005] INVl包括第一负载PMOS管TPl和第一驱动NMOS管TNl,而INV2包括第二负载PMOS管TP2和第二驱动匪OS管TN2。 [0005] INVl TPl comprises a first PMOS transistor and a first load drive NMOS transistor TNl, INV2 and the second load comprises a second PMOS transistor TP2 and the OS drive tube bandit TN2. 其中,TPl和TP2的源极与电源VDD相连,TPl的漏极和TNl的漏极相连得到Sl点,TP2的漏极和TN2的漏极相连得到S2点,TPl的栅极和TNl 的栅极相连并连接到Sl点,TP2的栅极和TN2的栅极相连并连接到Sl点。 Wherein, TPl and TP2 is connected to the power supply VDD and a source, a drain, and a drain connected TNl is obtained Sl point TPl, TP2 and the drain of the TN2 is connected to the point S2 obtained, TPl gate and the gate of TNl Sl and is connected to the connection point, and the gate of TP2 and TN2 are connected to the connection point Sl. 第一存取NMOS 管TAl的栅极与字线WL相连,它的源极与位线BL相连,而且它的漏极与Sl点相连。 The first access gate of NMOS transistor TAl word line WL is connected with its source connected to bit lines BL, and its drain connected to the point Sl. 与此类似,第二存取NMOS管TA2的栅极与字线相连,其源极与位线非(BitLineBar) DBL相连,而其漏极与S2点相连。 Similarly, the second access gate of NMOS transistor TA2 is connected to a word line, a source electrode and a non-bit line (BitLineBar) connected to the DBL, while its drain is connected to the point S2. 此处,DBL传送的信号与BL反相。 Here, DBL BL and inverted transmission signal.

[0006] 在如上所述的完全CMOS SRAM单元的操作中,如果字线札为高电平,存取NMOS管TAl和TA2导通,因此,位线BL和位线非DBL的信号分别被传送到INVl和INV2,使数据的写入或者读出得以执行。 [0006] In the operation as described above is fully CMOS SRAM cell, if the word line is high Sapporo, TAl access NMOS transistor TA2 is turned on and, therefore, the bit line BL and unselected bit line DBL signals are transmitted the INVl and INV2, the writing or reading of data is performed.

[0007] 在宇宙空间中,存在大量高能粒子,当它们入射到一个处于关闭状态的NMOS管中时,由于源漏之间的电压,会产生一个瞬态的电流,使得NMOS管相当于开态。 [0007] In space, there are a large number of high-energy particles, when they are incident on the NMOS transistor is in a closed state, since the voltage between the source and drain, a transient current is generated, so that the NMOS transistor corresponding to the ON state . 在一个SRAM 单元中,若本关闭的NMOS管处于了开态,会拉低输出端的电压,使得存储内容发生翻转。 In an SRAM cell, if present in the closed NMOS transistor ON state, it will pull down the voltage at the output, so that the stored content is flipped. 这就是单粒子翻转效应。 This is the single event upset.

[0008] 单粒子翻转效应的存在,使得在空间环境工作下的SRAM电路变得非常不可靠,所以在空间环境下使用的SRAM电路必须进行辐射加固。 The presence of a single event upset [0008], so that the space in the SRAM circuit working environment becomes extremely unreliable, the SRAM circuit used in a space environment must be radiation hardened.

[0009] 常用的加固技术包括添加反馈电路,增加负载等。 [0009] Commonly used reinforcement techniques include adding a feedback circuit increases the load and the like.

发明内容 SUMMARY

[0010](一)要解决的技术问题[0011] 有鉴于此,本发明的主要目的在于提供一种抗单粒子效应的静态随机存储器单元,以有效地抑制单粒子产生的瞬态电流及瞬态电流带来的关键节点电压变化,提高电路抗单粒子翻转的能力。 [0010] (a) Technical Problem to be Solved [0011] In view of this, the main object of the present invention to provide a static random access memory cell of an anti-single event effects, in order to effectively suppress the transient current and transient single particles generated current state voltage change of the node key to bring and improved anti-circuit SEU.

[0012] (二)技术方案 [0012] (ii) Technical Solution

[0013] 为达到上述目的,本发明提供了一种抗单粒子效应的静态随机存储器单元,包括第一反相器INV1、第二反相器INV2、第一NMOS传输门613、第二NMOS传输门614,其中:第一反相器INVl的输出端A接第一NMOS传输门613,第二反相器INV2的输出端B接第二NMOS 传输门614,第一NMOS传输门613的栅与第二NMOS传输门614的栅接WL,第一匪OS传输门613对应单元输出BL,第二NMOS传输门614对应单元输出DBL,第一反相器INVl的输出端A接第二反相器INV2的输入端,第二反相器INV2输出端B接第一反相器INVl的输入端。 [0013] To achieve the above object, the present invention provides a static random access memory cell of an anti-single event effects, comprising a first inverter inverters INV1, a second inverter INV2, a first NMOS transfer gate 613, a second NMOS pass gate 614, wherein: the output terminal a of the first inverter INVl 613 connected to the first NMOS transfer gate, a second inverter INV2 connected to the output terminal B of the second NMOS transfer gate 614, the gate of the first NMOS transfer gate 613 and the second NMOS access gate 614 transfer gate WL, OS bandit first transfer gate 613 outputs the corresponding unit BL, a second NMOS transfer gate 614 corresponds to the output unit DBL, the output terminal a of the first inverter is connected to the second inverter INVl the input of INV2, the output terminal of the second inverter INV2 connected to the input terminal B of the first inverter INVl is.

[0014] 上述方案中,所述第一反相器INVl包括第一PMOS管601、第二PMOS管602、第二匪OS管603、第一匪OS管604、第一传输门PM0S605和第二传输门NM0S606,其中:第一PMOS 管601的源极接电源VDD,漏极接第二PMOS管602的源极;第二PMOS管602的漏极接A ; 第一NMOS管604的源极接地,漏极接第二NMOS管603的源极;第二NMOS管603的漏极接A ;第二传输门NM0S606与第一传输门PM0S605的两端分别接第一PM0S601的漏极和第一NM0S604 的漏极;第一PMOS 管601、第二PMOS 管602、第二匪OS 管603、第一匪OS 管604、 第一传输门PM0S605和第二传输门NM0S606的栅都接第一反相器的输入。 [0014] In the above embodiment, the first inverter INVl comprises a first PMOS transistor 601, second PMOS transistor 602, the second tube 603 bandit OS, the first OS bandit tube 604, a first and a second transfer gate PM0S605 transfer gate NM0S606, wherein: a first source electrode of the PMOS transistor 601 connected to the power supply VDD, the drain of the second PMOS transistor connected to the source electrode 602; and a second PMOS transistor 602 is connected to the drain of a; source of the first NMOS transistor 604 is grounded , a source connected to the drain electrode of the second NMOS transistor 603; the drain of the second NMOS transistor 603 is connected to a; NM0S606 drain of the second transfer gates to both ends of the first transfer gate connected to the first PM0S601 PM0S605 respectively first and NM0S604 a drain; a first PMOS transistor 601, second PMOS transistor 602, the second tube 603 bandit OS, the first OS bandit tube 604, a first transfer gate and second transfer gate PM0S605 NM0S606 gate are connected to the first inverter input of.

[0015] 上述方案中,所述第二反相器包括第三PMOS管607、第四PMOS管608、第三NMOS管610、第四NMOS管609、第三传输门NM0S612和第四传输门PM0S611,其中:第三PMOS管607 的源极接电源VDD,漏极接第四PMOS管608的源极;第四PMOS管608的漏极接A ;第三NMOS 管610的源极接地,漏极接第四NMOS管609的源极;第四NMOS管609的漏极接A ;第三传输门NM0S612与第四传输门PM0S611的两端分别接第一PM0S607的漏极和第一NM0S610的漏极;第三PMOS管607、第四PMOS管608、第三NMOS管610、第四NMOS管609、第三传输门NM0S612和第四传输门PM0S611的栅都接第二反相器的输入。 [0015] In the above embodiment, the second inverter comprises a third PMOS transistor 607, fourth PMOS transistor 608, the third NMOS transistor 610, the fourth NMOS transistor 609, a third transfer gate and a fourth transmission gate PM0S611 NM0S612 wherein: the source electrode of the third PMOS transistor 607 connected to the VDD power supply, the drain of the fourth PMOS transistor connected to the source electrode 608; drain of the fourth PMOS transistor 608 is connected to a; source 610 of the third NMOS transistor is grounded, drain a fourth NMOS transistor 609 connected to the source electrode; a drain of the fourth NMOS transistor 609 is connected to a; ends of the third and the fourth transfer gate NM0S612 PM0S611 transfer gate and drain are respectively connected to the drain of the first first NM0S610 of PM0S607 ; third PMOS transistor 607, fourth PMOS transistor 608, the third NMOS transistor 610, the fourth NMOS transistor 609, the third transfer gate and the gate of the fourth transmission gate PM0S611 NM0S612 are connected to the input of the second inverter.

[0016] 上述方案中,所述第一PMOS管601、第二PMOS管602、第三PMOS管607和第四PMOS 管608的尺寸相同。 [0016] In the above embodiment, the first PMOS transistor 601, second PMOS transistor 602, third PMOS transistor 607 and the fourth PMOS transistor 608 of the same size.

[0017] 上述方案中,所述第二NMOS管603、第一NMOS管604、第三NMOS管610和第四NMOS 管609的尺寸相同。 [0017] In the above embodiment, the second NMOS transistor 603, first NMOS transistor 604, the same as the third NMOS transistor 610 and the fourth NMOS transistor 609 size.

[0018] 上述方案中,所述第二传输门NM0S606、第三传输门NM0S612、第一传输门PM0S605 和第四传输门PM0S611均使用工艺中的最小尺寸。 [0018] In the above embodiment, the second transfer gate NM0S606, the third transfer gate NM0S612, a first transfer gate and a fourth transmission gate PM0S605 PM0S611 minimum size are used in the process.

[0019] 上述方案中,该系统使用PD SOI工艺时,进一步采用体引出处理,将体与源极连接。 [0019] In the above embodiment, when the system is using PD SOI technology, the lead body is further processed using the source electrode and the linker.

[0020](三)有益效果 [0020] (c) beneficial effect

[0021] 本发明提供的这种抗单粒子效应的静态随机存储器单元,由两个串联的PMOS管替代负载PMOS管,两个串联的NMOS管替代驱动NMOS管,使用传输门连接两组串联MOS管的中间节点以调节电平,这种结构可以有效地抑制单粒子产生的瞬态电流及瞬态电流带来的关键节点电压变化,从而有效提高了电路抗单粒子翻转的能力。 [0021] This single event effects of anti-static random access memory cell according to the present invention is provided by the two series-connected PMOS transistors alternative load PMOS transistor, NMOS transistor in series two alternative drive NMOS transistor, using two transmission gates connected in series MOS the intermediate nodes adjust the tube to a level, such a structure can effectively suppress the voltage change of the node key and a transient current of the transient current generated caused by a single particle, thereby effectively improving the ability of the anti-circuit SEU.

附图说明 BRIEF DESCRIPTION

[0022] 图1是传统的完全CMOS SRAM的电路连接图。 [0022] FIG. 1 is a circuit connection diagram of a conventional full CMOS SRAM's.

4[0023] 图2是本发明提供的抗单粒子翻转的SRAM单元电路图。 4 [0023] FIG. 2 is a circuit diagram of the SRAM cell of the present invention provides an anti-SEU. 具体实施方式 detailed description

[0024] 为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明进一步详细说明。 [0024] To make the objectives, technical solutions, and advantages of the present invention will become more apparent hereinafter in conjunction with specific embodiments, and with reference to the accompanying drawings, the present invention is described in further detail.

[0025] 如图2所示,图2是本发明提供的抗单粒子翻转的SRAM单元电路图,包括第一反相器INV1、第二反相器INV2、第一NMOS传输门613、第二NMOS传输门614,其中:第一反相器INVl的输出端A接第一NMOS传输门613,第二反相器INV2的输出端B接第二NMOS传输门614,第一NMOS传输门613的栅与第二NMOS传输门614的栅接WL,第一NMOS传输门613对应单元输出BL,第二NMOS传输门614对应单元输出DBL,第一反相器INVl的输出端A接第二反相器INV2的输入端,第二反相器INV2输出端B接第一反相器INVl的输入端。 [0025] As shown in FIG. 2, FIG. 2 is a circuit diagram of the SRAM cell of the present invention provides an anti-SEU, a first inverter including inverters INV1, a second inverter INV2, a first NMOS transfer gate 613, a second NMOS transfer gate 614, wherein: the output terminal a of the first inverter INVl 613 connected to the first NMOS transfer gate, a second inverter INV2 connected to the output terminal B of the second NMOS transfer gate 614, the gate of the first NMOS transfer gate 613 and a second NMOS transfer gate 614 connected to gate WL, an NMOS pass gate 613 corresponding to the first cell output BL, a second NMOS pass gate 614 corresponding to the cell output DBL, the output terminal a of the first inverter is connected to the second inverter INVl the input of INV2, the output terminal of the second inverter INV2 connected to the input terminal B of the first inverter INVl is.

[0026] 第一反相器INVl包括第一PMOS管601、第二PMOS管602、第二NMOS管603、第一NMOS管604、第一传输门PM0S605和第二传输门匪0S606,其中,第一PMOS管601的源极接电源VDD,漏极接第二PMOS管602的源极;第二PMOS管602的漏极接A ;第一NMOS管604的源极接地,漏极接第二NMOS管603的源极;第二NMOS管603的漏极接A ;第二传输门NM0S606与第一传输门PM0S605的两端分别接第一PM0S601的漏极和第一NM0S604的漏极;第一PMOS管601、第二PMOS管602、第二NMOS管603、第一NMOS管604、第一传输门PM0S605和第二传输门NM0S606的栅都接第一反相器的输入。 [0026] The first inverter INVl comprises a first PMOS transistor 601, second PMOS transistor 602, second NMOS transistor 603, first NMOS transistor 604, a first transfer gate and second transfer gate PM0S605 bandit 0S606, wherein the first a source electrode connected PMOS transistor 601 of the VDD power supply, a second PMOS transistor having a drain connected to the source electrode 602; and a second PMOS transistor 602 is connected to the drain of a; source of the first NMOS transistor 604 is grounded, and a drain connected to the second NMOS a source electrode tube 603; a second NMOS transistor having a drain connected a 603; a second transfer gate NM0S606 PM0S605 both ends of the first transmission gate to the drain of the first drain of the first PM0S601 NM0S604 respectively; a first PMOS tube 601, second PMOS transistor 602, second NMOS transistor 603, first NMOS transistor 604, a first transfer gate and second transfer gate PM0S605 NM0S606 gate are connected to the input of the first inverter.

[0027] 第二反相器包括第三PMOS管607、第四PMOS管608、第三NMOS管610、第四NMOS 管609、第三传输门NM0S612和第四传输门PM0S611,其中,第三PMOS管607的源极接电源VDD,漏极接第四PMOS管608的源极;第四PMOS管608的漏极接A ;第三NMOS管610的源极接地,漏极接第四NMOS管609的源极;第四NMOS管609的漏极接A ;第三传输门NM0S612与第四传输门PM0S611的两端分别接第一PM0S607的漏极和第一NM0S610的漏极;第三PMOS 管607、第四PMOS管608、第三NMOS管610、第四NMOS管609、第三传输门NM0S612和第四传输门PM0S611的栅都接第二反相器的输入。 [0027] The second inverter includes a PMOS third PMOS transistor 607, fourth PMOS transistor 608, the third NMOS transistor 610, the fourth NMOS transistor 609, and a third transfer gate NM0S612 fourth transmission gate PM0S611, wherein the third a source electrode connected to the tube 607 the VDD power supply, the drain of the fourth PMOS transistor connected to the source electrode 608; drain of the fourth PMOS transistor 608 is connected to a; a third NMOS transistor 610. the source electrode is grounded, a drain connected to the fourth NMOS transistor 609 a source electrode; a drain of the fourth NMOS transistor 609 is connected to a; ends of the third and the fourth transfer gate NM0S612 PM0S611 transfer gate and drain are respectively connected to the drain of the first first NM0S610 PM0S607; a third PMOS transistor 607 fourth PMOS transistor 608, the third NMOS transistor 610, the fourth NMOS transistor 609, the third transfer gate and the gate of the fourth transmission gate PM0S611 NM0S612 are connected to the input of the second inverter.

[0028] 第一PMOS管601、第二PMOS管602、第三PMOS管607和第四PMOS管608的尺寸相同。 [0028] The first PMOS transistor 601, second PMOS transistor 602, third PMOS transistor 607 and the fourth PMOS transistor 608 of the same size. 第二NMOS管603、第一NMOS管604、第三NMOS管610和第四NMOS管609的尺寸相同。 The second NMOS transistor 603, first NMOS transistor 604, the same as the third NMOS transistor 610 and the fourth NMOS transistor 609 size. 第二传输门NM0S606、第三传输门NM0S612、第一传输门PM0S605和第四传输门PM0S611 均使用工艺中的最小尺寸。 A second transfer gate NM0S606, the third transfer gate NM0S612, a first transfer gate and a fourth transmission gate PM0S605 PM0S611 minimum size are used in the process.

[0029] 该系统若使用PD SOI工艺,应做体引出处理,将体与源极连接。 [0029] The PD SOI technology system if used, shall be drawn body treatment, the source electrode and the linker.

[0030] 由于PMOS管相比NMOS管对单粒子效应不敏感,所以本发明使用NMOS管说明本发明原理。 [0030] Since the NMOS transistor PMOS transistor is not sensitive to single event effects compared, the present invention uses NMOS transistor illustrating the principles of the present invention.

[0031 ] 假设单元存储内容为“ 1”,即节点A为“ 1”,节点B为“0 ” ;或者说,节点A为高电平,节点B为低电平。 [0031] Suppose storage content is "1", i.e., the node A is "1", the node B is "0"; or, the node A is high, the node B is low. 此时第二NMOS管603和第一NMOS管604的栅电压为低电平,MOS管处于关闭状态,第一PMOS管601和第二PMOS管602的栅电压为低电平,处于开态,则节点A为高电平。 At this time, the second NMOS transistor 603 and the gate voltage of the first NMOS transistor 604 is low, the MOS tube is in the closed state, the first PMOS transistor 601 and the gate voltage of the second PMOS transistor 602 is low, in the ON state, node A is high. 而因为第一传输门PM0S605的栅极也为低电平,其也处于开态,所以第二NMOS 管603的源极也为高电平。 And because the gate of the first transfer gate PM0S605 also low, which is also in the ON state, the second electrode of the NMOS transistor source 603 is also high.

[0032] 当高能粒子轰击在第二NMOS管603时,由于第二NMOS管603源漏两端同为高电平,所以并不会影响节点A的电平,所以关键节点A的电压不会发生变化。 [0032] When the energetic particle bombardment in the second NMOS transistor 603, since the second NMOS transistor 603 with the source and drain ends is high, and so does not affect the level of the node A, the voltage of the node A is not critical change. [0033] 当高能粒子轰击在第一NMOS管604时,第一NMOS管604源漏之间存在电压,所以会产生瞬态的电流,管子相当于开启状态。 [0033] When the energetic particle bombardment in a first NMOS transistor 604, there is a voltage between the source and drain of the first NMOS transistor 604, it will generate a transient current, the ON state corresponds to the tube. 其漏端电压会迅速下降。 The drain terminal voltage decreased rapidly. 但因为第二NMOS管603处于关闭状态,所以并不会影响到节点A的电平。 However, since the second NMOS transistor 603 is turned off, and thus would not affect the level of the node A. 又因为第一NMOS管604漏端通过第一传输门PM0S605和第一PMOS管601直接连接VDD,电源会迅速给受影响的节点充电,电路会恢复正常。 Since the first NMOS transistor 604 has a drain terminal directly connected to the VDD, the power to rapidly charge the affected nodes, the circuit will be restored by the first transfer gate of the first PMOS transistor 601 and PM0S605.

[0034] 通过软件模拟本发明与未加固的SRAM 6管单元在单粒子事件下的节点电压变化,本发明相对于未加固的SRAM 6管单元有明显的抗单粒子翻转的能力。 [0034] The present invention relates to voltage change of the node SRAM 6 unreinforced pipe unit at a single particle events by software simulation, with respect to the present invention, SRAM 6 unreinforced tube unit capable of significant anti SEU. 同样工艺条件下,模拟不同能量粒子的轰击,未加固的SRAM6管单元在粒子LET值为60MeV · mg—1 · cm2时发生翻转,而本发明在粒子LET值为150MeV · mg—1 · cm2时都未发生翻转。 Under the same conditions, different energy of the particles bombarding the analog flip SRAM6 tube unit unconsolidated LET particles occurs when the value of 60MeV · mg-1 · cm2, and the present invention · mg-1 · cm2 when the particle is 150MeV LET flip had happened.

[0035] 总之,本发明的电路相比传统6管单元的SRAM单元电路具有更好的抗单粒子翻转能力,提升了SRAM的可靠性。 [0035] In summary, the circuit of the present invention as compared to a conventional SRAM cell circuit unit 6 has a better resistance to SEU capacity, improve the reliability of the SRAM.

[0036] 以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。 Specific Example [0036] above, the objectives, technical solutions, and beneficial effects of the present invention will be further described in detail, it should be understood that the above descriptions are merely embodiments of the present invention, but not intended to limit the present invention, within the spirit and principle of the present invention, any modifications, equivalent replacements, improvements, etc., should be included within the scope of the present invention.

Claims (7)

  1. 1. 一种抗单粒子效应的静态随机存储器单元,其特征在于,包括第一反相器(INVl)、 第二反相器(INV2)、第一NMOS传输门(613)、第二NMOS传输门(614),其中:第一反相器(INVl)的输出端(A)接第一NMOS传输门(613),第二反相器(INV2)的输出端(B)接第二NMOS传输门(614),第一NMOS传输门(613)的栅与第二NMOS传输门(614) 的栅接札,第一NMOS传输门(613)对应单元输出BL,第二NMOS传输门(614)对应单元输出DBL,第一反相器(INVl)的输出端(A)接第二反相器(INV2)的输入端,第二反相器(INV2) 输出端⑶接第一反相器(INVl)的输入端。 Static random access memory cell 1. A single event effects anti, characterized in that it comprises a first inverter (INVL), a second inverter (INV2), the first NMOS transfer gate (613), a second NMOS pass a door (614), wherein: a first inverter (INVL) the output terminal (a) connected to the first NMOS transfer gate (613), an output terminal (B) a second inverter (INV2) is connected to a second NMOS pass a door (614), a first NMOS transfer gate (613) and a gate of the second NMOS transfer gate (614) connected to the gate of Sapporo, the first NMOS transfer gate (613) corresponding to the cell output BL, a second NMOS pass gate (614) unit outputs a corresponding DBL, a first inverter (INVL) the output terminal (a) connected to a second inverter (INV2) is an input terminal, (INV2) ⑶ output of the second inverter connected to the first inverter ( INVL) input.
  2. 2.根据权利要求1所述的抗单粒子效应的静态随机存储器单元,其特征在于,所述第一反相器(INVl)包括第一PMOS 管(601)、第二PMOS 管(602)、第二NMOS 管(603)、第一NMOS管(604)、第一传输门PMOS (60¾和第二传输门NMOS (606),其中:第一PMOS管(601)的源极接电源VDD,漏极接第二PMOS管(602)的源极;第二PMOS管(602)的漏极接A ;第一NMOS管(604)的源极接地,漏极接第二NMOS管(603)的源极;第二NMOS管(603)的漏极接A ;第二传输门NMOS (606)与第一传输门PMOS (60¾的两端分别接第一PMOS (601)的漏极和第一NMOS (604)的漏极;第一PMOS 管(601)、第二PMOS 管(602)、 第二NMOS 管(603)、第一NMOS 管(604)、第一传输门PMOS (605)和第二传输门NMOS (606) 的栅都接第一反相器的输入。 The static random access memory cell of claim 1 single event effects claim, wherein said first inverter (INVL) comprises a first PMOS transistor (601), a second PMOS transistor (602), a second NMOS transistor (603), a first NMOS transistor (604), a first transfer gate PMOS (60¾ and second NMOS transfer gate (606), wherein: the source of the first PMOS transistor (601) connected to the power supply of the VDD electrode, the drain a second electrode connected PMOS transistor (602) of the source electrode; a drain of the second PMOS transistor (602) is connected to a; source of the first NMOS transistor (604) is grounded, and a drain connected to a second NMOS transistor (603) of the source electrode; drain of the second NMOS transistor (603) is connected to a; ends of the second NMOS transfer gate (606) and a first transfer gate PMOS (60¾ are respectively connected to the drain of the first PMOS (601) and a first NMOS ( 604) drain; a first PMOS transistor (601), a second PMOS transistor (602), a second NMOS transistor (603), a first NMOS transistor (604), a first PMOS transfer gate (605) and a second transmission gate NMOS (606) are connected to a gate input of the first inverter.
  3. 3.根据权利要求1所述的抗单粒子效应的静态随机存储器单元,其特征在于,所述第二反相器包括第三PMOS管(607)、第四PMOS管(608)、第三NMOS管(610)、第四NMOS管(609)、第三传输门NMOS(612)和第四传输门PMOS(611),其中:第三PMOS管(607)的源极接电源VDD,漏极接第四PMOS管(608)的源极;第四PMOS管(608)的漏极接A ;第三NMOS管(610)的源极接地,漏极接第四NMOS管(60¾的源极;第四NMOS管(609)的漏极接A ;第三传输门NMOS (612)与第四传输门PMOS (611)的两端分别接第一PM0S(607)的漏极和第一NMOS(610)的漏极;第三PMOS管(607)、第四PMOS管(608)、 第三NMOS管(610)、第四NMOS管(609)、第三传输门NMOS(612)和第四传输门PMOS(611) 的栅都接第二反相器的输入。 The static random access memory cell of claim 1 single event effects claim, wherein said second inverter comprises a third PMOS transistor (607), a fourth PMOS transistor (608), the third NMOS tube (610), a fourth NMOS transistor (609), the third NMOS transfer gate (612) and a fourth PMOS transfer gate (611), wherein: the source of the third PMOS transistor (607) connected to the electrode power supply the VDD, a drain connected source of the fourth PMOS transistor (608) of the electrode; a drain of the fourth PMOS transistor (608) is connected to a; source of the third NMOS transistor (610) is grounded, a drain connected to the fourth NMOS transistor (60¾ a source electrode; a second four drain of the NMOS transistor (609) is connected to a; ends of the third NMOS transfer gate (612) and the fourth transfer gate PMOS (611) are respectively connected to a first PM0S (607) and the drain of a first NMOS (610) a drain; a third PMOS transistor (607), a fourth PMOS transistor (608), a third NMOS transistor (610), a fourth NMOS transistor (609), the third NMOS transfer gate (612) and a fourth transmission gate PMOS (611) are connected to a gate input of the second inverter.
  4. 4.根据权利要求1所述的抗单粒子效应的静态随机存储器单元,其特征在于,所述第一 PMOS管(601)、第二PMOS管(602)、第三PMOS管(607)和第四PMOS管(608)的尺寸相同。 The static random access memory cell of claim 1 single event effects claim, characterized in that said first PMOS transistor (601), a second PMOS transistor (602), a third PMOS transistor (607) and four of the same size PMOS transistor (608) is.
  5. 5.根据权利要求1所述的抗单粒子效应的静态随机存储器单元,其特征在于,所述第二 NMOS管(603)、第一NMOS管(604)、第三NMOS管(610)和第四NMOS管(609)的尺寸相同。 The static random access memory cell of claim 1 single event effects claim, wherein said second NMOS transistor (603), a first NMOS transistor (604), a third NMOS transistor (610) and four NMOS transistors of the same size (609) of.
  6. 6.根据权利要求1所述的抗单粒子效应的静态随机存储器单元,其特征在于,所述第二传输门NMOS (606)、第三传输门NMOS (612)、第一传输门PMOS (605)和第四传输门PMOS (611)均使用工艺中的最小尺寸。 The static random access memory cell of claim 1 single event effects claim, wherein said second transfer gate NMOS (606), a third transfer gate NMOS (612), a first transfer gate PMOS (605 ) and a fourth transmission gate PMOS (611) processes the minimum dimensions are used.
  7. 7.根据权利要求1所述的抗单粒子效应的静态随机存储器单元,其特征在于,该系统使用PD SOI工艺时,进一步采用体引出处理,将体与源极连接。 The static random access memory cell of claim 1 single event effects claim, wherein, when the system is using PD SOI technology, the lead body is further processed using the source electrode and the linker.
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CN105336364A (en) * 2014-05-29 2016-02-17 展讯通信(上海)有限公司 SRAM memory cell, storage array and memory
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CN104392745A (en) * 2014-11-27 2015-03-04 西安交通大学 SRAM unit with high writing speed, low static power consumption and single-particle overturning resistance
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CN104464795B (en) * 2014-11-27 2017-06-06 西安交通大学 An anti-static random SEU storage unit
CN104601164A (en) * 2015-02-04 2015-05-06 苏州大学 Phase inverter designed on basis of three MOS (metal oxide semiconductor) tubes and filter circuit
CN105653771A (en) * 2015-12-25 2016-06-08 北京时代民芯科技有限公司 Method for improving single event upset resistance of chips through logic design

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