CN102097123A - Anti-single event effect static random access memory unit - Google Patents
Anti-single event effect static random access memory unit Download PDFInfo
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Abstract
The invention discloses an anti-single event effect static random access memory unit, which can effectively improve the single event upset resistance of a static random access memory (SRAM) unit and remarkably increase an upset threshold of an SRAM. The SRAM unit is a 14-transistor memory unit, and comprises two access N-channel metal oxide semiconductor (NMOS) transistors and two phase inverters, wherein each phase inverter consists of six metal oxide semiconductor (MOS) transistors. Different from the phase inverters forming the most basic six-transistor unit, the inverter structure of the anti-single event effect SRAM unit regulates a level by the two NMOS transistors as drive transistors, two P-channel metal oxide semiconductor (PMOS) transistors as load transistors and a transmission gate consisting of the PMOS transistor and the NMOS transistor so as to realize the anti-single event upset of the memory unit. The SRAM unit has a relatively simpler structure, and is easy to realize in the designing of a radiation resistant SRAM chip.
Description
Technical field
The present invention relates to static RAM (SRAM) technical field, more specifically, relate to a kind of CMOS sram cell with anti-single particle overturn effect.
Background technology
According to data storage method, semiconductor memory is divided into dynamic RAM (DRAM), non-volatility memorizer and static RAM (SRAM).SRAM can realize operating speed fast in a kind of simple and mode low-power consumption, thereby sets up its special advantages.And, compare with DRAM, because SRAM does not need the periodic refresh canned data, so design and manufacturing are relatively easy.
Usually, sram cell is made up of two driving transistorss, two load devices and two access transistors.According to the type of contained load device, SRAM itself can be divided into complete CMOSSRAM again, high capacity resistance (High Load Resistor) SRAM and thin film transistor (TFT) (Thin FilmTransistor) SRAM.CMOS SRAM uses the PMOS pipe as load device fully, and HLRSRAM uses high capacity resistance as load device, and TFT SRAM uses multi-crystal TFT as load device.
The circuit of a traditional complete CMOS SRAM is shown in Figure 1.As shown in Figure 1, the first phase inverter INV1 and the second phase inverter INV2 constitute latch, and INV1 and INV2 are driven by access transistor TA1 and TA2 respectively selectively.
INV1 comprises the first load PMOS pipe TP1 and the first driving N metal-oxide-semiconductor TN1, and INV2 comprises the second load PMOS pipe TP2 and the second driving N metal-oxide-semiconductor TN2.Wherein, the source electrode of TP1 and TP2 links to each other with power vd D, and the drain electrode of TP1 links to each other with the drain electrode of TN1 and obtains the S1 point, and the drain electrode of TP2 links to each other with the drain electrode of TN2 and obtains the S2 point, the grid of TP1 links to each other with the grid of TN1 and is connected to the S1 point, and the grid of TP2 links to each other with the grid of TN2 and is connected to the S1 point.The grid of first access NMOS pipe TA1 links to each other with word line WL, and its source electrode links to each other with bit line BL, and its drain electrode links to each other with the S1 point.Similarly, the grid of second access NMOS pipe TA2 links to each other with word line, and its source electrode non-with bit line (BitLineBar) DBL links to each other, and its drain electrode links to each other with the S2 point.Herein, the signal and the BL of DBL transmission are anti-phase.
In the operation of aforesaid complete CMOS sram cell, if word line WL is a high level, access NMOS pipe TA1 and TA2 conducting, therefore, the signal of bit line BL and the non-DBL of bit line is sent to INV1 and INV2 respectively, makes writing or reading and carried out of data.
In the cosmic space, there are a large amount of high energy particles, when they incide in the NMOS pipe that is in closed condition, because the voltage of source between leaking, can produce the electric current of a transient state, make the NMOS pipe be equivalent to ON state.In a sram cell, if the NMOS pipe of originally closing has been in ON state, can drag down the voltage of output terminal, make memory contents overturn.Single-particle inversion effect that Here it is.
The existence of single-particle inversion effect makes that the SRAM circuit under space environment work becomes very unreliable, so the SRAM circuit that uses must carry out radiation hardened under space environment.
Reinforcement technique commonly used comprises the interpolation feedback circuit, increases load etc.
Summary of the invention
(1) technical matters that will solve
In view of this, fundamental purpose of the present invention is to provide a kind of static random access memory cell of anti-single particle effect, to suppress the key node change in voltage that transient current that single-particle produces and transient current bring effectively, improve the primary particle inversion resistant ability of circuit.
(2) technical scheme
For achieving the above object, the invention provides a kind of static random access memory cell of anti-single particle effect, comprise the first phase inverter INV1, the second phase inverter INV2, the one NMOS transmission gate 613, the 2nd NMOS transmission gate 614, wherein: the output terminals A of the first phase inverter INV1 connects a NMOS transmission gate 613, the output terminal B of the second phase inverter INV2 connects the 2nd NMOS transmission gate 614, the grid of the grid of the one NMOS transmission gate 613 and the 2nd NMOS transmission gate 614 meet WL, the one NMOS transmission gate 613 corresponding units output BL, the 2nd NMOS transmission gate 614 corresponding units output DBL, the output terminals A of the first phase inverter INV1 connects the input end of the second phase inverter INV2, and the second phase inverter INV2 output terminal B connects the input end of the first phase inverter INV1.
In the such scheme, the described first phase inverter INV1 comprises PMOS pipe the 601, the 2nd PMOS pipe the 602, the 2nd NMOS pipe the 603, the one NMOS pipe 604, the first transmission gate PMOS605 and the second transmission gate NMOS606, wherein: the source electrode of PMOS pipe 601 meets power vd D, and drain electrode connects the source electrode of the 2nd PMOS pipe 602; The drain electrode of the 2nd PMOS pipe 602 meets A; The source ground of the one NMOS pipe 604, drain electrode connect the source electrode of the 2nd NMOS pipe 603; The drain electrode of the 2nd NMOS pipe 603 meets A; The two ends of the second transmission gate NMOS606 and the first transmission gate PMOS605 connect the drain electrode of a PMOS601 and the drain electrode of a NMOS604 respectively; The grid of the one PMOS pipe the 601, the 2nd PMOS pipe the 602, the 2nd NMOS pipe the 603, the one NMOS pipe 604, the first transmission gate PMOS605 and the second transmission gate NMOS606 all connect the input of first phase inverter.
In the such scheme, described second phase inverter comprises the 3rd PMOS pipe the 607, the 4th PMOS pipe the 608, the 3rd NMOS pipe the 610, the 4th NMOS pipe the 609, the 3rd transmission gate NMOS612 and the 4th transmission gate PMOS611, wherein: the source electrode of the 3rd PMOS pipe 607 meets power vd D, and drain electrode connects the source electrode of the 4th PMOS pipe 608; The drain electrode of the 4th PMOS pipe 608 meets A; The source ground of the 3rd NMOS pipe 610, drain electrode connect the source electrode of the 4th NMOS pipe 609; The drain electrode of the 4th NMOS pipe 609 meets A; The two ends of the 3rd transmission gate NMOS612 and the 4th transmission gate PMOS611 connect the drain electrode of a PMOS607 and the drain electrode of a NMOS610 respectively; The grid of the 3rd PMOS pipe the 607, the 4th PMOS pipe the 608, the 3rd NMOS pipe the 610, the 4th NMOS pipe the 609, the 3rd transmission gate NMOS612 and the 4th transmission gate PMOS611 all connect the input of second phase inverter.
In the such scheme, described PMOS pipe the 601, the 2nd PMOS pipe the 602, the 3rd PMOS manages the measure-alike of the 607 and the 4th PMOS pipe 608.
In the such scheme, described the 2nd NMOS pipe the 603, the one NMOS pipe the 604, the 3rd NMOS manages the measure-alike of the 610 and the 4th NMOS pipe 609.
In the such scheme, the described second transmission gate NMOS606, the 3rd transmission gate NMOS612, the first transmission gate PMOS605 and the 4th transmission gate PMOS611 all use the minimum dimension in the technology.
In the such scheme, when this system uses PD SOI technology, further adopt body to draw processing, body is connected with source electrode.
(3) beneficial effect
The static random access memory cell of this anti-single particle effect provided by the invention, PMOS pipe by two series connection substitutes the load PMOS pipe, the NMOS pipe of two series connection substitutes the driving N metal-oxide-semiconductor, use transmission gate to connect the intermediate node of two groups of series connection metal-oxide-semiconductors to regulate level, this structure can suppress the transient current of single-particle generation and the key node change in voltage that transient current brings effectively, thereby has effectively improved the primary particle inversion resistant ability of circuit.
Description of drawings
Fig. 1 is the circuit connection diagram of traditional complete CMOS SRAM.
Fig. 2 is a primary particle inversion resistant sram cell circuit diagram provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 2, Fig. 2 is a primary particle inversion resistant sram cell circuit diagram provided by the invention, comprise the first phase inverter INV1, the second phase inverter INV2, the one NMOS transmission gate 613, the 2nd NMOS transmission gate 614, wherein: the output terminals A of the first phase inverter INV1 connects a NMOS transmission gate 613, the output terminal B of the second phase inverter INV2 connects the 2nd NMOS transmission gate 614, the grid of the grid of the one NMOS transmission gate 613 and the 2nd NMOS transmission gate 614 meet WL, the one NMOS transmission gate 613 corresponding units output BL, the 2nd NMOS transmission gate 614 corresponding units output DBL, the output terminals A of the first phase inverter INV1 connects the input end of the second phase inverter INV2, and the second phase inverter INV2 output terminal B connects the input end of the first phase inverter INV1.
The first phase inverter INV1 comprises PMOS pipe the 601, the 2nd PMOS pipe the 602, the 2nd NMOS pipe the 603, the one NMOS pipe 604, the first transmission gate PMOS605 and the second transmission gate NMOS606, wherein, the source electrode of the one PMOS pipe 601 meets power vd D, and drain electrode connects the source electrode of the 2nd PMOS pipe 602; The drain electrode of the 2nd PMOS pipe 602 meets A; The source ground of the one NMOS pipe 604, drain electrode connect the source electrode of the 2nd NMOS pipe 603; The drain electrode of the 2nd NMOS pipe 603 meets A; The two ends of the second transmission gate NMOS606 and the first transmission gate PMOS605 connect the drain electrode of a PMOS601 and the drain electrode of a NMOS604 respectively; The grid of the one PMOS pipe the 601, the 2nd PMOS pipe the 602, the 2nd NMOS pipe the 603, the one NMOS pipe 604, the first transmission gate PMOS605 and the second transmission gate NMOS606 all connect the input of first phase inverter.
Second phase inverter comprises the 3rd PMOS pipe the 607, the 4th PMOS pipe the 608, the 3rd NMOS pipe the 610, the 4th NMOS pipe the 609, the 3rd transmission gate NMOS612 and the 4th transmission gate PMOS611, wherein, the source electrode of the 3rd PMOS pipe 607 meets power vd D, and drain electrode connects the source electrode of the 4th PMOS pipe 608; The drain electrode of the 4th PMOS pipe 608 meets A; The source ground of the 3rd NMOS pipe 610, drain electrode connect the source electrode of the 4th NMOS pipe 609; The drain electrode of the 4th NMOS pipe 609 meets A; The two ends of the 3rd transmission gate NMOS612 and the 4th transmission gate PMOS611 connect the drain electrode of a PMOS607 and the drain electrode of a NMOS610 respectively; The grid of the 3rd PMOS pipe the 607, the 4th PMOS pipe the 608, the 3rd NMOS pipe the 610, the 4th NMOS pipe the 609, the 3rd transmission gate NMOS612 and the 4th transmission gate PMOS611 all connect the input of second phase inverter.
The one PMOS pipe the 601, the 2nd PMOS pipe the 602, the 3rd PMOS manages the measure-alike of the 607 and the 4th PMOS pipe 608.The 2nd NMOS pipe the 603, the one NMOS pipe the 604, the 3rd NMOS manages the measure-alike of the 610 and the 4th NMOS pipe 609.The second transmission gate NMOS606, the 3rd transmission gate NMOS612, the first transmission gate PMOS605 and the 4th transmission gate PMOS611 all use the minimum dimension in the technology.
This system should do body and draw processing if use PD SOI technology, and body is connected with source electrode.
Because it is insensitive to single particle effect that the PMOS pipe is compared the NMOS pipe, so the present invention uses the NMOS pipe explanation principle of the invention.
Suppose that the unit memory contents is " 1 ", promptly node A is " 1 ", and Node B is " 0 "; In other words, node A is a high level, and Node B is a low level.The gate voltage of the 2nd NMOS pipe the 603 and the one NMOS pipe 604 is a low level at this moment, and metal-oxide-semiconductor is in closed condition, and the gate voltage of PMOS pipe the 601 and the 2nd PMOS pipe 602 is a low level, is in ON state, and then node A is a high level.And because the grid of the first transmission gate PMOS605 also is a low level, it also is in ON state, so the source electrode of the 2nd NMOS pipe 603 also is a high level.
When high-energy particle bombardment when the 2nd NMOS manages 603 be all high level because two ends are leaked in the 2nd NMOS 603 sources of managing, thus can't influence the level of node A, so the voltage of key node A can not change.
When high-energy particle bombardment when a NMOS manages 604, have voltage between a NMOS leaks in 604 sources of managing, so can produce the electric current of transient state, pipe is equivalent to opening.Its drain terminal voltage can descend rapidly.But because the 2nd NMOS pipe 603 is in closed condition, so can't have influence on the level of node A.Directly be connected VDD by the first transmission gate PMOS605 with PMOS pipe 601 because a NMOS manages 604 drain terminals again, power supply can be given affected node charging rapidly, and it is normal that circuit can recover.
By software simulation the present invention and the unguyed node voltage variation of SRAM 6 pipe units under single event, the present invention has tangible primary particle inversion resistant ability with respect to unguyed SRAM 6 pipe units.Under the same process conditions, the bombardment of simulation different-energy particle, unguyed SRAM6 pipe unit is 60MeVmg in particle LET value
-1Cm
2The Shi Fasheng upset, and the present invention is 150MeVmg in particle LET value
-1Cm
2Shi Douwei overturns.
In a word, the sram cell circuit that circuit of the present invention is compared traditional 6 pipe units has better anti-single particle overturn ability, has promoted the reliability of SRAM.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. the static random access memory cell of an anti-single particle effect is characterized in that, comprises first phase inverter (INV1), second phase inverter (INV2), a NMOS transmission gate (613), the 2nd NMOS transmission gate (614), wherein:
The output terminal (A) of first phase inverter (INV1) connects a NMOS transmission gate (613), the output terminal (B) of second phase inverter (INV2) connects the 2nd NMOS transmission gate (614), the grid of the grid of the one NMOS transmission gate (613) and the 2nd NMOS transmission gate (614) meet WL, the one NMOS transmission gate (613) corresponding unit output BL, the 2nd NMOS transmission gate (614) corresponding unit output DBL, the output terminal (A) of first phase inverter (INV1) connects the input end of second phase inverter (INV2), and second phase inverter (INV2) output terminal (B) connects the input end of first phase inverter (INV1).
2. the static random access memory cell of anti-single particle effect according to claim 1, it is characterized in that, described first phase inverter (INV1) comprises that PMOS pipe (601), the 2nd PMOS pipe (602), the 2nd NMOS pipe (603), a NMOS manage (604), the first transmission gate PMOS (605) and the second transmission gate NMOS (606), wherein:
The source electrode of the one PMOS pipe (601) meets power vd D, and drain electrode connects the source electrode of the 2nd PMOS pipe (602); The drain electrode of the 2nd PMOS pipe (602) meets A; The source ground of the one NMOS pipe (604), drain electrode connects the source electrode of the 2nd NMOS pipe (603); The drain electrode of the 2nd NMOS pipe (603) meets A; The second transmission gate NMOS (606) connects the drain electrode of a PMOS (601) and the drain electrode of a NMOS (604) respectively with the two ends of the first transmission gate PMOS (605); The grid of the one PMOS pipe (601), the 2nd PMOS pipe (602), the 2nd NMOS pipe (603), NMOS pipe (604), the first transmission gate PMOS (605) and the second transmission gate NMOS (606) all connect the input of first phase inverter.
3. the static random access memory cell of anti-single particle effect according to claim 1, it is characterized in that, described second phase inverter comprises that the 3rd PMOS pipe (607), the 4th PMOS pipe (608), the 3rd NMOS pipe (610), the 4th NMOS manage (609), the 3rd transmission gate NMOS (612) and the 4th transmission gate PMOS (611), wherein:
The source electrode of the 3rd PMOS pipe (607) meets power vd D, and drain electrode connects the source electrode of the 4th PMOS pipe (608); The drain electrode of the 4th PMOS pipe (608) meets A; The source ground of the 3rd NMOS pipe (610), drain electrode connects the source electrode of the 4th NMOS pipe (609); The drain electrode of the 4th NMOS pipe (609) meets A; The 3rd transmission gate NMOS (612) connects the drain electrode of a PMOS (607) and the drain electrode of a NMOS (610) respectively with the two ends of the 4th transmission gate PMOS (611); The grid of the 3rd PMOS pipe (607), the 4th PMOS pipe (608), the 3rd NMOS pipe (610), the 4th NMOS pipe (609), the 3rd transmission gate NMOS (612) and the 4th transmission gate PMOS (611) all connect the input of second phase inverter.
4. the static random access memory cell of anti-single particle effect according to claim 1 is characterized in that, described PMOS pipe (601), the 2nd PMOS pipe (602), the 3rd PMOS pipe (607) and the 4th PMOS manage the measure-alike of (608).
5. the static random access memory cell of anti-single particle effect according to claim 1 is characterized in that, described the 2nd NMOS pipe (603), NMOS pipe (604), the 3rd NMOS pipe (610) and the 4th NMOS manage the measure-alike of (609).
6. the static random access memory cell of anti-single particle effect according to claim 1, it is characterized in that the described second transmission gate NMOS (606), the 3rd transmission gate NMOS (612), the first transmission gate PMOS (605) and the 4th transmission gate PMOS (611) all use the minimum dimension in the technology.
7. the static random access memory cell of anti-single particle effect according to claim 1 is characterized in that, when this system uses PD SOI technology, further adopts body to draw processing, and body is connected with source electrode.
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| CN102723109A (en) * | 2012-06-29 | 2012-10-10 | 西安交通大学 | Novel static random access memory (SRAM) storage unit preventing single particle from turning |
| CN102945682A (en) * | 2012-11-05 | 2013-02-27 | 上海集成电路研发中心有限公司 | Static random access memory unit capable of resisting single-event upset |
| CN103019878A (en) * | 2012-12-31 | 2013-04-03 | 清华大学 | Storage unit with redundant structure |
| CN103077739A (en) * | 2012-12-31 | 2013-05-01 | 清华大学 | Redundant-structure dynamic random access memory unit |
| CN103337252A (en) * | 2013-06-26 | 2013-10-02 | 清华大学 | Static random access memory (SRAM) with redundant structure |
| CN103546145A (en) * | 2013-09-24 | 2014-01-29 | 中国科学院微电子研究所 | Single-event transient pulse resistant CMOS circuit |
| CN103700396A (en) * | 2013-12-03 | 2014-04-02 | 中国航天科技集团公司第九研究院第七七一研究所 | SRAM (static random access memory)-oriented anti-SEU (single-event upset) error accumulation controller and method |
| CN104157304A (en) * | 2014-08-01 | 2014-11-19 | 中国科学院微电子研究所 | Tamper resistant memory element |
| CN104392745A (en) * | 2014-11-27 | 2015-03-04 | 西安交通大学 | SRAM unit with high writing speed, low static power consumption and single-particle overturning resistance |
| CN104464795A (en) * | 2014-11-27 | 2015-03-25 | 西安交通大学 | Static random access memory unit with single-particle-upset resistance |
| CN104601164A (en) * | 2015-02-04 | 2015-05-06 | 苏州大学 | Phase inverter designed on basis of three MOS (metal oxide semiconductor) tubes and filter circuit |
| CN105336364A (en) * | 2014-05-29 | 2016-02-17 | 展讯通信（上海）有限公司 | SRAM memory cell, storage array and memory |
| CN105653771A (en) * | 2015-12-25 | 2016-06-08 | 北京时代民芯科技有限公司 | Method for improving single event upset resistance of chips through logic design |
| CN105741868A (en) * | 2016-02-02 | 2016-07-06 | 北京时代民芯科技有限公司 | Multi-threshold asymmetric configuration memory used for single-particle reinforcement FPGA (Field Programmable Gate Array) |
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| CN106328193A (en) * | 2015-07-07 | 2017-01-11 | 复旦大学 | Method for fabricating anti-radiation SRAM unit based on well isolation and redundant transistors connected in series |
| CN106847333A (en) * | 2017-01-13 | 2017-06-13 | 青岛朗思信息科技有限公司 | A kind of new anti-single particle SRAM bit cell |
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| CN102723109A (en) * | 2012-06-29 | 2012-10-10 | 西安交通大学 | Novel static random access memory (SRAM) storage unit preventing single particle from turning |
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| CN102945682A (en) * | 2012-11-05 | 2013-02-27 | 上海集成电路研发中心有限公司 | Static random access memory unit capable of resisting single-event upset |
| CN102945682B (en) * | 2012-11-05 | 2017-09-29 | 上海集成电路研发中心有限公司 | A kind of primary particle inversion resistant static ram cell |
| CN103019878B (en) * | 2012-12-31 | 2015-01-14 | 清华大学 | Storage unit with redundant structure |
| CN103077739A (en) * | 2012-12-31 | 2013-05-01 | 清华大学 | Redundant-structure dynamic random access memory unit |
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| CN103337252B (en) * | 2013-06-26 | 2016-01-20 | 清华大学 | A kind of Redundant-structure static random storage unit |
| CN103546145A (en) * | 2013-09-24 | 2014-01-29 | 中国科学院微电子研究所 | Single-event transient pulse resistant CMOS circuit |
| CN103546145B (en) * | 2013-09-24 | 2016-01-27 | 中国科学院微电子研究所 | Single-event transient pulse resistant CMOS circuit |
| CN103700396B (en) * | 2013-12-03 | 2016-06-01 | 中国航天科技集团公司第九研究院第七七一研究所 | The controller of a kind of anti-SEU error accumulation towards SRAM and method |
| CN103700396A (en) * | 2013-12-03 | 2014-04-02 | 中国航天科技集团公司第九研究院第七七一研究所 | SRAM (static random access memory)-oriented anti-SEU (single-event upset) error accumulation controller and method |
| CN105336364B (en) * | 2014-05-29 | 2017-11-21 | 展讯通信（上海）有限公司 | SRAM memory cell, storage array and memory |
| CN105336364A (en) * | 2014-05-29 | 2016-02-17 | 展讯通信（上海）有限公司 | SRAM memory cell, storage array and memory |
| CN104157304A (en) * | 2014-08-01 | 2014-11-19 | 中国科学院微电子研究所 | Tamper resistant memory element |
| CN104392745A (en) * | 2014-11-27 | 2015-03-04 | 西安交通大学 | SRAM unit with high writing speed, low static power consumption and single-particle overturning resistance |
| CN104392745B (en) * | 2014-11-27 | 2017-04-26 | 西安交通大学 | SRAM unit with high writing speed, low static power consumption and single-particle overturning resistance |
| CN104464795B (en) * | 2014-11-27 | 2017-06-06 | 西安交通大学 | A kind of primary particle inversion resistant static ram cell |
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| CN104601164A (en) * | 2015-02-04 | 2015-05-06 | 苏州大学 | Phase inverter designed on basis of three MOS (metal oxide semiconductor) tubes and filter circuit |
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