CN103971730A - Static random access memory unit circuit - Google Patents

Static random access memory unit circuit Download PDF

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Publication number
CN103971730A
CN103971730A CN201310039841.9A CN201310039841A CN103971730A CN 103971730 A CN103971730 A CN 103971730A CN 201310039841 A CN201310039841 A CN 201310039841A CN 103971730 A CN103971730 A CN 103971730A
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CN
China
Prior art keywords
phase inverter
nmos pipe
output terminal
connects
pipe
Prior art date
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CN201310039841.9A
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Chinese (zh)
Inventor
朱红卫
赵郁炜
刘国军
唐敏
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上海华虹宏力半导体制造有限公司
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Priority to CN201310039841.9A priority Critical patent/CN103971730A/en
Publication of CN103971730A publication Critical patent/CN103971730A/en

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Abstract

The present invention discloses a static random access memory unit circuit, wherein an inverter is respectively added between the two signal output terminal of a bistable structure and the corresponding transmission pipe, and the further shaping on the output signal can be achieved with the added inverters so as to substantially reduce influence of nose on the output signal, increase nose resistance of the memory unit circuit, and make the signal output have high stability, such that the static random access memory unit circuit can be applied under the low power supply voltage working condition, and meets the CMOS feature size and the requirement of the continuously-decreased working voltage.

Description

SRAM cell circuit

Technical field

The present invention relates to a kind of SIC (semiconductor integrated circuit), particularly relate to a kind of SRAM cell circuit.

Background technology

Static RAM (SRAM) is a kind of internal memory with static access facility, does not need refresh circuit just can preserve the data of its storage inside, and speed is fast, and use low in energy consumption is extensive.In electronic system, be widely used, simultaneously also more and more higher to the requirement of performance, present static RAM is towards faster speed, more high integration, low-power consumption future development more.

As shown in Figure 1, be the circuit diagram of existing SRAM cell circuit; Existing SRAM cell circuit is one or six transistor memory units, and by four NMOS pipe N101, N102, N103 and N104, two PMOS manage P101 and P102 composition; PMOS pipe P101 and NMOS pipe N101 connect to form the first phase inverter, PMOS pipe P101 is connected with the grid of NMOS pipe N101 and as the input end of the first phase inverter, PMOS pipe P101 is connected with the drain electrode of NMOS pipe N101 and as the output terminal of the first phase inverter, the source electrode of PMOS pipe P101 meets operating voltage VDD, the source ground of NMOS pipe N101; PMOS pipe P102 and NMOS pipe N102 connect to form the second phase inverter, PMOS pipe P102 is connected with the grid of NMOS pipe N102 and as the input end of the second phase inverter, PMOS pipe P102 is connected with the drain electrode of NMOS pipe N102 and as the output terminal of the second phase inverter, the source electrode of PMOS pipe P102 meets operating voltage VDD, the source ground of NMOS pipe N102; The output terminal of input termination second phase inverter of the first phase inverter, the output terminal of input termination first phase inverter of the second phase inverter, the first phase inverter and a bistable structure of the second phase inverter composition, this bistable structure is conducive to improve the stability of storage unit.The output terminal of the first phase inverter is output node Q1, and the output terminal of the second phase inverter is output node Q2, output node Q1 and a pair of anti-phase signal of Q2 output.NMOS pipe N103 and NMOS pipe N104 are transfer tube, and the source electrode of NMOS pipe N103 connects the output terminal of the first phase inverter, and NMOS pipe N104 source electrode connects the output terminal of the second phase inverter; The drain electrode of NMOS pipe N103 meets bit line BL, and the drain electrode of NMOS pipe N104 meets bit line BLB, bit line BL and the BLB bit line that partners; The grid of NMOS pipe N103 and NMOS pipe N104 all meets word line WL.

The write operation process of existing static RAM is: suppose that write signal is for " 1 ", before writing, bit line BL is set to " 1 ", and bit line BLB is set to " 0 "; Carry out after write operation, word line WL is high level by low transition, at this moment NMOS pipe N103 and all conductings of N104, and data " 1 " are written in output node Q1, and data " 0 " are written in output node Q2.

The read operation process of existing static RAM is: before read operation starts, bit line BL and BLB are precharged to high level; When entering after read operation, word line WL is high level by low transition, at this moment NMOS pipe N103 and all conductings of N104, suppose that current output node Q1 is that " 1 ", output node Q2 are " 0 ", at this moment, bit line BLB manages N104 and N102 electric discharge by NMOS, and the current potential of bit line BL is higher than the current potential of bit line BLB, data reading.

Six transistor memory units of existing static RAM have used two cross-coupled phase inverters, higher at middle and high operating voltage stability inferior.But along with constantly reducing of CMOS characteristic dimension and operating voltage, gap between the low and high level of storage unit also can constantly be dwindled, it is obvious that noise becomes the impact of signal output, the stability of storage unit reduces, and existing SRAM cell circuit cannot overcome this impact.

Summary of the invention

Technical matters to be solved by this invention is to provide a kind of SRAM cell circuit, can improve the noise robustness of storage unit circuit, makes signal output have higher stability, can be applied under the condition of work of low supply voltage.

For solving the problems of the technologies described above, SRAM cell circuit provided by the invention comprises:

The bistable structure being formed by the first phase inverter and the second phase inverter, the input end that the input end of described the first phase inverter connects the output terminal of described the second phase inverter, described the second phase inverter connects the output terminal of described the first phase inverter, a pair of anti-phase signal of output terminal storage of the output terminal of described the first phase inverter and described the second phase inverter; Described the first phase inverter is connected to form by a PMOS pipe and a NMOS pipe, and described the second phase inverter is connected to form by the 2nd PMOS pipe and the 2nd NMOS pipe.

The 3rd phase inverter being connected to form by the 3rd PMOS pipe and the 3rd NMOS pipe, the input end of described the 3rd phase inverter connects the output terminal of described the first phase inverter.

The 4th phase inverter being connected to form by the 4th PMOS pipe and the 4th NMOS pipe, the input end of described the 4th phase inverter connects the output terminal of described the second phase inverter.

As the 5th NMOS pipe and the 6th NMOS pipe of transfer tube, the drain electrode that the source electrode of described the 5th NMOS pipe connects the output terminal of described the 3rd phase inverter, described the 5th NMOS pipe connects bit line one, the drain electrode that the source electrode of described the 6th NMOS pipe connects the output terminal of described the 4th phase inverter, described the 6th NMOS pipe connects bit line two, and the grid of the grid of described the 5th NMOS pipe and described the 6th NMOS pipe all connects word line.

SRAM cell circuit of the present invention is by increasing and increase respectively a phase inverter between two signal output parts in bistable structure and corresponding transfer tube, can realize output signal is carried out to further shaping by the phase inverter increasing, thereby can greatly reduce the impact of noise on output signal, improve the noise robustness of storage unit circuit, make signal output there is higher stability, make like this present invention can be applied under the condition of work of low supply voltage, meet the ever-reduced requirement of CMOS characteristic dimension and operating voltage.

Brief description of the drawings

Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:

Fig. 1 is the circuit diagram of existing SRAM cell circuit;

Fig. 2 is the circuit diagram of embodiment of the present invention SRAM cell circuit.

Embodiment

As shown in Figure 2, be the circuit diagram of embodiment of the present invention SRAM cell circuit.Embodiment of the present invention SRAM cell circuit comprises:

The bistable structure being formed by the first phase inverter and the second phase inverter, the input end that the input end of described the first phase inverter connects the output terminal of described the second phase inverter, described the second phase inverter connects the output terminal of described the first phase inverter, the output terminal of described the first phase inverter is output node Q1, the output terminal of described the second phase inverter is output node Q2, a pair of anti-phase signal of output node Q1 and output node Q2 storage.

Described the first phase inverter is connected to form by a PMOS pipe P1 and NMOS pipe N1, specifically be connected to: a described PMOS pipe P1 is connected with the grid of a described NMOS pipe N1 and as the input end of described the first phase inverter, a described PMOS pipe P1 is connected with the drain electrode of a described NMOS pipe N1 and as the output terminal of described the first phase inverter, the source electrode of a described PMOS pipe P1 meets operating voltage VDD, the source ground of a described NMOS pipe N1.

Described the second phase inverter is connected to form by the 2nd PMOS pipe P2 and the 2nd NMOS pipe N2, specifically be connected to: described the 2nd PMOS pipe P2 is connected with the grid of described the 2nd NMOS pipe N2 and as the input end of described the second phase inverter, described the 2nd PMOS pipe P2 is connected with the drain electrode of described the 2nd NMOS pipe N2 and as the output terminal of described the second phase inverter, the source electrode of described the 2nd PMOS pipe P2 meets operating voltage VDD, the source ground of described the 2nd NMOS pipe N2.

The 3rd phase inverter being connected to form by the 3rd PMOS pipe P3 and the 3rd NMOS pipe N3, specifically be connected to: described the 3rd PMOS pipe P3 is connected with the grid of described the 3rd NMOS pipe N3 and as the input end of described the 3rd phase inverter, described the 3rd PMOS pipe P3 is connected with the drain electrode of described the 3rd NMOS pipe N3 and as the output terminal of described the 3rd phase inverter, the source electrode of described the 3rd PMOS pipe P3 meets operating voltage VDD, the source ground of described the 3rd NMOS pipe N3.The input end of described the 3rd phase inverter connects the output terminal of described the first phase inverter.

The 4th phase inverter being connected to form by the 4th PMOS pipe P4 and the 4th NMOS pipe N4, specifically be connected to: described the 4th PMOS pipe P4 is connected with the grid of described the 4th NMOS pipe N4 and as the input end of described the 4th phase inverter, described the 4th PMOS pipe P4 is connected with the drain electrode of described the 4th NMOS pipe N4 and as the output terminal of described the 4th phase inverter, the source electrode of described the 4th PMOS pipe P4 meets operating voltage VDD, the source ground of described the 4th NMOS pipe N4.The input end of described the 4th phase inverter connects the output terminal of described the second phase inverter.

As the 5th NMOS pipe N5 and the 6th NMOS pipe N6 of transfer tube, the source electrode of described the 5th NMOS pipe N5 connects the output terminal of described the 3rd phase inverter, the drain electrode of described the 5th NMOS pipe N5 connects bit line one BL, the source electrode of described the 6th NMOS pipe N6 connects the output terminal of described the 4th phase inverter, the drain electrode of described the 6th NMOS pipe N6 connects bit line two BLB, and the grid of the grid of described the 5th NMOS pipe N5 and described the 6th NMOS pipe N6 all meets word line WL.

The 3rd phase inverter described in the embodiment of the present invention and described the 4th phase inverter can carry out further shaping to the information of output node Q1 and Q2 output respectively, thereby can greatly reduce the impact of noise on output signal, improve the noise robustness of storage unit circuit, make signal output there is higher stability, make like this embodiment of the present invention can be applied under the condition of work of low supply voltage, meet the ever-reduced requirement of CMOS characteristic dimension and operating voltage.

By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (1)

1. a SRAM cell circuit, is characterized in that, comprising:
The bistable structure being formed by the first phase inverter and the second phase inverter, the input end that the input end of described the first phase inverter connects the output terminal of described the second phase inverter, described the second phase inverter connects the output terminal of described the first phase inverter, a pair of anti-phase signal of output terminal storage of the output terminal of described the first phase inverter and described the second phase inverter; Described the first phase inverter is connected to form by a PMOS pipe and a NMOS pipe, and described the second phase inverter is connected to form by the 2nd PMOS pipe and the 2nd NMOS pipe;
The 3rd phase inverter being connected to form by the 3rd PMOS pipe and the 3rd NMOS pipe, the input end of described the 3rd phase inverter connects the output terminal of described the first phase inverter;
The 4th phase inverter being connected to form by the 4th PMOS pipe and the 4th NMOS pipe, the input end of described the 4th phase inverter connects the output terminal of described the second phase inverter;
As the 5th NMOS pipe and the 6th NMOS pipe of transfer tube, the drain electrode that the source electrode of described the 5th NMOS pipe connects the output terminal of described the 3rd phase inverter, described the 5th NMOS pipe connects bit line one, the drain electrode that the source electrode of described the 6th NMOS pipe connects the output terminal of described the 4th phase inverter, described the 6th NMOS pipe connects bit line two, and the grid of the grid of described the 5th NMOS pipe and described the 6th NMOS pipe all connects word line.
CN201310039841.9A 2013-02-01 2013-02-01 Static random access memory unit circuit CN103971730A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1477642A (en) * 2002-08-22 2004-02-25 三菱电机株式会社 Semiconductor storage for storing 3 value data signal
US20060164881A1 (en) * 2005-01-26 2006-07-27 Nec Electronics Corporation Static semiconductor memory device
US20100142258A1 (en) * 2008-12-05 2010-06-10 Tsai Tsung-Heng Ten-transistor static random access memory architecture
US20120057399A1 (en) * 2010-09-07 2012-03-08 Shyh-Jye Jou Asymmetric virtual-ground single-ended sram and system thereof
CN102903386A (en) * 2012-09-19 2013-01-30 上海集成电路研发中心有限公司 Static random memory unit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1477642A (en) * 2002-08-22 2004-02-25 三菱电机株式会社 Semiconductor storage for storing 3 value data signal
US20060164881A1 (en) * 2005-01-26 2006-07-27 Nec Electronics Corporation Static semiconductor memory device
US20100142258A1 (en) * 2008-12-05 2010-06-10 Tsai Tsung-Heng Ten-transistor static random access memory architecture
US20120057399A1 (en) * 2010-09-07 2012-03-08 Shyh-Jye Jou Asymmetric virtual-ground single-ended sram and system thereof
CN102903386A (en) * 2012-09-19 2013-01-30 上海集成电路研发中心有限公司 Static random memory unit

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Application publication date: 20140806