CN106328210A - Method for producing radiation-resistant fault-tolerant memory cell - Google Patents
Method for producing radiation-resistant fault-tolerant memory cell Download PDFInfo
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- CN106328210A CN106328210A CN201510336387.2A CN201510336387A CN106328210A CN 106328210 A CN106328210 A CN 106328210A CN 201510336387 A CN201510336387 A CN 201510336387A CN 106328210 A CN106328210 A CN 106328210A
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Abstract
The invention belongs to the field of an integrated circuit, and relates to a radiation-resistant memory cell formed by four inverters which are mutually intertwisted and connected, wherein a latch register is formed by two inverters, when a storage node value is error due to radiation, a circuit which is analogous to the inverter can guarantee that the output of the memory cell still keeps at an original correct value, the mutually intertwisted and connected other storage node drives the storage node which generates error to recover the original correct value after the radiation effect disappears, so that the memory cell has radiation-resistant fault-tolerant characteristic. The error generation frequency of the radiation-resistant fault-tolerant memory cell and a triple modular redundancy scheme is little and equal, radiation-resistant capability of the radiation-resistant fault-tolerant memory cell and the triple modular redundancy scheme is same, the area and power consumption of the radiation-resistant fault-tolerant memory cell is smaller than that of the triple modular redundancy scheme.
Description
Technical field
The invention belongs to integrated circuit fields, relate to Anti-radioactive Fault-tolerant memory element, be specifically related to a kind of Anti-radioactive Fault-tolerant
The circuit design method of memory element.
Background technology
According to data, along with the minimizing of process, the integrated circuit in chip is in high-rise space or near-earth spherical space
Become increasingly susceptible to heavy particle or proton irradiation impact and produce mistake.Studies have reported that, radiation is if it occur that depositing
The memory node of storage unit, may directly result in memory element storage erroneous values, produce single event upset；Spoke
Penetrate if it occur that at combinational circuit node, single event transient pulse may be caused, change the logic state of circuit node；
The improper value that this single event transient pulse causes is transmitted to memory element can be likely to the storage that is captured, and produces single-particle and turns over
Turn event；So single event upset can change the logic state of memory element storage, it is likely to result in integrated circuit merit
Can mistake.Therefore, need in the art to propose to support radiation-resistant storage unit circuit method for designing.
The method for designing of the radioprotective storage unit circuit of prior art mainly comprises multi-mode redundant, error correcting code and radioprotective
Reinforcement technique etc.；Wherein, multi-mode redundant method, with triplication redundancy technology as representative, uses redundant circuit module and majority
The output of voting circuit shielding erroneous circuits module, but this method can bring the biggest area overhead；Error correction code approach
With Hamming code as representative, by the check value of calculation code, the position of Wrong localization bit；Radiation hardening technology with
Double interlock memory element is representative, increases extra transistor and the most stranded on the basis of basic unit of storage structure
Interconnection line, strengthen sensitive nodes capability of resistance to radiation；But error correcting code and radiation hardening technology can bring bigger face
Long-pending expense, and reduce circuit performance.
In consideration of it, present inventor intends providing the preparation method of a kind of new Anti-radioactive Fault-tolerant memory element.
List of references related to the present invention has:
[1]Baumann R.Soft Errors in Advanced Computer Systems[J],IEEE Transactions on
Device and Materials Reliability,2005,22(3),pp.258-266
[2] Oliveira R., Jagirdar A., Chakraborty T.J.:A TMR Scheme for SEU Mitigation in Scan
Flip-Flops [C], in International Symposium on Quality Electronic Design, 2007, pp.905
–910
[3]Tausch H.J.Simplified Birthday Statistics and Hamming EDAC[J],IEEE Transactions
on Nuclear Science,2009,56(2),pp.474–478
[4]Calin T.,Nicolaidis M.,Velazco R.Upset hardened memory design for submicron
CMOS technology[J],IEEE Transactions on Nuclear Science,1996,43(6),pp.
2874–2878
[5]S.Yang.Logic Synthesis and Optimization Benchmarks User Guide,Research Triangle
Park,NC:Microelectronics Center of North Carolina(MCNC),1991。
Summary of the invention
It is an object of the invention to for defect present in integrated circuit prior art, propose a kind of Anti-radioactive Fault-tolerant storage
Element circuit method for designing.
Specifically, the preparation method of a kind of Anti-radioactive Fault-tolerant memory element of the present invention, it is characterised in that use four
One radioprotective memory element of individual inverter configuration, wherein one latch of each two phase inverter composition, thus this storage
Unit contains two latch；The mutual stranded connection of transistor of the two redundant latch, when a circuit section point value
When changing because of radiation, other node of mutual stranded connection can suppress this change, so that this memory element tool
There is Anti-radioactive Fault-tolerant characteristic.
The preparation method of the Anti-radioactive Fault-tolerant memory element of the present invention, its bag expands following two steps, the most in addition
Describe in detail.
Step 1: according to circuit structure shown in Fig. 1, uses traditional integrated circuit method for designing design Anti-radioactive Fault-tolerant to deposit
Storage unit circuit:
Circuit structure as shown in Figure 1, design radioprotective storage unit circuit: Fig. 1 contains 4 phase inverter INV1-INV4,
INV1 is made up of PMOS P1 and NMOS tube N3；INV2 is by PMOS P2 and NMOS tube N4 structure
Become；INV3 is made up of PMOS P3 and NMOS tube N7；INV4 is by PMOS P5 and NMOS tube N6
Constitute；If PMOS grid is identical with NMOS tube grid numerical value in these phase inverters, then export inverse value, as
Fruit is different, then value before output；Such as, in phase inverter INV1, the grid of PMOS P1 is m2, NMOS tube
The grid of N3 is m4, and inverter output is m1；If m2 and m4 holds identical value 1, then PMOS P1 is broken
Opening, NMOS tube N3 turns on, so inverter output m1 value is 0；If m2 and m4 is identical value 0, then
PMOS P1 turns on, and NMOS tube N3 disconnects, so inverter output m1 value is 1；If m2 and m4
Hold different value 1 and 0 respectively, then PMOS P1 disconnects, and NMOS tube N3 disconnects, so phase inverter can not export
Inverse value, its outfan m1 value is worth before maintaining；If m2 and m4 holds different value 0 and 1, then PMOS respectively
Pipe P1 turn on, NMOS tube N3 turn on, so phase inverter can not export inverse value, its outfan m1 value maintenance with
Front value；In like manner, for phase inverter INV2, if m2 and m4 holds identical value, then inverter output m3 is defeated
Go out inverse value, if m2 and m4 holds different value, then value before inverter output m3 maintains；To phase inverter INV3
For, if m1 and m3 holds identical value, then inverter output m2 output inverse value, if m1 and m3 holds
Different value, then value before inverter output m2 maintains；For phase inverter INV4, if m1 and m3 holds phase
With value, then inverter output m4 output inverse value, if m1 and m3 holds different value, then inverter output
M4 is worth before maintaining；In Fig. 1, PMOS P3, P4 also constitute a similar phase inverter with NMOS tube N5, N6
Circuit, if the grid m1 value of PMOS P3, P4 is identical with the grid m3 value of NMOS tube N5, N6,
Then outfan Out exports inverse value, if it is different, then value before outfan Out output；Such as, if m1 and
M3 holds identical value 1, then PMOS P3, P4 disconnect, and NMOS tube N5, N6 turn on, so outfan Out
Value is 0；If m1 and m3 holds identical value 0, then PMOS P3, P4 conducting, NMOS tube N5, N6 are disconnected
Open, so outfan Out value is 1；If m1 and m3 holds different value 1 and 0, then PMOS P3, P4 respectively
Disconnecting, NMOS tube N5, N6 disconnect, so outfan Out value is worth before maintaining；If m1 and m3 holds respectively
Different value 0 and 1, then PMOS P3, P4 conducting, NMOS tube N5, N6 turn on, so outfan Out
Value is worth before maintaining；
In the present invention (as shown in Figure 1), phase inverter INV1 Yu INV3 constitutes a latch, m1 with m2 is to deposit
Storage node；Phase inverter INV2 Yu INV4 constitutes a latch, m3 Yu m4 is memory node；When write control
When signal WR value is 1, NMOS tube N1 turns on N2, and the data on input Data are simultaneously written storage joint
Point m1 and m3；When the data on input Data are 0, m1 Yu m3 value is 0, so phase inverter INV3
Outfan m2 value becomes 1, and phase inverter INV4 outfan m4 value also becomes 1；Owing to m2 Yu m4 value is 1,
So phase inverter INV1 outfan m1 value is again 0；Phase inverter INV2 outfan m3 value is 0 again, and this adds further
Numerical value 0 before strong m1 Yu m3, so that the storage numerical value 0 and 1 that memory node m1 and m2 is the most stable,
Storage numerical value 0 and 1 the most stable for memory node m3 and m4；In like manner, it is 1 when the data on input Data
Time, m1 Yu m3 value is 1, so phase inverter INV3 outfan m2 value becomes 0, and phase inverter INV4 outfan
M4 value also becomes 0；Owing to m2 Yu m4 value is 0, so phase inverter INV1 outfan m1 value is again 1；Instead
Phase device INV2 outfan m3 value is again 1, and this strengthens the numerical value 1 before m1 Yu m3 further, so that storage
Storage numerical value 1 and 0 the most stable for node m1 and m2, storage number the most stable for memory node m3 and m4
Value 1 and 0；When m1 and m3 value is all 0, memory element outfan Out value is 1；When m1 and m3 value is all
When 1, memory element outfan Out value is 0；
As it is shown in figure 1, wherein on memory node m1 Yu m2 and memory node m3 Yu m4 after data stabilization, write
Enter control signal WR value and be set to 0, then NMOS tube N1 disconnects with N2, memory node m1 Yu m2 and storage
Node m3 Yu m4 can stable storage data, now, memory node m1 and m3 value is identical, memory node m2 and
M4 value is identical；If memory node m1 value changes because of radiation, owing to NMOS tube N1 disconnects with N2, m3
Remain in that original right value, so memory element outfan Out maintains original right value；Due to m1 and m3
Value difference, phase inverter INV3 outfan m2 maintains original right value, and phase inverter INV4 outfan m4 remains former
The right value come；After effect to be irradiated disappears, m2 with m4 of identical right value is maintained to be driven by phase inverter INV1
Memory node m1 recovers original right value；In like manner, if memory node m2 value changes because of radiation, storage joint
Point m1, m3, m4 can maintain original right value, and memory element outfan Out also can maintain original right value,
After effect to be irradiated disappears, m1 Yu m3 of identical right value is maintained to drive memory node m2 by phase inverter INV3
Recover original right value；If memory node m3 value changes because of radiation, memory node m1, m2, m4 meeting
Maintain original right value, memory element outfan Out also can maintain original right value, after effect to be irradiated disappears,
M2 Yu m4 maintaining identical right value passes through the right value that phase inverter INV2 driving memory node m3 recovers original；
If memory node m4 value changes because of radiation, memory node m1, m2, m3 can maintain original right value,
Memory element outfan Out also can maintain original right value, after effect to be irradiated disappears, maintains identical right value
M1 Yu m3 passes through the right value that phase inverter INV4 driving memory node m4 recovers original；If memory element exports
End Out value changes because of radiation, and memory node m1, m2, m3, m4 can maintain original right value, to be irradiated
After effect disappears, maintain m1, m3 of identical right value by by PMOS P3, P4 and NMOS tube N5,
Similar inverter circuit drive output Out that N6 is constituted recovers original right value；
Step 2: operate the write control signal WR of memory element in Fig. 1, makes data can write this storage list
Unit, and make this memory element have Anti-radioactive Fault-tolerant characteristic；
As it is shown in figure 1, wherein memory element has both of which: write data, stable storage data；
If memory element is under write-ining data mode, arranging write control signal WR value is 1, NMOS tube N1 with
N2 turns on, and the data on input Data are simultaneously written memory node m1 and m3, memory node m2 and m4 value and are
The inverse value of input Data value, memory element outfan Out value is also for the inverse value of input Data value；
If memory element is under stable storage data pattern, arranging write control signal WR value is 0, memory node
M1 Yu m2 and memory node m3 Yu m4 meeting stable storage data, wherein, memory node m1 and m3 value is identical,
Memory node m2 and m4 value is identical；If any one nodal value is because of spoke in memory node m1, m2, m3, m4
Penetrating generation temporarily change, remaining memory node value and memory element outfan Out value will not change, but remain original
Right value, effect to be irradiated disappear after, because of radiation occur that the memory node of improper value can recover original right value；
If memory element outfan Out value occurs temporarily change because of radiation, memory node m1, m2, m3, m4 value will not
Change, but maintain original right value, after effect to be irradiated disappears, memory element outfan Out can recover original
Right value.
The present invention has carried out experiment test, and result shows, the Anti-radioactive Fault-tolerant memory element of the present invention and triplication redundancy side
The wrong frequency of case the most less and also quite, so their capability of resistance to radiation is close, but the area of the present invention and
The area of power dissipation ratio triplication redundancy scheme and the little comparison of power consumption are many.
The invention have the advantages that
The present invention proposes a kind of radioprotective memory element being made up of four phase inverters of mutual stranded connection.Wherein,
When a memory node value makes a mistake because of radiation, the circuit of a similar phase inverter can ensure that memory element exports still
So maintain original right value, and other memory node of mutual stranded connection is after radiation effect disappears, and can drive
The memory node made a mistake recovers original right value, so that this memory element has Anti-radioactive Fault-tolerant characteristic.
Accompanying drawing illustrates:
Fig. 1 is the electrical block diagram of the Anti-radioactive Fault-tolerant memory element of the present invention.
Detailed description of the invention
Embodiment 1 experiment test
In experiment, realize 6 benchmark test circuit without capability of resistance to radiation initially with traditional standard circuit design method
Bigkey, dsip, S38417, S13207.1, S15850.1, S38584.1, the most again by triplication redundancy scheme [2] and the present invention
Realize these benchmark test circuit respectively, be allowed to that there is capability of resistance to radiation；Different schemes is used to realize these respectively
Benchmark test circuit random radiation 1000 times, the test wrong frequency of gained, area and power consumption meansigma methods such as table 1
Shown in, area therein and power consumption have passed through normalized, and its numerical value is circuit realized relative to the present invention program
Area and the multiple of power consumption；Test experiments result shows (as shown in table 1), the present invention and the mistake of triplication redundancy scheme
Frequency is the most less and suitable by mistake, so their capability of resistance to radiation is close, but the area of the present invention and power dissipation ratio
The area of triplication redundancy scheme and the little comparison of power consumption are many.
Table 1 area, power consumption and capability of resistance to radiation compare
| Scheme | Mistake frequency | Area | Power consumption |
| Traditional standard method for designing without capability of resistance to radiation | 253 | 0.65 | 0.58 |
| The radiation-hardened design method of the present invention | 0 | 1 | 1 |
| The radiation-hardened design method of triplication redundancy | 4 | 1.84 | 1.78 |
Claims (3)
1. the circuit design method of an Anti-radioactive Fault-tolerant memory element, it is characterised in that it comprises the steps:
Step 1: circuit structure as shown in Figure 1, uses the design Anti-radioactive Fault-tolerant storage of traditional integrated circuit method for designing single
Unit's circuit；
Step 2: operate the write control signal WR of the memory element shown in Fig. 1, makes data can write this and deposits
Storage unit, and make this memory element have Anti-radioactive Fault-tolerant characteristic.
2. the method as described in claim 1, it is characterised in that described step 1) in, circuit as shown in Figure 1
Structure, designs radioprotective storage unit circuit, wherein contains 4 phase inverter INV1-INV4, and INV1 is by PMOS
Pipe P1 and NMOS tube N3 are constituted, and INV2 is made up of PMOS P2 and NMOS tube N4, and INV3 is by PMOS
Pipe P3 and NMOS tube N7 are constituted, and INV4 is made up of PMOS P5 and NMOS tube N6；Described is anti-phase
If PMOS grid is identical with NMOS tube grid numerical value in device, then export inverse value, if it is different, then output
Value in the past；If m2 and m4 holds identical value, then m1 and m3 exports inverse value, if m2 and m4 holds difference
Value, then value before m1 and m3 maintains；If m1 and m3 holds identical value, then m2 and m4 exports inverse value,
If m1 and m3 holds different value, then value before m2 and m4 maintains；Described PMOS P3, P4 and NMOS
Pipe N5, N6 also constitute the circuit of a similar phase inverter, if the grid m1 value of PMOS P3, P4 and NMOS
The grid m3 value of pipe N5, N6 is identical, then memory element outfan Out exports inverse value, if it is different, then storage
Value before unit outfan Out output；Described phase inverter INV1 Yu INV3 constitutes a latch, m1 and m2
It it is memory node；Described phase inverter INV2 Yu INV4 constitutes a latch, m3 Yu m4 is memory node.
3. the method as described in claim 1, it is characterised in that described step 2) including: shown in Fig. 1
The memory element of both of which, including write data, stable storage data；
If described memory element is under write-ining data mode, arranging write control signal WR value is 1, input
It is input Data value that data on Data are simultaneously written memory node m1 and m3, memory node m2 with m4 value
Inverse value, memory element outfan Out value is also for the inverse value of input Data value；
If described memory element is under stable storage data pattern, arranging write control signal WR value is 0, deposits
Storage node m1 Yu m2 and memory node m3 Yu m4 meeting stable storage data, wherein, memory node m1 and m3
Being worth identical, memory node m2 and m4 value is identical, if any one joint in memory node m1, m2, m3, m4
There is temporarily change because of radiation in point value, remaining memory node value and memory element outfan Out value will not change, and maintain
Right value originally, after effect to be irradiated disappears, because radiation occurs that the memory node of improper value can recover original correct
Value；If there is temporarily change, memory node m1, m2, m3, m4 value because of radiation in memory element outfan Out value
Will not change, maintain original right value, after effect to be irradiated disappears, memory element outfan Out can recover original
Right value.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956183A (en) * | 2014-04-24 | 2014-07-30 | 中国科学院微电子研究所 | Anti-radiation static random access memory (SRAM) unit |
| CN103971734A (en) * | 2014-05-23 | 2014-08-06 | 中国科学院微电子研究所 | Anti-radiation SRAM (Static Random Access Memory) unit |
| CN104392745A (en) * | 2014-11-27 | 2015-03-04 | 西安交通大学 | SRAM unit with high writing speed, low static power consumption and single-particle overturning resistance |
| CN104409093A (en) * | 2014-12-09 | 2015-03-11 | 复旦大学 | Differential ten-tube storage cell resistant to single-event upset |
| CN104464795A (en) * | 2014-11-27 | 2015-03-25 | 西安交通大学 | Static random access memory unit with single-particle-upset resistance |
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2015
- 2015-06-17 CN CN201510336387.2A patent/CN106328210B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956183A (en) * | 2014-04-24 | 2014-07-30 | 中国科学院微电子研究所 | Anti-radiation static random access memory (SRAM) unit |
| CN103971734A (en) * | 2014-05-23 | 2014-08-06 | 中国科学院微电子研究所 | Anti-radiation SRAM (Static Random Access Memory) unit |
| CN104392745A (en) * | 2014-11-27 | 2015-03-04 | 西安交通大学 | SRAM unit with high writing speed, low static power consumption and single-particle overturning resistance |
| CN104464795A (en) * | 2014-11-27 | 2015-03-25 | 西安交通大学 | Static random access memory unit with single-particle-upset resistance |
| CN104409093A (en) * | 2014-12-09 | 2015-03-11 | 复旦大学 | Differential ten-tube storage cell resistant to single-event upset |
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