CN109687850B - Latch completely tolerating any three-node overturning - Google Patents

Latch completely tolerating any three-node overturning Download PDF

Info

Publication number
CN109687850B
CN109687850B CN201811556555.9A CN201811556555A CN109687850B CN 109687850 B CN109687850 B CN 109687850B CN 201811556555 A CN201811556555 A CN 201811556555A CN 109687850 B CN109687850 B CN 109687850B
Authority
CN
China
Prior art keywords
nmos transistor
signal input
pmos
transistor
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811556555.9A
Other languages
Chinese (zh)
Other versions
CN109687850A (en
Inventor
李锐
闫爱斌
路璐
冯祥凤
刘思佳
周俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anhui University
Original Assignee
Anhui University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anhui University filed Critical Anhui University
Priority to CN201811556555.9A priority Critical patent/CN109687850B/en
Publication of CN109687850A publication Critical patent/CN109687850A/en
Application granted granted Critical
Publication of CN109687850B publication Critical patent/CN109687850B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits

Abstract

The invention relates to a latch with complete tolerance to any three-node upset, which comprises: two memory modules, namely a first memory module DICE1 and a second memory module DICE2, each constructed with 4 pairs of PN transistors; three C cells, i.e., a first C cell CE1, a second C cell CE2, a third C cell CE3, the third C cell CE3 having a clock control terminal; five transmission gates, namely a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4 and a fifth transmission gate TG 5. According to the invention, two isomorphic storage modules for storing data are respectively constructed by four pairs of PN transistors which are mutually fed back, then two C units are respectively used for receiving output data of the two storage modules, so that primary filtering of node overturning is realized, and finally, secondary filtering of node overturning is realized, so that complete tolerance to any double-node overturning is realized, and a complete tolerance function to any three-node overturning is realized.

Description

Latch completely tolerating any three-node overturning
Technical Field
The invention relates to the technical field of design of a reinforced latch for resisting multi-node overturning of a nano integrated circuit, in particular to a latch completely tolerant to any three-node overturning.
Background
Under the nanometer technology, along with the continuous improvement of the manufacturing process level of the integrated circuit, the integration level of the integrated circuit is higher and higher, the interval between the transistors is smaller and smaller, and the electric charge quantity which can be stored by a single node is also reduced continuously. As a result, integrated circuits are increasingly susceptible to soft errors caused by high energy particles (e.g., neutrons, alpha particles, protons, heavy ions, electrons) in the radiation environment. Soft errors refer to the flipping of the logic state of a circuit node without damage to the device itself in the circuit. Under the nano-technology, in a strong radiation environment, the soft error greatly affects the reliability of the circuit.
Latches are the basic memory cells of an integrated circuit that can change state at a particular input pulse level. Under the nanometer technology, the latch circuit node without the reinforcement design is easy to have single-node turnover, double-node turnover and even three-node turnover under the space radiation environment, and a serious challenge is brought to the design of the nanoscale latch circuit. For a latch circuit working in a strong radiation environment for a long time, the latch circuit can only resist single event upset and double-node upset, the requirement of high reliability is difficult to meet, and a multi-node upset resistance reinforcement design must be carried out on the latch circuit.
At present, the following problems mainly exist in the aspect of the multi-node turnover resisting reinforcement design of the latch: one is that double node flips occurring in the latch cannot be completely tolerated, i.e., there is a point pair, when the point pair flips, the latch will output a wrong logic value; the three-node upset in the latch cannot be completely tolerated, namely a three-point sequence exists, and when the three-point sequence is overturned, the latch outputs an incorrect logic value; thirdly, the overhead (such as area, power consumption, delay and the like) of the latch capable of tolerating multi-node upset is large.
Disclosure of Invention
The invention aims to provide a latch with complete tolerance on any three-node upset, which can meet the requirements on high reliability and low overhead for completely tolerating any three-node upset and improve the performance of a multi-node upset resistant reinforced latch.
In order to realize the purpose, the invention adopts the following technical scheme: an arbitrary three-node flip-flop fully tolerant latch comprising:
two memory modules, namely a first memory module DICE1 and a second memory module DICE2, each constructed with 4 pairs of PN transistors;
three C cells, a first C cell CE1, a second C cell CE2, and a third C cell CE3, wherein the third C cell CE3 has a clock control terminal;
five transmission gates, namely a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4 and a fifth transmission gate TG 5;
the first memory module DICE1 has a first signal input/output common terminal I1, a second signal input/output common terminal I3, a first internal node I2, and a second internal node I4; the second memory module DICE2 has a first signal input/output common terminal I5, a second signal input/output common terminal I7, a first internal node I6, and a second internal node I8; the first C cell CE1 is provided with a first signal input terminal, a second signal input terminal and a signal output terminal I9; the second C cell CE2 is provided with a first signal input terminal, a second signal input terminal and a signal output terminal I10; the third C unit CE3 is provided with a first signal input terminal, a second signal input terminal, a clock signal input terminal CLK, an inverted clock signal input terminal CLKB, and a signal output terminal Q;
a signal input end of the first transmission gate TG1, a signal input end of the second transmission gate TG2, a signal input end of the third transmission gate TG3, a signal input end of the fourth transmission gate TG4 and a signal input end of the fifth transmission gate TG5 are used as data input ends D of the latch;
a signal output end of the first transmission gate TG1 is connected with a first signal input and output common end I1 of the memory module DICE 1; a signal output end of the second transmission gate TG2 is connected to a second signal input/output common terminal I3 of the memory module DICE 1; a signal output end of the third transmission gate TG3 is connected to the first signal input/output common terminal I5 of the memory module DICE 2; a signal output end of the fourth transmission gate TG4 is connected to a second signal input/output common terminal I7 of the memory module DICE 2; a signal output terminal of the fifth transmission gate TG5 is connected to the signal output terminal Q of the third C cell CE 3;
a first signal input/output common terminal I1 of the first memory module DICE1 is connected to a first signal input terminal of the first C-cell CE 1; a second signal input/output common terminal I3 of the first memory module DICE1 is connected to a first signal input terminal of the second C-cell CE 2; a first signal input/output common terminal I5 of the second memory module DICE2 is connected to a second signal input terminal of the first C-cell CE 1; a second signal input/output common terminal I7 of the second memory module DICE2 is connected to a second signal input terminal of the second C cell CE 2;
the signal output terminal I9 of the first C cell CE1 is a first signal input terminal of the third C cell CE 3; the signal output terminal I10 of the second C cell CE2 is a second signal input terminal of the third C cell CE3, the clock signal input terminal CLK of the third C cell CE3 is connected to the system clock CLK, and the inverted clock signal input terminal CLKB of the third C cell CE3 is connected to the inverted system clock CLKB; when CLK is 0 and CLKB is 1, the signal output Q of the third C unit CE3 serves as the data output Q of the latch; when CLK is equal to 1 and CLKB is equal to 0, the signal output terminal of the fifth transmission gate TG5 serves as the data output terminal Q of the latch.
The first storage module DICE1 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4; wherein:
the drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, the gate of the second PMOS transistor P2, and the gate of the fourth NMOS transistor N4 are connected, and the connection point is used as the first signal input/output common terminal I1 of the first memory module DICE 1;
the drain of the second PMOS transistor P2, the drain of the second NMOS transistor N2, the gate of the third PMOS transistor P3, and the gate of the first NMOS transistor N1 are connected, and the connection point is used as a first internal node I2 of the first memory module DICE 1;
the drain of the third PMOS transistor P3, the drain of the third NMOS transistor N3, the gate of the fourth PMOS transistor P4, and the gate of the second NMOS transistor N2 are connected, and the connection point is used as the second signal input/output common terminal I3 of the first memory module DICE 1;
a drain electrode of the fourth PMOS transistor P4, a drain electrode of the fourth NMOS transistor N4, a gate electrode of the first PMOS transistor P1, and a gate electrode of the third NMOS transistor N3 are connected, and a connection point is used as a second internal node I4 of the first memory module DICE 1;
the source electrodes and the substrates of the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 are all connected with a power supply VDD;
the sources and the substrates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 are all grounded GND.
The second storage module DICE2 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8; wherein:
a drain electrode of the fifth PMOS transistor P5, a drain electrode of the fifth NMOS transistor N5, a gate electrode of the sixth PMOS transistor P6, and a gate electrode of the eighth NMOS transistor N8 are connected, and a connection point is used as a first signal input/output common terminal I5 of the second memory module DICE 2;
a drain electrode of the sixth PMOS transistor P6, a drain electrode of the sixth NMOS transistor N6, a gate electrode of the seventh PMOS transistor P7, and a gate electrode of the fifth NMOS transistor N5 are connected, and a connection point is used as a first internal node I6 of the second memory module DICE 2;
a drain electrode of the seventh PMOS transistor P7, a drain electrode of the seventh NMOS transistor N7, a gate electrode of the eighth PMOS transistor P8, and a gate electrode of the sixth NMOS transistor N6 are connected, and a connection point is used as a second signal input/output common terminal I7 of the second memory module DICE 2;
a drain electrode of the eighth PMOS transistor P8, a drain electrode of the eighth NMOS transistor N8, a gate electrode of the fifth PMOS transistor P5, and a gate electrode of the seventh NMOS transistor N7 are connected, and a connection point is used as a second internal node I8 of the second memory module DICE 2;
the source electrodes and the substrates of the fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7 and the eighth PMOS tube P8 are all connected with a power supply VDD;
the sources and the substrates of the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are all grounded GND.
The first C unit CE1 is composed of two PMOS transistors P9 and a tenth PMOS transistor P10, and two NMOS transistors N9 and a tenth NMOS transistor N10; wherein:
the gate of the ninth PMOS transistor P9 is connected to the gate of the ninth NMOS transistor N9, and the connection point is the first signal input terminal of the first C unit CE 1; the gate of the tenth PMOS transistor P10 is connected to the gate of the tenth NMOS transistor N10, and the connection point is the second signal input terminal of the first C unit CE 1; the drain of the tenth PMOS transistor P10 is connected to the drain of the ninth NMOS transistor N9, and the connection point is the signal output terminal I9 of the first C cell CE 1;
the drain electrode of the ninth PMOS tube P9 is connected with the source electrode of the tenth PMOS tube P10; the source electrode of the ninth NMOS transistor N9 is connected with the drain electrode of the tenth NMOS transistor N10; the source electrode of the ninth PMOS tube P9, the substrate of the ninth PMOS tube P9 and the substrate of the tenth PMOS tube P10 are all connected with a power supply VDD; the substrate of the ninth NMOS transistor N9, the substrate of the tenth NMOS transistor N10, and the source of the tenth NMOS transistor N10 are all grounded.
The second C unit CE2 is composed of two PMOS transistors P11 and a twelfth PMOS transistor P12, and two NMOS transistors N11 and a twelfth NMOS transistor N12; wherein:
the gate of the eleventh PMOS transistor P11 is connected to the gate of the eleventh NMOS transistor N11, and the connection point is the first signal input end of the second C unit CE 2; the gate of the twelfth PMOS transistor P12 is connected to the gate of the twelfth NMOS transistor N12, and the connection point is the second signal input end of the second C unit CE 2; the drain of the twelfth PMOS tube P12 is connected to the drain of the eleventh NMOS tube N11, and the connection point is the signal output end I10 of the second C unit CE 2;
the drain electrode of the eleventh PMOS tube P11 is connected with the source electrode of the twelfth PMOS tube P12; the source electrode of the eleventh NMOS tube N11 is connected with the drain electrode of the twelfth NMOS tube N12; the source electrode of the eleventh PMOS tube P11, the substrate of the eleventh PMOS tube P11 and the substrate of the twelfth PMOS tube P12 are all connected with a power supply VDD; the substrate of the eleventh NMOS transistor N11, the substrate of the twelfth NMOS transistor N12 and the source of the twelfth NMOS transistor N12 are all grounded.
The third C unit CE3 is composed of three PMOS transistors P13, a fourteenth PMOS transistor P14 and a fifteenth PMOS transistor P15, and three NMOS transistors N13, a fourteenth NMOS transistor N14 and a fifteenth NMOS transistor N15; wherein:
the gate of the fourteenth PMOS transistor P14 is connected to the gate of the thirteenth NMOS transistor N13, and the connection point is the first signal input terminal of the third C unit CE 3; the gate of the fifteenth PMOS transistor P15 is connected to the gate of the fourteenth NMOS transistor N14, and the connection point is the second signal input terminal of the third C unit CE 3; the grid electrode of the thirteenth PMOS pipe P13 is connected with the system clock CLK; the gate of the fifteenth NMOS transistor N15 is connected to the inverted system clock CLKB; the drain of the fifteenth PMOS transistor P15 is connected to the drain of the thirteenth NMOS transistor N13, and the connection point is the signal output terminal Q of the third C unit CE 3;
the drain electrode of the thirteenth PMOS tube P13 is connected with the source electrode of the fourteenth PMOS tube P14; the drain electrode of the fourteenth PMOS tube P14 is connected with the source electrode of the fifteenth PMOS tube P15; the drain electrode of the fifteenth PMOS pipe P15 is connected with the drain electrode of the thirteenth NMOS pipe N13; the source electrode of the thirteenth NMOS tube N13 is connected with the drain electrode of the fourteenth NMOS tube N14; the source electrode of the fourteenth NMOS transistor N14 is connected with the drain electrode of the fifteenth NMOS transistor N15; the source electrode of the thirteenth PMOS tube P13, the substrate of the thirteenth PMOS tube P13, the substrate of the fourteenth PMOS tube P14 and the substrate of the fifteenth PMOS tube P15 are all connected with a power supply VDD; the substrate of the thirteenth NMOS transistor N13, the substrate of the fourteenth NMOS transistor N14, the substrate of the fifteenth NMOS transistor N15, and the source of the fifteenth NMOS transistor N15 are all grounded.
According to the technical scheme, the invention has the advantages that: firstly, four pairs of PN transistors which are fed back mutually are respectively used for constructing two isomorphic storage modules for storing data, then two C units are used for respectively receiving output data of the two storage modules, the two C units respectively output the received data to realize primary filtering of node overturning, finally, the output of the two C units after the primary filtering is fed back to an output stage, two input C units based on clock control and finally output, and secondary filtering of node overturning is realized, so that complete tolerance to any double-node overturning is realized, and complete tolerance function to any three-node overturning is realized; secondly, due to the low-overhead characteristic, a high-speed path is constructed between the input end and the output end of the latch, and a clock gating technology is used at the output stage of the latch, so that the current competition of the output end is reduced, the delay overhead is reduced, and the extra power consumption of the output end due to the current competition is saved; the latch is constructed using a smaller number of transistors, effectively reducing area overhead.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention.
Detailed Description
As shown in fig. 1, an arbitrary three-node flip-flop fully tolerant latch comprises:
two memory modules, namely a first memory module DICE1 and a second memory module DICE2, each constructed with 4 pairs of PN transistors;
three C cells, a first C cell CE1, a second C cell CE2, and a third C cell CE3, wherein the third C cell CE3 has a clock control terminal;
five transmission gates, namely a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4 and a fifth transmission gate TG 5;
the first memory module DICE1 has a first signal input/output common terminal I1, a second signal input/output common terminal I3, a first internal node I2, and a second internal node I4; the second memory module DICE2 has a first signal input/output common terminal I5, a second signal input/output common terminal I7, a first internal node I6 and a second internal node I8; the first C cell CE1 is provided with a first signal input terminal, a second signal input terminal and a signal output terminal I9; the second C unit CE2 is provided with a first signal input terminal, a second signal input terminal and a signal output terminal I10; the third C unit CE3 is provided with a first signal input terminal, a second signal input terminal, a clock signal input terminal CLK, an inverted clock signal input terminal CLKB, and a signal output terminal Q;
a signal input end of the first transmission gate TG1, a signal input end of the second transmission gate TG2, a signal input end of the third transmission gate TG3, a signal input end of the fourth transmission gate TG4 and a signal input end of the fifth transmission gate TG5 are used as data input ends D of the latch;
a signal output end of the first transmission gate TG1 is connected with a first signal input and output common end I1 of the memory module DICE 1; a signal output end of the second transmission gate TG2 is connected to a second signal input/output common terminal I3 of the memory module DICE 1; a signal output end of the third transmission gate TG3 is connected to the first signal input/output common terminal I5 of the memory module DICE 2; a signal output end of the fourth transmission gate TG4 is connected to a second signal input/output common terminal I7 of the memory module DICE 2; a signal output terminal of the fifth transmission gate TG5 is connected to the signal output terminal Q of the third C cell CE 3;
a first signal input/output common terminal I1 of the first memory module DICE1 is connected to a first signal input terminal of the first C-cell CE 1; a second signal input/output common terminal I3 of the first memory module DICE1 is connected to a first signal input terminal of the second C-cell CE 2; a first signal input/output common terminal I5 of the second memory module DICE2 is connected to a second signal input terminal of the first C cell CE 1; a second signal input/output common terminal I7 of the second memory module DICE2 is connected to a second signal input terminal of the second C cell CE 2;
the signal output terminal I9 of the first C-cell CE1 is a first signal input terminal of the third C-cell CE 3; the signal output terminal I10 of the second C cell CE2 is a second signal input terminal of the third C cell CE3, the clock signal input terminal CLK of the third C cell CE3 is connected to the system clock CLK, and the inverted clock signal input terminal CLKB of the third C cell CE3 is connected to the inverted system clock CLKB; when CLK is 0 and CLKB is 1, the signal output Q of the third C unit CE3 serves as the data output Q of the latch; when CLK is equal to 1 and CLKB is equal to 0, the signal output terminal of the fifth transmission gate TG5 serves as the data output terminal Q of the latch.
As shown in fig. 1, the first storage module DICE1 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4; wherein:
the drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, the gate of the second PMOS transistor P2, and the gate of the fourth NMOS transistor N4 are connected, and the connection point is used as the first signal input/output common terminal I1 of the first memory module DICE 1;
the drain of the second PMOS transistor P2, the drain of the second NMOS transistor N2, the gate of the third PMOS transistor P3, and the gate of the first NMOS transistor N1 are connected, and the connection point is used as a first internal node I2 of the first memory module DICE 1;
a drain electrode of the third PMOS transistor P3, a drain electrode of the third NMOS transistor N3, a gate electrode of the fourth PMOS transistor P4, and a gate electrode of the second NMOS transistor N2 are connected, and a connection point is used as a second signal input/output common terminal I3 of the first memory module DICE 1;
a drain electrode of the fourth PMOS transistor P4, a drain electrode of the fourth NMOS transistor N4, a gate electrode of the first PMOS transistor P1, and a gate electrode of the third NMOS transistor N3 are connected, and a connection point is used as a second internal node I4 of the first memory module DICE 1;
the source electrodes and the substrates of the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 are all connected with a power supply VDD;
the sources and the substrates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 are all grounded GND.
As shown in fig. 1, the second storage module DICE2 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8; wherein:
a drain electrode of the fifth PMOS transistor P5, a drain electrode of the fifth NMOS transistor N5, a gate electrode of the sixth PMOS transistor P6, and a gate electrode of the eighth NMOS transistor N8 are connected, and a connection point is used as a first signal input/output common terminal I5 of the second memory module DICE 2;
a drain electrode of the sixth PMOS transistor P6, a drain electrode of the sixth NMOS transistor N6, a gate electrode of the seventh PMOS transistor P7, and a gate electrode of the fifth NMOS transistor N5 are connected, and a connection point is used as a first internal node I6 of the second memory module DICE 2;
a drain electrode of the seventh PMOS transistor P7, a drain electrode of the seventh NMOS transistor N7, a gate electrode of the eighth PMOS transistor P8, and a gate electrode of the sixth NMOS transistor N6 are connected, and a connection point is used as a second signal input/output common terminal I7 of the second memory module DICE 2;
the drain of the eighth PMOS transistor P8, the drain of the eighth NMOS transistor N8, the gate of the fifth PMOS transistor P5, and the gate of the seventh NMOS transistor N7 are connected, and the connection point is used as a second internal node I8 of the second memory module DICE 2;
the source electrodes and the substrates of the fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7 and the eighth PMOS tube P8 are all connected with a power supply VDD;
the sources and the substrates of the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are all grounded GND.
As shown in fig. 1, the first C unit CE1 is composed of two PMOS transistors P9 and a tenth PMOS transistor P10 and two NMOS transistors N9 and a tenth NMOS transistor N10; wherein:
the gate of the ninth PMOS transistor P9 is connected to the gate of the ninth NMOS transistor N9, and the connection point is the first signal input terminal of the first C unit CE 1; the gate of the tenth PMOS transistor P10 is connected to the gate of the tenth NMOS transistor N10, and the connection point is the second signal input terminal of the first C unit CE 1; the drain of the tenth PMOS transistor P10 is connected to the drain of the ninth NMOS transistor N9, and the connection point is the signal output terminal I9 of the first C cell CE 1;
the drain electrode of the ninth PMOS tube P9 is connected with the source electrode of the tenth PMOS tube P10; the source electrode of the ninth NMOS transistor N9 is connected with the drain electrode of the tenth NMOS transistor N10; the source electrode of the ninth PMOS tube P9, the substrate of the ninth PMOS tube P9 and the substrate of the tenth PMOS tube P10 are all connected with a power supply VDD; the substrate of the ninth NMOS transistor N9, the substrate of the tenth NMOS transistor N10, and the source of the tenth NMOS transistor N10 are all grounded.
As shown in fig. 1, the second C unit CE2 is composed of two PMOS transistors, an eleventh PMOS transistor P11 and a twelfth PMOS transistor P12, and two NMOS transistors, an eleventh NMOS transistor N11 and a twelfth NMOS transistor N12; wherein:
the gate of the eleventh PMOS transistor P11 is connected to the gate of the eleventh NMOS transistor N11, and the connection point is the first signal input end of the second C unit CE 2; the gate of the twelfth PMOS transistor P12 is connected to the gate of the twelfth NMOS transistor N12, and the connection point is the second signal input end of the second C unit CE 2; the drain of the twelfth PMOS transistor P12 is connected to the drain of the eleventh NMOS transistor N11, and the connection point is the signal output terminal I10 of the second C unit CE 2;
the drain electrode of the eleventh PMOS tube P11 is connected with the source electrode of the twelfth PMOS tube P12; the source electrode of the eleventh NMOS tube N11 is connected with the drain electrode of the twelfth NMOS tube N12; the source electrode of the eleventh PMOS tube P11, the substrate of the eleventh PMOS tube P11 and the substrate of the twelfth PMOS tube P12 are all connected with a power supply VDD; the substrate of the eleventh NMOS transistor N11, the substrate of the twelfth NMOS transistor N12 and the source of the twelfth NMOS transistor N12 are all grounded.
As shown in fig. 1, the third C unit CE3 is composed of three PMOS transistors and three NMOS transistors, where the three PMOS transistors are a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14 and a fifteenth PMOS transistor P15, and the three NMOS transistors are a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14 and a fifteenth NMOS transistor N15; wherein:
the gate of the fourteenth PMOS transistor P14 is connected to the gate of the thirteenth NMOS transistor N13, and the connection point is the first signal input terminal of the third C unit CE 3; the gate of the fifteenth PMOS transistor P15 is connected to the gate of the fourteenth NMOS transistor N14, and the connection point is the second signal input terminal of the third C unit CE 3; the gate of the thirteenth PMOS transistor P13 is connected to the system clock CLK; the gate of the fifteenth NMOS transistor N15 is connected to the inverted system clock CLKB; the drain of the fifteenth PMOS transistor P15 is connected to the drain of the thirteenth NMOS transistor N13, and the connection point is the signal output terminal Q of the third C unit CE 3;
the drain electrode of the thirteenth PMOS tube P13 is connected with the source electrode of the fourteenth PMOS tube P14; the drain electrode of the fourteenth PMOS tube P14 is connected with the source electrode of the fifteenth PMOS tube P15; the drain electrode of the fifteenth PMOS pipe P15 is connected with the drain electrode of the thirteenth NMOS pipe N13; the source electrode of the thirteenth NMOS tube N13 is connected with the drain electrode of the fourteenth NMOS tube N14; the source electrode of the fourteenth NMOS transistor N14 is connected with the drain electrode of the fifteenth NMOS transistor N15; the source electrode of the thirteenth PMOS tube P13, the substrate of the thirteenth PMOS tube P13, the substrate of the fourteenth PMOS tube P14 and the substrate of the fifteenth PMOS tube P15 are all connected with a power supply VDD; the substrate of the thirteenth NMOS transistor N13, the substrate of the fourteenth NMOS transistor N14, the substrate of the fifteenth NMOS transistor N15, and the source of the fifteenth NMOS transistor N15 are all grounded.
Table 1 truth tables for first C-cell CE1 and second C-cell CE2 are as follows:
Figure BDA0001912077490000101
table 1 above is a truth table for cell C. From the table, when the first signal input terminal and the second signal input terminal have the same logic value, the signal output terminal will output the opposite logic value to the input; when the first signal input end and the second signal input end have different logic values, the signal output end enters a holding state and outputs the logic value in the previous state. It can be seen that the first C cell CE1 and the second C cell CE2 can be used to shield the node from logic value inversion, i.e. prevent part of the logic value inversion from propagating to the signal output terminal.
TABLE 2 truth table for a clocked third C-cell CE3
Figure BDA0001912077490000102
Table 2 above is a truth table based on clocked C cells. As can be seen from the table, in the case where the clock signal input terminal CLK of the C-unit is 0 and the inverted clock signal input terminal CLKB is 1, note that the clock signal of the C-unit and the clock signal of the transmission gate are inverted, and when the first signal input terminal and the second signal input terminal have the same logic value, the signal output terminal will output the opposite logic value to the input; when the first signal input end and the second signal input end have different logic values, the signal output end enters a holding state and outputs the logic value in the previous state. When the clock signal input terminal CLK is equal to 1 and the inverted clock signal input terminal CLKB is equal to 0, the signal output terminal enters the hold state under the control of the clock signal, and outputs the logic value in the previous state. It can be seen that the clock-based third C cell CE3 can cooperate with the system clock to mask the node from logic value inversion, i.e., under the control of different system clock signals, it can still prevent the part of logic value inversion in the signal input terminal from propagating to the signal output terminal.
The normal operation of the latch proposed by the present invention is explained below.
When CLK is high and CLKB is low, the structure operates in the transparent mode. At this time, the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, the fourth transmission gate TG4, and the fifth transmission gate TG5 are turned on. For example, D ═ 1, i.e., D ═ I1 ═ I3 ═ I5 ═ I7 ═ 1. At this time, the NMOS transistors N2 and N4 in the first memory module DICE1 and the NMOS transistors N6 and N8 in the second memory module DICE2 are turned on, so that I2 ═ I4 ═ I6 ═ I8 ═ 0. That is, it can be determined that all the inputs of the first C cell CE1 and the second C cell CE2 are 1, and the outputs of the first C cell CE1 and the second C cell CE2 are 0. At this time, after the output signal 0 of the first C cell CE1 and the second C cell CE2 passes through the third C cell CE3, since the CLK terminal of the third C cell CE3 is at a high level and the CLKB terminal of the third C cell CE3 is at a low level, the third C cell CE3 does not output a 1. On the other hand, having turned on the fifth transfer gate TG5, Q is 1, i.e., Q is not driven by the output terminal of the third C-cell CE3 and the output terminal of the fifth transfer gate TG5 in common, but only by the output terminal of the fifth transfer gate TG 5. Therefore, current contention at the output of the latch is reduced, thereby reducing the D to Q propagation delay and saving circuit power consumption. The structure operates in the latch mode when CLK is low and CLKB is high. At this time, the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, the fourth transmission gate TG4, and the fifth transmission gate TG5 are all closed. Since the CLK terminal of the third C-cell CE3 is at a low level and the CLKB terminal of the third C-cell CE3 is at a high level, the third C-cell CE3 outputs the values stored in the first memory module die 1 and the second memory module die 2, i.e., Q is determined only by the output terminal of the third C-cell CE 3. Since the odd nodes of the first and second memory modules DICE1 and 2 feed back data to the even nodes and the even nodes feed back data to the odd nodes, several data feedback loops exist in the first and second memory modules DICE1 and 2 to ensure that the first and second memory modules DICE1 and 2 can effectively latch data. Since the two outputs of the first memory module DICE1 are fed back to one input of the first C-cell CE1 and the second C-cell CE2, respectively, the two outputs of the second memory module DICE2 are fed back to the other input of the first C-cell CE1 and the second C-cell CE2, respectively, and the outputs of the first C-cell CE1 and the second C-cell CE2 are fed back to the input of the third C-cell CE3, Q is able to output data stored in the first memory module DICE1 and the second memory module DICE 2.
The principle of the fault-tolerant operation of the latch proposed by the present invention is explained below.
In the following description, a logic value "1" is stored (i.e., Q — I1 — I3 — I5 — I7 — 1, I2 — I4 — I6 — I8 — 0 in the lockout mode). The situation is similar when storing a logical value of "0", limited to space, and omitted herein.
First, discussing the single-node flip case, since the first and second storage modules DICE1 and 2 are key modules for storing data, and the first and second storage modules DICE1 and 2 are symmetric, the key single-node sequence may consider only { I5, I6, I7, I8 }. Since the nodes in the first storage module DICE1 or the second storage module DICE2 are loop-fed, only one node has to be discussed for the fault-tolerant case of single-node inversion. Here, a single node inversion occurs at I6 as an example. When I6 is inverted, the temporary change of I6 from 0 to 1 will turn off the seventh PMOS transistor P7, but the value of I7 is not changed, so the sixth NMOS transistor N6 is still turned on, and the sixth NMOS transistor N6 outputs 0 to I6. On the other hand, when I6 is temporarily inverted to 1, since I8 is not affected by 0 (I7 is also not affected), the fifth PMOS transistor P5 is turned on, and the output of the fifth PMOS transistor P5 is stronger than that of I5 by 1. Meanwhile, the fifth NMOS transistor N5 is turned on temporarily due to the inversion of I6, which makes the output of the fifth NMOS transistor N5 weaker than I5. However, the strong 1 of I5 can neutralize the weak 0, so I5 is still the correct value 1, so that the sixth PMOS transistor P6 is still turned off. The sixth NMOS transistor N6 outputs 0 in I6, which makes it easy to know that I6 is restored to the correct original value of 0. When a single node flip occurs at a single node other than the first storage module DICE1 or the second storage module DICE2, the flipped node can be recovered since neither the first storage module DICE1 nor the second storage module DICE2 is affected. In summary, any single node of the latch can be self-restored by a single node flip. That is, the latch is single node flipped on line self-healing.
Next, a two-node flip (DNU) scenario is discussed, where there are six representative cases in the latch mode because the data state of any two nodes may flip: (1) the first storage module DICE1 or the second storage module DICE2 takes place internally in the DNU; (2) a node inside the first memory module DICE1 or the second memory module DICE2 and I9 or I10 are DNU-occurring simultaneously; (3) a node and Q concurrent DNU within the first storage module DICE1 or the second storage module DICE 2; (4) a node inside the first storage module DICE1 and a node inside the second storage module DICE2 are simultaneously DNU; (5) i9 and I10 were concurrent DNUs; (6) i9 or I10 and Q occur DNU simultaneously.
For the case (1), since the first storage module DICE1 and the second storage module DICE2 are symmetric, taking the node in the first storage module DICE1 as an example, the key node sequence of the first storage module DICE1 is { I1, I2, I3, I4}, so that there are cases where DNU occurs, C _4^2 in total, 6. If the distance between two nodes is expressed as N · L, the distance between any two nodes in the first storage module DICE1 may only be 1L, 2L, because the nodes inside the first storage module DICE1 are fed back circularly, for example, the distance from I1 to I4 is actually the distance from I4 to I1, which is not 3L but L. Thus, 2 exemplary DNU node pair sequences { < I1, I2>, < I1, I3> } may be chosen. Obviously, the distance between the respective two nodes in the sequence is 1L, 2L, respectively, and all other pairs of nodes in the latch are similar to one of the 2 node pairs described above, respectively. The fault-tolerant principle of the above exemplary DNU node pair sequence { < I1, I2>, < I1, I3> } is discussed below:
for the case of < I1, I2> flips, the following analysis is made: before < I1 and I2> are turned over, the values of I1 and I3 are 1, the values of I2 and I4 are 0, the first PMOS tube P1 and the third PMOS tube P3 are all conducted, the second NMOS tube N2 and the fourth NMOS tube N4 are all conducted, and other MOS tubes are not conducted. When the < I1, I2> flips, if the energy of the particles is large enough, i.e. I1 flips from 1 to 0 temporarily, I2 flips from 0 to 1 temporarily, it is obvious that the error value generated by the flipping of the < I1, I2> may only affect the second PMOS transistor P2 and the first NMOS transistor N1, i.e. does not affect the nodes I3, I4. Obviously, I4 still outputs 0, the first PMOS transistor P1 is still turned on, and therefore I1 outputs 1 (strong 1). Since I2 is temporarily inverted from 0 to 1, the first NMOS transistor N1 will be temporarily turned on, and I1 will output 0 (weak 0). But the strong 1 of I1 neutralizes the weak 0, so I1 is still correct (i.e., self-healing) and the second PMOS transistor P2 is turned off. Similarly, I3 still correctly turns on N2, and N2 outputs a stronger 0 than I2, and it is clear that the stronger 0 of I2 neutralizes the weaker 1 than I2 due to particle impact, so I2 is still correct (i.e. self-recovery). It follows that the first memory module DICE1 is able to self-restore from the DNU, and therefore the inputs of the first C-cell CE1 and the second C-cell CE2 are all correct, it is clear that Q still maintains the correct value, i.e. the latch is able to self-restore from the DNU.
For the case of < I1, I3> flips, the following analysis is made: before the inversion occurs, I1 and I3>, I1 ═ I3 ═ 1. When DNU occurs in < I1, I3>, if the particle energy is large enough, I1 and I3 flip from 1 to 0, the second PMOS transistor P2 and the fourth PMOS transistor P4 are turned on and the second NMOS transistor N2 and the fourth NMOS transistor N4 are turned off. Therefore, I2 and I4 are flipped and kept at 1, so that the first PMOS transistor P1 and the third PMOS transistor P3 are turned off, and it is obvious that I1 and I3 can only keep the flipped values, that is, all nodes inside the first memory module die 1 are flipped all over. The case where a double-dot flip results in all node flips is defined herein as the worst case of the storage module DICE for subsequent use. It can be seen that both the first C cell CE1 and the second C cell CE2 have only one input toggle. Due to the filtering effect of the first C cell CE1 and the second C cell CE2 on errors, I9 and I10 are still at the original values, and it is clear that Q still maintains the correct value, i.e., the latch is DNU tolerant for the case of (1).
For the cases (2) - (4), it has been discussed that any single point in the first and second storage modules DICE1, 2 may be self-recovering, and the output of the first and second storage modules DICE1, 2 is not changed, i.e., the first and second C-cells CE1, CE2 are input with logical values. It can be seen that the first memory module DICE1 and the second memory module DICE2 feed back the correct data to the respective C-cells, regardless of whether I9, I10 or Q is affected. Obviously, the latch is self-recovering from the DNU for both cases (2) - (4).
For the cases (5) - (6), since the first storage module DICE1 and the second storage module DICE2 are not flipped, correct data will be fed back to the respective C-cells. Obviously, the latch is self-recovering from the DNU for both cases (5) - (6).
Finally, the case of internal three-node rollover (TNU) is discussed. In the latch mode, since the data states of any three internal nodes may flip, it is analyzed that ten representative situations are included: (1) TNU occurs internally in the first memory module DICE1 or in the second memory module DICE 2; (2) two nodes inside the first storage module DICE1 and one node inside the second storage module DICE2 occur TNU simultaneously; (3) two nodes inside the first storage module DICE1 and I9 occur TNU simultaneously; (4) two nodes inside the first storage module DICE1 and I10 occur TNU simultaneously; (5) two nodes inside the first storage module DICE1 and Q occur TNU simultaneously; (6) a node inside the first memory module DICE1 and a node inside the second memory module DICE2 are TNU-concurrent with I9 or I10; (7) a node inside the first storage module DICE1 and a node inside the second storage module DICE2 and Q occur simultaneously TNU; (8) one node inside the first storage module DICE1 and the I9 and I10 concurrent TNU; (9) a node inside the first storage module DICE1 and I9 or I10 and Q occur TNU simultaneously; (10) TNU occurred simultaneously for I9 and I10 and Q.
For the case of (1), since the first storage module DICE1 and the second storage module DICE2 are symmetrical, take three nodes in the first storage module DICE1 as an example. As will be appreciated, taking three nodes from the first storage module DICE1 is equivalent to removing a single node from its four nodes, which are circularly symmetric. Thus, an exemplary TNU sequence < I1, I2, I3> was selected. The following analyses were carried out for the case where < I1, I2, I3> developed TNU: when I1 and I3 are inverted from 1 to 0, I2 is inverted from 0 to 1, so the fourth PMOS transistor P4 is turned on, and the fourth NMOS transistor N4 is turned off, so I4 is inverted to 1. It is clear that I1, I2, I3 can only be kept at flipped values. In addition, as can be seen from the above discussion, the flip of < I1, I3> results in the entire flip of the internal nodes of the first memory module die 1, i.e. the worst case of the memory module die. It can be seen that the set of inputs of both the first C-cell CE1 and the second C-cell CE2 are flipped. However, the second storage module DICE2 is not affected, and the other set of inputs of the first C-cell CE1 and the second C-cell CE2 still maintains the original values, and therefore I9 and I10 are still correct, and it is clear that Q still maintains the correct value, i.e. the latch is tolerant to the TNU.
For the cases (2) to (5), the following analysis was performed: the worst case of the storage module DICE occurs because of the flipping of two nodes inside the first storage module DICE1, so that one set of inputs of both the first C-cell CE1 and the second C-cell CE2 flip. However, whether the third node is tied to the second memory module DICE2 or to I9 or I10 or Q, it is clear that the output of the second memory module DICE2 will be the correct value, so the other set of inputs of the first C-cell CE1 and the second C-cell CE2 still maintain the original value, so I9 and I10 are still correct, and it is clear that Q still maintains the correct value, i.e. the latch is tolerant of the TNU.
For the remaining cases, the following analysis is performed: since the single-node flip self-recovery of the first and second storage modules DICE1 and 2 results in that the inputs of the first and second C-cells CE1 and CE2 will keep the original values, and therefore, the first and second C-cells CE1 and CE2 will output the correct values regardless of whether I9, I10 or Q is flipped, and obviously, the latch can tolerate the TNU and is completely self-recovery.
In summary, the present invention provides a latch design scheme that is fully tolerant of any three-node flip (let alone two-node flip and single-node flip), thereby improving the reliability of the latch circuit. Meanwhile, the output stage C unit uses a clock control technology, and a high-speed path technology is used on a path from the input end to the output end, so that current competition of the output end is effectively avoided, extra power consumption caused by the current competition is avoided, and data propagation delay from the input end to the output end is reduced. Furthermore, circuit area overhead is reduced due to the use of a smaller number of crystals. The invention can be effectively applied to integrated circuits and systems with high reliability and low overhead requirements, and can be widely applied to the field of radiation-resistant reinforcement design with higher requirements on the reliability and the overhead of latches, such as aerospace and the like.
It will be appreciated by those skilled in the art that the foregoing is only a preferred embodiment of the invention, and is not intended to limit the invention, which is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims (6)

1. An arbitrary three-node flip fully tolerant latch characterized by: the method comprises the following steps:
two memory modules, namely a first memory module DICE1 and a second memory module DICE2, each constructed with 4 pairs of PN transistors;
three C cells, i.e., a first C cell CE1, a second C cell CE2, and a third C cell CE3, wherein the third C cell CE3 has a clock control terminal;
five transmission gates, i.e., a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, and a fifth transmission gate TG 5;
the first memory module DICE1 has a first signal input/output common terminal I1, a second signal input/output common terminal I3, a first internal node I2, and a second internal node I4; the second memory module DICE2 has a first signal input/output common terminal I5, a second signal input/output common terminal I7, a first internal node I6, and a second internal node I8; the first C cell CE1 is provided with a first signal input terminal, a second signal input terminal and a signal output terminal I9; the second C unit CE2 is provided with a first signal input terminal, a second signal input terminal and a signal output terminal I10; the third C unit CE3 is provided with a first signal input terminal, a second signal input terminal, a clock signal input terminal CLK, an inverted clock signal input terminal CLKB, and a signal output terminal Q;
a signal input end of the first transmission gate TG1, a signal input end of the second transmission gate TG2, a signal input end of the third transmission gate TG3, a signal input end of the fourth transmission gate TG4 and a signal input end of the fifth transmission gate TG5 are used as data input ends D of the latch;
the signal output end of the first transmission gate TG1 is connected to the first signal input/output common terminal I1 of the memory module DICE 1; a signal output end of the second transmission gate TG2 is connected to a second signal input/output common terminal I3 of the memory module DICE 1; a signal output end of the third transmission gate TG3 is connected to the first signal input/output common terminal I5 of the memory module DICE 2; a signal output end of the fourth transmission gate TG4 is connected to a second signal input/output common terminal I7 of the memory module DICE 2; a signal output terminal of the fifth transmission gate TG5 is connected to the signal output terminal Q of the third C cell CE 3;
a first signal input/output common terminal I1 of the first memory module DICE1 is connected to a first signal input terminal of the first C-cell CE 1; a second signal input/output common terminal I3 of the first memory module DICE1 is connected to a first signal input terminal of the second C-cell CE 2; a first signal input/output common terminal I5 of the second memory module DICE2 is connected to a second signal input terminal of the first C-cell CE 1; a second signal input/output common terminal I7 of the second memory module DICE2 is connected to a second signal input terminal of the second C cell CE 2;
the signal output terminal I9 of the first C-cell CE1 is a first signal input terminal of the third C-cell CE 3; the signal output terminal I10 of the second C cell CE2 is a second signal input terminal of the third C cell CE3, the clock signal input terminal CLK of the third C cell CE3 is connected to the system clock CLK, and the inverted clock signal input terminal CLKB of the third C cell CE3 is connected to the inverted system clock CLKB; when CLK is 0 and CLKB is 1, the signal output Q of the third C unit CE3 serves as the data output Q of the latch; when CLK is equal to 1 and CLKB is equal to 0, the signal output terminal of the fifth transmission gate TG5 serves as the data output terminal Q of the latch.
2. The latch of claim 1 that is fully tolerant of any three-node flip, wherein: the first storage module DICE1 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4; wherein:
the drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, the gate of the second PMOS transistor P2, and the gate of the fourth NMOS transistor N4 are connected, and the connection point is used as the first signal input/output common terminal I1 of the first memory module DICE 1;
the drain of the second PMOS transistor P2, the drain of the second NMOS transistor N2, the gate of the third PMOS transistor P3, and the gate of the first NMOS transistor N1 are connected, and the connection point is used as a first internal node I2 of the first memory module DICE 1;
a drain electrode of the third PMOS transistor P3, a drain electrode of the third NMOS transistor N3, a gate electrode of the fourth PMOS transistor P4, and a gate electrode of the second NMOS transistor N2 are connected, and a connection point is used as a second signal input/output common terminal I3 of the first memory module DICE 1;
a drain electrode of the fourth PMOS transistor P4, a drain electrode of the fourth NMOS transistor N4, a gate electrode of the first PMOS transistor P1, and a gate electrode of the third NMOS transistor N3 are connected, and a connection point is used as a second internal node I4 of the first memory module DICE 1;
the source electrodes and the substrates of the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 are all connected with a power supply VDD;
the sources and the substrates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 are all grounded GND.
3. The latch of claim 1 that is fully tolerant of any three-node flip, wherein: the second storage module DICE2 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8; wherein:
a drain electrode of the fifth PMOS transistor P5, a drain electrode of the fifth NMOS transistor N5, a gate electrode of the sixth PMOS transistor P6, and a gate electrode of the eighth NMOS transistor N8 are connected, and a connection point is used as a first signal input/output common terminal I5 of the second memory module DICE 2;
a drain electrode of the sixth PMOS transistor P6, a drain electrode of the sixth NMOS transistor N6, a gate electrode of the seventh PMOS transistor P7, and a gate electrode of the fifth NMOS transistor N5 are connected, and a connection point is used as a first internal node I6 of the second memory module DICE 2;
a drain electrode of the seventh PMOS transistor P7, a drain electrode of the seventh NMOS transistor N7, a gate electrode of the eighth PMOS transistor P8, and a gate electrode of the sixth NMOS transistor N6 are connected, and a connection point is used as a second signal input/output common terminal I7 of the second memory module DICE 2;
a drain electrode of the eighth PMOS transistor P8, a drain electrode of the eighth NMOS transistor N8, a gate electrode of the fifth PMOS transistor P5, and a gate electrode of the seventh NMOS transistor N7 are connected, and a connection point is used as a second internal node I8 of the second memory module DICE 2;
the source electrodes and the substrates of the fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7 and the eighth PMOS tube P8 are all connected with a power supply VDD;
the sources and the substrates of the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are all grounded GND.
4. The latch of claim 1 that is fully tolerant of any three-node flip, wherein: the first C unit CE1 is composed of two PMOS transistors P9 and a tenth PMOS transistor P10, and two NMOS transistors N9 and a tenth NMOS transistor N10; wherein:
the gate of the ninth PMOS transistor P9 is connected to the gate of the ninth NMOS transistor N9, and the connection point is the first signal input terminal of the first C unit CE 1; the gate of the tenth PMOS transistor P10 is connected to the gate of the tenth NMOS transistor N10, and the connection point is the second signal input end of the first C unit CE 1; the drain of the tenth PMOS transistor P10 is connected to the drain of the ninth NMOS transistor N9, and the connection point is the signal output terminal I9 of the first C unit CE 1;
the drain electrode of the ninth PMOS tube P9 is connected with the source electrode of the tenth PMOS tube P10; the source electrode of the ninth NMOS transistor N9 is connected with the drain electrode of the tenth NMOS transistor N10; the source electrode of the ninth PMOS tube P9, the substrate of the ninth PMOS tube P9 and the substrate of the tenth PMOS tube P10 are all connected with a power supply VDD; the substrate of the ninth NMOS transistor N9, the substrate of the tenth NMOS transistor N10, and the source of the tenth NMOS transistor N10 are all grounded.
5. The latch of claim 1 that is fully tolerant of any three-node flip, wherein: the second C unit CE2 is composed of two PMOS transistors P11 and a twelfth PMOS transistor P12, and two NMOS transistors N11 and a twelfth NMOS transistor N12; wherein:
the gate of the eleventh PMOS transistor P11 is connected to the gate of the eleventh NMOS transistor N11, and the connection point is the first signal input end of the second C unit CE 2; the gate of the twelfth PMOS transistor P12 is connected to the gate of the twelfth NMOS transistor N12, and the connection point is the second signal input end of the second C unit CE 2; the drain of the twelfth PMOS tube P12 is connected to the drain of the eleventh NMOS tube N11, and the connection point is the signal output end I10 of the second C unit CE 2;
the drain electrode of the eleventh PMOS tube P11 is connected with the source electrode of the twelfth PMOS tube P12; the source electrode of the eleventh NMOS tube N11 is connected with the drain electrode of the twelfth NMOS tube N12; the source electrode of the eleventh PMOS tube P11, the substrate of the eleventh PMOS tube P11 and the substrate of the twelfth PMOS tube P12 are all connected with a power supply VDD; the substrate of the eleventh NMOS transistor N11, the substrate of the twelfth NMOS transistor N12 and the source of the twelfth NMOS transistor N12 are all grounded.
6. The latch of claim 1 that is fully tolerant of any three-node flip, wherein: the third C unit CE3 is composed of three PMOS transistors P13, a fourteenth PMOS transistor P14 and a fifteenth PMOS transistor P15, and three NMOS transistors N13, a fourteenth NMOS transistor N14 and a fifteenth NMOS transistor N15; wherein:
the gate of the fourteenth PMOS transistor P14 is connected to the gate of the thirteenth NMOS transistor N13, and the connection point is the first signal input terminal of the third C unit CE 3; the gate of the fifteenth PMOS transistor P15 is connected to the gate of the fourteenth NMOS transistor N14, and the connection point is the second signal input end of the third C unit CE 3; the grid electrode of the thirteenth PMOS pipe P13 is connected with the system clock CLK; the gate of the fifteenth NMOS transistor N15 is connected to the inverted system clock CLKB; the drain of the fifteenth PMOS transistor P15 is connected to the drain of the thirteenth NMOS transistor N13, and the connection point is the signal output terminal Q of the third C unit CE 3;
the drain electrode of the thirteenth PMOS tube P13 is connected with the source electrode of the fourteenth PMOS tube P14; the drain electrode of the fourteenth PMOS tube P14 is connected with the source electrode of the fifteenth PMOS tube P15; the drain electrode of the fifteenth PMOS pipe P15 is connected with the drain electrode of the thirteenth NMOS pipe N13; the source of the thirteenth NMOS transistor N13 is connected to the drain of the fourteenth NMOS transistor N14; the source electrode of the fourteenth NMOS transistor N14 is connected with the drain electrode of the fifteenth NMOS transistor N15; the source electrode of the thirteenth PMOS tube P13, the substrate of the thirteenth PMOS tube P13, the substrate of the fourteenth PMOS tube P14 and the substrate of the fifteenth PMOS tube P15 are all connected with a power supply VDD; the substrate of the thirteenth NMOS transistor N13, the substrate of the fourteenth NMOS transistor N14, the substrate of the fifteenth NMOS transistor N15 and the source of the fifteenth NMOS transistor N15 are all grounded.
CN201811556555.9A 2018-12-19 2018-12-19 Latch completely tolerating any three-node overturning Active CN109687850B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811556555.9A CN109687850B (en) 2018-12-19 2018-12-19 Latch completely tolerating any three-node overturning

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811556555.9A CN109687850B (en) 2018-12-19 2018-12-19 Latch completely tolerating any three-node overturning

Publications (2)

Publication Number Publication Date
CN109687850A CN109687850A (en) 2019-04-26
CN109687850B true CN109687850B (en) 2022-09-23

Family

ID=66186353

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811556555.9A Active CN109687850B (en) 2018-12-19 2018-12-19 Latch completely tolerating any three-node overturning

Country Status (1)

Country Link
CN (1) CN109687850B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110572146B (en) * 2019-08-29 2022-10-14 安徽大学 Latch capable of tolerating any three-node turnover and filtering transient pulse
CN110912551A (en) * 2019-12-09 2020-03-24 合肥工业大学 Single-particle three-point upset reinforced latch based on DICE unit
CN111211769B (en) * 2020-01-08 2023-04-25 中国人民武装警察部队海警学院 Latch capable of resisting single event upset and data trigger
CN111162772B (en) * 2020-01-15 2022-09-20 合肥工业大学 High-performance low-overhead three-point flip self-recovery latch
CN111223503B (en) * 2020-03-11 2021-10-01 河海大学常州校区 Double-node single-particle upset immune memory cell and latch
CN114900176B (en) * 2022-05-11 2024-03-05 合肥工业大学 Three-point flip self-recovery latch based on heterogeneous C unit

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013201770A (en) * 2013-05-24 2013-10-03 Japan Aerospace Exploration Agency Latch circuit with resistance to single event
US8773929B1 (en) * 2008-03-11 2014-07-08 Xilinx, Inc. Single-event-upset resistant memory cell with triple well
CN104852722A (en) * 2015-06-04 2015-08-19 合肥工业大学 Self-recovery latch register for preventing single event upset
CN104901676A (en) * 2015-06-06 2015-09-09 合肥工业大学 Latch resistant to single-particle multi-node overturning
CN105577161A (en) * 2015-12-21 2016-05-11 合肥工业大学 Single particle resistance multi-node overturning reinforcement latch register based on dual modular redundancy
CN106505976A (en) * 2017-01-12 2017-03-15 深圳大学 A kind of primary particle inversion resistant d type flip flop
CN106788379A (en) * 2016-11-29 2017-05-31 合肥工业大学 A kind of radiation hardening latch based on isomery duplication redundancy
CN108134597A (en) * 2018-01-08 2018-06-08 安徽大学 A kind of completely immune latch of three internal nodes overturning

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4332652B2 (en) * 2005-12-12 2009-09-16 独立行政法人 宇宙航空研究開発機構 Single event resistant latch circuit and flip-flop circuit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8773929B1 (en) * 2008-03-11 2014-07-08 Xilinx, Inc. Single-event-upset resistant memory cell with triple well
JP2013201770A (en) * 2013-05-24 2013-10-03 Japan Aerospace Exploration Agency Latch circuit with resistance to single event
CN104852722A (en) * 2015-06-04 2015-08-19 合肥工业大学 Self-recovery latch register for preventing single event upset
CN104901676A (en) * 2015-06-06 2015-09-09 合肥工业大学 Latch resistant to single-particle multi-node overturning
CN105577161A (en) * 2015-12-21 2016-05-11 合肥工业大学 Single particle resistance multi-node overturning reinforcement latch register based on dual modular redundancy
CN106788379A (en) * 2016-11-29 2017-05-31 合肥工业大学 A kind of radiation hardening latch based on isomery duplication redundancy
CN106505976A (en) * 2017-01-12 2017-03-15 深圳大学 A kind of primary particle inversion resistant d type flip flop
CN108134597A (en) * 2018-01-08 2018-06-08 安徽大学 A kind of completely immune latch of three internal nodes overturning

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
一种新颖的双节点翻转自恢复的抗辐射加固锁存器;闫爱斌;《Journal of Southeast University（English Edition）》;20180630;第34卷(第2期);182-186 *

Also Published As

Publication number Publication date
CN109687850A (en) 2019-04-26

Similar Documents

Publication Publication Date Title
CN109687850B (en) Latch completely tolerating any three-node overturning
CN108134597B (en) Latch with three internal nodes completely immune in overturning
CN108011628B (en) Latch capable of tolerating three-node turnover
CN109905117B (en) Latch capable of completely self-recovering by overturning any three nodes
CN106788379B (en) A kind of radiation hardening latch based on isomery duplication redundancy
US8324951B1 (en) Dual data rate flip-flop circuit
CN103633990B (en) A kind of anti-single particle upset and the adjustable latch of transient effect time delay
CN103326711A (en) Anti-radiation hardening latch based on TMR and DICE
CN110572146B (en) Latch capable of tolerating any three-node turnover and filtering transient pulse
CN109547006B (en) Anti-radiation D latch
CN111988030B (en) Single-particle three-point overturning reinforced latch
CN111162772B (en) High-performance low-overhead three-point flip self-recovery latch
CN114337611A (en) Three-node overturning self-recovery latch based on cyclic feedback C unit
CN109525236B (en) D latch resistant to double-node overturning
CN110518904B (en) N-1 level fault filtering voter
CN111223503B (en) Double-node single-particle upset immune memory cell and latch
CN107332552B (en) Tolerant double-point flip latch based on double-input phase inverter
CN111162771A (en) Small-sized double-node-overturn-resistant D latch
CN111193504A (en) Three-node fault-tolerant stacked D latch for low-power-consumption circuit application
CN112260679B (en) Three-node overturning self-recovery latch based on C unit
CN115800990A (en) Double-node overturning self-recovery latch based on seven C units
KR102635205B1 (en) Radiaion-resilent latch circuit and memory cell with stacked transistors
CN116614110A (en) Four-node overturning-resistant latch circuit and module based on reinforcement technology
CN117176112A (en) Low-overhead anti-double-node flip latch circuit
CN115967393A (en) Latch capable of tolerating three-node turnover

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant