CN108134597B

CN108134597B - Latch with three internal nodes completely immune in overturning

Info

Publication number: CN108134597B
Application number: CN201810015566.XA
Authority: CN
Inventors: 闫爱斌; 吴珍; 凌亚飞; 杨康; 崔杰; 陈志立
Original assignee: Anhui University
Current assignee: Anhui University
Priority date: 2018-01-08
Filing date: 2018-01-08
Publication date: 2021-05-25
Anticipated expiration: 2038-01-08
Also published as: CN108134597A

Abstract

The invention provides a latch with complete immunity by three internal node overturn.A storage module is constructed by eight pairs of PN transistors to realize a reliable data storage feedback loop, and then the storage module is fed back to a four-input C unit, thereby not only realizing complete tolerance to double node overturn, but also realizing the complete tolerance (immunity) function of three internal node overturn. On the other hand, the circuit area overhead, the delay overhead and the power consumption overhead are reduced because a smaller number of transistors and high-speed path technology are used and a transmission gate is inserted in the output stage, thereby avoiding current competition. The invention can be effectively applied to integrated circuits and systems with high reliability requirements, and can be widely applied to the fields of aerospace and the like with high requirements on the reliability and the overhead of the latch.

Description

Latch with three internal nodes completely immune in overturning

Technical Field

The invention belongs to the technical field of multi-node overturning resistant reinforcement fault-tolerant design of an integrated circuit, and particularly relates to a latch with three internal nodes completely immune to overturning.

Background

With the rapid development of semiconductor technology, the fabrication process of integrated circuits has gone from ultra-deep sub-micron scale to nano-scale. The amount of charge stored in the circuit nodes is also getting smaller and smaller due to the reduction of the supply voltage and the node capacitance. When an energetic particle such as a neutron or proton strikes a sensitive node of the memory cell, the amount of charge (critical charge) required to cause the logic state of the circuit node to flip is also reduced. Soft errors are a significant cause of failure of integrated circuits. In a strongly radiated environment, multi-node flipping induced by particles striking circuit nodes under a charge sharing mechanism is a typical soft error. The multi-node upset caused by particle impact is becoming increasingly non-negligible.

A latch is a pulse level sensitive circuit of a memory cell that changes state under a specific input pulse level. Statistical data have shown that under nano-technology, especially in a strong radiation environment, multi-node flipping has become a major problem affecting the reliability design of latch circuits. For a latch circuit which works in a strong radiation environment with a large number of high-energy particles and cosmic rays for a long time, the single-particle upset reinforcement design is not sufficient, and a multi-node upset reinforcement design must be carried out on the latch circuit.

At present, the multi-node overturning resistant reinforcement design aiming at the latch mainly has the following problems: firstly, double-node inversion cannot be effectively tolerated, namely, a fragile node pair exists, and when each node in the node pair is inverted, the output of the latch is kept to be a wrong logic value; secondly, the simultaneous turning of three nodes in the latch cannot be completely tolerated, namely a fragile node sequence exists, and when three nodes are turned simultaneously, the output end of the latch can output wrong logic values; thirdly, the overhead (such as area, power consumption and the like) of the latch capable of tolerating multi-node upset is large.

Disclosure of Invention

In order to overcome the defects of the existing multi-node-overturn-resisting reinforced latch structure, the invention provides a latch circuit design scheme capable of tolerating three-node overturn, a high-reliability data storage module is constructed by eight pairs of mutually-fed PN transistors, and a four-input C unit is used in an output stage to realize the immune function of three-node overturn. Meanwhile, the high-speed path is used for reducing the delay overhead of the latch and reducing the current competition at the output end of the latch, thereby saving part of the power consumption of the circuit. The latch provided by the invention can be widely applied to various fields with higher requirements on reliability and expenditure.

The invention is realized by the following technical scheme:

a three internal node flip fully immune latch comprising: the circuit comprises a storage module, a C unit and six transmission gates, wherein the storage module is constructed by 8 pairs of PN transistors; the storage module is provided with a first signal input end, a second signal input end, a third signal input end, a fourth signal input end, a first signal output end, a second signal output end, a third signal output end and a fourth signal output end; the unit C is provided with a first signal input end, a second signal input end, a third signal input end, a fourth signal input end and a signal output end.

Wherein, six transmission gates are respectively the same clock: the first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate, the fifth transmission gate and the sixth transmission gate.

And the signal input end of the first transmission gate, the signal input end of the second transmission gate, the signal input end of the third transmission gate, the signal input end of the fourth transmission gate and the signal input end of the fifth transmission gate are connected, and the connection point is used as the data input end of the latch.

The signal output end of the first transmission gate is connected with the first signal input end of the storage module; the signal output end of the second transmission gate is connected with the second signal input end of the storage module; the signal output end of the third transmission gate is connected with the third signal input end of the storage module; and the signal output end of the fourth transmission gate is connected with the fourth signal input end of the storage module.

A first signal output end of the storage module is connected with a first signal input end of the C unit; a second signal output end of the storage module is connected with a second signal input end of the C unit; a third signal output end of the storage module is connected with a third signal input end of the C unit; and a fourth signal output end of the storage module is connected with a fourth signal input end of the C unit. And the signal output end of the C unit is connected with the signal input end of the sixth transmission gate.

And the signal output end of the fifth transmission gate is connected with the signal output end of the sixth transmission gate, and the connection point is used as the data output end of the latch.

Compared with the prior art, the invention has the beneficial effects that:

(1) a storage module is constructed by eight groups of PN transistor pairs, a reliable data storage feedback loop is realized, and the storage module is fed back to a four-input C unit, so that complete tolerance to double-node overturning is realized, and complete tolerance (immunity) function of three internal node overturning is realized.

(2) The overhead such as delay and area is low. Delay is reduced through a high-speed path, and circuit performance is improved; the current competition of an output end is reduced by using a transmission gate at an output stage, and the power consumption expense is reduced; the construction is performed with a smaller number of transistors, reducing area overhead.

Drawings

Fig. 1 is a schematic diagram of a latch circuit with three internal node flip complete immunity provided in embodiment 1.

Fig. 2 is a schematic circuit diagram of a memory module (MCell).

Fig. 3 is a circuit schematic of a four input C cell.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

Example 1:

as shown in fig. 1, a latch with three internal node flips full immunity includes: the memory module comprises a memory module MCell constructed by 8 pairs of PN transistors, a C unit and six transmission gates; the memory module MCell is provided with a first signal input terminal I2, a second signal input terminal I4, a third signal input terminal I6, a fourth signal input terminal I8, a first signal output terminal I1, a second signal output terminal I3, a third signal output terminal I5 and a fourth signal output terminal I7; the unit C is provided with a first signal input end, a second signal input end, a third signal input end, a fourth signal input end and a signal output end. Wherein, six transmission gates are respectively the same clock: the transmission device comprises a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, a fifth transmission gate TG5 and a sixth transmission gate TG 6.

The signal input terminal of the first transmission gate TG1, the signal input terminal of the second transmission gate TG2, the signal input terminal of the third transmission gate TG3, the signal input terminal of the fourth transmission gate TG4 and the signal input terminal of the fifth transmission gate TG5 are connected, and the connection point serves as the data input terminal of the latch.

The signal output end of the first transmission gate TG1 is connected with a first signal input end I2 of the memory module MCell; the signal output end of the second transmission gate TG2 is connected with a second signal input end I4 of the memory module MCell; the signal output end of the third transmission gate TG3 is connected with a third signal input end I6 of the memory module MCell; a signal output of the fourth transmission gate TG4 is connected to a fourth signal input I8 of the memory module MCell.

A first signal output terminal I1 of the memory module MCell is connected to a first signal input terminal of the C cell; a second signal output end I3 of the memory module MCell is connected with a second signal input end of the C unit; a third signal output end I5 of the memory module MCell is connected with a third signal input end of the C unit; the fourth signal output I7 of the memory module MCell is connected to the fourth signal input of the C cell.

The signal output of the C-cell is connected to the signal input of the sixth transmission gate TG 6.

The signal output terminal of the fifth transmission gate TG5 is connected to the signal output terminal of the sixth transmission gate TG6, and the connection point serves as the data output terminal of the latch.

As shown in fig. 2, the specific structure of the memory module MCell is as follows: the method comprises the following steps: a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8.

Wherein:

the drain of the first PMOS transistor P1, the drain of the first NMOS transistor N1, the gate of the eighth PMOS transistor P8, and the gate of the second NMOS transistor N2 are connected, and the connection point is used as the first signal output terminal I1 of the memory module MCell.

The drain of the second PMOS transistor P2, the drain of the second NMOS transistor N2, the gate of the first PMOS transistor P1, and the gate of the third NMOS transistor N3 are connected, and the connection point is used as the first signal input terminal I2 of the memory module MCell.

The drain of the third PMOS transistor P3, the drain of the third NMOS transistor N3, the gate of the second PMOS transistor P2, and the gate of the fourth NMOS transistor N4 are connected, and the connection point is used as the second signal output terminal I3 of the memory module MCell.

The drain of the fourth PMOS transistor P4, the drain of the fourth NMOS transistor N4, the gate of the third PMOS transistor P3, and the gate of the fifth NMOS transistor N5 are connected, and the connection point is used as the second signal input terminal I4 of the memory module MCell.

The drain of the fifth PMOS transistor P5, the drain of the fifth NMOS transistor N5, the gate of the fourth PMOS transistor P4, and the gate of the sixth NMOS transistor N6 are connected, and the connection point is used as the third signal output terminal I5 of the memory module MCell.

The drain of the sixth PMOS transistor P6, the drain of the sixth NMOS transistor N6, the gate of the fifth PMOS transistor P5, and the gate of the seventh NMOS transistor N7 are connected, and the connection point is used as the third signal input terminal I6 of the memory module MCell.

The drain of the seventh PMOS transistor P7, the drain of the seventh NMOS transistor N7, the gate of the sixth PMOS transistor P6, and the gate of the eighth NMOS transistor N8 are connected, and the connection point is used as the fourth signal output terminal I7 of the memory module MCell.

The drain of the eighth PMOS transistor P8, the drain of the eighth NMOS transistor N8, the gate of the seventh PMOS transistor P7, and the gate of the first NMOS transistor N1 are connected, and the connection point is used as the fourth signal input terminal I8 of the memory module MCell.

The source electrodes and the substrates of the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the seventh PMOS tube P7 and the eighth PMOS tube P8 are all connected with a power supply VDD.

The source electrodes and the substrate of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are all grounded GND.

As shown in fig. 3, the specific structure of the C unit CE is as follows: the method comprises the following steps: four PMOS tubes and four NMOS tubes; the four PMOS tubes are respectively a ninth PMOS tube MP1, a tenth PMOS tube MP2, an eleventh PMOS tube MP3 and a twelfth PMOS tube MP4, and the four NMOS tubes are respectively a ninth NMOS tube MN1, a tenth NMOS tube MN2, an eleventh NMOS tube MN3 and a twelfth NMOS tube MN 4; wherein:

the grid electrode of the twelfth PMOS tube MP4 is connected with the grid electrode of the twelfth NMOS tube MN4, and the connection point is the first signal input end of the C unit; the grid electrode of the eleventh PMOS tube MP3 is connected with the grid electrode of the eleventh NMOS tube MN3, and the connection point is the second signal input end of the C unit; the grid electrode of the tenth PMOS tube MP2 is connected with the grid electrode of the tenth NMOS tube MN2, and the connection point is the third signal input end of the C unit; the grid electrode of the ninth PMOS tube MP1 is connected with the grid electrode of the ninth NMOS tube MN1, and the connection point is the fourth signal input end of the C unit; the drain electrode of the twelfth PMOS tube MP4 is connected with the drain electrode of the ninth NMOS tube MN1, and the connection point is the signal output end of the C unit; the drain electrode of the ninth PMOS transistor MP1 is connected to the source electrode of the tenth PMOS transistor MP 2; the drain electrode of the tenth PMOS transistor MP2 is connected to the source electrode of the eleventh PMOS transistor MP 3; the drain electrode of the eleventh PMOS tube MP3 is connected with the source electrode of the twelfth PMOS tube MP 4; the source electrode of the ninth NMOS transistor MN1 is connected with the drain electrode of the tenth NMOS transistor MN 2; the source electrode of the tenth NMOS transistor MN2 is connected with the drain electrode of the eleventh NMOS transistor MN 3; the source electrode of the eleventh NMOS transistor MN3 is connected with the drain electrode of the twelfth NMOS transistor MN 4; the source electrode of the ninth PMOS tube MP1, the substrate of the ninth PMOS tube MP1, the substrate of the tenth PMOS tube MP2, the substrate of the eleventh PMOS tube MP3 and the substrate of the twelfth PMOS tube MP4 are all connected with a power supply VDD; the substrate of the ninth NMOS transistor MN1, the substrate of the tenth NMOS transistor MN2, the substrate of the eleventh NMOS transistor MN3, the substrate of the twelfth NMOS transistor MN4 and the source of the twelfth NMOS transistor MN4 are all grounded.

Truth table of Table 1C cell

Table 1 above is a truth table for cell C. From this table, when the logic values of the first signal input terminal I1, the second signal input terminal I3, the third signal input terminal I5 and the fourth signal input terminal I7 are the same, the signal output terminal will output the opposite logic value to the input, and the C cell behaves as an inverter; when the first signal input terminal I1, the second signal input terminal I3, the third signal input terminal I5 and the fourth signal input terminal I7 have different logic values, the signal output terminal enters a hold state and outputs a logic value in the previous state. It can be seen that the C cell can be used to mask the logic value flip of the node, i.e. prevent the flip of part of the logic values in the input terminals I1, I3, I5, I7 from propagating to the output terminal.

The normal operation of the latch proposed by the present invention is explained below. When CLK is high and CLKB is low, the structure operates in the transparent mode. At this time, the transmission gates TG1, TG2, TG3, TG4, and TG5 are turned on. For example, D ═ 1, i.e., D ═ I2 ═ I4 ═ I6 ═ I8 ═ Q ═ 1. At this time, NMOS transistors N1, N3, N5, N7 in MCell are turned on, so I1 ═ I3 ═ I5 ═ I7 ═ 0, the input of C cell is asserted, and thus C cell will output 1. On the other hand, TG6 is turned off, TG5 is turned on, D can be directly transmitted to Q, and Q is not driven by the output end of the C unit, so that current competition at the output end of the latch is reduced, and circuit power consumption is saved. The structure operates in the latch mode when CLK is low and CLKB is high. At this time, TG1, TG2, TG3, TG4, TG5 are turned off, TG6 is turned on, and thus Q is driven only by the output terminal of the C cell. On the other hand, because the even-numbered nodes of the MCell feed back data to the odd-numbered nodes and the odd-numbered nodes feed back data to the even-numbered nodes, a plurality of data feedback loops are formed to ensure that the MCell can effectively latch the data. Since four sets of outputs of MCell are fed back to four sets of inputs of C cell, Q can also latch correct data.

The principle of the fault-tolerant operation of the latch proposed by the present invention is explained below. The storage 1 (i.e., in the lock mode, Q — I2 — I4 — I6 — I8 — 1, I1 — I3 — I5 — I7 — 0) is specifically described as an example. When storing 0, the situation is similar, limited to space, and is omitted here. First, the single node flip case is discussed, and the key node sequences are { I1, I2, I3, I4, I5, I6, I7, I8, Q }. In the first 8 nodes, the logic values of the odd nodes are the same, the logic values of the even nodes are the same, and the logic values of the odd nodes are different from those of the even nodes. Here, a single node inversion occurs at I5 as an example. Before the inversion occurs, I4 is 1, and after the inversion occurs, the temporary change of I5 from 0 to 1 will cause P4 to be turned off, but the value of I4 does not change, so N5 is turned on, and I5 is self-recovered. On the other hand, when I5 is inverted to 1, I7 is not affected, so P6 is on and I6 is 1 (strong 1). At the same time, N6 is temporarily turned on, I6 ═ 0 (weak 0). But a strong 1 of I6 can neutralize a weak 0, so I6 is still correct. Similarly, similar fault tolerance mechanisms can be obtained for other nodes. But for Q to have a single node rollover, Q is able to self-recover because MCell is unaffected. In summary, any node of the latch is capable of self-recovering from a single node. That is, the latch is single node flipped on line self-healing.

In the following discussion of the dual node flip scenario, there are two possible scenarios in the latch mode due to the possibility of data state flip between any two nodes: (1) double-node overturning occurs to the MCell; (2) one node in the MCell and Q flip at the same time.

For the case of (1), the key node sequences of MCell are { I1, I2, I3, I4, I5, I6, I7, I8}, so that there are 28 kinds of cases where double node flipping occurs in total, C82. If the distance between two adjacent nodes is expressed as N · L, the distance between any two nodes in the MCell may only be 1L, 2L, 3L, 4L, because the nodes in the MCell are cyclic, for example, the distance from I1 to I6 is actually the distance from I6 to I1 is not 5L but 3L. On the other hand, from the perspective of the layout, the farther the distance between the nodes is, the smaller the probability of the double-node turnover is, and even the probability can be ignored. Thus, 4 exemplary sequences of two-node flip node pairs { < I1, I2>, < I1, I3>, < I1, I4>, < I1, I5> } can be selected. Obviously, the distances between the respective two nodes in the sequence are 1L, 2L, 3L, 4L, respectively, and all other pairs of nodes in the latch are similar to one of the 4 node pairs described above, respectively. The fault tolerance principle of the above-mentioned exemplary two-node flip node sequence { < I1, I2>, < I1, I3>, < I1, I4>, < I1, I5> } is discussed below: for the case of < I1, I2> flips, the following analysis is performed: before < I1 and I2> are inverted, the values of all odd nodes (such as I1 and I3) are 0, the values of all even nodes (such as I2 and I4) are 1, odd NMOS transistors (such as N1 and N3) are all conducted, even PMOS transistors (such as P2 and P4) are all conducted, and other MOS transistors are not conducted. When the < I1 and I2> are turned over, namely I1 is temporarily turned over from 0 to 1, I2 is temporarily turned over from 1 to 0, N2 and P1 are temporarily conducted, and other nodes are not influenced. The I8 output 1, N1 is conductive, so I1 self-recovers. When I2 is inverted from 1 to 0, I3 is not affected, so I3 is still 0 and P2 is turned on, so I2 recovers itself. It follows that MCell is able to self-recover from the DNU (i.e. two-node flip) and therefore the inputs to the C cells are all correct, it is clear that Q still maintains the correct value, i.e. the latch is able to self-recover from the DNU. Similarly, for the case of < I1, I4> or < I1, I5> flip, the MCell can still self-recover from the DNU, and thus the latch can self-recover from the DNU.

For the case of < I1, I3> flips, the following analysis is performed: before the < I1 and I3> are overturned, I1 is equal to I3 is equal to 0. When DNU occurs in < I1, I3>, i.e. I1 and I3 are inverted from 0 to 1, both N2 and N4 are turned on, and I2 is inverted to 0, and P1 is turned on. Since the original value 1 of I8 is not affected, N1 is turned on, and I1 enters an indeterminate state and does not affect I8. When < I1, I3> is inverted, the original value 0 of I5 is not affected, P4 is always on, and N4 is also on, so that the value of I4 is indefinite and I5, i.e., I5 is not affected. It follows that the inputs of the C cells are not all affected, and it is clear that Q still maintains the correct value, i.e. the latch is tolerant to the DNU.

For the case of (2), Q is then self-healing as the MCell single node self-heals. I.e. the latch is self-recovering from the DNU for the case of (2).

Finally, the internal three-node rollover situation is discussed. In the latch mode, since the data states of any three internal nodes may flip, three conditions are included in total as shown by analysis.

In the first case, three nodes are input to the C unit, and the input key node sequence of the C unit is { I1, I3, I5, I7}, so that there are cases where three-node inversion occurs, which totals C43 { < I1, I3, I5>, < I1, I3, I7>, < I1, I5, I7>, < I3, I5, I7> }. The following analyses were performed with the examples of < I1, I3, I5 >: when I1, I3, I5 were flipped from 0 to 1, I7 and I8 would not be affected because even if I6 was flipped from 1 to 0, flipping of I1 from 0 to 1 would not propagate errors to I7 and I8. When I1 is flipped to 1, N2 is turned on, so I2 is equal to 0. Since I3 is also inverted, P2 cannot conduct, I2 remains at the wrong value 0, at which point P1 conducts, and I1 goes to an indeterminate value because I8 becomes 1 and N1 also conducts. When I3 is flipped to 1, N4 is turned on, so I4 is equal to 0. Since I5 also flips, P4 is not conductive, I4 remains at the wrong value of 0, and P3 is conductive, so I3 remains at the wrong value of 1. When I5 is inverted to 1, N6 is turned on, and since I7 is not affected by 0, P6 is also turned on, so I6 goes to an indeterminate value. In summary, the inputs of the C-cell are not all inverted, so the logic state of the signal output of the C-cell will remain unchanged, i.e. the latch can tolerate the three-node inversion. The inversion occurs for < I1, I3, I7>, < I1, I5, I7> and < I3, I5, I7>, similar to the above, and will not be repeated here.

In the second case, none of the three nodes is the input of the C cell, and the key node sequence of the input of the non-C cell is { I2, I4, I6, I8}, so that there are 4 cases where three-node inversion occurs, i.e., { < I2, I4, I6>, < I2, I4, I8>, < I2, I6, I8>, < I4, I6, I8> }. The following analyses were performed with the examples of < I2, I4, I6 >: when I2, I4, I6 were flipped from the original value of 1 to 0, I7 and I8 would not be affected because I2 caused I1 to flip from the original value of 0 to 1 would not propagate errors to I7 and I8 even if I6 was flipped from the original value of 1 to 0. Analysis shows that when I2, I4 and I6 are turned to 0, I1 and I6 enter indeterminate values, and I2, I3, I4 and I5 are all turned and cannot recover. However, the inputs of the C-cells are not all inverted, so the logic state of the signal output of the C-cells will remain unchanged, i.e., the latch can tolerate the three-node inversion. The inversion occurs for < I2, I4, I8>, < I2, I6, I8> and < I4, I6, I8>, similar to the above, and will not be repeated here.

In the third case, the three nodes have inputs of both C cells and non-C cells, and the two cases are divided into: (A) two odd nodes and one even node are arranged in the three nodes, and C42 multiplied by 4 is the total of 24 cases; (B) among the three nodes, there are an odd node and two even nodes, and there are 24 cases of C42 × 4.

For the case of (a), the following analyses were performed with the inversion case < I1, I2, I3 >: when I1, I2, I3 are inverted from original values 0, 1, 0 to 1, 0, 1, respectively, I5, I6, I7 and I8 are not affected because even if I4 is inverted from original value 1 to 0, the inversion of I1 from original value 0 to 1 will not propagate errors to I5 and I8, and therefore will not propagate errors to I6, I7. Analysis shows that when I1, I2 and I3 are overturned, I1 and I4 enter indeterminate values, and I2 and I3 are overturned and cannot recover. However, the inputs of the C-cells are not all inverted, so the logic state of the signal output of the C-cells will remain unchanged, i.e., the latch can tolerate the three-node inversion. For the case where the other nodes flip, similar to the above, it is omitted here.

For the case of (B), the following analyses were performed with the inversion case < I2, I4, I5 >: when I2, I4, I5 are flipped from the original values 1, 0 to 0, 1, respectively, I7 and I8 are not affected because even if I5 causes I6 to flip from the original value 1 to 0, I2 causes I1 to flip from the original value 0 to 1 will not propagate errors to I7 and I8. Analysis shows that when I2, I4 and I5 are overturned, I1 and I6 enter indeterminate values, and I2, I3, I4 and I5 are overturned and cannot recover. However, the inputs of the C-cells are not all inverted, so the logic state of the signal output of the C-cells will remain unchanged, i.e., the latch can tolerate the three-node inversion. For the case where the other nodes flip, similar to the above, it is omitted here.

In summary, the present invention provides an online self-healing solution for multi-node (mainly dual-node and triple-node) flips caused by radiation particles hitting latch circuits in a radiation environment, thereby improving the reliability of the latch circuits. Meanwhile, as a small number of transistors and a high-speed path technology are respectively used and a transmission gate is inserted into an output stage, current competition is avoided, and the circuit area overhead, the delay overhead and the power consumption overhead are reduced. The invention can be effectively applied to integrated circuits and systems with high reliability requirements, and can be widely applied to the fields of aerospace and the like with high requirements on the reliability and the expense of the latch.

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A latch with three internal node flip full immunity, comprising: a memory module (MCell) constructed by 8 pairs of PN transistors, a C unit and six transmission gates; the memory module (MCell) is provided with a first signal input end (I2), a second signal input end (I4), a third signal input end (I6), a fourth signal input end (I8), a first signal output end (I1), a second signal output end (I3), a third signal output end (I5) and a fourth signal output end (I7); the unit C is provided with a first signal input end, a second signal input end, a third signal input end, a fourth signal input end and a signal output end;

wherein, six transmission gates are respectively the same clock: a first transmission gate (TG 1), a second transmission gate (TG 2), a third transmission gate (TG 3), a fourth transmission gate (TG 4), a fifth transmission gate (TG 5) and a sixth transmission gate (TG 6);

a signal input end of the first transmission gate (TG 1), a signal input end of the second transmission gate (TG 2), a signal input end of the third transmission gate (TG 3), a signal input end of the fourth transmission gate (TG 4) and a signal input end of the fifth transmission gate (TG 5) are connected, and a connection point is used as a data input end of the latch;

a signal output of the first transmission gate (TG 1) is connected to a first signal input (I2) of the memory module (MCell); a signal output of the second transmission gate (TG 2) is connected to a second signal input (I4) of the memory module (MCell); a signal output of the third transmission gate (TG 3) is connected to a third signal input (I6) of the memory module (MCell); a signal output of the fourth transmission gate (TG 4) is connected to a fourth signal input (I8) of the memory module (MCell);

a first signal output (I1) of the memory module (MCell) is connected to a first signal input of the C cell; a second signal output (I3) of the memory module (MCell) is connected to a second signal input of the C cell; a third signal output (I5) of the memory module (MCell) is connected to a third signal input of the C cell; a fourth signal output (I7) of the memory module (MCell) is connected to a fourth signal input of the C cell;

the signal output end of the C unit is connected with the signal input end of the sixth transmission gate (TG 6);

the signal output end of the fifth transmission gate (TG 5) is connected with the signal output end of the sixth transmission gate (TG 6), and the connection point is used as the data output end of the latch;

the memory module (MCell) comprises: a first PMOS tube (P1), a second PMOS tube (P2), a third PMOS tube (P3), a fourth PMOS tube (P4), a fifth PMOS tube (P5), a sixth PMOS tube (P6), a seventh PMOS tube (P7), an eighth PMOS tube (P8), a first NMOS tube (N1), a second NMOS tube (N2), a third NMOS tube (N3), a fourth NMOS tube (N4), a fifth NMOS tube (N5), a sixth NMOS tube (N6), a seventh NMOS tube (N7), and an eighth NMOS tube (N8); wherein:

the drain electrode of the first PMOS tube (P1), the drain electrode of the first NMOS tube (N1), the grid electrode of the eighth PMOS tube (P8) and the grid electrode of the second NMOS tube (N2) are connected, and the connection point is used as a first signal output end (I1) of the memory module (MCell);

the drain electrode of the second PMOS tube (P2), the drain electrode of the second NMOS tube (N2), the grid electrode of the first PMOS tube (P1) and the grid electrode of the third NMOS tube (N3) are connected, and the connection point is used as a first signal input end (I2) of the memory module (MCell);

the drain electrode of the third PMOS tube (P3), the drain electrode of the third NMOS tube (N3), the grid electrode of the second PMOS tube (P2) and the grid electrode of the fourth NMOS tube (N4) are connected, and the connection point is used as a second signal output end (I3) of the memory module (MCell);

the drain electrode of the fourth PMOS tube (P4), the drain electrode of the fourth NMOS tube (N4), the grid electrode of the third PMOS tube (P3) and the grid electrode of the fifth NMOS tube (N5) are connected, and the connection point is used as a second signal input end (I4) of the memory module (MCell);

the drain electrode of the fifth PMOS tube (P5), the drain electrode of the fifth NMOS tube (N5), the grid electrode of the fourth PMOS tube (P4) and the grid electrode of the sixth NMOS tube (N6) are connected, and the connection point is used as a third signal output end (I5) of the memory module (MCell);

the drain electrode of the sixth PMOS tube (P6), the drain electrode of the sixth NMOS tube (N6), the grid electrode of the fifth PMOS tube (P5) and the grid electrode of the seventh NMOS tube (N7) are connected, and the connection point is used as a third signal input end (I6) of the memory module (MCell);

the drain electrode of the seventh PMOS tube (P7), the drain electrode of the seventh NMOS tube (N7), the grid electrode of the sixth PMOS tube (P6) and the grid electrode of the eighth NMOS tube (N8) are connected, and the connection point is used as a fourth signal output end (I7) of the memory module (MCell);

the drain electrode of the eighth PMOS tube (P8), the drain electrode of the eighth NMOS tube (N8), the grid electrode of the seventh PMOS tube (P7) and the grid electrode of the first NMOS tube (N1) are connected, and the connection point is used as a fourth signal input end (I8) of the memory module (MCell);

the source electrode and the substrate of the first PMOS tube (P1), the second PMOS tube (P2), the third PMOS tube (P3), the fourth PMOS tube (P4), the fifth PMOS tube (P5), the sixth PMOS tube (P6), the seventh PMOS tube (P7) and the eighth PMOS tube (P8) are all connected with a power supply (VDD);

the source electrode and the substrate of the first NMOS tube (N1), the second NMOS tube (N2), the third NMOS tube (N3), the fourth NMOS tube (N4), the fifth NMOS tube (N5), the sixth NMOS tube (N6), the seventh NMOS tube (N7) and the eighth NMOS tube (N8) are all Grounded (GND).

2. The latch of claim 1 wherein said latch is fully immune by three internal node flip:

the C unit consists of four PMOS tubes and four NMOS tubes; the four PMOS tubes are respectively a ninth PMOS tube (MP 1), a tenth PMOS tube (MP 2), an eleventh PMOS tube (MP 3) and a twelfth PMOS tube (MP 4), and the four NMOS tubes are respectively a ninth NMOS tube (MN 1), a tenth NMOS tube (MN 2), an eleventh NMOS tube (MN 3) and a twelfth NMOS tube (MN 4); wherein:

the grid electrode of a twelfth PMOS tube (MP 4) is connected with the grid electrode of a twelfth NMOS tube (MN 4), and the connection point is a first signal input end of the C unit; the grid electrode of an eleventh PMOS (MP 3) is connected with the grid electrode of an eleventh NMOS (MN 3), and the connection point is the second signal input end of the C unit; the grid electrode of the tenth PMOS tube (MP 2) is connected with the grid electrode of the tenth NMOS tube (MN 2), and the connection point is the third signal input end of the C unit; the grid electrode of the ninth PMOS tube (MP 1) is connected with the grid electrode of the ninth NMOS tube (MN 1), and the connection point is the fourth signal input end of the C unit; the drain electrode of the twelfth PMOS tube (MP 4) is connected with the drain electrode of the ninth NMOS tube (MN 1), and the connection point is the signal output end of the C unit;

the drain electrode of the ninth PMOS tube (MP 1) is connected with the source electrode of the tenth PMOS tube (MP 2); the drain electrode of the tenth PMOS tube (MP 2) is connected with the source electrode of the eleventh PMOS tube (MP 3); the drain electrode of the eleventh PMOS tube (MP 3) is connected with the source electrode of the twelfth PMOS tube (MP 4); the source electrode of the ninth NMOS transistor (MN 1) is connected with the drain electrode of the tenth NMOS transistor (MN 2); the source electrode of the tenth NMOS transistor (MN 2) is connected with the drain electrode of the eleventh NMOS transistor (MN 3); the source electrode of the eleventh NMOS tube (MN 3) is connected with the drain electrode of the twelfth NMOS tube (MN 4); a source electrode of the ninth PMOS tube (MP 1), a substrate of the ninth PMOS tube (MP 1), a substrate of the tenth PMOS tube (MP 2), a substrate of the eleventh PMOS tube (MP 3) and a substrate of the twelfth PMOS tube (MP 4) are all connected with a power supply (VDD); the substrate of the ninth NMOS transistor (MN 1), the substrate of the tenth NMOS transistor (MN 2), the substrate of the eleventh NMOS transistor (MN 3), the substrate of the twelfth NMOS transistor (MN 4) and the source electrode of the twelfth NMOS transistor (MN 4) are all grounded.