CN109104167A - latch - Google Patents
latch Download PDFInfo
- Publication number
- CN109104167A CN109104167A CN201810947260.8A CN201810947260A CN109104167A CN 109104167 A CN109104167 A CN 109104167A CN 201810947260 A CN201810947260 A CN 201810947260A CN 109104167 A CN109104167 A CN 109104167A
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- China
- Prior art keywords
- grid
- nmos transistor
- pmos transistor
- transistor
- memory node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0233—Bistable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
- H03K19/00338—In field effect transistor circuits
Abstract
The invention discloses a kind of latch, are made of the Muller C cell that a storage element, 5 transmission gates and four input clocks control, and CLK is clock signal, and CLKB is the clock signal that CLK passes through that level-one phase inverter FX1 is obtained；The storage unit is latched mutually by 8 group of two input inverter and is constituted, every group of phase inverter is composed in series by a PMOS transistor and a NMOS transistor, wherein, the source electrode of PMOS transistor is connected with supply voltage VDD, the source electrode of NMOS transistor is grounded, and the node of the drain electrode connection of the drain electrode and NMOS transistor of PMOS transistor is denoted as memory node, the storage unit shares 8 memory node S1~S8, is located in every group of phase inverter.The present invention can resist two node overturnings, intercept the soft error of storage unit transmission.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of latch.
Background technique
The reliability for first feeding chip of integrated circuit technique node brings many challenges, and one of challenge is exactly single
Particle overturns (SEU) bring soft error.
Soft error may occur in different electronic equipments, such as automotive electronics, Medical Devices etc..
In recent years, since process node is constantly advanced, the distance between device is increasingly closer, and device size is also increasingly
Small, this makes an important sources of the single event multiple bit upset caused by charge-trapping and charge share as soft error.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of latch, can resist two node overturnings, intercept storage
The soft error of unit transmission.
It is four defeated by a storage element, 5 transmission gates and one in order to solve the above technical problems, latch of the invention
Enter the Muller C cell composition of clock control, CLK is clock signal, and CLKB is the clock that CLK passes through that level-one phase inverter FX1 is obtained
Signal；
The storage unit is latched mutually by 8 group of two input inverter and is constituted, and every group of phase inverter is by a PMOS crystal
Pipe and a NMOS transistor are composed in series, wherein the source electrode of PMOS transistor is connected with supply voltage VDD, NMOS crystal
The source electrode of pipe is grounded, and the node of the drain electrode connection of the drain electrode and NMOS transistor of PMOS transistor is denoted as memory node, described to deposit
Storage unit shares 8 memory node S1~S8, is located in every group of phase inverter；First group of two input inverter is by the first PMOS
Transistor and the first NMOS transistor composition, memory node S1；Second group of two input inverter by the second PMOS transistor and
Second NMOS transistor composition, memory node S2；Two input inverter of third group is by third PMOS transistor and the 3rd NMOS
Transistor composition, memory node S3；4th group of two input inverters are by the 4th PMOS transistor and the 4th NMOS transistor group
At memory node S4；5th group of two input inverters are made of the 5th PMOS transistor and the 5th NMOS transistor, storage section
Point is S5；6th group of two input inverters are made of the 6th PMOS transistor and the 6th NMOS transistor, memory node S6；The
Seven group of two input inverter is made of the 7th PMOS transistor and the 7th NMOS transistor, memory node S7；8th group two defeated
Enter phase inverter to be made of the 8th PMOS transistor and the 8th NMOS transistor, memory node S8；
First transmission gate~the 5th transmission gate input terminal is connected, as the data input pin D of latch, control terminal
CLK is inputted, inverted control terminals input CLKB, and the output end for passing the 5th defeated door is connected with the output end Q of latch；
The Muller C cell of the four input clocks control is by the 9th~the 13rd and 5 NMOS crystal of 5 PMOS transistors
Pipe the 9th~the 13rd is sequentially connected in series；The source electrode of 9th PMOS transistor is connected with power voltage terminal, the 13rd PMOS
The drain electrode of transistor is connected with the drain electrode of the 9th NMOS transistor, output end Q of the node of connection as latch, and the tenth
The source electrode of three NMOS transistors is grounded；The grid input clock signal CLK of 13rd PMOS transistor, the 9th NMOS transistor
Grid input clock signal CLKB；
Memory node S1 is defeated with the grid of the second PMOS transistor, the grid of the 8th PMOS transistor and the first transmission gate
Outlet is connected；Memory node S2 and the grid of third PMOS transistor, the grid of the 9th PMOS transistor, the first NMOS crystal
The grid of the grid of pipe and the 13rd NMOS transistor is connected；The grid of memory node S3 and the second NMOS transistor, the 4th
The output end of the grid of PMOS transistor and the second transmission gate is connected；Memory node S4 and the grid of the tenth PMOS transistor,
The grid of the grid of third NMOS transistor, the grid of the 5th NMOS transistor and the tenth bi-NMOS transistor is connected；Storage
Node S5 is connected with the output end of the grid of the 4th NMOS transistor, the grid of the 6th NMOS transistor and third transmission gate TG3
It connects；Memory node S6 and the grid of the 5th PMOS transistor, the grid of the 11st PMOS transistor, the 7th NMOS transistor grid
Pole is connected with the grid of the 11st NMOS transistor；Memory node S7 and the grid of the 6th PMOS transistor, the 8th NMOS are brilliant
The output end of the grid of body pipe and the 4th transmission gate is connected；Memory node S8 and the grid of the first PMOS transistor, the 7th
The grid of the grid of PMOS transistor, the grid of the 12nd PMOS transistor and the tenth NMOS transistor is connected.
Latch of the invention have the characteristics that high speed, it is highly reliable, Muller C cell can be intercepted and be deposited under latch mode
The soft error that storage unit transmission comes, therefore, the present invention have the function of resisting two node overturnings.Under break-through mode, the 5th
Transmission gate can be used to realize high-speed transfer.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the one embodiment schematic diagram of latch；
Fig. 2 is each point waveform diagram in latch shown in Fig. 1.
Specific embodiment
As shown in connection with fig. 1, the latch has the function of resisting two node overturnings, in the embodiment shown in fig. 1,
The latch is made of the Muller C cell that a storage element, 5 transmission gates and four input clocks control.CLK is clock letter
Number, CLKB is the clock signal that CLK passes through that level-one phase inverter FX1 is obtained.
The storage unit is latched mutually by 8 group of two input inverter and is constituted.Every group of phase inverter is by a PMOS crystal
Pipe and a NMOS transistor are composed in series, wherein the source electrode of PMOS transistor is connected with supply voltage VDD, NMOS crystal
The source electrode of pipe is grounded, and the node of the drain electrode connection of the drain electrode and NMOS transistor of PMOS transistor is denoted as memory node.It is described to deposit
Storage unit shares 8 memory node S1~S8, is located in every group of phase inverter.
First group of two input inverter is made of PMOS transistor PM1 and NMOS transistor NM1, memory node S1.
Second group of two input inverter is made of PMOS transistor PM2 and NMOS transistor NM2, memory node S2.
Two input inverter of third group is made of PMOS transistor PM3 and NMOS transistor NM3, memory node S3.
4th group of two input inverters are made of PMOS transistor PM4 and NMOS transistor NM4, memory node S4.
5th group of two input inverters are made of PMOS transistor PM5 and NMOS transistor NM5, memory node S5.
6th group of two input inverters are made of PMOS transistor PM6 and NMOS transistor NM6, memory node S6.
7th group of two input inverters are made of PMOS transistor PM7 and NMOS transistor NM7, memory node S7.
8th group of two input inverters are made of PMOS transistor PM8 and NMOS transistor NM8, memory node S8.
The transmission gate is cmos transmission gate, is made of a NMOS transistor and a PMOS transistor.
The input terminal of five transmission gate TG1~TG5 is connected, the data input pin D as latch.Five transmission gates
The control terminal input clock signal CLK of TG1~TG5, inverted control terminals input clock signal CLKB.The output end of transmission gate TG5
It is connected with the output end Q of latch.
Muller C cell has similar inverter function.When the input logic level of Muller C cell is consistent (in conjunction with Fig. 1
It is shown, when wherein memory node S2, S4, S6, S8 is high level or is low level), Muller C cell is phase inverter function
Energy；When the input logic level of Muller C cell is not complete consistent, high-impedance state is exported.
The Muller C cell of the four input clocks control is by 5 PMOS transistor PM9~PM13 and 5 NMOS transistors
NM9~NM13 is sequentially connected in series.The source electrode of PMOS transistor PM9 is connected with power voltage terminal, PMOS transistor PM13's
Drain electrode is connected with the drain electrode of NMOS transistor NM9, output end Q of the node of connection as latch, NMOS transistor
The source electrode of NM13 is grounded.When the grid input of grid the input clock signal CLK, NMOS transistor NM9 of PMOS transistor PM13
Clock signal CLKB.PMOS transistor PM13 and NMOS transistor NM9 are as Clock control end.
The output of the grid, the grid and transmission gate TG1 of PMOS transistor PM8 of memory node S1 and PMOS transistor PM2
End is connected.
Memory node S2 and the grid of PMOS transistor PM3, the grid of PMOS transistor PM9, NMOS transistor NM1 grid
Pole is connected with the grid of NMOS transistor NM13.
The output of the grid, the grid and transmission gate TG2 of PMOS transistor PM4 of memory node S3 and NMOS transistor NM2
End is connected.
Memory node S4 and the grid of PMOS transistor PM10, the grid of NMOS transistor NM3, NMOS transistor NM5
Grid is connected with the grid of NMOS transistor NM12.
The output of the grid, the grid and transmission gate TG3 of NMOS transistor NM6 of memory node S5 and NMOS transistor NM4
End is connected.
Memory node S6 and the grid of PMOS transistor PM5, the grid of PMOS transistor PM11, NMOS transistor NM7
Grid is connected with the grid of NMOS transistor NM11.
The output of the grid, the grid and transmission gate TG4 of NMOS transistor NM8 of memory node S7 and PMOS transistor PM6
End is connected.
Memory node S8 and the grid of PMOS transistor PM1, the grid of PMOS transistor PM7, PMOS transistor PM12
Grid is connected with the grid of NMOS transistor NM10.
When the work of above-mentioned latch is in break-through mode, if clock signal clk is high level, CLKB is low level.
Data are incoming from input terminal D, by transmission gate TG1-TG5, reach 4 memory nodes S1, S3, S5, S7 in storage unit, and
Latch outputs Q.
When the work of above-mentioned latch is in latch mode, if clock signal clk is low level, CLKB is high level.
Transmission gate TG1-TG5 is closed, and PMOS transistor PM13, NMOS transistor NM9 are opened, data 4 storage sections from latch units
Point S2, S4, S6, S8 outflow, by reaching latch outputs Q by Muller C cell.
The each point waveform of the latch is as shown in Figure 2.Wherein:
1. applying single-particle inversion (SEU) pulse 1 simultaneously at memory node S2, S3, it can be seen that deposit in 3.5ns
Storage node S2, S3 are pulled back to rapidly original correct logic level, and the logic state of the output end Q of latch is unaffected,
Still keep 0 logic state.
2. applying single-particle inversion (SEU) pulse 1, memory node S6, S8 simultaneously at memory node S6, S8 in 6ns
It cannot be pulled back to original correct logic level, and memory node S5 and S7 are flipped, but due to memory node S2 at this time
Keep original correct logic state, the input logic level of Muller C cell be not it is complete consistent, Muller C cell can enter high-impedance state,
The soft error shielding that will be come out from storage unit, output end Q keep original correct 0 logic state.
3. applying single-particle inversion (SEU) pulse 1, storage section simultaneously at storage node S1, S7 in 16.6ns
Point S1, S7 cannot be pulled back to original correct logic level, and memory node S2 and S8 are flipped, but due to storing at this time
Node S4 keeps original correct logic state, the input logic level of Muller C cell be not it is complete consistent, Muller C cell can enter
High-impedance state shields the soft error come out from storage unit, and output end Q keeps original correct 1 logic state.
4. applying single-particle inversion (SEU) pulse 1 simultaneously at memory node S4, S5, it can be seen that deposit in 25.5ns
Storage node S4, S5 are pulled back to rapidly original correct logic level, and the logic state of the output end Q of latch is unaffected,
Still keep 1 logic state.
Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (5)
1. a kind of latch, which is characterized in that Mu controlled by a storage element, 5 transmission gates and four input clocks
C cell composition is strangled, CLK is clock signal, and CLKB is the clock signal that CLK passes through that level-one phase inverter FX1 is obtained；
The storage unit is latched mutually by 8 group of two input inverter and is constituted, every group of phase inverter by a PMOS transistor and
One NMOS transistor is composed in series, wherein the source electrode of PMOS transistor is connected with supply voltage VDD, NMOS transistor
Source electrode ground connection, the node of the drain electrode connection of the drain electrode and NMOS transistor of PMOS transistor, is denoted as memory node, the storage is single
Member shares 8 memory node S1~S8, is located in every group of phase inverter；
First group of two input inverter is made of the first PMOS transistor and the first NMOS transistor, memory node S1；Second
Two input inverters of group are made of the second PMOS transistor and the second NMOS transistor, memory node S2；Third group two inputs
Phase inverter is made of third PMOS transistor and third NMOS transistor, memory node S3；4th group of two input inverters by
4th PMOS transistor and the 4th NMOS transistor composition, memory node S4；5th group of two input inverters are by the 5th PMOS
Transistor and the 5th NMOS transistor composition, memory node S5；6th group of two input inverters by the 6th PMOS transistor and
6th NMOS transistor composition, memory node S6；7th group of two input inverters are by the 7th PMOS transistor and the 7th NMOS
Transistor composition, memory node S7；8th group of two input inverters are by the 8th PMOS transistor and the 8th NMOS transistor group
At memory node S8；
First transmission gate~the 5th transmission gate input terminal is connected, as the data input pin D of latch, control terminal input
CLK, inverted control terminals input CLKB, and the output end for passing the 5th defeated door is connected with the output end Q of latch；
The Muller C cell of four input clock control is by the 9th~the 13 and 5 NMOS transistor of 5 PMOS transistors the
Nine~the 13rd is sequentially connected in series；The source electrode of 9th PMOS transistor is connected with power voltage terminal, the 13rd PMOS crystal
The drain electrode of pipe is connected with the drain electrode of the 9th NMOS transistor, output end Q of the node of connection as latch, and the 13rd
The source electrode of NMOS transistor is grounded；The grid input clock signal CLK of 13rd PMOS transistor, the grid of the 9th NMOS transistor
Pole input clock signal CLKB；
The output end of memory node S1 and the grid of the second PMOS transistor, the grid of the 8th PMOS transistor and the first transmission gate
It is connected；Memory node S2 and the grid of third PMOS transistor, the grid of the 9th PMOS transistor, the first NMOS transistor
The grid of grid and the 13rd NMOS transistor is connected；The grid of memory node S3 and the second NMOS transistor, the 4th PMOS
The output end of the grid of transistor and the second transmission gate is connected；Memory node S4 and the grid of the tenth PMOS transistor, third
The grid of the grid of NMOS transistor, the grid of the 5th NMOS transistor and the tenth bi-NMOS transistor is connected；Memory node
S5 is connected with the output end of the grid of the 4th NMOS transistor, the grid of the 6th NMOS transistor and third transmission gate TG3；It deposits
Store up the grid of node S6 and the 5th PMOS transistor, the grid of the 11st PMOS transistor, the grid of the 7th NMOS transistor and
The grid of 11st NMOS transistor is connected；Memory node S7 and the grid of the 6th PMOS transistor, the 8th NMOS transistor
Grid and the output end of the 4th transmission gate be connected；Memory node S8 and the grid of the first PMOS transistor, the 7th PMOS are brilliant
The grid of the grid of body pipe, the grid of the 12nd PMOS transistor and the tenth NMOS transistor is connected.
2. latch as described in claim 1, it is characterised in that: the latch work is in break-through mode, if clock is believed
When number CLK is high level, then CLKB is low level, and data are incoming from input terminal D, by the first transmission gate~the 5th transmission gate,
Reach 4 the memory nodes S1, S3, S5, S7 and latch outputs Q in storage unit.
3. latch as described in claim 1, it is characterised in that: the latch work is in latch mode, if clock is believed
When number CLK is low level, then CLKB is high level, and the first transmission gate~the 5th transmission gate is closed, the 13rd of Muller C cell the
PMOS transistor, the 9th NMOS transistor NM9 are opened, data 4 memory nodes S2, S4, S6 from latch units, S8 outflow,
By reaching latch outputs Q by Muller C cell.
4. latch as described in claim 1, it is characterised in that: the transmission gate is cmos transmission gate, by a NMOS crystalline substance
Body pipe and a PMOS transistor are constituted.
5. latch as described in claim 1, it is characterised in that: when the input logic level of the Muller C cell is consistent,
Then Muller C cell tool is inverter function, and when the input logic level of Muller C cell is inconsistent, output is in high-impedance state；13rd
PMOS transistor and the 9th NMOS transistor are as Clock control end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810947260.8A CN109104167A (en) | 2018-08-20 | 2018-08-20 | latch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810947260.8A CN109104167A (en) | 2018-08-20 | 2018-08-20 | latch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109104167A true CN109104167A (en) | 2018-12-28 |
Family
ID=64850427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810947260.8A Pending CN109104167A (en) | 2018-08-20 | 2018-08-20 | latch |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109104167A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109936358A (en) * | 2019-02-13 | 2019-06-25 | 天津大学 | Resist the latch structure of the double overturnings of single-particle |
| CN111865291A (en) * | 2020-07-08 | 2020-10-30 | 上海华虹宏力半导体制造有限公司 | Latch of anti two node upset |
| CN112636738A (en) * | 2020-12-28 | 2021-04-09 | 长沙理工大学 | Self-recovery latch and integrated chip allowing three-node turnover |
| CN111865291B (en) * | 2020-07-08 | 2024-04-19 | 上海华虹宏力半导体制造有限公司 | Latch capable of resisting double-node overturning |
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| US20070132496A1 (en) * | 2005-12-12 | 2007-06-14 | Satoshi Kuboyama | Single-event effect tolerant latch circuit and flip-flop circuit |
| CN101431321A (en) * | 2007-11-08 | 2009-05-13 | 恩益禧电子股份有限公司 | Latch circuit and flip-flop circuit |
| US7719304B1 (en) * | 2007-05-08 | 2010-05-18 | Arizona Board Of Regents For And On Behalf Of Arizonia State University | Radiation hardened master-slave flip-flop |
| CN103474092A (en) * | 2013-09-04 | 2013-12-25 | 华中科技大学 | Anti-radiation hardened storage cell circuit |
| CN103956184A (en) * | 2014-05-16 | 2014-07-30 | 中国科学院微电子研究所 | Improved SRAM (Static Random Access Memory) memory cell based on DICE (Dual Interlocked Storage Cell) structure |
| CN104202037A (en) * | 2014-08-20 | 2014-12-10 | 合肥工业大学 | Single event radiation effect resistant reinforced latch circuit |
| CN107332552A (en) * | 2017-07-04 | 2017-11-07 | 合肥工业大学 | A kind of tolerance two point upset latch based on dual input phase inverter |
| US20180076797A1 (en) * | 2016-09-15 | 2018-03-15 | Board Of Trustees Of Southern Illinois University On Behalf Of Southern Illinois University Carbonda | Systems and methods for a robust double node upset tolerant latch |
| CN108134597A (en) * | 2018-01-08 | 2018-06-08 | 安徽大学 | A kind of completely immune latch of three internal nodes overturning |
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2018
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Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070132496A1 (en) * | 2005-12-12 | 2007-06-14 | Satoshi Kuboyama | Single-event effect tolerant latch circuit and flip-flop circuit |
| US7719304B1 (en) * | 2007-05-08 | 2010-05-18 | Arizona Board Of Regents For And On Behalf Of Arizonia State University | Radiation hardened master-slave flip-flop |
| CN101431321A (en) * | 2007-11-08 | 2009-05-13 | 恩益禧电子股份有限公司 | Latch circuit and flip-flop circuit |
| CN103474092A (en) * | 2013-09-04 | 2013-12-25 | 华中科技大学 | Anti-radiation hardened storage cell circuit |
| CN103956184A (en) * | 2014-05-16 | 2014-07-30 | 中国科学院微电子研究所 | Improved SRAM (Static Random Access Memory) memory cell based on DICE (Dual Interlocked Storage Cell) structure |
| CN104202037A (en) * | 2014-08-20 | 2014-12-10 | 合肥工业大学 | Single event radiation effect resistant reinforced latch circuit |
| US20180076797A1 (en) * | 2016-09-15 | 2018-03-15 | Board Of Trustees Of Southern Illinois University On Behalf Of Southern Illinois University Carbonda | Systems and methods for a robust double node upset tolerant latch |
| CN107332552A (en) * | 2017-07-04 | 2017-11-07 | 合肥工业大学 | A kind of tolerance two point upset latch based on dual input phase inverter |
| CN108134597A (en) * | 2018-01-08 | 2018-06-08 | 安徽大学 | A kind of completely immune latch of three internal nodes overturning |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109936358A (en) * | 2019-02-13 | 2019-06-25 | 天津大学 | Resist the latch structure of the double overturnings of single-particle |
| CN111865291A (en) * | 2020-07-08 | 2020-10-30 | 上海华虹宏力半导体制造有限公司 | Latch of anti two node upset |
| CN111865291B (en) * | 2020-07-08 | 2024-04-19 | 上海华虹宏力半导体制造有限公司 | Latch capable of resisting double-node overturning |
| CN112636738A (en) * | 2020-12-28 | 2021-04-09 | 长沙理工大学 | Self-recovery latch and integrated chip allowing three-node turnover |
| CN112636738B (en) * | 2020-12-28 | 2024-03-22 | 长沙理工大学 | Self-recovery latch allowing three-node overturn and integrated chip |
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Application publication date: 20181228 |