CN108777570A

CN108777570A - Flip-flop circuit is mutually latched on a kind of three tunnels detected based on transmission gate and SET

Info

Publication number: CN108777570A
Application number: CN201810973021.XA
Authority: CN
Inventors: 丁文祥; 蔡雪原; 程飞; 夏强胜
Original assignee: Anqing Normal University
Current assignee: Anqing Normal University
Priority date: 2018-08-24
Filing date: 2018-08-24
Publication date: 2018-11-09

Abstract

The invention discloses a kind of three tunnels detected based on transmission gate and SET mutually to latch flip-flop circuit, which mutually latches flip-flop circuit by clocked inverter chain circuit, D input inverters chain circuit, set-reset signal generating circuit, main DICE latch cicuits and form from DICE latch cicuits；Technical scheme of the present invention detects the mutual latch technique in three tunnels using SET, and the larger settling time so as to reduce filtering wave by prolonging time generation improves the working frequency of circuit to keep the timing performance of trigger more preferable, has better anti-SEU characteristics.

Description

Flip-flop circuit is mutually latched on a kind of three tunnels detected based on transmission gate and SET

Technical field

The present invention relates to the designs of radiation-hardened ic, and it is mutual to be specifically related to a kind of three tunnels detected based on transmission gate and SET Latched flip flop circuit.

Background technology

With the progress of integrated circuit fabrication process, the promotion of the diminution of device size and operating rate, radiate to circuit Influence also become increasingly severe.Radiation is presented as single particle effect (Single Event to the main influence of digital circuit Effect, SEE) and total dose effect (Total Ionizing Dose, TID), as Deep Submicron MOSFETs become master Stream, when the process node of especially MOS circuits reaches 65nm or less, it is main that single particle effect has become influence MOS device Radiation effect.Single particle effect is broadly divided into single-ion transient state (Single Event Transient, SET) and simple grain Son overturning (Single Event Upset, SEU).

Under radiation environment, MOS integrated circuits are by the charged particle bombardment of high energy.When charged particle bombardment ends to script Metal-oxide-semiconductor drain region when, will produce due to the energy transmission of high energy charged particles, in the short time largely can be with free-moving current-carrying Son, i.e. hole and electronics, to make the metal-oxide-semiconductor ended originally conducting, to change the output level of device.Due to high energy particle The carrier of generation over time can be compound quickly or releases and return to the carrier concentration state before bombardment, therefore is hit Metal-oxide-semiconductor can there are one from by the end of being conducting to the process ended again, be reflected in metal-oxide-semiconductor output on, just will produce a positive arteries and veins The waveform of punching or negative pulse.The pulse effects of this transient state is referred to as single-ion transient state.For combinational logic circuit, single-particle Transient effect can influence the output of circuit.And in sequence circuit, when the positive pulse or negative pulse that single-ion transient state generates are touched Hair device or other storage circuits receive or the storage section of circuit is directly hit by high energy particle and generates overturning, due to electricity The memory function on road so that this overturning can not restore, and to make the output of entire circuit generate mistake, this effect is referred to as single Particle is overturn.

Either single-ion transient state effect or Single event upset effecf can all influence the normal work of circuit, therefore having must The MOS integrated circuits to work under radiation environment are reinforced（Radiation Harden）.At present on trigger structure It is main to be reinforced using DICE structures to reduce the influence of single-particle inversion, and it is general to the single-ion transient state of data terminal input When being filtered using C cell circuit, but being filtered using C cell circuit, the settling time of trigger（setup time） Also increase therewith, the timing performance of entire circuit is caused to deteriorate, working frequency declines.

Invention content

The purpose of the present invention is to provide a kind of three tunnels detected based on transmission gate and SET mutually to latch flip-flop circuit, should Three tunnels mutually latch flip-flop circuit and overcome the deficiencies in the prior art, shorten the settling time of trigger, substantially improve whole The timing performance of a circuit improves the working frequency of circuit, has better anti-SEU characteristics.

In order to achieve the above objectives, the technical solution adopted by the present invention to solve the technical problems is：One kind being based on transmission gate Flip-flop circuit is mutually latched with three tunnels of SET detections, it is characterised in that：It includes that clock is anti-that flip-flop circuit is mutually latched on three tunnel Phase device chain circuit, D input inverters chain circuit, set-reset signal generating circuit, main DICE latch cicuits and from DICE latch Circuit；External clock signal CK is separately input to clocked inverter chain circuit and set-reset signal generating circuit, external When clock signal CK generates three road in-phase clock signal bclk1, bclk2, bclk3 and three tunnel reverse phases through clocked inverter chain circuit Clock signal nclk1, nclk2, nclk3；External data signal D is separately input to D input inverters chain circuit and set-reset letter Number generation circuit, external data signal D generate two circuit-switched data signal d1, d2 and all the way reverse phase number through D input inverter chain circuits It is believed that number nd；Clock signal CK, data-signal D, D input inverter chain circuit generate data-signal d1 all the way and all the way reverse phase number It is believed that number nd and two road inverting clock signal nclk1, nclk2 and all the way in-phase clock signal bclk2 are through set-reset signal Set signal sn and reset signal r is exported after generation circuit；The data-signal D, three road in-phase clock signal bclk1, Bclk2, bclk3 and three road inverting clock signal nclk1, nclk2, nclk3 and two circuit-switched data signal d1, d2 and set signal Sn and reset signal r is input to main DICE latch cicuits, and three data signal m1, m2, m3 are exported after main DICE latch cicuits； The set signal sn and reset signal r of set-reset signal generating circuit output, three road in-phase clock signal bclk1, Three ways of bclk2, bclk3 and three road inverting clock signal nclk1, nclk2, nclk3 and main DICE latch cicuits output It is believed that number m1, m2 and m3 are input to from DICE latch cicuits, the then outputting data signals Q after from DICE latch cicuits；

The clocked inverter chain circuit be by 12 PMOS tube PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12 and 12 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12 is formed；The PM1 and NM1, PM2 and NM2, PM3 and NM3, PM4 and NM4, PM5 and NM5, PM6 and NM6, PM7 and NM7, PM8 and NM8, PM9 and NM9, PM10 and NM10, PM11 and NM11, PM12 and NM12 respectively constitute a phase inverter, the clock letter Number CK is connect with the input terminal of phase inverter PM1 and NM1, and inverting clock signal nclk1 is exported after inverted device PM1 and NM1；It is described The input terminal of phase inverter PM2 and NM2 are connect with the output end of phase inverter PM1 and NM1, and same phase is exported after inverted device PM2 and NM2 Clock signal bclk1；The input terminal of the phase inverter PM3 and NM3 is connect with clock signal CK, output end and phase inverter PM4 and The input terminal of NM4 connects, and the input terminal of the phase inverter PM5 and NM5 is connect with the output end of phase inverter PM4 and NM4, exports End is connect with the input terminal of phase inverter PM6 and NM6, after clock signal CK inverted device PM3 and NM3, PM4 and NM4, PM5 and NM5 In-phase clock signal bclk2 is exported after exporting inverting clock signal nclk2, then inverted device PM6 and NM6；The phase inverter PM7 It is connect with the input terminal of NM7 with clock signal CK, output end is connect with the input terminal of phase inverter PM8 and NM8, the phase inverter The input terminal of PM9 and NM9 is connect with the output end of phase inverter PM8 and NM8, the input of output end and phase inverter PM10 and NM10 End connection, the input terminal of the phase inverter PM11 and NM11 connect with the output end of phase inverter PM10 and NM10, output end and Phase inverter PM12 is connected with the input terminal of NM12, clock signal CK inverted device PM7 and NM7, PM8 and NM8, PM9 and NM9, When output is with phase after output inverting clock signal nclk3, then inverted device PM12 and NM12 after PM10 and NM10, PM11 and NM11 Clock signal bclk3；

The D input inverters chain circuit be by 4 PMOS tube PM13, PM14, PM15, PM16 and 4 NMOS tube NM13, NM14, NM15, NM16 are formed；The PM13 and NM13, PM14 and NM14, PM15 and NM15, PM16 and NM16 respectively constitute one Phase inverter；The data-signal D is connect with the input terminal of phase inverter PM13 and NM13, is exported after inverted device PM13 and NM13 anti- To data-signal nd；The anti-phase data signal nd is input to the input terminal of phase inverter PM14 and NM14, inverted device PM14 and Outputting data signals d1 after NM14；The input terminal of the phase inverter PM15 and NM15 connects with the output end of phase inverter PM14 and NM14 It connects, output end output reverse data signal nd1, the anti-phase data signal nd1 are input to the input of phase inverter PM16 and NM16 It holds, outputting data signals d2 after inverted device PM16 and NM16；

The set-reset signal generating circuit be by 10 PMOS tube PM17, PM18, PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26 and 10 NMOS tubes NM17, NM18, NM19, NM20, NM21, NM22, NM23, NM24, NM25, NM26 Composition；The grid of the PM21 and NM21 is connect with the output end of clock signal CK；The grid and clock of the PM20 and NM20 The signal output end of the inverting clock signal nclk2 of chain of inverters circuit evolving connects, and the grid and D of the PM19 and NM19 are defeated Enter the signal output end connection of the data-signal d1 of chain of inverters circuit evolving, the grid and D inputs of the PM18 and NM18 are anti- The grid external data letter of the signal output end connection for the reverse data signal nd that phase device chain circuit generates, the PM17 and NM17 Number D；The equal external power supply of source electrode of described PM17, PM18, PM19, PM20, PM21；Described PM17, PM18, PM19, PM20, PM21 Drain electrode connect with the signal output end of the set signal sn of set-reset signal generating circuit；The drain electrode of the NM21 with The drain electrode of PM17 connects, and the source electrode of NM21 is connected with the drain electrode of NM20, and the source electrode of NM20 is connected with the drain electrode of NM19, the source of NM19 Pole is connected with the drain electrode of NM18, and the source electrode of NM18 is connected with the drain electrode of NM17, the source electrode ground connection of NM17；The PM22's and NM22 Grid is connect with the signal output end for the inverting clock signal nclk1 that clocked inverter chain circuit generates；The PM23 and NM23 The signal output end of in-phase clock signal bclk2 that generates of grid and clocked inverter chain circuit connect, the PM24 and The grid of NM24 is connect with the signal output end for the data-signal d1 that D input inverter chain circuits generate, the PM25 and NM25 The signal output end of reverse data signal nd that generates of grid and D input inverter chain circuits connect, the PM26 and NM26 Grid external data signal D；The source electrode external power supply of the PM22；The drain electrode of the PM22 is connect with the source electrode of PM23, institute The drain electrode for stating PM23 is connect with the source electrode of PM24, and the drain electrode of the PM24 is connect with the source electrode of PM25, the drain electrode of PM25 and PM26 Source electrode connection, the drain electrode of the PM26 connect with the drain electrode of NM26, the drain electrode of described NM22, NM23, NM24, NM25, NM26 It is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The NM22, NM23, NM24, NM25, The source grounding of NM26；

The main DICE latch cicuits be by 21 PMOS tube PM27, PM28, PM29, PM30, PM31, PM32, PM33, PM34, PM35, PM36, PM37, PM38, PM39, PM40, PM41, PM42, PM43, PM44, PM45, PM46, PM47 and 24 NMOS Pipe NM27, NM28, NM29, NM30, NM31, NM32, NM33, NM34, NM35, NM36, NM37, NM38, NM39, NM40, NM41, NM42, NM43, NM44, NM45, NM46, NM47, NM48, NM49, NM50 and 6 transmission gate TM1, TM2, TM3, TM4, TM5, TM6 are formed；The grid external data signal D of the PM27, and be connected with the grid of NM27, the source electrode of PM27 is external Power supply, drain electrode are connect with the left data input port of the drain electrode of NM27 and transmission gate TM1 respectively, the right side of the transmission gate TM1 Side data port is connect with the grid of the drain electrode of the grid of PM32, PM31 and NM31 and NM41 respectively；The grid of the PM28 External data signal d1, and being connected with the grid of NM28, the source electrode external power supply of PM28, drain electrode respectively with the drain electrode of NM28 and biography The left data input port of defeated door TM2 connects, the right side data port of the transmission gate TM2 respectively with the grid of PM36, PM35 is connected with the grid of the drain electrode of NM35 and NM33；The grid external data signal d2 of the PM29, and with the grid of NM29 Extremely it is connected, the source electrode external power supply of PM29, drain electrode connects with the left data input port of the drain electrode of NM29 and transmission gate TM3 respectively Connect, the right side data port of the transmission gate TM3 respectively with the drain electrode of the grid of PM40, PM39 and NM39 and the grid of NM37 Connection；

The grid of the PM30 is connected with the grid of the drain electrode of the drain electrode of PM41 and NM41, PM44 and NM44, NM38 respectively, PM30 Source electrode external power supply, drain electrode connect with the source electrode of PM31；The grid of the PM31 generates anti-with clocked inverter chain circuit The signal output end of clock signal nclk1 connects, and the drain electrode of PM31 is connected with the drain electrode of NM31 respectively；The grid of the NM31 It is connect with the signal output end of the in-phase clock signal bclk1 of clocked inverter chain circuit generation, the drain electrode of source electrode and NM30 It is connected；The grid of the NM30 is connected with the drain electrode of the drain electrode of the grid of PM34, PM33 and NM33, PM42 and NM42 respectively；Institute The source electrode external power supply of PM32 is stated, the drain electrode of PM32 is connected with the source electrode of PM33；The grid of the PM33 and set-reset signal The signal output end of the reset signal r of generation circuit connects, and the drain electrode of PM33 is connect with the drain electrode of NM33 respectively；The NM33's The drain electrode of source electrode and NM32 connect, and the grid of the NM32 and the signal of the set signal sn of set-reset signal generating circuit are defeated Outlet connects；The drain electrode of the source electrode external power supply of the PM34, PM34 is connected with the source electrode of PM35 respectively；The grid of the PM35 The signal output end of inverting clock signal nclk2 generated with clocked inverter chain circuit is connect, the drain electrode of PM35 respectively with The drain electrode of NM35 connects；The signal for the in-phase clock signal bclk2 that the grid of the NM35 is generated with clocked inverter chain circuit Output end connects, the drain electrode connection of source electrode and NM34；The source electrode external power supply of the PM36, the source of the drain electrode and PM37 of PM36 Extremely it is connected；The grid of the PM37 is connect with the signal output end of the reset signal r of set-reset signal generating circuit, PM37's Drain electrode is connect with the drain electrode of NM37 respectively；The drain electrode of the source electrode and NM36 of the NM37 connects, the grid of the NM36 and set The signal output end of the set signal sn of reset signal generating circuit connects；The source electrode external power supply of the PM38, the leakage of PM38 Pole is connected with the source electrode of PM39 respectively；The inverting clock signal that the grid of the PM39 is generated with clocked inverter chain circuit The signal output end of nclk3 connects, and the drain electrode of PM39 is connect with the drain electrode of NM39 respectively；The grid and clock inversion of the NM39 The signal output end connection for the in-phase clock signal bclk3 that device chain circuit generates, the drain electrode connection of source electrode and NM38；It is described The drain electrode of the source electrode external power supply of PM40, PM40 is connected with the source electrode of PM41；The grid of the PM41 is produced with set-reset signal The signal output end connection of the reset signal r of raw circuit, the drain electrode of PM41 are connect with the drain electrode of NM41 respectively；The source of the NM41 The drain electrode of pole and NM40 connect, and the grid of the NM40 and the signal of the set signal sn of set-reset signal generating circuit export End connection；The grid of the PM42 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, source Pole external power supply, drain electrode are connect with the left data input port of the drain electrode of NM42, transmission gate TM4 respectively；The grid of the NM42 Pole is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM45 and the grid of NM46 It is extremely connect with the signal output end of the set signal sn of set-reset signal generating circuit, the source electrode external power supply of PM45, Drain electrode is connect with the drain electrode of the right side data-out port, NM46 of transmission gate TM4 respectively；The leakage of the source electrode and NM45 of the NM46 Pole connects, and the grid of the NM45 is connect with the signal output end of the reset signal r of set-reset signal generating circuit；It is described The drain electrode output of PM45 all the way data-signal m1 to from DICE latch cicuits；The grid of the PM43 is generated with set-reset signal The signal output end of the set signal sn of circuit connects, source electrode external power supply, drain electrode respectively with the drain electrode of NM43, transmission gate The left data input port of TM5 connects；The letter of the grid of the NM43 and the reset signal r of set-reset signal generating circuit The connection of number output end；The grid of the PM46 and the grid of NM48 are with the set signal sn's of set-reset signal generating circuit Signal output end connect, the source electrode external power supply of PM46, drain electrode respectively with the right side data-out port of transmission gate TM5, The drain electrode of NM48 connects；The drain electrode of the source electrode and NM47 of the NM48 connects, and grid and the set-reset signal of the NM47 produce The signal output end connection of the reset signal r of raw circuit；The drain electrode output another way data-signal m2 of the PM46 is extremely from DICE Latch cicuit；The grid of the PM44 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, Source electrode external power supply, drain electrode are connect with the left data input port of the drain electrode of NM44, transmission gate TM6 respectively；The NM44's Grid is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM47 and NM50's Grid is connect with the signal output end of the set signal sn of set-reset signal generating circuit, the source electrode external power supply of PM47, Its drain electrode is connect with the drain electrode of the right side data-out port, NM50 of transmission gate TM6 respectively；The source electrode of the NM50 and NM49's Drain electrode connection, the grid of the NM49 are connect with the signal output end of the reset signal r of set-reset signal generating circuit；It is described The drain electrode output another way data-signal m3 of PM47 is extremely from DICE latch cicuits；The NM27, NM28, NM29, NM30, NM32, The source grounding of NM34, NM36, NM38, NM40, NM42, NM43, NM44, NM45, NM47, NM49；The transmission gate TM1 The signal output end of inverting clock signal nclk1 that generates of same phase control end and clocked inverter chain circuit connect, transmission gate The inverted control terminals of TM1 are connect with the signal output end for the in-phase clock signal bclk1 that clocked inverter chain circuit generates, described The signal output end for the inverting clock signal nclk2 that the same phase control end of transmission gate TM2 is generated with clocked inverter chain circuit connects It connects, the signal output end of the inverted control terminals and the in-phase clock signal bclk2 of clocked inverter chain circuit generation of transmission gate TM2 Connection, the signal at the same phase control end and the inverting clock signal nclk3 of clocked inverter chain circuit generation of the transmission gate TM3 Output end connects, the letter of the inverted control terminals and the in-phase clock signal bclk3 of clocked inverter chain circuit generation of transmission gate TM3 The connection of number output end, the inverting clock signal that the inverted control terminals of the transmission gate TM4 are generated with clocked inverter chain circuit The signal output end of nclk1 connects, and the in-phase clock that same phase control end and the clocked inverter chain circuit of transmission gate TM4 generate is believed The signal output end connection of number bclk1, the reverse phase that the inverted control terminals of the transmission gate TM5 are generated with clocked inverter chain circuit The signal output end of clock signal nclk2 connects, and same phase control end and the clocked inverter chain circuit of transmission gate TM5 generate same The signal output end of clock signal bclk2 connects；The inverted control terminals of the transmission gate TM6 are given birth to clocked inverter chain circuit At inverting clock signal nclk3 signal output end connection, the same phase control end of transmission gate TM6 and clocked inverter chain circuit The signal output end of the in-phase clock signal bclk3 of generation connects；

It is described from DICE latch cicuits be by 15 PMOS tube PM48, PM49, PM50, PM51, PM52, PM53, PM54, PM55, PM56, PM57, PM58, PM59, PM60, PM61, PM62 and 15 NMOS tube NM51, NM52, NM53, NM54, NM55, NM56, NM57, NM58, NM59, NM60, NM61, NM62, NM63, NM64, NM65 are formed；The grid of the PM48 and set-reset signal The signal output end of the reset signal r of generation circuit connects, source electrode external power supply, and drain electrode is connect with the source electrode of PM49；It is described The grid of PM49 is connect with the grid of the drain electrode of PM59 and NM62, the grid of the grid of NM60 and PM60 and NM63 respectively, Drain electrode is connected with the source electrode of PM50；The in-phase clock signal bclk1 that the grid of the PM50 is generated with clocked inverter chain circuit Signal output end connection, PM50 drain electrode respectively with the drain electrode of NM53, the grid of PM51, the grid of NM62 and main DICE latch The output end connection of data-signal m1 all the way in circuit；When the reverse phase that the grid of the NM53 is generated with clocked inverter chain circuit The signal output end of clock signal nclk1 connects, and source electrode is connected with the drain electrode of NM52；The grid of the NM52 respectively with PM51 and The drain electrode of NM54, the grid of PM53 and PM62 are connected with the grid of NM65, and source electrode is connected with the drain electrode of NM51；The NM51 Grid connect with the signal output end of the set signal sn of set-reset signal generating circuit；The external electricity of source electrode of the PM51 Source, drain electrode are connect with the drain electrode of NM54；The grid of the NM54 respectively with the drain electrode of PM54 and NM57, the grid of PM55 and master The output end connection of data-signal m2 all the way in DICE latch cicuits；The grid of the PM52 and set-reset signal generating circuit Reset signal r signal output end connection, source electrode external power supply, drain electrode connect with the source electrode of PM53；The drain electrode of the PM53 It is connected with the source electrode of PM54；The letter for the in-phase clock signal bclk2 that the grid of the PM54 is generated with clocked inverter chain circuit The connection of number output end, the drain electrode of PM54 are connect with the drain electrode of NM57；The grid of the NM57 is generated with clocked inverter chain circuit Inverting clock signal nclk2 signal output end connection, source electrode is connected with the drain electrode of NM56；The source electrode of the NM56 with The drain electrode of NM55 is connected；The grid of the NM55 and the signal output end of the set signal sn of set-reset signal generating circuit connect It connects；The source electrode external power supply of the PM55, drain electrode are connect with the drain electrode of NM58；The grid of the NM58 respectively with PM58 and NM61 Drain electrode, PM59 grid with the output end of data-signal m3 connects all the way in main DICE latch cicuits；The grid of the PM56 It is connect with the signal output end of the reset signal r of set-reset signal generating circuit, source electrode external power supply, the source of drain electrode and PM57 Pole connects；The drain electrode of the PM57 is connected with the source electrode of PM58；The grid of the PM58 is generated with clocked inverter chain circuit The signal output end of in-phase clock signal bclk3 connects, and the drain electrode of PM58 is connect with the drain electrode of NM61；The grid of the NM61 with The signal output end connection for the inverting clock signal nclk3 that clocked inverter chain circuit generates, the drain electrode phase of source electrode and NM60 Even；The source electrode of the NM60 is connected with the drain electrode of NM59；The set of the grid and set-reset signal generating circuit of the NM59 The signal output end of signal sn connects；The source electrode external power supply of the PM59, drain electrode are connect with the drain electrode of NM62；The PM60's Source electrode external power supply, drain electrode are connect with the source electrode of PM61；The grid of the PM61 and the grid of NM64 connect, drain electrode and PM62 Source electrode connection, the drain electrode of the PM62 connect with the drain electrode of NM65；The source electrode of the NM65 is connected with the drain electrode of NM64, NM64 Source electrode and NM63 drain electrode connect；The drain electrode outputting data signals Q of the PM62；The NM51, NM54, NM55, NM58, The source grounding of NM59, NM62, NM63.

In the above-mentioned technical solutions, when rising edge clock signal arrives, if data terminal D is receiving a SET just just Pulse carries out asynchronous reset, conversely, working as then reset-set signal generating circuit will generate a reset signal r to trigger When data terminal D receives a SET negative pulse, reset-set signal generating circuit generates a set signal sn, to trigger Asynchronous set is carried out, when trigger is not at rising edge clock signal or data terminal D does not have SET pulse interference, resets letter Number and set signal all in invalid state, r is low level, and sn is high level, at this time circuit maintain normal work.Due to not having Using C cell filter circuit, the settling time of the trigger will shorten, and to make timing performance be improved, improve electricity The working frequency on road.The circuit also uses three and mutually latches simultaneously（TICE）Technology, relative to the common anti-spoke based on DICE Trigger is penetrated, there is better anti-SEU characteristics.

Description of the drawings

Fig. 1 is the principle assumption diagram that flip-flop circuit is mutually latched on a kind of three tunnels detected based on transmission gate and SET of the present invention；

Fig. 2 is the clocked inverter chain electricity that flip-flop circuit is mutually latched on a kind of three tunnels detected based on transmission gate and SET of the present invention Lu Tu；

Fig. 3 is the D input inverters chain electricity that flip-flop circuit is mutually latched on a kind of three tunnels detected based on transmission gate and SET of the present invention Lu Tu；

Fig. 4 is the set-reset signal production that flip-flop circuit is mutually latched on a kind of three tunnels detected based on transmission gate and SET of the present invention Raw circuit diagram；

Fig. 5 is the main DICE latch cicuits that flip-flop circuit is mutually latched on a kind of three tunnels detected based on transmission gate and SET of the present invention Figure；

Fig. 6 is the slave DICE latch cicuits that flip-flop circuit is mutually latched on a kind of three tunnels detected based on transmission gate and SET of the present invention Figure；

Fig. 7 is that set-reset signal production in flip-flop circuit is mutually latched on a kind of three tunnels detected based on transmission gate and SET of the present invention The reset signal r of raw circuit generates sequence diagram；

Fig. 8 is that set-reset signal production in flip-flop circuit is mutually latched on a kind of three tunnels detected based on transmission gate and SET of the present invention The set signal sn of raw circuit generates sequence diagram.

Specific implementation mode

The mutual latched flip flop in three tunnels detected based on transmission gate and SET a kind of to the present invention with reference to the accompanying drawings and examples Circuit is described in further detail.The attached drawing for constituting the application is used to provide further understanding of the present invention, and of the invention shows Meaning property embodiment and its explanation are not constituted improper limitations of the present invention for explaining the present invention.

By Fig. 1-Fig. 6 as it can be seen that a kind of mutual latched flip flop electricity in three tunnels detected based on transmission gate and SET of the present embodiment Road includes clocked inverter chain circuit, D input inverters chain circuit, set-reset signal generating circuit, main DICE latch cicuits With from DICE latch cicuits.External clock signal CK is separately input to clocked inverter chain circuit and set-reset signal generates Circuit, external clock signal CK generate three road in-phase clock signal bclk1, bclk2, bclk3 through clocked inverter chain circuit With three road inverting clock signal nclk1, nclk2, nclk3；External data signal D is separately input to D input inverter chain circuits With set-reset signal generating circuit, external data signal D generates two circuit-switched data signal d1, d2 through D input inverter chain circuits Anti-phase data signal nd all the way；Clock signal CK, data-signal D, D input inverter chain circuit generate data-signal d1 all the way Anti-phase data signal nd and two road inverting clock signal nclk1, nclk2 and all the way in-phase clock signal bclk2 warps all the way Set signal sn and reset signal r is exported after set-reset signal generating circuit；The data-signal D, three road in-phase clock letters Number bclk1, bclk2, bclk3 and three road inverting clock signal nclk1, nclk2, nclk3 and two circuit-switched data signal d1, d2 and Set signal sn and reset signal r is input to main DICE latch cicuits, and three data signal is exported after main DICE latch cicuits m1,m2,m3；The set signal sn and reset signal r, three road in-phase clock signals of the set-reset signal generating circuit output What bclk1, bclk2, bclk3 and three road inverting clock signal nclk1, nclk2, nclk3 and main DICE latch cicuits were exported Three data signal m1, m2 and m3 are input to from DICE latch cicuits, and then output data is believed after from DICE latch cicuits Number Q.

By Fig. 1, Fig. 2 as it can be seen that the clocked inverter chain circuit of the present embodiment be by 12 PMOS tube PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12 and 12 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12 are formed.The PM1 and NM1, PM2 and NM2, PM3 and NM3, PM4 and NM4, PM5 and NM5, PM6 and NM6, PM7 and NM7, PM8 and NM8, PM9 and NM9, PM10 and NM10, PM11 and NM11, PM12 and NM12 difference A phase inverter is constituted, the clock signal CK is connect with the input terminal of phase inverter PM1 and NM1, defeated after inverted device PM1 and NM1 Go out inverting clock signal nclk1；The input terminal of the phase inverter PM2 and NM2 is connect with the output end of phase inverter PM1 and NM1, warp In-phase clock signal bclk1 is exported after phase inverter PM2 and NM2；The input terminal of the phase inverter PM3 and NM3 and clock signal CK Connection, output end are connect with the input terminal of phase inverter PM4 and NM4, input terminal and the phase inverter PM4 of the phase inverter PM5 and NM5 It is connected with the output end of NM4, output end is connect with the input terminal of phase inverter PM6 and NM6, the inverted device PM3 of clock signal CK When with being exported with phase after output inverting clock signal nclk2, then inverted device PM6 and NM6 after NM3, PM4 and NM4, PM5 and NM5 Clock signal bclk2；The input terminal of the phase inverter PM7 and NM7 is connect with clock signal CK, output end and phase inverter PM8 and NM8 Input terminal connection, the input terminal of the phase inverter PM9 and NM9 connect with the output end of phase inverter PM8 and NM8, output end It is connect with the input terminal of phase inverter PM10 and NM10, input terminal and the phase inverter PM10 and NM10 of the phase inverter PM11 and NM11 Output end connection, output end connect with the input terminal of phase inverter PM12 and NM12, the inverted device PM7 of clock signal CK with Inverting clock signal nclk3, then inverted device are exported after NM7, PM8 and NM8, PM9 and NM9, PM10 and NM10, PM11 and NM11 In-phase clock signal bclk3 is exported after PM12 and NM12.

By Fig. 1, Fig. 3 as it can be seen that the D input inverter chain circuits of the present embodiment be by 4 PMOS tube PM13, PM14, PM15, PM16 and 4 NMOS tube NM13, NM14, NM15, NM16 composition；The PM13 and NM13, PM14 and NM14, PM15 and NM15, PM16 and NM16 respectively constitutes a phase inverter；The data-signal D is connect with the input terminal of phase inverter PM13 and NM13, inverted Reverse data signal nd is exported after device PM13 and NM13；The anti-phase data signal nd is input to the defeated of phase inverter PM14 and NM14 Enter to hold, outputting data signals d1 after inverted device PM14 and NM14；The input terminal and phase inverter of the phase inverter PM15 and NM15 PM14 is connected with the output end of NM14, and output end exports reverse data signal nd1, and the anti-phase data signal nd1 is input to instead The input terminal of phase device PM16 and NM16, outputting data signals d2 after inverted device PM16 and NM16.

By Fig. 1, Fig. 4 as it can be seen that the set-reset signal generating circuit of the present embodiment be by 10 PMOS tube PM17, PM18, PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26 and 10 NMOS tube NM17, NM18, NM19, NM20, NM21, NM22, NM23, NM24, NM25, NM26 are formed；The grid of the PM21 and NM21 is connect with the output end of clock signal CK；Institute It states the grid of PM20 and NM20 and the signal output end of inverting clock signal nclk2 that clocked inverter chain circuit generates is connect, The grid of the PM19 and NM19 is connect with the signal output end for the data-signal d1 that D input inverter chain circuits generate, described The grid of PM18 and NM18 is connect with the signal output end for the reverse data signal nd that D input inverter chain circuits generate, described The grid external data signal D of PM17 and NM17；The equal external power supply of source electrode of described PM17, PM18, PM19, PM20, PM21；Institute The drain electrode for stating PM17, PM18, PM19, PM20, PM21 is defeated with the signal of the set signal sn of set-reset signal generating circuit Outlet connects；The drain electrode of the NM21 is connect with the drain electrode of PM17, and the source electrode of NM21 is connected with the drain electrode of NM20, the source electrode of NM20 It is connected with the drain electrode of NM19, the source electrode of NM19 is connected with the drain electrode of NM18, and the source electrode of NM18 is connected with the drain electrode of NM17, NM17's Source electrode is grounded；The signal for the inverting clock signal nclk1 that the grid of the PM22 and NM22 is generated with clocked inverter chain circuit Output end connects；The letter for the in-phase clock signal bclk2 that the grid of the PM23 and NM23 is generated with clocked inverter chain circuit The signal of the connection of number output end, the data-signal d1 that the grid and D input inverter chain circuits of the PM24 and NM24 generate is defeated Outlet connects, and the signal for the reverse data signal nd that the grid and D input inverter chain circuits of the PM25 and NM25 generate is defeated Outlet connects, the grid external data signal D of the PM26 and NM26；The source electrode external power supply of the PM22；The PM22's Drain electrode is connect with the source electrode of PM23, and the drain electrode of the PM23 is connect with the source electrode of PM24, the source of the drain electrode and PM25 of the PM24 Pole connects, and the drain electrode of PM25 is connect with the source electrode of PM26, and the drain electrode of the PM26 is connect with the drain electrode of NM26, the NM22, The drain electrode of NM23, NM24, NM25, NM26 are connect with the signal output end of the reset signal r of set-reset signal generating circuit； The source grounding of described NM22, NM23, NM24, NM25, NM26.

By Fig. 1, Fig. 5 as it can be seen that the main DICE latch cicuits of the present embodiment be by 21 PMOS tube PM27, PM28, PM29, PM30、PM31、PM32、PM33、PM34、PM35 、PM36、PM37、PM38、PM39、PM40、PM41、PM42 、PM43、PM44、 PM45, PM46, PM47 and 24 NMOS tube NM27, NM28, NM29, NM30, NM31, NM32, NM33, NM34, NM35, NM36, NM37, NM38, NM39, NM40, NM41, NM42, NM43, NM44, NM45, NM46, NM47, NM48, NM49, NM50 and 6 transmission gate TM1, TM2, TM3, TM4, TM5, TM6 compositions；The grid external data signal D of the PM27, and with the grid of NM27 Extremely it is connected, the source electrode external power supply of PM27, drain electrode connects with the left data input port of the drain electrode of NM27 and transmission gate TM1 respectively Connect, the right side data port of the transmission gate TM1 respectively with the drain electrode of the grid of PM32, PM31 and NM31 and the grid of NM41 Connection；The grid external data signal d1 of the PM28, and be connected with the grid of NM28, the source electrode external power supply of PM28, drain electrode It is connect respectively with the left data input port of the drain electrode of NM28 and transmission gate TM2, the right side data port of the transmission gate TM2 It is connect respectively with the grid of the drain electrode of the grid of PM36, PM35 and NM35 and NM33；The grid external data of the PM29 is believed Number d2, and being connected with the grid of NM29, the source electrode external power supply of PM29, drain electrode respectively with the drain electrode of NM29 and transmission gate TM3 Left data input port connects, the right side data port of the transmission gate TM3 respectively with the grid of PM40, PM39 and NM39 The connection of the grid of drain electrode and NM37；The grid of the PM30 respectively with the drain electrode of the drain electrode of PM41 and NM41, PM44 and NM44, The grid of NM38 is connected, the source electrode external power supply of PM30, and drain electrode connects with the source electrode of PM31；The grid of the PM31 and clock are anti- Phase device chain circuit generate inverting clock signal nclk1 signal output end connection, PM31 drain electrode respectively with the drain electrode of NM31 It is connected；The grid of the NM31 is connect with the signal output end for the in-phase clock signal bclk1 that clocked inverter chain circuit generates, Its source electrode is connected with the drain electrode of NM30；The grid of the NM30 respectively with the drain electrode of the grid of PM34, PM33 and NM33, PM42 and The drain electrode of NM42 is connected；The drain electrode of the source electrode external power supply of the PM32, PM32 is connected with the source electrode of PM33；The grid of the PM33 Pole is connect with the signal output end of the reset signal r of set-reset signal generating circuit, PM33 drain electrode respectively with the leakage of NM33 Pole connects；The drain electrode of the source electrode and NM32 of the NM33 connects, grid and the set-reset signal generating circuit of the NM32 The signal output end of set signal sn connects；The source electrode external power supply of the PM34, PM34 drain electrode respectively with the source electrode of PM35 It is connected；The grid of the PM35 is connect with the signal output end for the inverting clock signal nclk2 that clocked inverter chain circuit generates, The drain electrode of PM35 is connect with the drain electrode of NM35 respectively；The in-phase clock that the grid of the NM35 is generated with clocked inverter chain circuit The signal output end of signal bclk2 connects, the drain electrode connection of source electrode and NM34；The source electrode external power supply of the PM36, PM36 Drain electrode be connected with the source electrode of PM37；The signal of the grid of the PM37 and the reset signal r of set-reset signal generating circuit Output end connects, and the drain electrode of PM37 is connect with the drain electrode of NM37 respectively；The drain electrode of the source electrode and NM36 of the NM37 connects, described The grid of NM36 is connect with the signal output end of the set signal sn of set-reset signal generating circuit；Outside the source electrode of the PM38 Power supply is connect, the drain electrode of PM38 is connected with the source electrode of PM39 respectively；The grid of the PM39 is generated with clocked inverter chain circuit The signal output end of inverting clock signal nclk3 connects, and the drain electrode of PM39 is connect with the drain electrode of NM39 respectively；The grid of the NM39 Pole is connect with the signal output end for the in-phase clock signal bclk3 that clocked inverter chain circuit generates, the leakage of source electrode and NM38 Pole connects；The drain electrode of the source electrode external power supply of the PM40, PM40 is connected with the source electrode of PM41；The grid of the PM41 and set The signal output end of the reset signal r of reset signal generating circuit connects, and the drain electrode of PM41 is connect with the drain electrode of NM41 respectively；Institute The drain electrode for stating the source electrode and NM40 of NM41 connects, the grid of the NM40 and the set signal sn of set-reset signal generating circuit Signal output end connection；The signal output end of the grid of the PM42 and the set signal sn of set-reset signal generating circuit Connection, source electrode external power supply, drain electrode are connect with the left data input port of the drain electrode of NM42, transmission gate TM4 respectively；It is described The grid of NM42 is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM45 and The grid of NM46 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, and the source electrode of PM45 is external Power supply, drain electrode are connect with the drain electrode of the right side data-out port, NM46 of transmission gate TM4 respectively；The source electrode of the NM46 with The drain electrode of NM45 connects, and the grid of the NM45 and the signal output end of the reset signal r of set-reset signal generating circuit connect It connects；The drain electrode output of the PM45 all the way data-signal m1 to from DICE latch cicuits；The grid and set-reset of the PM43 The signal output end of the set signal sn of signal generating circuit connects, source electrode external power supply, drain electrode respectively with the drain electrode of NM43, The left data input port of transmission gate TM5 connects；The grid of the NM43 is believed with the reset of set-reset signal generating circuit The signal output end connection of number r；The set of the grid of the PM46 and the grid of NM48 with set-reset signal generating circuit The signal output end of signal sn connects, the source electrode external power supply of PM46, and drain electrode is exported with the right side data of transmission gate TM5 respectively The drain electrode connection of port, NM48；The drain electrode of the source electrode and NM47 of the NM48 connects, and grid and the set-reset of the NM47 are believed The signal output end connection of the reset signal r of number generation circuit；The drain electrode output another way data-signal m2 of the PM46 to from DICE latch cicuits；The grid of the PM44 and the signal output end of the set signal sn of set-reset signal generating circuit connect It connects, source electrode external power supply, drain electrode is connect with the left data input port of the drain electrode of NM44, transmission gate TM6 respectively；It is described The grid of NM44 is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM47 and The grid of NM50 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, and the source electrode of PM47 is external Power supply, drain electrode are connect with the drain electrode of the right side data-out port, NM50 of transmission gate TM6 respectively；The source electrode of the NM50 with The drain electrode of NM49 connects, and the grid of the NM49 and the signal output end of the reset signal r of set-reset signal generating circuit connect It connects；The drain electrode output another way data-signal m3 of the PM47 is extremely from DICE latch cicuits；The NM27, NM28, NM29, The source grounding of NM30, NM32, NM34, NM36, NM38, NM40, NM42, NM43, NM44, NM45, NM47, NM49；It is described The signal output end for the inverting clock signal nclk1 that the same phase control end of transmission gate TM1 is generated with clocked inverter chain circuit connects It connects, the signal output end of the inverted control terminals and the in-phase clock signal bclk1 of clocked inverter chain circuit generation of transmission gate TM1 Connection, the signal at the same phase control end and the inverting clock signal nclk2 of clocked inverter chain circuit generation of the transmission gate TM2 Output end connects, the letter of the inverted control terminals and the in-phase clock signal bclk2 of clocked inverter chain circuit generation of transmission gate TM2 The connection of number output end, the inverting clock signal that the same phase control end of the transmission gate TM3 is generated with clocked inverter chain circuit The signal output end of nclk3 connects, and the in-phase clock that inverted control terminals and the clocked inverter chain circuit of transmission gate TM3 generate is believed The signal output end connection of number bclk3, the reverse phase that the inverted control terminals of the transmission gate TM4 are generated with clocked inverter chain circuit The signal output end of clock signal nclk1 connects, and same phase control end and the clocked inverter chain circuit of transmission gate TM4 generate same The signal output end of clock signal bclk1 connects, and inverted control terminals and the clocked inverter chain circuit of the transmission gate TM5 are given birth to At inverting clock signal nclk2 signal output end connection, the same phase control end of transmission gate TM5 and clocked inverter chain circuit The signal output end of the in-phase clock signal bclk2 of generation connects；The inverted control terminals and clocked inverter of the transmission gate TM6 The signal output end connection for the inverting clock signal nclk3 that chain circuit generates, the same phase control end of transmission gate TM6 and clock inversion The signal output end connection for the in-phase clock signal bclk3 that device chain circuit generates.

By Fig. 1, Fig. 6 as it can be seen that the slave DICE latch cicuits of the present embodiment be by 15 PMOS tube PM48, PM49, PM50, PM51, PM52, PM53, PM54, PM55, PM56, PM57, PM58, PM59, PM60, PM61, PM62 and 15 NMOS tube NM51, NM52, NM53, NM54, NM55, NM56, NM57, NM58, NM59, NM60, NM61, NM62, NM63, NM64, NM65 are formed；Institute The signal output end for stating the grid of PM48 and the reset signal r of set-reset signal generating circuit is connect, source electrode external power supply, leakage The source electrode of pole and PM49 connect；The grid of the PM49 respectively with the drain electrode of PM59 and NM62, the grid of the grid of NM60 and PM60 The grid of pole and NM63 connect, and drain electrode is connected with the source electrode of PM50；The grid of the PM50 and clocked inverter chain circuit The signal output end of the in-phase clock signal bclk1 of generation connects, the drain electrode of PM50 respectively with the drain electrode of NM53, the grid of PM51 Pole, NM62 grid with the output end of data-signal m1 connects all the way in main DICE latch cicuits；The grid of the NM53 and when The signal output end of the inverting clock signal nclk1 of clock chain of inverters circuit evolving connects, and source electrode is connected with the drain electrode of NM52； The grid of the NM52 is connect with the grid of the drain electrode of PM51 and NM54, the grid of PM53 and PM62 and NM65 respectively, source Pole is connected with the drain electrode of NM51；The grid of the NM51 and the signal of the set signal sn of set-reset signal generating circuit export End connection；The source electrode external power supply of the PM51, drain electrode are connect with the drain electrode of NM54；The grid of the NM54 respectively with PM54 and The output end of data-signal m2 connects all the way in the drain electrode of NM57, the grid of PM55 and main DICE latch cicuits；The PM52's Grid is connect with the signal output end of the reset signal r of set-reset signal generating circuit, source electrode external power supply, drain electrode and PM53 Source electrode connection；The drain electrode of the PM53 is connected with the source electrode of PM54；The grid of the PM54 is given birth to clocked inverter chain circuit At in-phase clock signal bclk2 signal output end connection, the drain electrode of PM54 connect with the drain electrode of NM57；The grid of the NM57 Pole is connect with the signal output end for the inverting clock signal nclk2 that clocked inverter chain circuit generates, the leakage of source electrode and NM56 Extremely it is connected；The source electrode of the NM56 is connected with the drain electrode of NM55；The grid of the NM55 and set-reset signal generating circuit The signal output end of set signal sn connects；The source electrode external power supply of the PM55, drain electrode are connect with the drain electrode of NM58；It is described The grid of NM58 respectively with data-signal m3 all the way in the drain electrode of PM58 and NM61, the grid of PM59 and main DICE latch cicuits Output end connects；The grid of the PM56 is connect with the signal output end of the reset signal r of set-reset signal generating circuit, source Pole external power supply, drain electrode are connect with the source electrode of PM57；The drain electrode of the PM57 is connected with the source electrode of PM58；The grid of the PM58 It is connect with the signal output end of the in-phase clock signal bclk3 of clocked inverter chain circuit generation, the drain electrode of PM58 is with NM61's Drain electrode connection；The signal output end for the inverting clock signal nclk3 that the grid of the NM61 is generated with clocked inverter chain circuit Connection, source electrode are connected with the drain electrode of NM60；The source electrode of the NM60 is connected with the drain electrode of NM59；The grid of the NM59 with set The signal output end connection of the set signal sn of position reset signal generating circuit；The source electrode external power supply of the PM59, drain electrode with The drain electrode of NM62 connects；The source electrode external power supply of the PM60, drain electrode are connect with the source electrode of PM61；The grid of the PM61 with The grid of NM64 connects, and drain electrode is connect with the source electrode of PM62, and the drain electrode of the PM62 is connect with the drain electrode of NM65；The NM65 Source electrode be connected with the drain electrode of NM64, the drain electrode of the source electrode of NM64 and NM63 connect；The drain electrode outputting data signals of the PM62 Q；The source grounding of described NM51, NM54, NM55, NM58, NM59, NM62, NM63.

As seen from Figure 7, the present embodiment generated on sequence diagram from reset signal r as can be seen that nclk1 signals be by PM1 and The inverting clock signal that the phase inverter that NM1 is constituted generates, certain delay is will produce relative to CK signals, likewise, bclk1 believes Number it is the in-phase clock signal generated by the phase inverter that PM2 and NM2 are constituted, there is also certain to prolong relative to nclk1 by bclk1 When, the appropriate breadth length ratio that each metal-oxide-semiconductor in clocked inverter chain circuit is arranged, can making nclk2, there are one with respect to bclk1 Fixed delay, there is also certain delays with respect to nclk2 by bclk2.

If in rising edge clock, when data input pin D receives a SET positive pulse, this positive pulse is possible to meeting Allow the TICE structures of trigger to store data of this mistake, but being generated on sequence diagram in reset signal r can be with just Find out, in the period between two dotted lines, D, nd, d1, nclk1 and bclk2 are all in low level state, and in Fig. 4 The nor gate that NM22 ~ NM26 and PM22 ~ PM26 are constituted, simultaneously and if only if D, nd, d1, nclk1 and bclk2 this five signals For low level when, it is high level to export as r, and when r signals be high level when, can by main TICE latch cicuits and from TICE latch Circuit resets simultaneously, so that it is guaranteed that trigger is not influenced by SET positive pulses.

In the present embodiment, r signals are high level effectively and sn signals are when being that high level is invalid, main TICE and are in from TICE Reset state, the principle resetted are as follows：PM33 and PM42 cut-offs, NM42 conductings, to make node a1 be reset to low level. PM37 and PM43 cut-offs, NM43 conductings, to make node a2 be reset to low level.PM41 and PM44 cut-offs, NM44 conductings, to Node a3 is set to be reset to low level.

In the present embodiment, PM45 and PM48 cut-offs, NM45 and NM46 are connected, to make node m1 be reset to low level. PM46 and PM52 cut-offs, NM47 and NM48 conductings, to make node m2 be reset to low level.PM47 and PM56 cut-off, NM49 and NM50 is connected, to make node m3 be reset to low level.When m1, m2 and m3 are reset to low level, by TICE, mutually latch acts on It influences, q1, q2 and q3 can become high level, be low level so as to cause output Q.

Similar, as seen from Figure 8, in the present embodiment, if in rising edge clock, data input pin D receives a SET When negative pulse, this negative pulse is possible to that the TICE structures of trigger can be allowed to store the data of this mistake just, but It is generated in the period that can be seen that on sequence diagram between two dotted lines in set signal sn, D, nd, d1, CK and nclk2 are The NAND gate that NM17 ~ NM21 and PM17 ~ PM21 in high level state, and in Fig. 4 are constituted, and if only if D, d1, d2, CK When being high level simultaneously with this five signals of nclk2, it is low level to export as sn, and when sn signals are low level, it can be by master TICE latch cicuits and from TICE latch cicuits simultaneously set, so that it is guaranteed that trigger is not influenced by SET negative pulses.

In the present embodiment, sn signals are low level effectively and r signals are when being that low level is invalid, main TICE and are in from TICE The principle of SM set mode, set is as follows：NM32 and NM42 cut-offs, PM42 conductings, to make node a1 set be high level. NM36 and NM43 cut-offs, PM43 conductings, to make node a2 set be high level.NM40 and NM44 cut-offs, PM44 conductings, to It is high level to make node a3 set.

In the present embodiment, PM45 conductings, NM45, NM46 and NM51 cut-off, to make node m1 set be high level.PM46 Conducting, NM47, NM48 and NM55 cut-off, to make node m2 set be high level.PM47 is connected, and NM49, NM50 and NM59 are cut Only, to make node m3 set be high level.When m1, m2 and m3 set are high level, function influence is mutually latched by TICE, Q1, q2 and q3 can become low level, be high level so as to cause output Q.

Three tunnels based on SET detections described in the present embodiment are mutually latched flip-flop circuit and are filtered based on previous C cell Radioresistance trigger is compared, and to more advanced in the SET pulse processing mode of data input pin, be embodied in and withouted waiting for inputting The filtering of data, the data no matter sampled are high level or low level, can all be sent directly into main TICE latches Get up, then judges whether the data being sent into are SET pulse and decide whether pair by set-reset signal generating circuit Trigger carries out set or reset, reduces the larger settling time of filtering wave by prolonging time generation, to make the sequential of trigger Performance is more preferable.

The above is only the embodiment of the present invention, is not imposed any restrictions to the present invention, every according to the technology of the present invention Essence still falls within the technology of the present invention to any simple modification, change and the variation of equivalent method made by above example In the protection domain of scheme.

Claims

1. flip-flop circuit is mutually latched on a kind of three tunnels detected based on transmission gate and SET, it is characterised in that：It mutually latches on three tunnel Flip-flop circuit includes clocked inverter chain circuit, D input inverters chain circuit, set-reset signal generating circuit, main DICE Latch cicuit and from DICE latch cicuits；External clock signal CK is separately input to clocked inverter chain circuit and set-reset Signal generating circuit, external clock signal CK through clocked inverter chain circuit generate three road in-phase clock signal bclk1, Bclk2, bclk3 and three road inverting clock signal nclk1, nclk2, nclk3；It is anti-that external data signal D is separately input to D inputs Phase device chain circuit and set-reset signal generating circuit, external data signal D generate two circuit-switched datas through D input inverter chain circuits Signal d1, d2 and all the way anti-phase data signal nd；Clock signal CK, data-signal D, D input inverter chain circuit generate all the way Data-signal d1 and all the way anti-phase data signal nd and two road inverting clock signal nclk1, nclk2 and all the way in-phase clock are believed Number bclk2 exports set signal sn and reset signal r after set-reset signal generating circuit；The data-signal D, three tunnels are same Clock signal bclk1, bclk2, bclk3 and three road inverting clock signal nclk1, nclk2, nclk3 and two circuit-switched data signals D1, d2 and set signal sn and reset signal r are input to main DICE latch cicuits, and three tunnels are exported after main DICE latch cicuits Data-signal m1, m2, m3；The set signal sn and reset signal r, the same phase in three tunnels of the set-reset signal generating circuit output Clock signal bclk1, bclk2, bclk3 and three road inverting clock signal nclk1, nclk2, nclk3 and main DICE latch electricity Three data signal m1, m2 and m3 of road output are input to from DICE latch cicuits, then defeated after from DICE latch cicuits Go out data-signal Q；

The main DICE latch cicuits be by 21 PMOS tube PM27, PM28, PM29, PM30, PM31, PM32, PM33, PM34, PM35, PM36, PM37, PM38, PM39, PM40, PM41, PM42, PM43, PM44, PM45, PM46, PM47 and 24 NMOS Pipe NM27, NM28, NM29, NM30, NM31, NM32, NM33, NM34, NM35, NM36, NM37, NM38, NM39, NM40, NM41, NM42, NM43, NM44, NM45, NM46, NM47, NM48, NM49, NM50 and 6 transmission gate TM1, TM2, TM3, TM4, TM5, TM6 are formed；The grid external data signal D of the PM27, and be connected with the grid of NM27, the source electrode of PM27 is external Power supply, drain electrode are connect with the left data input port of the drain electrode of NM27 and transmission gate TM1 respectively, the right side of the transmission gate TM1 Side data port is connect with the grid of the drain electrode of the grid of PM32, PM31 and NM31 and NM41 respectively；The grid of the PM28 External data signal d1, and being connected with the grid of NM28, the source electrode external power supply of PM28, drain electrode respectively with the drain electrode of NM28 and biography The left data input port of defeated door TM2 connects, the right side data port of the transmission gate TM2 respectively with the grid of PM36, PM35 is connected with the grid of the drain electrode of NM35 and NM33；The grid external data signal d2 of the PM29, and with the grid of NM29 Extremely it is connected, the source electrode external power supply of PM29, drain electrode connects with the left data input port of the drain electrode of NM29 and transmission gate TM3 respectively Connect, the right side data port of the transmission gate TM3 respectively with the drain electrode of the grid of PM40, PM39 and NM39 and the grid of NM37 Connection；The grid of the PM30 is connected with the grid of the drain electrode of the drain electrode of PM41 and NM41, PM44 and NM44, NM38 respectively, The source electrode external power supply of PM30, drain electrode connect with the source electrode of PM31；The grid of the PM31 is generated with clocked inverter chain circuit Inverting clock signal nclk1 signal output end connection, the drain electrode of PM31 is connected with the drain electrode of NM31 respectively；The NM31's Grid is connect with the signal output end for the in-phase clock signal bclk1 that clocked inverter chain circuit generates, source electrode and NM30's Drain electrode is connected；The grid of the NM30 drain electrode phase with the drain electrode of the grid of PM34, PM33 and NM33, PM42 and NM42 respectively Even；The drain electrode of the source electrode external power supply of the PM32, PM32 is connected with the source electrode of PM33；The grid and set-reset of the PM33 The signal output end of the reset signal r of signal generating circuit connects, and the drain electrode of PM33 is connect with the drain electrode of NM33 respectively；It is described The drain electrode of the source electrode and NM32 of NM33 connects, and the grid of the NM32 is with the set signal sn's of set-reset signal generating circuit Signal output end connects；The drain electrode of the source electrode external power supply of the PM34, PM34 is connected with the source electrode of PM35 respectively；The PM35 The signal output end of inverting clock signal nclk2 that generates of grid and clocked inverter chain circuit connect, the drain electrode point of PM35 It is not connect with the drain electrode of NM35；The in-phase clock signal bclk2's that the grid of the NM35 is generated with clocked inverter chain circuit Signal output end connects, the drain electrode connection of source electrode and NM34；The source electrode external power supply of the PM36, the drain electrode of PM36 and PM37 Source electrode be connected；The grid of the PM37 is connect with the signal output end of the reset signal r of set-reset signal generating circuit, The drain electrode of PM37 is connect with the drain electrode of NM37 respectively；The drain electrode of the source electrode and NM36 of the NM37 connects, the grid of the NM36 It is connect with the signal output end of the set signal sn of set-reset signal generating circuit；The source electrode external power supply of the PM38, The drain electrode of PM38 is connected with the source electrode of PM39 respectively；The inversion clock that the grid of the PM39 is generated with clocked inverter chain circuit The signal output end of signal nclk3 connects, and the drain electrode of PM39 is connect with the drain electrode of NM39 respectively；The grid and clock of the NM39 The signal output end of the in-phase clock signal bclk3 of chain of inverters circuit evolving connects, the drain electrode connection of source electrode and NM38；Institute The source electrode external power supply of PM40 is stated, the drain electrode of PM40 is connected with the source electrode of PM41；The grid of the PM41 and set-reset signal The signal output end of the reset signal r of generation circuit connects, and the drain electrode of PM41 is connect with the drain electrode of NM41 respectively；The NM41's The drain electrode of source electrode and NM40 connect, and the grid of the NM40 and the signal of the set signal sn of set-reset signal generating circuit are defeated Outlet connects；The grid of the PM42 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, Source electrode external power supply, drain electrode are connect with the left data input port of the drain electrode of NM42, transmission gate TM4 respectively；The NM42's Grid is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM45 and NM46's Grid is connect with the signal output end of the set signal sn of set-reset signal generating circuit, the source electrode external power supply of PM45, Its drain electrode is connect with the drain electrode of the right side data-out port, NM46 of transmission gate TM4 respectively；The source electrode of the NM46 and NM45's Drain electrode connection, the grid of the NM45 are connect with the signal output end of the reset signal r of set-reset signal generating circuit；It is described The drain electrode output of PM45 all the way data-signal m1 to from DICE latch cicuits；The grid of the PM43 is generated with set-reset signal The signal output end of the set signal sn of circuit connects, source electrode external power supply, drain electrode respectively with the drain electrode of NM43, transmission gate The left data input port of TM5 connects；The letter of the grid of the NM43 and the reset signal r of set-reset signal generating circuit The connection of number output end；The grid of the PM46 and the grid of NM48 are with the set signal sn's of set-reset signal generating circuit Signal output end connect, the source electrode external power supply of PM46, drain electrode respectively with the right side data-out port of transmission gate TM5, The drain electrode of NM48 connects；The drain electrode of the source electrode and NM47 of the NM48 connects, and grid and the set-reset signal of the NM47 produce The signal output end connection of the reset signal r of raw circuit；The drain electrode output another way data-signal m2 of the PM46 is extremely from DICE Latch cicuit；The grid of the PM44 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, Source electrode external power supply, drain electrode are connect with the left data input port of the drain electrode of NM44, transmission gate TM6 respectively；The NM44's Grid is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM47 and NM50's Grid is connect with the signal output end of the set signal sn of set-reset signal generating circuit, the source electrode external power supply of PM47, Its drain electrode is connect with the drain electrode of the right side data-out port, NM50 of transmission gate TM6 respectively；The source electrode of the NM50 and NM49's Drain electrode connection, the grid of the NM49 are connect with the signal output end of the reset signal r of set-reset signal generating circuit；It is described The drain electrode output another way data-signal m3 of PM47 is extremely from DICE latch cicuits；The NM27, NM28, NM29, NM30, NM32, The source grounding of NM34, NM36, NM38, NM40, NM42, NM43, NM44, NM45, NM47, NM49；The transmission gate TM1 The signal output end of inverting clock signal nclk1 that generates of same phase control end and clocked inverter chain circuit connect, transmission gate The inverted control terminals of TM1 are connect with the signal output end for the in-phase clock signal bclk1 that clocked inverter chain circuit generates, described The signal output end for the inverting clock signal nclk2 that the same phase control end of transmission gate TM2 is generated with clocked inverter chain circuit connects It connects, the signal output end of the inverted control terminals and the in-phase clock signal bclk2 of clocked inverter chain circuit generation of transmission gate TM2 Connection, the signal at the same phase control end and the inverting clock signal nclk3 of clocked inverter chain circuit generation of the transmission gate TM3 Output end connects, the letter of the inverted control terminals and the in-phase clock signal bclk3 of clocked inverter chain circuit generation of transmission gate TM3 The connection of number output end, the inverting clock signal that the inverted control terminals of the transmission gate TM4 are generated with clocked inverter chain circuit The signal output end of nclk1 connects, and the in-phase clock that same phase control end and the clocked inverter chain circuit of transmission gate TM4 generate is believed The signal output end connection of number bclk1, the reverse phase that the inverted control terminals of the transmission gate TM5 are generated with clocked inverter chain circuit The signal output end of clock signal nclk2 connects, and same phase control end and the clocked inverter chain circuit of transmission gate TM5 generate same The signal output end of clock signal bclk2 connects；The inverted control terminals of the transmission gate TM6 are given birth to clocked inverter chain circuit At inverting clock signal nclk3 signal output end connection, the same phase control end of transmission gate TM6 and clocked inverter chain circuit The signal output end of the in-phase clock signal bclk3 of generation connects；