CN108712163A - A kind of radioresistance trigger circuit based on SET detections - Google Patents

Abstract

The invention discloses a kind of radioresistance trigger circuit based on SET detections, which forms by clocked inverter chain circuit, D input inverters chain circuit, set-reset signal generating circuit, main DICE latch cicuits and from DICE latch cicuits；Technical scheme of the present invention uses SET detection techniques, the data of sampling are sent directly into main DICE latches, then it decides whether to carry out set or reset to trigger to judge whether the data being sent into are SET pulses by set-reset signal generating circuit, so as to reduce the larger settling time of filtering wave by prolonging time generation, to keep the timing performance of trigger more preferable.

Description

A kind of radioresistance trigger circuit based on SET detections

Technical field

The present invention relates to the designs of radiation-hardened ic, are specifically related to a kind of radioresistance trigger electricity detected based on SET Road.

Background technology

With the progress of integrated circuit fabrication process, the promotion of the diminution of device size and operating rate, radiate to circuit Influence also become increasingly severe.Radiation is presented as single particle effect (Single Event to the main influence of digital circuit Effect, SEE) and total dose effect (Total Ionizing Dose, TID), as Deep Submicron MOSFETs become master Stream, when the process node of especially MOS circuits reaches 65nm or less, it is main that single particle effect has become influence MOS device Radiation effect.Single particle effect is broadly divided into single-ion transient state (Single Event Transient, SET) and simple grain Son overturning (Single Event Upset, SEU).

Under radiation environment, MOS integrated circuits are by the charged particle bombardment of high energy.When charged particle bombardment ends to script Metal-oxide-semiconductor drain region when, will produce due to the energy transmission of high energy charged particles, in the short time largely can be with free-moving current-carrying Son, i.e. hole and electronics, to make the metal-oxide-semiconductor ended originally conducting, to change the output level of device.Due to high energy particle The carrier of generation over time can be compound quickly or releases and return to the carrier concentration state before bombardment, therefore is hit Metal-oxide-semiconductor can there are one from by the end of being conducting to the process ended again, be reflected in metal-oxide-semiconductor output on, just will produce a positive arteries and veins The waveform of punching or negative pulse.The pulse effects of this transient state is referred to as single-ion transient state.For combinational logic circuit, single-particle Transient effect can influence the output of circuit.And in sequence circuit, when the positive pulse or negative pulse that single-ion transient state generates are touched Hair device or other storage circuits receive or the storage section of circuit is directly hit by high energy particle and generates overturning, due to electricity The memory function on road so that this overturning can not restore, and to make the output of entire circuit generate mistake, this effect is referred to as single Particle is overturn.

Either single-ion transient state effect or Single event upset effecf can all influence the normal work of circuit, therefore having must The MOS integrated circuits to work under radiation environment are reinforced（Radiation Harden）.At present on trigger structure It is main to be reinforced using DICE structures to reduce the influence of single-particle inversion, and it is general to the single-ion transient state of data terminal input When being filtered using C cell circuit, but being filtered using C cell circuit, the settling time of trigger also increases therewith, makes Deteriorate at the timing performance of entire circuit, working frequency declines.

Invention content

The purpose of the present invention is to provide a kind of radioresistance trigger circuit based on SET detections, the radioresistance triggers Circuit overcomes the deficiencies in the prior art, shortens the settling time of trigger, and the timing performance of entire circuit has obtained very greatly Improve, improves the working frequency of circuit.

In order to achieve the above objectives, the technical solution adopted by the present invention to solve the technical problems is：One kind is detected based on SET Radioresistance trigger circuit, it is characterised in that：The radioresistance trigger circuit includes clocked inverter chain circuit, D inputs Chain of inverters circuit, set-reset signal generating circuit, main DICE latch cicuits and from DICE latch cicuits；External clock letter Number CK is separately input to clocked inverter chain circuit and set-reset signal generating circuit, and external clock signal CK is anti-through clock Phase device chain circuit generates two road in-phase clock signal bclk1, bclk2 and two road inverting clock signal nclk1, nclk2；External number It is believed that a number D is separately input to D input inverters chain circuit and set-reset signal generating circuit, external data signal D is inputted through D Chain of inverters circuit evolving two circuit-switched data signal d1, d2；Clock signal CK, data-signal D, D input inverter chain circuit generate Two circuit-switched data signal d1, d2 and two road inverting clock signal nclk1 and nclk2 and all the way in-phase clock signal bclk2 are through setting Set signal sn and reset signal r is exported after the reset signal generating circuit of position；Data-signal D, two road in-phase clock signals Bclk1, bclk2, two road inverting clock signal nclk1, nclk2 and all the way data-signal d2 and set signal sn and reset letter Number r is input to main DICE latch cicuits, and two circuit-switched data signal m1, m2 are exported after main DICE latch cicuits；Two road in-phase clocks Signal bclk1 and bclk2, two road inverting clock signal nclk1 and nclk2, set signal sn and reset signal r and main DICE Two circuit-switched data signal m1 and m2 of latch cicuit output are input to from DICE latch cicuits, then after from DICE latch cicuits Outputting data signals Q；

The clocked inverter chain circuit be by 6 PMOS tube PM1, PM2, PM3, PM4, PM5, PM6 and 6 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6 are formed；The PM1 and NM1, PM2 and NM2, PM3 and NM3, PM4 and NM4, PM5 and NM5, PM6 A phase inverter is respectively constituted with NM6, the clock signal CK is connect with the input terminal of phase inverter PM1 and NM1, inverted device PM1 With generation inverting clock signal nclk1 after NM1；The output of the input terminal and phase inverter PM1 and NM1 of the phase inverter PM2 and NM2 End connects, and in-phase clock signal bclk1 is generated after inverted device PM2 and NM2；The input terminal of the phase inverter PM3 and NM3 and when The CK connections of clock signal, output end are connect with the input terminal of phase inverter PM4 and NM4, the input terminal of the phase inverter PM5 and NM5 with Phase inverter PM4 is connected with the output end of NM4, and output end is connect with the input terminal of phase inverter PM6 and NM6, clock signal CK warps After inverting clock signal nclk2, then inverted device PM6 and NM6 being generated after phase inverter PM3 and NM3, PM4 and NM4, PM5 and NM5 Generate in-phase clock signal bclk2；

The D input inverters chain circuit by 2 PMOS tube PM7, PM8 and 2 NMOS tube NM7, NM8, form；The PM7 A phase inverter is respectively constituted with NM7, PM8 and NM8；The data-signal D is connect with the input terminal of phase inverter PM7 and NM7, through anti- Data-signal d1 is generated after phase device PM7 and NM7；The output of the input terminal and phase inverter PM7 and NM7 of the phase inverter PM8 and NM8 End connects, and data-signal d2 is generated after inverted device PM8 and NM8；

The set-reset signal generating circuit be by 10 PMOS tube PM9, PM10, PM11, PM12, PM13, PM14, PM15, PM16, PM17, PM18 and 10 NMOS tubes NM9, NM10, NM11, NM12, NM13, NM14, NM15, NM16, NM17, NM18 Composition；The grid of the PM9 and NM9 is connect with the output end of clock signal CK；The grid of the PM10 and NM10 and clock are anti- The grid of the signal output end connection for the inverting clock signal nclk2 that phase device chain circuit generates, the PM11 and NM11 are inputted with D The signal output end of the data-signal d2 of chain of inverters circuit evolving connects, grid and the D input inversions of the PM12 and NM12 The signal output end connection for the data-signal d1 that device chain circuit generates, the grid external data signal D of the PM13 and NM13；Institute State the equal external power supply of source electrode of PM9, PM10, PM11, PM12, PM13；The drain electrode of described PM9, PM10, PM11, PM12, PM13 are equal It is connect with the signal output end of the set signal sn of set-reset signal generating circuit；The drain electrode of the drain electrode and PM13 of the NM9 Connection, the source electrode of NM9 is connected with the drain electrode of NM10, and the source electrode of NM10 is connected with the drain electrode of NM11, the source electrode of NM11 and NM12's Drain electrode is connected, and the source electrode of NM12 is connected with the drain electrode of NM13, the source electrode ground connection of NM13；The grid and clock of the PM14 and NM18 The signal output end of the inverting clock signal nclk1 of chain of inverters circuit evolving connects；The grid of the PM15 and NM17 and when The signal output end of the in-phase clock signal bclk2 of clock chain of inverters circuit evolving connects, the grid and D of the PM16 and NM16 The grid of the signal output end connection for the data-signal d2 that input inverter chain circuit generates, the PM17 and NM15 are inputted with D The signal output end of the data-signal d1 of chain of inverters circuit evolving connects, the grid external data signal of the PM18 and NM14 D；The equal external power supply of source electrode of the PM14；The drain electrode of the PM14 is connect with the source electrode of PM15, and the drain electrode of PM15 is with PM16's Source electrode connects, and the drain electrode of the PM16 is connect with the source electrode of PM17, and the drain electrode of PM17 is connect with the source electrode of PM18, the PM18's Drain electrode is connect with the drain electrode of NM18, and the drain electrode of described NM14, NM15, NM16, NM17, NM18 generate electricity with set-reset signal The signal output end of the reset signal r on road connects；The source grounding of described NM14, NM15, NM16, NM17, NM18；

The main DICE latch cicuits be by 16 PMOS tube PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26, PM27, PM28, PM29, PM30, PM31, PM32, PM33, PM34 and 18 NMOS tube NM19, NM20, NM21, NM22, NM23, NM24, NM25, NM26, NM27, NM28, NM29, NM30, NM31, NM32, NM33, NM34, NM35, NM36 and two A transmission gate TM1, TM2 composition；The grid external data signal D of the PM19, and be connected with the grid of NM19, the source electrode of PM19 External power supply, drain electrode connect with the source electrode of PM20；The in-phase clock that the grid of the PM20 is generated with clocked inverter chain circuit The signal output end of signal bclk1 connects, the drain electrode of PM20 respectively with the drain electrode of NM20, the grid of PM25, PM24 and NM24 Drain electrode, the grid of NM30 are connected；The inverting clock signal nclk1's that the grid of the NM20 is generated with clocked inverter chain circuit Signal output end connects, and source electrode is connected with the drain electrode of NM19；The grid external data signal d2 of the PM21, and with NM22's Grid is connected, the source electrode external power supply of PM21, and drain electrode connects with the source electrode of PM22；The grid of the PM22 and clocked inverter chain The signal output end of the in-phase clock signal bclk2 of circuit evolving connects, the drain electrode of PM22 respectively with the drain electrode of NM21, NM26 Grid, the grid of PM29, PM28 are connected with the drain electrode of NM28；The grid of the NM21 generates anti-with clocked inverter chain circuit The signal output end of clock signal nclk2 connects, and source electrode is connected with the drain electrode of NM22；The grid of the PM23 respectively with PM30 is connected with the grid of the drain electrode of the drain electrode of NM30, PM32 and NM32, NM27, the source electrode external power supply of PM23, drain electrode with The source electrode of PM24 connects；The signal for the inverting clock signal nclk1 that the grid of the PM24 is generated with clocked inverter chain circuit Output end connects, and the drain electrode of PM24 is connected with the drain electrode of NM24 respectively；The grid of the NM24 is given birth to clocked inverter chain circuit At in-phase clock signal bclk1 signal output end connection, source electrode is connected with the drain electrode of NM23；The grid of the NM23 point It is not connected with the drain electrode of the drain electrode of the grid of PM27, PM26 and NM26, PM31 and NM31；The source electrode external power supply of the PM25, The drain electrode of PM25 is connected with the source electrode of PM26；The grid of the PM26 is with the reset signal r's of set-reset signal generating circuit Signal output end connects, and the drain electrode of PM26 is connect with the drain electrode of NM26 respectively；The drain electrode of the source electrode and NM25 of the NM26 connects, The grid of the NM25 is connect with the signal output end of the set signal sn of set-reset signal generating circuit；The source of the PM27 The drain electrode of pole external power supply, PM27 is connected with the source electrode of PM28 respectively；The grid of the PM28 is given birth to clocked inverter chain circuit At inverting clock signal nclk2 signal output end connection, the drain electrode of PM28 connect with the drain electrode of NM28 respectively；The NM28 The signal output end of in-phase clock signal bclk2 that generates of grid and clocked inverter chain circuit connect, source electrode and NM27 Drain electrode connection；The drain electrode of the source electrode external power supply of the PM29, PM29 is connected with the source electrode of PM30；The grid of the PM30 with The signal output end of the reset signal r of set-reset signal generating circuit connects, and the drain electrode of PM30 connects with the drain electrode of NM30 respectively It connects；The drain electrode of the source electrode and NM29 of the NM30 connects, the set of the grid and set-reset signal generating circuit of the NM29 The signal output end of signal sn connects；The signal of the grid of the PM31 and the set signal sn of set-reset signal generating circuit Output end connects, source electrode external power supply, and drain electrode connects with the left data input port of the drain electrode of NM31, transmission gate TM1 respectively It connects；The grid of the NM31 is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The PM33's The grid of grid and NM34 are connect with the signal output end of the set signal sn of set-reset signal generating circuit, the source of PM33 Pole external power supply, drain electrode are connect with the drain electrode of the right side data-out port, NM34 of transmission gate TM1 respectively；The NM34's The drain electrode of source electrode and NM33 connect, and the grid of the NM33 and the signal of the reset signal r of set-reset signal generating circuit are defeated Outlet connects；The drain electrode output of the PM33 all the way data-signal m1 to from DICE latch cicuits；The grid of the PM32 with set Position reset signal generating circuit set signal sn signal output end connection, source electrode external power supply, drain electrode respectively with NM32 Drain electrode, transmission gate TM2 left data input port connection；The grid of the NM32 and set-reset signal generating circuit The signal output end of reset signal r connects；The grid of the PM34 and the grid of NM36 with set-reset signal generating circuit Set signal sn signal output end connection, the source electrode external power supply of PM34, the drain electrode right-hand component with transmission gate TM2 respectively It is connected according to the drain electrode of output port, NM36；The drain electrode of the source electrode and NM35 of the NM36 connects, the grid of the NM35 and set The signal output end of the reset signal r of reset signal generating circuit connects；The drain electrode of the PM34 exports another way data-signal M2 is extremely from DICE latch cicuits；The source of described NM19, NM22, NM23, NM25, NM27, NM29, NM31, NM32, NM33, NM35 Extremely it is grounded；The inverting clock signal nclk1's that the inverted control terminals of the transmission gate TM1 are generated with clocked inverter chain circuit Signal output end connects, the in-phase clock signal bclk1 at the same phase control end and the generation of clocked inverter chain circuit of transmission gate TM1 Signal output end connection, the inverted control terminals of the transmission gate TM2 believe with the inversion clock that clocked inverter chain circuit generates The signal output end connection of number nclk2, the in-phase clock that the same phase control end of transmission gate TM2 is generated with clocked inverter chain circuit The signal output end of signal bclk2 connects；

It is described from DICE latch cicuits be by 10 PMOS tube PM35, PM36, PM37, PM38, PM39, PM40, PM41, PM42, PM43, PM44 and 10 NMOS tube NM37, NM38, NM39, NM40, NM41, NM42, NM43, NM44, NM45, NM46 compositions；Institute The signal output end for stating the grid of PM35 and the reset signal r of set-reset signal generating circuit is connect, source electrode external power supply, leakage The source electrode of pole and PM36 connect；The grid of the PM36 respectively with the drain electrode of PM42 and NM44, the grid of the grid of NM42 and PM43 The grid of pole and NM45 connect, and drain electrode is connected with the source electrode of PM37；The grid of the PM37 and clocked inverter chain circuit The signal output end of the in-phase clock signal bclk1 of generation connects, the drain electrode of PM37 respectively with the drain electrode of NM39, the grid of PM38 Pole, NM44 grid with the output end of data-signal m1 connects all the way in main DICE latch cicuits；The grid of the NM39 and when The signal output end of the inverting clock signal nclk1 of clock chain of inverters circuit evolving connects, and source electrode is connected with the drain electrode of NM38； The grid of the NM38 is connect with the grid of the drain electrode of PM38 and NM40, the grid of PM40 and PM44 and NM46 respectively, source Pole is connected with the drain electrode of NM37；The grid of the NM37 and the signal of the set signal sn of set-reset signal generating circuit export End connection；The source electrode external power supply of the PM38, drain electrode are connect with the drain electrode of NM40；The grid of the NM40 respectively with PM41 and The output end of another way data-signal m2 connects in the drain electrode of NM43, the grid of PM42 and main DICE latch cicuits；The PM39 Grid connect with the signal output end of the reset signal r of set-reset signal generating circuit, source electrode external power supply, drain electrode with The source electrode of PM40 connects；The drain electrode of the PM40 is connected with the source electrode of PM41；The grid of the PM41 and clocked inverter chain electricity The signal output end connection for the in-phase clock signal bclk2 that road generates, the drain electrode of PM41 are connect with the drain electrode of NM43；The NM43 The signal output end of inverting clock signal nclk2 that generates of grid and clocked inverter chain circuit connect, source electrode and NM42 Drain electrode be connected；The source electrode of the NM42 is connected with the drain electrode of NM41；The grid of the NM41 generates electricity with set-reset signal The signal output end of the set signal sn on road connects；The source electrode external power supply of the PM42, drain electrode are connect with the drain electrode of NM44；Institute The source electrode external power supply of PM43 is stated, drain electrode is connect with the source electrode of PM44；The grid of the PM44 and the grid of NM46 connect, leakage The drain electrode of pole and NM46 connect；The drain electrode of the source electrode and NM45 of the NM46 connects；The drain electrode outputting data signals of the PM44 Q；The source grounding of described NM37, NM40, NM41, NM44, NM45.

In the above-mentioned technical solutions, when rising edge clock signal arrives, if data terminal D is receiving a SET just just Pulse carries out asynchronous reset, conversely, working as then reset-set signal generating circuit will generate a reset signal r to trigger When data terminal D receives a SET negative pulse, reset-set signal generating circuit generates a set signal sn, to trigger Carry out asynchronous set, when trigger is not at rising edge clock signal or data terminal does not have SET pulse interference, reset signal With set signal all in invalid state, circuit maintains normal work.Due to there is no to use C cell filter circuit, the trigger Settling time will shorten, to make timing performance be improved, improve the working frequency of circuit.

Description of the drawings

Fig. 1 is a kind of principle assumption diagram of the radioresistance trigger circuit detected based on SET of the present invention；

Fig. 2 is a kind of clocked inverter chain circuit figure of the radioresistance trigger circuit detected based on SET of the present invention；

Fig. 3 is a kind of D input inverter chain circuit figures of the radioresistance trigger circuit detected based on SET of the present invention；

Fig. 4 is a kind of set-reset signal generating circuit figure of the radioresistance trigger circuit detected based on SET of the present invention；

Fig. 5 is a kind of main DICE latch cicuits figure of the radioresistance trigger circuit detected based on SET of the present invention；

Fig. 6 is a kind of slave DICE latch cicuits figure of the radioresistance trigger circuit detected based on SET of the present invention；

Fig. 7 is the reset of set-reset signal generating circuit in a kind of radioresistance trigger circuit detected based on SET of the present invention Signal r generates sequence diagram；

Fig. 8 is the set of set-reset signal generating circuit in a kind of radioresistance trigger circuit detected based on SET of the present invention Signal sn generates sequence diagram.

Specific implementation mode

The radioresistance trigger circuit based on SET detections a kind of to the present invention is made further with reference to the accompanying drawings and examples It is described in detail.Constitute the application attached drawing be used to provide further understanding of the present invention, illustrative examples of the invention and It illustrates, for explaining the present invention, not constituting improper limitations of the present invention.

By Fig. 1-Fig. 6 as it can be seen that a kind of radioresistance latch circuit based on C cell and transmission gate of the present embodiment includes Clocked inverter chain circuit, D input inverters chain circuit, set-reset signal generating circuit, main DICE latch cicuits and from DICE latch cicuits.In the present embodiment, external clock signal CK is separately input to clocked inverter chain circuit and set-reset Signal generating circuit, external clock signal CK through clocked inverter chain circuit generate two road in-phase clock signal bclk1, Bclk2 and two road inverting clock signal nclk1, nclk2；External data signal D be separately input to D input inverters chain circuit and Set-reset signal generating circuit, external data signal D generate two circuit-switched data signal d1, d2 through D input inverter chain circuits；When Clock signal CK, data-signal D, D input inverter chain circuit generate two circuit-switched data signal d1, d2 and two road inverting clock signals Nclk1 and nclk2 and all the way in-phase clock signal bclk2 exported after set-reset signal generating circuit set signal sn and Reset signal r；Data-signal D, two road in-phase clock signal bclk1, bclk2, two road inverting clock signal nclk1, nclk2 and Data-signal d2 and set signal sn and reset signal r is input to main DICE latch cicuits all the way, through main DICE latch cicuits After export two circuit-switched data signal m1, m2；Two road in-phase clock signal bclk1 and bclk2, two road inverting clock signal nclk1 and Nclk2, set signal sn and reset signal r and two circuit-switched data signal m1 and m2 of main DICE latch cicuits output are input to From DICE latch cicuits, the then outputting data signals Q after from DICE latch cicuits.

By Fig. 1, Fig. 2 as it can be seen that the clocked inverter chain circuit of the present embodiment be by 6 PMOS tube PM1, PM2, PM3, PM4, PM5, PM6 and 6 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6 compositions.The PM1 and NM1 of the present embodiment, PM2 and NM2, PM3 and NM3, PM4 and NM4, PM5 and NM5, PM6 and NM6 respectively constitute a phase inverter, in the present embodiment, clock signal CK with it is anti- Phase device PM1 is connected with the input terminal of NM1, after inverted device PM1 and NM1 generate inverting clock signal nclk1, phase inverter PM2 and The input terminal of NM2 is connect with the output end of phase inverter PM1 and NM1, and in-phase clock signal is generated after inverted device PM2 and NM2 bclk1.The input terminal of phase inverter PM3 and NM3 are connect with clock signal CK, and the input terminal of output end and phase inverter PM4 and NM4 connects It connects, the input terminal of the phase inverter PM5 and NM5 is connect with the output end of phase inverter PM4 and NM4, output end and phase inverter PM6 It is connected with the input terminal of NM6, inversion clock is generated after clock signal CK inverted device PM3 and NM3, PM4 and NM4, PM5 and NM5 In-phase clock signal bclk2 is generated after signal nclk2, then inverted device PM6 and NM6.

By Fig. 1, Fig. 3 as it can be seen that the D input inverter chain circuits of the present embodiment are by 2 PMOS tube PM7, PM8 and 2 NMOS tube NM7, NM8, composition；The PM7 and NM7, PM8 and NM8 respectively constitute a phase inverter；The data-signal D and reverse phase Device PM7 is connected with the input terminal of NM7, and data-signal d1 is generated after inverted device PM7 and NM7；The phase inverter PM8's and NM8 Input terminal is connect with the output end of phase inverter PM7 and NM7, and data-signal d2 is generated after inverted device PM8 and NM8.

By Fig. 1, Fig. 4 as it can be seen that the set-reset signal generating circuit of the present embodiment be by 10 PMOS tube PM9, PM10, PM11, PM12, PM13, PM14, PM15, PM16, PM17, PM18 and 10 NMOS tube NM9, NM10, NM11, NM12, NM13, NM14, NM15, NM16, NM17, NM18 are formed；The grid of the PM9 and NM9 is connect with the output end of clock signal CK；It is described The grid of PM10 and NM10 is connect with the signal output end for the inverting clock signal nclk2 that clocked inverter chain circuit generates, institute It states the grid of PM11 and NM11 and the signal output end of data-signal d2 that D input inverter chain circuits generate is connect, it is described The grid of PM12 and NM12 is connect with the signal output end for the data-signal d1 that D input inverter chain circuits generate, the PM13 With the grid external data signal D of NM13；The equal external power supply of source electrode of described PM9, PM10, PM11, PM12, PM13；It is described Signal output end of the drain electrode of PM9, PM10, PM11, PM12, PM13 with the set signal sn of set-reset signal generating circuit Connection；The drain electrode of the NM9 is connect with the drain electrode of PM13, and the source electrode of NM9 is connected with the drain electrode of NM10, the source electrode and NM11 of NM10 Drain electrode be connected, the source electrode of NM11 is connected with the drain electrode of NM12, and the source electrode of NM12 is connected with the drain electrode of NM13, and the source electrode of NM13 connects Ground；The signal output end for the inverting clock signal nclk1 that the grid of the PM14 and NM18 is generated with clocked inverter chain circuit Connection；The signal for the in-phase clock signal bclk2 that the grid of the PM15 and NM17 is generated with clocked inverter chain circuit exports The signal output end for the data-signal d2 that the grid of end connection, the PM16 and NM16 are generated with D input inverter chain circuits connects It connects, the signal output end for the data-signal d1 that grid and the D input inverter chain circuits of the PM17 and NM15 generate is connect, institute State the grid external data signal D of PM18 and NM14；The equal external power supply of source electrode of the PM14；The drain electrode of the PM14 and PM15 Source electrode connection, the drain electrode of PM15 connect with the source electrode of PM16, and the drain electrode of the PM16 is connect with the source electrode of PM17, the leakage of PM17 The source electrode of pole and PM18 connect, and the drain electrode of the PM18 connect with the drain electrode of NM18, the NM14, NM15, NM16, NM17, The drain electrode of NM18 is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The NM14, NM15, The source grounding of NM16, NM17, NM18.

By Fig. 1, Fig. 5 as it can be seen that the main DICE latch cicuits of the present embodiment be by 16 PMOS tube PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26, PM27, PM28, PM29, PM30, PM31, PM32, PM33, PM34 and 18 NMOS tubes NM19 、NM20、NM21、NM22、NM23、NM24、NM25、NM26、NM27、NM28、NM29、NM30、 NM31 、NM32、 NM33, NM34, NM35, NM36 and two transmission gate TM1, TM2 compositions；The grid external data signal D of the PM19, and with The grid of NM19 is connected, the source electrode external power supply of PM19, and drain electrode connects with the source electrode of PM20；The grid of the PM20 and clock are anti- Phase device chain circuit generate in-phase clock signal bclk1 signal output end connection, PM20 drain electrode respectively with the drain electrode of NM20, Grid, the PM24 of PM25 is connected with the grid of the drain electrode of NM24, NM30；The grid of the NM20 is given birth to clocked inverter chain circuit At inverting clock signal nclk1 signal output end connection, source electrode is connected with the drain electrode of NM19；Outside the grid of the PM21 Data-signal d2 is met, and is connected with the grid of NM22, the source electrode external power supply of PM21, drain electrode connects with the source electrode of PM22；It is described The grid of PM22 is connect with the signal output end for the in-phase clock signal bclk2 that clocked inverter chain circuit generates, the leakage of PM22 Pole is connected with the drain electrode of NM21, the drain electrode of the grid of NM26, the grid of PM29, PM28 and NM28 respectively；The grid of the NM21 It is connect with the signal output end of the inverting clock signal nclk2 of clocked inverter chain circuit generation, the drain electrode of source electrode and NM22 It is connected；The grid of the PM23 is connected with the grid of the drain electrode of the drain electrode of PM30 and NM30, PM32 and NM32, NM27 respectively, The source electrode external power supply of PM23, drain electrode connect with the source electrode of PM24；The grid of the PM24 is generated with clocked inverter chain circuit Inverting clock signal nclk1 signal output end connection, the drain electrode of PM24 is connected with the drain electrode of NM24 respectively；The NM24's Grid is connect with the signal output end for the in-phase clock signal bclk1 that clocked inverter chain circuit generates, source electrode and NM23's Drain electrode is connected；The grid of the NM23 drain electrode phase with the drain electrode of the grid of PM27, PM26 and NM26, PM31 and NM31 respectively Even；The drain electrode of the source electrode external power supply of the PM25, PM25 is connected with the source electrode of PM26；The grid and set-reset of the PM26 The signal output end of the reset signal r of signal generating circuit connects, and the drain electrode of PM26 is connect with the drain electrode of NM26 respectively；It is described The drain electrode of the source electrode and NM25 of NM26 connects, and the grid of the NM25 is with the set signal sn's of set-reset signal generating circuit Signal output end connects；The drain electrode of the source electrode external power supply of the PM27, PM27 is connected with the source electrode of PM28 respectively；The PM28 The signal output end of inverting clock signal nclk2 that generates of grid and clocked inverter chain circuit connect, the drain electrode point of PM28 It is not connect with the drain electrode of NM28；The in-phase clock signal bclk2's that the grid of the NM28 is generated with clocked inverter chain circuit Signal output end connects, the drain electrode connection of source electrode and NM27；The source electrode external power supply of the PM29, the drain electrode of PM29 and PM30 Source electrode be connected；The grid of the PM30 is connect with the signal output end of the reset signal r of set-reset signal generating circuit, The drain electrode of PM30 is connect with the drain electrode of NM30 respectively；The drain electrode of the source electrode and NM29 of the NM30 connects, the grid of the NM29 It is connect with the signal output end of the set signal sn of set-reset signal generating circuit；The grid of the PM31 is believed with set-reset The signal output end connection of the set signal sn of number generation circuit, source electrode external power supply, drain electrode respectively with the drain electrode of NM31, pass The left data input port of defeated door TM1 connects；The grid of the NM31 and the reset signal r of set-reset signal generating circuit Signal output end connection；The grid of the PM33 and the grid of NM34 with the set signal of set-reset signal generating circuit The signal output end of sn connects, the source electrode external power supply of PM33, drain electrode respectively with the right side data output end of transmission gate TM1 The drain electrode connection of mouth, NM34；The drain electrode of the source electrode and NM33 of the NM34 connects, grid and the set-reset signal of the NM33 The signal output end of the reset signal r of generation circuit connects；The drain electrode output of the PM33 all the way data-signal m1 to from DICE Latch cicuit；The grid of the PM32 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, Source electrode external power supply, drain electrode are connect with the left data input port of the drain electrode of NM32, transmission gate TM2 respectively；The NM32's Grid is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM34 and NM36's Grid is connect with the signal output end of the set signal sn of set-reset signal generating circuit, the source electrode external power supply of PM34, Its drain electrode is connect with the drain electrode of the right side data-out port, NM36 of transmission gate TM2 respectively；The source electrode of the NM36 and NM35's Drain electrode connection, the grid of the NM35 are connect with the signal output end of the reset signal r of set-reset signal generating circuit；It is described The drain electrode output another way data-signal m2 of PM34 is extremely from DICE latch cicuits；The NM19, NM22, NM23, NM25, NM27, The source grounding of NM29, NM31, NM32, NM33, NM35；The inverted control terminals of the transmission gate TM1 and clocked inverter chain The signal output end of the inverting clock signal nclk1 of circuit evolving connects, the same phase control end of transmission gate TM1 and clocked inverter The signal output end connection for the in-phase clock signal bclk1 that chain circuit generates, the inverted control terminals and clock of the transmission gate TM2 The signal output end of the inverting clock signal nclk2 of chain of inverters circuit evolving connects, the same phase control end of transmission gate TM2 and when The signal output end of the in-phase clock signal bclk2 of clock chain of inverters circuit evolving connects.

By Fig. 1, Fig. 6 as it can be seen that the slave DICE latch cicuits of the present embodiment be by 10 PMOS tube PM35, PM36, PM37, PM38, PM39, PM40, PM41, PM42, PM43, PM44 and 10 NMOS tube NM37, NM38, NM39, NM40, NM41, NM42, NM43, NM44, NM45, NM46 are formed；The signal of the grid of the PM35 and the reset signal r of set-reset signal generating circuit Output end connects, source electrode external power supply, and drain electrode is connect with the source electrode of PM36；The grid of the PM36 is respectively with PM42's and NM44 Drain electrode, the grid of NM42 are connected with the grid of the grid of PM43 and NM45, and drain electrode is connected with the source electrode of PM37；The PM37 The signal output end of in-phase clock signal bclk1 that generates of grid and clocked inverter chain circuit connect, the drain electrode point of PM37 Not with the output end of data-signal m1 all the way in the drain electrode of NM39, the grid of PM38, the grid of NM44 and main DICE latch cicuits Connection；The grid of the NM39 is connect with the signal output end for the inverting clock signal nclk1 that clocked inverter chain circuit generates, Its source electrode is connected with the drain electrode of NM38；The grid of the NM38 respectively with the drain electrode of PM38 and NM40, PM40 grid and PM44 is connected with the grid of NM46, and source electrode is connected with the drain electrode of NM37；The grid of the NM37 is generated with set-reset signal The signal output end of the set signal sn of circuit connects；The source electrode external power supply of the PM38, drain electrode are connect with the drain electrode of NM40； The grid of the NM40 is believed with another circuit-switched data in the drain electrode of PM41 and NM43, the grid of PM42 and main DICE latch cicuits respectively The output end connection of number m2；The signal output end of the grid of the PM39 and the reset signal r of set-reset signal generating circuit Connection, source electrode external power supply, drain electrode are connect with the source electrode of PM40；The drain electrode of the PM40 is connected with the source electrode of PM41；It is described The grid of PM41 is connect with the signal output end for the in-phase clock signal bclk2 that clocked inverter chain circuit generates, the leakage of PM41 The drain electrode of pole and NM43 connect；The inverting clock signal nclk2's that the grid of the NM43 is generated with clocked inverter chain circuit Signal output end connects, and source electrode is connected with the drain electrode of NM42；The source electrode of the NM42 is connected with the drain electrode of NM41；The NM41 Grid connect with the signal output end of the set signal sn of set-reset signal generating circuit；The external electricity of source electrode of the PM42 Source, drain electrode are connect with the drain electrode of NM44；The source electrode external power supply of the PM43, drain electrode are connect with the source electrode of PM44；The PM44 Grid and NM46 grid connect, drain electrode connect with the drain electrode of NM46；The drain electrode of the source electrode and NM45 of the NM46 connects； The drain electrode outputting data signals Q of the PM44；The source grounding of described NM37, NM40, NM41, NM44, NM45.

As seen from Figure 7, the present embodiment generated on sequence diagram from reset signal r as can be seen that nclk1 signals be by PM1 and The inverting clock signal that the phase inverter that NM1 is constituted generates, certain delay is will produce relative to CK signals, likewise, bclk1 believes Number it is the in-phase clock signal generated by the phase inverter that PM2 and NM2 are constituted, there is also certain to prolong relative to nclk1 by bclk1 When, the appropriate breadth length ratio that each metal-oxide-semiconductor in clocked inverter chain circuit is arranged, can making nclk2, there are one with respect to bclk1 Fixed delay, there is also certain delays with respect to nclk2 by bclk2.If in rising edge clock, data input pin D receives one When a SET positive pulses, this positive pulse is possible to that the DICE structures of trigger can be allowed to store the data of this mistake just Come, but generate on sequence diagram in reset signal r as can be seen that in period between two dotted lines, D, d1, d2, nclk1 and Bclk2 is all in low level state, and the nor gate that NM14 ~ NM18 in Fig. 4 and PM14 ~ PM18 is constituted, and if only if D, When this five signals of d1, d2, nclk1 and bclk2 are low level simultaneously, it is high level to export as r, and when r signals are high level When, it can simultaneously be resetted by main DICE latch cicuits and from DICE latch cicuits, so that it is guaranteed that trigger is not by the shadow of SET positive pulses It rings.

When r signals are that high level is effective and sn signals are that high level is invalid, latched to main DICE latch cicuits and from DICE The principle of circuit reset is as follows：When r signals are high level and sn signals are high level, PM26 and PM31 cut-offs, NM31 conductings, To make node a1 be reset to low level.PM30 and PM32 cut-offs, NM32 conductings, to make node a2 be reset to low level. PM33 and PM35 cut-offs, NM33 and NM34 conductings, to make node m1 be reset to low level.PM34 and PM39 cut-off, NM35 and NM36 is connected, to make node m2 be reset to low level.When m1 and m2 are reset to low level, by DICE, mutually latch acts on shadow It rings, q1 and q2 can become high level, be low level so as to cause output Q.

Similar, as seen from Figure 8, if in rising edge clock, when data input pin D receives a SET negative pulse, this A negative pulse is possible to that the DICE structures of trigger can be allowed to store the data of this mistake just, but in set signal sn It generates in the period that can be seen that on sequence diagram between two dotted lines, D, d1, d2, CK and nclk2 are all in high level shape State, and the NAND gate that NM9 ~ NM13 in Fig. 4 and PM9 ~ PM13 is constituted, and if only if D, d1, d2, CK and nclk2 this five Signal simultaneously for high level when, it is low level to export as sn, and when sn signals are low level, can by main DICE latch cicuits and From the set simultaneously of DICE latch cicuits, so that it is guaranteed that trigger is not influenced by SET negative pulses.

When sn signals are that low level is effective and r signals are that low level is invalid, latched to main DICE latch cicuits and from DICE The principle of circuit set is as follows：When sn signals are low level and r signals are low level, NM25 and NM31 cut-offs, PM31 conductings, To make node a1 set be high level.NM29 and NM32 cut-offs, PM32 conductings, to make node a2 set be high level. PM33 is connected, NM33, NM34 and NM37 cut-off, to make node m1 set be high level.PM34 be connected, NM35, NM36 and NM41 ends, to make node m2 set be high level.When m1 and m2 set is high level, by DICE, mutually latch acts on shadow It rings, q1 and q2 can become low level, be high level so as to cause output Q.

Radioresistance trigger as described herein based on SET detections and the radioresistance trigger in the past based on C cell filtering It compares, withouts waiting for the filtering of input data, the data no matter sampled are high level or low level, all can directly be sent Become owner of DICE latches, then by set-reset signal generating circuit come judge be sent into data whether be SET Pulse decides whether to carry out set or reset to trigger, so as to reducing larger the building of filtering wave by prolonging time generation Between immediately, to keep the timing performance of trigger more preferable.

The above is only the embodiment of the present invention, is not imposed any restrictions to the present invention, every according to the technology of the present invention Essence still falls within the technology of the present invention to any simple modification, change and the variation of equivalent method made by above example In the protection domain of scheme.

Claims (1)

1. a kind of radioresistance trigger circuit based on SET detections, it is characterised in that：When the radioresistance trigger circuit includes Clock chain of inverters circuit, D input inverters chain circuit, set-reset signal generating circuit, main DICE latch cicuits and from DICE Latch cicuit；External clock signal CK is separately input to clocked inverter chain circuit and set-reset signal generating circuit, outside The clock signal CK in portion generates two road in-phase clock signal bclk1, bclk2 and two road inversion clocks through clocked inverter chain circuit Signal nclk1, nclk2；External data signal D is separately input to D input inverters chain circuit and set-reset signal generates electricity Road, external data signal D generate two circuit-switched data signal d1, d2 through D input inverter chain circuits；Clock signal CK, data-signal D, D input inverters chain circuit generates two circuit-switched data signal d1, d2 and two road inverting clock signal nclk1 and nclk2 and one Road in-phase clock signal bclk2 exports set signal sn and reset signal r after set-reset signal generating circuit；Data-signal D, two road in-phase clock signal bclk1, bclk2, two road inverting clock signal nclk1, nclk2 and all the way data-signal d2 and Set signal sn and reset signal r is input to main DICE latch cicuits, and two circuit-switched data signals are exported after main DICE latch cicuits m1,m2；Two road in-phase clock signal bclk1 and bclk2, two road inverting clock signal nclk1 and nclk2, set signal sn and Reset signal r and two circuit-switched data signal m1 and m2 of main DICE latch cicuits output are input to from DICE latch cicuits, so By from outputting data signals Q after DICE latch cicuits；

The clocked inverter chain circuit be by 6 PMOS tube PM1, PM2, PM3, PM4, PM5, PM6 and 6 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6 are formed；The PM1 and NM1, PM2 and NM2, PM3 and NM3, PM4 and NM4, PM5 and NM5, PM6 A phase inverter is respectively constituted with NM6, the clock signal CK is connect with the input terminal of phase inverter PM1 and NM1, inverted device PM1 With generation inverting clock signal nclk1 after NM1；The output of the input terminal and phase inverter PM1 and NM1 of the phase inverter PM2 and NM2 End connects, and in-phase clock signal bclk1 is generated after inverted device PM2 and NM2；The input terminal of the phase inverter PM3 and NM3 and when The CK connections of clock signal, output end are connect with the input terminal of phase inverter PM4 and NM4, the input terminal of the phase inverter PM5 and NM5 with Phase inverter PM4 is connected with the output end of NM4, and output end is connect with the input terminal of phase inverter PM6 and NM6, clock signal CK warps After inverting clock signal nclk2, then inverted device PM6 and NM6 being generated after phase inverter PM3 and NM3, PM4 and NM4, PM5 and NM5 Generate in-phase clock signal bclk2；

The D input inverters chain circuit by 2 PMOS tube PM7, PM8 and 2 NMOS tube NM7, NM8, form；The PM7 A phase inverter is respectively constituted with NM7, PM8 and NM8；The data-signal D is connect with the input terminal of phase inverter PM7 and NM7, through anti- Data-signal d1 is generated after phase device PM7 and NM7；The output of the input terminal and phase inverter PM7 and NM7 of the phase inverter PM8 and NM8 End connects, and data-signal d2 is generated after inverted device PM8 and NM8；

The set-reset signal generating circuit be by 10 PMOS tube PM9, PM10, PM11, PM12, PM13, PM14, PM15, PM16, PM17, PM18 and 10 NMOS tubes NM9, NM10, NM11, NM12, NM13, NM14, NM15, NM16, NM17, NM18 Composition；The grid of the PM9 and NM9 is connect with the output end of clock signal CK；The grid of the PM10 and NM10 and clock are anti- The grid of the signal output end connection for the inverting clock signal nclk2 that phase device chain circuit generates, the PM11 and NM11 are inputted with D The signal output end of the data-signal d2 of chain of inverters circuit evolving connects, grid and the D input inversions of the PM12 and NM12 The signal output end connection for the data-signal d1 that device chain circuit generates, the grid external data signal D of the PM13 and NM13；Institute State the equal external power supply of source electrode of PM9, PM10, PM11, PM12, PM13；The drain electrode of described PM9, PM10, PM11, PM12, PM13 are equal It is connect with the signal output end of the set signal sn of set-reset signal generating circuit；The drain electrode of the drain electrode and PM13 of the NM9 Connection, the source electrode of NM9 is connected with the drain electrode of NM10, and the source electrode of NM10 is connected with the drain electrode of NM11, the source electrode of NM11 and NM12's Drain electrode is connected, and the source electrode of NM12 is connected with the drain electrode of NM13, the source electrode ground connection of NM13；The grid and clock of the PM14 and NM18 The signal output end of the inverting clock signal nclk1 of chain of inverters circuit evolving connects；The grid of the PM15 and NM17 and when The signal output end of the in-phase clock signal bclk2 of clock chain of inverters circuit evolving connects, the grid and D of the PM16 and NM16 The grid of the signal output end connection for the data-signal d2 that input inverter chain circuit generates, the PM17 and NM15 are inputted with D The signal output end of the data-signal d1 of chain of inverters circuit evolving connects, the grid external data signal of the PM18 and NM14 D；The source electrode external power supply of the PM14；The drain electrode of the PM14 is connect with the source electrode of PM15, the drain electrode of the PM15 and PM16 Source electrode connection, the drain electrode of the PM16 connect with the source electrode of PM17, and the drain electrode of PM17 is connect with the source electrode of PM18, the PM18 Drain electrode connect with the drain electrode of NM18, the drain electrode of described NM14, NM15, NM16, NM17, NM18 is generated with set-reset signal The signal output end of the reset signal r of circuit connects；The source grounding of described NM14, NM15, NM16, NM17, NM18；

The main DICE latch cicuits be by 16 PMOS tube PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26, PM27, PM28, PM29, PM30, PM31, PM32, PM33, PM34 and 18 NMOS tube NM19, NM20, NM21, NM22, NM23, NM24, NM25, NM26, NM27, NM28, NM29, NM30, NM31, NM32, NM33, NM34, NM35, NM36 and two A transmission gate TM1, TM2 composition；The grid external data signal D of the PM19, and be connected with the grid of NM19, the source electrode of PM19 External power supply, drain electrode connect with the source electrode of PM20；The in-phase clock that the grid of the PM20 is generated with clocked inverter chain circuit The signal output end of signal bclk1 connects, the drain electrode of PM20 respectively with the drain electrode of NM20, the grid of PM25, PM24 and NM24 Drain electrode, the grid of NM30 are connected；The inverting clock signal nclk1's that the grid of the NM20 is generated with clocked inverter chain circuit Signal output end connects, and source electrode is connected with the drain electrode of NM19；The grid external data signal d2 of the PM21, and with NM22's Grid is connected, the source electrode external power supply of PM21, and drain electrode connects with the source electrode of PM22；The grid of the PM22 and clocked inverter chain The signal output end of the in-phase clock signal bclk2 of circuit evolving connects, the drain electrode of PM22 respectively with the drain electrode of NM21, NM26 Grid, the grid of PM29, PM28 are connected with the drain electrode of NM28；The grid of the NM21 generates anti-with clocked inverter chain circuit The signal output end of clock signal nclk2 connects, and source electrode is connected with the drain electrode of NM22；The grid of the PM23 respectively with PM30 is connected with the grid of the drain electrode of the drain electrode of NM30, PM32 and NM32, NM27, the source electrode external power supply of PM23, drain electrode with The source electrode of PM24 connects；The signal for the inverting clock signal nclk1 that the grid of the PM24 is generated with clocked inverter chain circuit Output end connects, and the drain electrode of PM24 is connected with the drain electrode of NM24 respectively；The grid of the NM24 is given birth to clocked inverter chain circuit At in-phase clock signal bclk1 signal output end connection, source electrode is connected with the drain electrode of NM23；The grid of the NM23 point It is not connected with the drain electrode of the drain electrode of the grid of PM27, PM26 and NM26, PM31 and NM31；The source electrode external power supply of the PM25, The drain electrode of PM25 is connected with the source electrode of PM26；The grid of the PM26 is with the reset signal r's of set-reset signal generating circuit Signal output end connects, and the drain electrode of PM26 is connect with the drain electrode of NM26 respectively；The drain electrode of the source electrode and NM25 of the NM26 connects, The grid of the NM25 is connect with the signal output end of the set signal sn of set-reset signal generating circuit；The source of the PM27 The drain electrode of pole external power supply, PM27 is connected with the source electrode of PM28 respectively；The grid of the PM28 is given birth to clocked inverter chain circuit At inverting clock signal nclk2 signal output end connection, the drain electrode of PM28 connect with the drain electrode of NM28 respectively；The NM28 The signal output end of in-phase clock signal bclk2 that generates of grid and clocked inverter chain circuit connect, source electrode and NM27 Drain electrode connection；The drain electrode of the source electrode external power supply of the PM29, PM29 is connected with the source electrode of PM30；The grid of the PM30 with The signal output end of the reset signal r of set-reset signal generating circuit connects, and the drain electrode of PM30 connects with the drain electrode of NM30 respectively It connects；The drain electrode of the source electrode and NM29 of the NM30 connects, the set of the grid and set-reset signal generating circuit of the NM29 The signal output end of signal sn connects；The signal of the grid of the PM31 and the set signal sn of set-reset signal generating circuit Output end connects, source electrode external power supply, and drain electrode connects with the left data input port of the drain electrode of NM31, transmission gate TM1 respectively It connects；The grid of the NM31 is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The PM33's The grid of grid and NM34 are connect with the signal output end of the set signal sn of set-reset signal generating circuit, the source of PM33 Pole external power supply, drain electrode are connect with the drain electrode of the right side data-out port, NM34 of transmission gate TM1 respectively；The NM34's The drain electrode of source electrode and NM33 connect, and the grid of the NM33 and the signal of the reset signal r of set-reset signal generating circuit are defeated Outlet connects；The drain electrode output of the PM33 all the way data-signal m1 to from DICE latch cicuits；The grid of the PM32 with set Position reset signal generating circuit set signal sn signal output end connection, source electrode external power supply, drain electrode respectively with NM32 Drain electrode, transmission gate TM2 left data input port connection；The grid of the NM32 and set-reset signal generating circuit The signal output end of reset signal r connects；The grid of the PM34 and the grid of NM36 with set-reset signal generating circuit Set signal sn signal output end connection, the source electrode external power supply of PM34, the drain electrode right-hand component with transmission gate TM2 respectively It is connected according to the drain electrode of output port, NM36；The drain electrode of the source electrode and NM35 of the NM36 connects, the grid of the NM35 and set The signal output end of the reset signal r of reset signal generating circuit connects；The drain electrode of the PM34 exports another way data-signal M2 is extremely from DICE latch cicuits；The source of described NM19, NM22, NM23, NM25, NM27, NM29, NM31, NM32, NM33, NM35 Extremely it is grounded；The inverting clock signal nclk1's that the inverted control terminals of the transmission gate TM1 are generated with clocked inverter chain circuit Signal output end connects, the in-phase clock signal bclk1 at the same phase control end and the generation of clocked inverter chain circuit of transmission gate TM1 Signal output end connection, the inverted control terminals of the transmission gate TM2 believe with the inversion clock that clocked inverter chain circuit generates The signal output end connection of number nclk2, the in-phase clock that the same phase control end of transmission gate TM2 is generated with clocked inverter chain circuit The signal output end of signal bclk2 connects；

It is described from DICE latch cicuits be by 10 PMOS tube PM35, PM36, PM37, PM38, PM39, PM40, PM41, PM42, PM43, PM44 and 10 NMOS tube NM37, NM38, NM39, NM40, NM41, NM42, NM43, NM44, NM45, NM46 compositions；Institute The signal output end for stating the grid of PM35 and the reset signal r of set-reset signal generating circuit is connect, source electrode external power supply, leakage The source electrode of pole and PM36 connect；The grid of the PM36 respectively with the drain electrode of PM42 and NM44, the grid of the grid of NM42 and PM43 The grid of pole and NM45 connect, and drain electrode is connected with the source electrode of PM37；The grid of the PM37 and clocked inverter chain circuit The signal output end of the in-phase clock signal bclk1 of generation connects, the drain electrode of PM37 respectively with the drain electrode of NM39, the grid of PM38 Pole, NM44 grid with the output end of data-signal m1 connects all the way in main DICE latch cicuits；The grid of the NM39 and when The signal output end of the inverting clock signal nclk1 of clock chain of inverters circuit evolving connects, and source electrode is connected with the drain electrode of NM38； The grid of the NM38 is connect with the grid of the drain electrode of PM38 and NM40, the grid of PM40 and PM44 and NM46 respectively, source Pole is connected with the drain electrode of NM37；The grid of the NM37 and the signal of the set signal sn of set-reset signal generating circuit export End connection；The source electrode external power supply of the PM38, drain electrode are connect with the drain electrode of NM40；The grid of the NM40 respectively with PM41 and The output end of another way data-signal m2 connects in the drain electrode of NM43, the grid of PM42 and main DICE latch cicuits；The PM39 Grid connect with the signal output end of the reset signal r of set-reset signal generating circuit, source electrode external power supply, drain electrode with The source electrode of PM40 connects；The drain electrode of the PM40 is connected with the source electrode of PM41；The grid of the PM41 and clocked inverter chain electricity The signal output end connection for the in-phase clock signal bclk2 that road generates, the drain electrode of PM41 are connect with the drain electrode of NM43；The NM43 The signal output end of inverting clock signal nclk2 that generates of grid and clocked inverter chain circuit connect, source electrode and NM42 Drain electrode be connected；The source electrode of the NM42 is connected with the drain electrode of NM41；The grid of the NM41 generates electricity with set-reset signal The signal output end of the set signal sn on road connects；The source electrode external power supply of the PM42, drain electrode are connect with the drain electrode of NM44；Institute The source electrode external power supply of PM43 is stated, drain electrode is connect with the source electrode of PM44；The grid of the PM44 and the grid of NM46 connect, leakage The drain electrode of pole and NM46 connect；The drain electrode of the source electrode and NM45 of the NM46 connects；The drain electrode outputting data signals of the PM44 Q；The source grounding of described NM37, NM40, NM41, NM44, NM45.