CN208707605U - It is a kind of based on SET detection three tunnels mutually latch flip-flop circuit - Google Patents

Abstract

The utility model discloses a kind of three tunnels based on SET detection mutually to latch flip-flop circuit, which mutually latches flip-flop circuit by clocked inverter chain circuit, D input inverter chain circuit, set-reset signal generating circuit, main DICE latch cicuit and form from DICE latch cicuit；The technical solution of the utility model uses SET detection technique, and the settling time of trigger can be made to greatly shorten, to improve the timing performance of radioresistance trigger, improve the working frequency of circuit, has better anti-SEU characteristic.

Description

It is a kind of based on SET detection three tunnels mutually latch flip-flop circuit

Technical field

The utility model relates to the design of radiation-hardened ic, it is specifically related to a kind of three tunnels based on SET detection and mutually latches Flip-flop circuit.

Background technique

With the progress of integrated circuit fabrication process, the promotion of the diminution of device size and operating rate, radiate to circuit Influence also become increasingly severe.Radiation is presented as single particle effect (Single Event to the main influence of digital circuit Effect, SEE) and total dose effect (Total Ionizing Dose, TID), as Deep Submicron MOSFETs become master Stream, when the process node of especially MOS circuit reaches 65nm or less, it is main that single particle effect has become influence MOS device Radiation effect.Single particle effect is broadly divided into single-ion transient state (Single Event Transient, SET) and simple grain Son overturning (Single Event Upset, SEU).

Under radiation environment, MOS integrated circuit is by the charged particle bombardment of high energy.When charged particle bombardment ends to script Metal-oxide-semiconductor drain region when, can generate due to the energy transmission of high energy charged particles, in the short time largely can be with free-moving current-carrying Son, i.e. hole and electronics, to make the metal-oxide-semiconductor ended originally conducting, to change the output level of device.Due to high energy particle The carrier of generation over time can be compound quickly or releases and return to the carrier concentration state before bombardment, therefore is hit Metal-oxide-semiconductor have one from by the end of being conducting to the process ended again, be reflected in metal-oxide-semiconductor output on, a positive arteries and veins will be generated The waveform of punching or negative pulse.The pulse effects of this transient state is referred to as single-ion transient state.For combinational logic circuit, single-particle Transient effect will affect the output of circuit.And in sequence circuit, when the positive pulse or negative pulse of single-ion transient state generation are touched Hair device or other storage circuits receive or the storage section of circuit is directly hit by high energy particle and generates overturning, due to electricity The memory function on road, so that this overturning can not restore, so that the output of entire circuit be made to generate mistake, this effect is referred to as single Particle overturning.

Either single-ion transient state effect or Single event upset effecf can all influence the normal work of circuit, therefore having must (Radiation Harden) is reinforced to the MOS integrated circuit to work under radiation environment.At present on trigger structure It is mainly reinforced using DICE structure to reduce the influence of single-particle inversion, and it is general to the single-ion transient state of data terminal input When being filtered using C cell circuit, but being filtered using C cell circuit, the settling time (setup time) of trigger Also it increases with it, the timing performance of entire circuit is caused to deteriorate, working frequency decline.

Summary of the invention

The purpose of this utility model is to provide a kind of three tunnels based on SET detection mutually to latch flip-flop circuit, three tunnel It mutually latches flip-flop circuit and overcomes the deficiencies in the prior art, shorten the settling time of trigger, the timing of entire circuit Very big improvement can have been obtained, the working frequency of circuit is improved, there is better anti-SEU characteristic.

In order to achieve the above objectives, the technical scheme adopted by the utility model to solve the technical problem is as follows: a kind of be based on SET Mutually latch flip-flop circuit in three tunnels of detection, it is characterised in that: it includes clocked inverter that flip-flop circuit is mutually latched on three tunnel Chain circuit, D input inverter chain circuit, set-reset signal generating circuit, main DICE latch cicuit and from DICE latch cicuit； External clock signal CK is separately input to clocked inverter chain circuit and set-reset signal generating circuit, external clock letter Number CK generates three road in-phase clock signal bclk1, bclk2, bclk3 and three road inverting clock signals through clocked inverter chain circuit nclk1,nclk2,nclk3；External data signal D is separately input to D input inverter chain circuit and set-reset signal generates Circuit, external data signal D generate two circuit-switched data signal d1, d2 and all the way anti-phase data signal through D input inverter chain circuit nd；Clock signal CK, data-signal D, D input inverter chain circuit generate data-signal d1 all the way and all the way anti-phase data signal Nd and two road inverting clock signal nclk1, nclk2 and all the way in-phase clock signal bclk2 generate electricity through set-reset signal Set signal sn and reset signal r is exported behind road；The data-signal D, three road in-phase clock signal bclk1, bclk2, bclk3 With three road inverting clock signal nclk1, nclk2, nclk3 and two circuit-switched data signal d1, d2 and set signal sn and reset letter Number r is input to main DICE latch cicuit, and three data signal m1, m2, m3 are exported after main DICE latch cicuit；The set is multiple Position signal generating circuit output set signal sn and reset signal r, three road in-phase clock signal bclk1, bclk2, bclk3 and Three road inverting clock signal nclk1, nclk2, nclk3 and main DICE latch cicuit output three data signal m1, m2 and M3 is input to from DICE latch cicuit, then the outputting data signals Q after from DICE latch cicuit；

The clocked inverter chain circuit be by 12 PMOS tube PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12 and 12 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12 composition；The PM1 and NM1, PM2 and NM2, PM3 and NM3, PM4 and NM4, PM5 and NM5, PM6 and NM6, PM7 and NM7, PM8 and NM8, PM9 and NM9, PM10 and NM10, PM11 and NM11, PM12 and NM12 respectively constitute a phase inverter, when described Clock signal CK is connect with the input terminal of phase inverter PM1 and NM1, and inverting clock signal nclk1 is generated after inverted device PM1 and NM1； The input terminal of the phase inverter PM2 and NM2 is connect with the output end of phase inverter PM1 and NM1, is generated after inverted device PM2 and NM2 In-phase clock signal bclk1；The input terminal of the phase inverter PM3 and NM3 is connect with clock signal CK, output end and phase inverter PM4 is connected with the input terminal of NM4, and the input terminal of the phase inverter PM5 and NM5 is connect with the output end of phase inverter PM4 and NM4, Its output end is connect with the input terminal of phase inverter PM6 and NM6, clock signal CK inverted device PM3 and NM3, PM4 and NM4, PM5 With generation in-phase clock signal bclk2 after generation inverting clock signal nclk2, then inverted device PM6 and NM6 after NM5；It is described anti- The input terminal of phase device PM7 and NM7 are connect with clock signal CK, and output end is connect with the input terminal of phase inverter PM8 and NM8, described The input terminal of phase inverter PM9 and NM9 are connect with the output end of phase inverter PM8 and NM8, output end and phase inverter PM10 and NM10 Input terminal connection, the input terminal of the phase inverter PM11 and NM11 is connect with the output end of phase inverter PM10 and NM10, defeated Outlet is connect with the input terminal of phase inverter PM12 and NM12, clock signal CK inverted device PM7 and NM7, PM8 and NM8, PM9 and It is generated together after generating inverting clock signal nclk3, then inverted device PM12 and NM12 after NM9, PM10 and NM10, PM11 and NM11 Clock signal bclk3；

The D input inverter chain circuit be by 4 PMOS tube PM13, PM14, PM15, PM16 and 4 NMOS tube NM13, NM14, NM15, NM16 composition；The PM13 and NM13, PM14 and NM14, PM15 and NM15, PM16 and NM16 respectively constitute one Phase inverter；The data-signal D is connect with the input terminal of phase inverter PM13 and NM13, is generated after inverted device PM13 and NM13 anti- To data-signal nd；The anti-phase data signal nd is input to the input terminal of phase inverter PM14 and NM14, inverted device PM14 and Data-signal d1 is generated after NM14；The input terminal of the phase inverter PM15 and NM15 and the output end of phase inverter PM14 and NM14 connect It connects, output end generates reverse data signal nd1, and the anti-phase data signal nd1 is input to the input of phase inverter PM16 and NM16 It holds, data-signal d2 is generated after inverted device PM16 and NM16；

The set-reset signal generating circuit be by 10 PMOS tube PM17, PM18, PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26 and 10 NMOS tube NM17, NM18, NM19, NM20, NM21, NM22, NM23, NM24, NM25, NM26 composition；The grid of the PM21 and NM21 is connect with the output end of clock signal CK；The grid of the PM20 and NM20 with The signal output end connection for the inverting clock signal nclk2 that clocked inverter chain circuit generates, the grid of the PM19 and NM19 It is connect with the signal output end of the data-signal d1 of D input inverter chain circuit generation, the grid and D of the PM18 and NM18 are defeated Enter the signal output end connection of the reverse data signal nd of chain of inverters circuit evolving, the external number of the grid of the PM17 and NM17 It is believed that number D；The equal external power supply of the source electrode of described PM17, PM18, PM19, PM20, PM21；The PM17, PM18, PM19, PM20, The drain electrode of PM21 is connect with the signal output end of the set signal sn of set-reset signal generating circuit；The drain electrode of the NM21 It is connect with the drain electrode of PM17, the source electrode of NM21 is connected with the drain electrode of NM20, and the source electrode of NM20 is connected with the drain electrode of NM19, NM19's Source electrode is connected with the drain electrode of NM18, and the source electrode of NM18 is connected with the drain electrode of NM17, the source electrode ground connection of NM17；The PM22 and NM22 The signal output end of inverting clock signal nclk1 that generates of grid and clocked inverter chain circuit connect；The PM23 and The grid of NM23 is connect with the signal output end for the in-phase clock signal bclk2 that clocked inverter chain circuit generates, the PM24 The signal output end of the data-signal d1 generated with the grid of NM24 and D input inverter chain circuit is connect, the PM25 and The grid of NM25 is connect with the signal output end for the reverse data signal nd that D input inverter chain circuit generates, the PM26 and The grid external data signal D of NM26；The source electrode external power supply of the PM22；The drain electrode of the PM22 connects with the source electrode of PM23 Connect, the drain electrode of the PM23 is connect with the source electrode of PM24, and the drain electrode of the PM24 is connect with the source electrode of PM25, the drain electrode of PM25 with The source electrode of PM26 connects, and the drain electrode of the PM26 is connect with the drain electrode of NM26, described NM22, NM23, NM24, NM25, NM26's Drain electrode is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The NM22, NM23, NM24, The source grounding of NM25, NM26；

The main DICE latch cicuit be by 24 PMOS tube PM27, PM28, PM29, PM30, PM31, PM32, PM33, PM34、PM35 、PM36、PM37、PM38、PM39、PM40、PM41、PM42 、PM43、PM44、PM45、PM46、PM47、PM48、 PM49, PM50 and 27 NMOS tube NM27, NM28, NM29, NM30, NM31, NM32, NM33, NM34, NM35, NM36, NM37, NM38、 NM39 、NM40、NM41、NM42、NM43、NM44 、NM45 、NM46、NM47、NM48、NM49、NM50、NM51、 NM52, NM53 and three transmission gate TM1, TM2, TM3 compositions；The grid external data signal D of the PM27, and with NM27's Grid is connected, the source electrode external power supply of PM27, and drain electrode connects with the source electrode of PM28；The grid and clocked inverter chain of the PM28 The signal output end of the in-phase clock signal bclk1 of circuit evolving connects, the drain electrode of PM28 respectively with the drain electrode of NM28, PM35 Grid, PM34 are connected with the grid of the drain electrode of NM34, NM44；The grid of the NM28 generates anti-with clocked inverter chain circuit The signal output end of clock signal nclk1 connects, and source electrode is connected with the drain electrode of NM27；The grid external data of the PM29 Signal d1, and be connected with the grid of NM29, the source electrode external power supply of PM29, drain electrode connects with the source electrode of PM30；The PM30's Grid is connect with the signal output end for the in-phase clock signal bclk2 that clocked inverter chain circuit generates, the drain electrode difference of PM30 It is connected with the drain electrode of NM30, the drain electrode of the grid of NM36, the grid of PM39, PM38 and NM38；The grid and clock of the NM30 The signal output end of the inverting clock signal nclk2 of chain of inverters circuit evolving connects, and source electrode is connected with the drain electrode of NM29；Institute The grid external data signal d2 of PM31 is stated, and is connected with the grid of NM31, the source electrode external power supply of PM31, drain electrode is with PM32's Source electrode connects；The signal output end for the in-phase clock signal bclk3 that the grid and clocked inverter chain circuit of the PM32 generates Connection, the drain electrode of PM32 are connected with the drain electrode of NM32, the drain electrode of the grid of NM40, the grid of PM43, PM42 and NM42 respectively；Institute It states the grid of NM32 and the signal output end of inverting clock signal nclk3 that clocked inverter chain circuit generates is connect, source electrode It is connected with the drain electrode of NM31；The grid of the PM33 respectively with the drain electrode of the drain electrode of PM44 and NM44, PM47 and NM47, NM41 Grid is connected, the source electrode external power supply of PM33, and drain electrode connects with the source electrode of PM34；The grid and clocked inverter chain of the PM34 The signal output end of the inverting clock signal nclk1 of circuit evolving connects, and the drain electrode of PM34 is connected with the drain electrode of NM34 respectively；Institute It states the grid of NM34 and the signal output end of in-phase clock signal bclk1 that clocked inverter chain circuit generates is connect, source electrode It is connected with the drain electrode of NM33；The grid of the NM33 respectively with the drain electrode of the grid of PM37, PM36 and NM36, PM45 and NM45 Drain electrode is connected；The drain electrode of the source electrode external power supply of the PM35, PM35 is connected with the source electrode of PM36；The grid of the PM36 with set The signal output end connection of the reset signal r of position reset signal generating circuit, the drain electrode of PM36 are connect with the drain electrode of NM36 respectively； The drain electrode of the source electrode and NM35 of the NM36 connects, the grid of the NM35 and the set signal of set-reset signal generating circuit The signal output end of sn connects；The drain electrode of the source electrode external power supply of the PM37, PM37 is connected with the source electrode of PM38 respectively；It is described The grid of PM38 is connect with the signal output end for the inverting clock signal nclk2 that clocked inverter chain circuit generates, the leakage of PM38 Pole is connect with the drain electrode of NM38 respectively；The in-phase clock signal that the grid and clocked inverter chain circuit of the NM38 generates The signal output end of bclk2 connects, the drain electrode connection of source electrode and NM37；The source electrode external power supply of the PM39, the leakage of PM39 Pole is connected with the source electrode of PM40；The signal of the reset signal r of the grid and set-reset signal generating circuit of the PM40 exports End connection, the drain electrode of PM40 are connect with the drain electrode of NM40 respectively；The drain electrode of the source electrode and NM39 of the NM40 connects, the NM39 Grid connect with the signal output end of the set signal sn of set-reset signal generating circuit；The external electricity of the source electrode of the PM41 The drain electrode in source, PM41 is connected with the source electrode of PM42 respectively；The reverse phase that the grid and clocked inverter chain circuit of the PM42 generates The signal output end of clock signal nclk3 connects, and the drain electrode of PM42 is connect with the drain electrode of NM42 respectively；The grid of the NM42 with The signal output end connection for the in-phase clock signal bclk3 that clocked inverter chain circuit generates, the drain electrode of source electrode and NM41 connect It connects；The drain electrode of the source electrode external power supply of the PM43, PM43 is connected with the source electrode of PM44；The grid and set-reset of the PM44 The signal output end of the reset signal r of signal generating circuit connects, and the drain electrode of PM44 is connect with the drain electrode of NM44 respectively；It is described The drain electrode of the source electrode and NM43 of NM44 connects, the set signal sn's of the grid and set-reset signal generating circuit of the NM43 Signal output end connection；The signal output end of the set signal sn of the grid and set-reset signal generating circuit of the PM45 connects It connects, source electrode external power supply, drain electrode is connect with the left data input port of the drain electrode of NM45, transmission gate TM1 respectively；It is described The grid of NM45 is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM48 and The grid of NM49 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, and the source electrode of PM48 is external Power supply, drain electrode are connect with the drain electrode of the right side data-out port, NM49 of transmission gate TM1 respectively；The source electrode of the NM49 with The drain electrode of NM48 connects, and the signal output end of the reset signal r of the grid and set-reset signal generating circuit of the NM48 connects It connects；The drain electrode output of the PM48 all the way data-signal m1 to from DICE latch cicuit；The grid and set-reset of the PM46 The signal output end of the set signal sn of signal generating circuit connects, source electrode external power supply, drain electrode respectively with the drain electrode of NM46, The left data input port of transmission gate TM2 connects；The reset of the grid and set-reset signal generating circuit of the NM46 is believed The signal output end connection of number r；The set of the grid of the PM49 and the grid of NM51 with set-reset signal generating circuit The signal output end of signal sn connects, the source electrode external power supply of PM49, and drain electrode is exported with the right side data of transmission gate TM2 respectively The drain electrode connection of port, NM51；The drain electrode of the source electrode and NM50 of the NM51 connects, and the grid and set-reset of the NM50 is believed The signal output end connection of the reset signal r of number generation circuit；The PM49 drain electrode output another way data-signal m2 to from DICE latch cicuit；The signal output end of the set signal sn of the grid and set-reset signal generating circuit of the PM47 connects It connects, source electrode external power supply, drain electrode is connect with the left data input port of the drain electrode of NM47, transmission gate TM3 respectively；It is described The grid of NM47 is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM50 and The grid of NM53 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, and the source electrode of PM50 is external Power supply, drain electrode are connect with the drain electrode of the right side data-out port, NM53 of transmission gate TM3 respectively；The source electrode of the NM53 with The drain electrode of NM52 connects, and the signal output end of the reset signal r of the grid and set-reset signal generating circuit of the NM52 connects It connects；The drain electrode output another way data-signal m3 of the PM50 is extremely from DICE latch cicuit；The NM27, NM29, NM31, The source grounding of NM33, NM35, NM37, NM39, NM41, NM43, NM45, NM46, NM47, NM48, NM50, NM52；It is described The signal output end for the inverting clock signal nclk1 that the inverted control terminals and clocked inverter chain circuit of transmission gate TM1 generate connects It connects, the signal output end of the in-phase clock signal bclk1 of the same phase control end of transmission gate TM1 and the generation of clocked inverter chain circuit Connection, the signal for the inverting clock signal nclk2 that the inverted control terminals and clocked inverter chain circuit of the transmission gate TM2 generate The letter for the in-phase clock signal bclk2 that output end connection, the same phase control end of transmission gate TM2 and clocked inverter chain circuit generate The connection of number output end；The inverting clock signal that the inverted control terminals and clocked inverter chain circuit of the transmission gate TM3 generate The signal output end of nclk3 connects, and the in-phase clock of the same phase control end of transmission gate TM3 and the generation of clocked inverter chain circuit is believed The signal output end connection of number bclk3；

It is described from DICE latch cicuit be by 15 PMOS tube PM51, PM52, PM53, PM54, PM55, PM56, PM57, PM58, PM59, PM60, PM61, PM62, PM63, PM64, PM65 and 15 NMOS tube NM54, NM55, NM56, NM57, NM58, NM59, NM60, NM61, NM62, NM63, NM64, NM65, NM66, NM67, NM68 composition；The grid of the PM51 and set are multiple The signal output end connection of the reset signal r of position signal generating circuit, source electrode external power supply, drain electrode are connect with the source electrode of PM52； The grid of the PM52 connects with the grid of the drain electrode of PM62 and NM65, the grid of the grid of NM63 and PM63 and NM66 respectively It connects, drain electrode is connected with the source electrode of PM53；The in-phase clock signal that the grid and clocked inverter chain circuit of the PM53 generates The signal output end of bclk1 connects, the drain electrode of PM53 respectively with the drain electrode of NM56, the grid of PM54, the grid of NM65 and master The output end connection of data-signal m1 all the way in DICE latch cicuit；The grid and clocked inverter chain circuit of the NM56 generates Inverting clock signal nclk1 signal output end connection, source electrode is connected with the drain electrode of NM55；The grid of the NM55 is distinguished It is connect with the grid of the drain electrode of PM54 and NM57, the grid of PM56 and PM65 and NM68, source electrode is connected with the drain electrode of NM54； The grid of the NM54 is connect with the signal output end of the set signal sn of set-reset signal generating circuit；The source of the PM54 Pole external power supply, drain electrode are connect with the drain electrode of NM57；The grid of NM57 grid with the drain electrode of PM57 and NM60, PM58 respectively Pole with the output end of data-signal m2 connects all the way in main DICE latch cicuit；The grid and set-reset signal of the PM55 produces The signal output end connection of the reset signal r of raw circuit, source electrode external power supply, drain electrode are connect with the source electrode of PM56；The PM56 Drain electrode be connected with the source electrode of PM57；The in-phase clock signal that the grid and clocked inverter chain circuit of the PM57 generates The signal output end of bclk2 connects, and the drain electrode of PM57 is connect with the drain electrode of NM60；The grid and clocked inverter chain of the NM60 The signal output end of the inverting clock signal nclk2 of circuit evolving connects, and source electrode is connected with the drain electrode of NM59；The NM59's Source electrode is connected with the drain electrode of NM58；The grid of the NM58 and the signal of the set signal sn of set-reset signal generating circuit are defeated Outlet connection；The source electrode external power supply of the PM58, drain electrode are connect with the drain electrode of NM61；The grid of the NM61 respectively with PM61 With the drain electrode of NM64, PM62 grid with the output end of data-signal m3 connects all the way in main DICE latch cicuit；The PM59 Grid connect with the signal output end of the reset signal r of set-reset signal generating circuit, source electrode external power supply, drain electrode with The source electrode of PM60 connects；The drain electrode of the PM60 is connected with the source electrode of PM61；Grid and clocked inverter the chain electricity of the PM61 The signal output end connection for the in-phase clock signal bclk3 that road generates, the drain electrode of PM61 are connect with the drain electrode of NM64；The NM64 The signal output end of inverting clock signal nclk3 that generates of grid and clocked inverter chain circuit connect, source electrode and NM63 Drain electrode be connected；The source electrode of the NM63 is connected with the drain electrode of NM62；The grid and set-reset signal of the NM62 generates electricity The signal output end of the set signal sn on road connects；The source electrode external power supply of the PM62, drain electrode are connect with the drain electrode of NM65；Institute The source electrode external power supply of PM63 is stated, drain electrode is connect with the source electrode of PM64；The grid of the PM64 and the grid of NM67 connect, leakage The connection of the source electrode of pole and PM65, the drain electrode of the PM65 are connect with the drain electrode of NM68；The drain electrode of the source electrode and NM67 of the NM68 It is connected, the drain electrode of the source electrode and NM66 of NM67 connects；The drain electrode outputting data signals Q of the PM65；The NM54, NM57, The source grounding of NM58, NM61, NM62, NM65, NM66.

In the above-mentioned technical solutions, when rising edge clock signal arrives, if data terminal D is receiving a SET just just Pulse carries out trigger asynchronous then the reset signal r of reset-set signal generating circuit output will generate a positive pulse It resets, conversely, when data terminal D receives a SET negative pulse, the set signal sn of reset-set signal generating circuit output A negative pulse will be generated, asynchronous set is carried out to trigger, when trigger is not at rising edge clock signal or data terminal D When not having SET pulse interference, reset signal and set signal are all in invalid state, i.e. r is low level, and sn is high level, this When circuit maintain work normally.Since using C cell filter circuit, the settling time of the trigger will not shorten, thus Improve timing performance.The circuit also uses three and mutually latches (TICE) technology simultaneously, relative to common based on DICE Radioresistance trigger, there is better anti-SEU characteristic.

Detailed description of the invention

Fig. 1 is the principle assumption diagram that flip-flop circuit is mutually latched on a kind of three tunnels based on SET detection of the utility model；

Fig. 2 is the clocked inverter chain electricity that flip-flop circuit is mutually latched on a kind of three tunnels based on SET detection of the utility model Lu Tu；

Fig. 3 is the D input inverter chain electricity that flip-flop circuit is mutually latched on a kind of three tunnels based on SET detection of the utility model Lu Tu；

Fig. 4 is that a kind of set-reset signal that flip-flop circuit is mutually latched on three tunnels based on SET detection of the utility model produces Raw circuit diagram；

Fig. 5 is the main DICE latch cicuit that flip-flop circuit is mutually latched on a kind of three tunnels based on SET detection of the utility model Figure；

Fig. 6 is the slave DICE latch cicuit that flip-flop circuit is mutually latched on a kind of three tunnels based on SET detection of the utility model Figure；

Fig. 7 is that set-reset signal production in flip-flop circuit is mutually latched on a kind of three tunnels based on SET detection of the utility model The reset signal r of raw circuit generates timing diagram；

Fig. 8 is that set-reset signal production in flip-flop circuit is mutually latched on a kind of three tunnels based on SET detection of the utility model The set signal sn of raw circuit generates timing diagram.

Specific embodiment

Flip-flop circuit is mutually latched on three tunnels based on SET detection a kind of to the utility model with reference to the accompanying drawings and examples It is described in further detail.The attached drawing for constituting the application is used to provide a further understanding of the present invention, the utility model Illustrative embodiments and their description for explaining the utility model, do not constitute improper limits to the present invention.

By Fig. 1-Fig. 6 as it can be seen that the present embodiment it is a kind of based on SET detection three tunnels mutually latch flip-flop circuit include when Clock chain of inverters circuit, D input inverter chain circuit, set-reset signal generating circuit, main DICE latch cicuit and from DICE Latch cicuit.The clock signal CK of the outside of the present embodiment is separately input to clocked inverter chain circuit and set-reset signal produces Raw circuit, external clock signal CK through clocked inverter chain circuit generate three road in-phase clock signal bclk1, bclk2, Bclk3 and three road inverting clock signal nclk1, nclk2, nclk3；External data signal D is separately input to D input inverter chain Circuit and set-reset signal generating circuit, external data signal D generate two circuit-switched data signals through D input inverter chain circuit D1, d2 and all the way anti-phase data signal nd；Clock signal CK, data-signal D, D input inverter chain circuit generate a circuit-switched data Signal d1 and all the way anti-phase data signal nd and two road inverting clock signal nclk1, nclk2 and all the way in-phase clock signal Bclk2 exports set signal sn and reset signal r after set-reset signal generating circuit；The data-signal D, three Lu Tongxiang Clock signal bclk1, bclk2, bclk3 and three road inverting clock signal nclk1, nclk2, nclk3 and two circuit-switched data signal d1, D2 and set signal sn and reset signal r is input to main DICE latch cicuit, exports three numbers after main DICE latch cicuit It is believed that number m1, m2, m3；When the set signal sn and reset signal r, three Lu Tongxiang of the set-reset signal generating circuit output Clock signal bclk1, bclk2, bclk3 and three road inverting clock signal nclk1, nclk2, nclk3 and main DICE latch cicuit Three data signal m1, m2 and m3 of output are input to from DICE latch cicuit, are then exported through after DICE latch cicuit Data-signal Q.

By Fig. 1, Fig. 2 as it can be seen that the clocked inverter chain circuit of the present embodiment be by 12 PMOS tube PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12 and 12 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12 composition；The PM1 and NM1, PM2 and NM2, PM3 and NM3, PM4 and NM4, PM5 and NM5, PM6 and NM6, PM7 and NM7, PM8 and NM8, PM9 and NM9, PM10 and NM10, PM11 and NM11, PM12 and NM12 difference A phase inverter is constituted, the clock signal CK is connect with the input terminal of phase inverter PM1 and NM1, is produced after inverted device PM1 and NM1 Raw inverting clock signal nclk1；The input terminal of the phase inverter PM2 and NM2 is connect with the output end of phase inverter PM1 and NM1, warp In-phase clock signal bclk1 is generated after phase inverter PM2 and NM2；The input terminal and clock signal CK of the phase inverter PM3 and NM3 Connection, output end are connect with the input terminal of phase inverter PM4 and NM4, the input terminal and phase inverter PM4 of the phase inverter PM5 and NM5 It is connected with the output end of NM4, output end is connect with the input terminal of phase inverter PM6 and NM6, the inverted device PM3 of clock signal CK When with generating after generation inverting clock signal nclk2, then inverted device PM6 and NM6 after NM3, PM4 and NM4, PM5 and NM5 with phase Clock signal bclk2；The input terminal of the phase inverter PM7 and NM7 is connect with clock signal CK, output end and phase inverter PM8 and NM8 Input terminal connection, the input terminal of the phase inverter PM9 and NM9 connect with the output end of phase inverter PM8 and NM8, output end It is connect with the input terminal of phase inverter PM10 and NM10, the input terminal and phase inverter PM10 and NM10 of the phase inverter PM11 and NM11 Output end connection, output end connect with the input terminal of phase inverter PM12 and NM12, the inverted device PM7 of clock signal CK with Inverting clock signal nclk3, then inverted device are generated after NM7, PM8 and NM8, PM9 and NM9, PM10 and NM10, PM11 and NM11 In-phase clock signal bclk3 is generated after PM12 and NM12.

By Fig. 1, Fig. 3 as it can be seen that the D input inverter chain circuit of the present embodiment be by 4 PMOS tube PM13, PM14, PM15, PM16 and 4 NMOS tube NM13, NM14, NM15, NM16 composition；The PM13 and NM13, PM14 and NM14, PM15 and NM15, PM16 and NM16 respectively constitutes a phase inverter；The data-signal D is connect with the input terminal of phase inverter PM13 and NM13, inverted Reverse data signal nd is generated after device PM13 and NM13；The anti-phase data signal nd is input to the defeated of phase inverter PM14 and NM14 Enter end, generates data-signal d1 after inverted device PM14 and NM14；The input terminal and phase inverter of the phase inverter PM15 and NM15 PM14 is connected with the output end of NM14, and output end generates reverse data signal nd1, and the anti-phase data signal nd1 is input to instead The input terminal of phase device PM16 and NM16 generate data-signal d2 after inverted device PM16 and NM16.

By Fig. 1, Fig. 4 as it can be seen that the set-reset signal generating circuit of the present embodiment be by 10 PMOS tube PM17, PM18, PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26 and 10 NMOS tube NM17, NM18, NM19, NM20, NM21, NM22, NM23, NM24, NM25, NM26 composition；The grid of the PM21 and NM21 is connect with the output end of clock signal CK；Institute It states the grid of PM20 and NM20 and the signal output end of inverting clock signal nclk2 that clocked inverter chain circuit generates is connect, The grid of the PM19 and NM19 is connect with the signal output end for the data-signal d1 that D input inverter chain circuit generates, described The grid of PM18 and NM18 is connect with the signal output end for the reverse data signal nd that D input inverter chain circuit generates, described The grid external data signal D of PM17 and NM17；The equal external power supply of the source electrode of described PM17, PM18, PM19, PM20, PM21；Institute The drain electrode for stating PM17, PM18, PM19, PM20, PM21 is defeated with the signal of the set signal sn of set-reset signal generating circuit Outlet connection；The drain electrode of the NM21 is connect with the drain electrode of PM17, and the source electrode of NM21 is connected with the drain electrode of NM20, the source electrode of NM20 It is connected with the drain electrode of NM19, the source electrode of NM19 is connected with the drain electrode of NM18, and the source electrode of NM18 is connected with the drain electrode of NM17, NM17's Source electrode ground connection；The signal for the inverting clock signal nclk1 that the grid and clocked inverter chain circuit of the PM22 and NM22 generates Output end connection；The letter for the in-phase clock signal bclk2 that the grid and clocked inverter chain circuit of the PM23 and NM23 generates The signal of the connection of number output end, the data-signal d1 that the grid and D input inverter chain circuit of the PM24 and NM24 generate is defeated The grid of outlet connection, the PM25 and NM25 and the signal for the reverse data signal nd that D input inverter chain circuit generates are defeated Outlet connection, the grid external data signal D of the PM26 and NM26；The source electrode external power supply of the PM22；The PM22's Drain electrode is connect with the source electrode of PM23, and the drain electrode of the PM23 is connect with the source electrode of PM24, the drain electrode of the PM24 and the source of PM25 Pole connection, the drain electrode of PM25 are connect with the source electrode of PM26, and the drain electrode of the PM26 is connect with the drain electrode of NM26, the NM22, The drain electrode of NM23, NM24, NM25, NM26 are connect with the signal output end of the reset signal r of set-reset signal generating circuit； The source grounding of described NM22, NM23, NM24, NM25, NM26.

By Fig. 1, Fig. 5 as it can be seen that the main DICE latch cicuit of the present embodiment be by 24 PMOS tube PM27, PM28, PM29, PM30、PM31、PM32、PM33、PM34、PM35 、PM36、PM37、PM38、PM39、PM40、PM41、PM42 、PM43、PM44、 PM45, PM46, PM47, PM48, PM49, PM50 and 27 NMOS tube NM27, NM28, NM29, NM30, NM31, NM32, NM33, NM34、NM35、NM36、NM37、NM38、 NM39 、NM40、NM41、NM42、NM43、NM44 、NM45 、NM46、NM47、 NM48, NM49, NM50, NM51, NM52, NM53 and three transmission gate TM1, TM2, TM3 compositions；The grid of the PM27 is external Data-signal D, and be connected with the grid of NM27, the source electrode external power supply of PM27, drain electrode connects with the source electrode of PM28；The PM28 The signal output end of in-phase clock signal bclk1 that generates of grid and clocked inverter chain circuit connect, the drain electrode point of PM28 It is not connected with the grid of the drain electrode of the drain electrode of NM28, the grid of PM35, PM34 and NM34, NM44；The grid of the NM28 and when The signal output end of the inverting clock signal nclk1 of clock chain of inverters circuit evolving connects, and source electrode is connected with the drain electrode of NM27； The grid external data signal d1 of the PM29, and being connected with the grid of NM29, the source electrode external power supply of PM29, drain electrode and PM30 Source electrode connect；The signal for the in-phase clock signal bclk2 that the grid and clocked inverter chain circuit of the PM30 generates exports End connection, the drain electrode of PM30 are connected with the drain electrode of NM30, the drain electrode of the grid of NM36, the grid of PM39, PM38 and NM38 respectively； The grid of the NM30 is connect with the signal output end for the inverting clock signal nclk2 that clocked inverter chain circuit generates, source Pole is connected with the drain electrode of NM29；The grid external data signal d2 of the PM31, and be connected with the grid of NM31, the source electrode of PM31 External power supply, drain electrode connect with the source electrode of PM32；The in-phase clock that the grid and clocked inverter chain circuit of the PM32 generates The signal output end of signal bclk3 connects, the drain electrode of PM32 respectively with the drain electrode of NM32, the grid of NM40, PM43 grid, PM42 is connected with the drain electrode of NM42；The inverting clock signal nclk3 that the grid and clocked inverter chain circuit of the NM32 generates Signal output end connection, source electrode is connected with the drain electrode of NM31；The grid of the PM33 respectively with the drain electrode of PM44 and NM44, PM47 is connected with the grid of the drain electrode of NM47, NM41, the source electrode external power supply of PM33, and drain electrode connects with the source electrode of PM34；It is described The grid of PM34 is connect with the signal output end for the inverting clock signal nclk1 that clocked inverter chain circuit generates, the leakage of PM34 Pole is connected with the drain electrode of NM34 respectively；The in-phase clock signal that the grid and clocked inverter chain circuit of the NM34 generates The signal output end of bclk1 connects, and source electrode is connected with the drain electrode of NM33；The grid of the NM33 respectively with the grid of PM37, PM36 is connected with the drain electrode of the drain electrode of NM36, PM45 and NM45；The source electrode external power supply of the PM35, the drain electrode of PM35 and PM36 Source electrode be connected；The grid of the PM36 is connect with the signal output end of the reset signal r of set-reset signal generating circuit, The drain electrode of PM36 is connect with the drain electrode of NM36 respectively；The drain electrode of the source electrode and NM35 of the NM36 connects, the grid of the NM35 It is connect with the signal output end of the set signal sn of set-reset signal generating circuit；The source electrode external power supply of the PM37, The drain electrode of PM37 is connected with the source electrode of PM38 respectively；The inversion clock that the grid and clocked inverter chain circuit of the PM38 generates The signal output end of signal nclk2 connects, and the drain electrode of PM38 is connect with the drain electrode of NM38 respectively；The grid and clock of the NM38 The signal output end of the in-phase clock signal bclk2 of chain of inverters circuit evolving connects, the drain electrode connection of source electrode and NM37；Institute The source electrode external power supply of PM39 is stated, the drain electrode of PM39 is connected with the source electrode of PM40；The grid and set-reset signal of the PM40 The signal output end of the reset signal r of generation circuit connects, and the drain electrode of PM40 is connect with the drain electrode of NM40 respectively；The NM40's The drain electrode of source electrode and NM39 connect, and the signal of the set signal sn of the grid and set-reset signal generating circuit of the NM39 is defeated Outlet connection；The drain electrode of the source electrode external power supply of the PM41, PM41 is connected with the source electrode of PM42 respectively；The grid of the PM42 The signal output end of inverting clock signal nclk3 generated with clocked inverter chain circuit is connect, the drain electrode of PM42 respectively with The drain electrode of NM42 connects；The signal for the in-phase clock signal bclk3 that the grid and clocked inverter chain circuit of the NM42 generates Output end connection, the drain electrode connection of source electrode and NM41；The source electrode external power supply of the PM43, the drain electrode of PM43 and the source of PM44 Extremely it is connected；The grid of the PM44 is connect with the signal output end of the reset signal r of set-reset signal generating circuit, PM44's Drain electrode is connect with the drain electrode of NM44 respectively；The drain electrode of the source electrode and NM43 of the NM44 connects, the grid of the NM43 and set The signal output end of the set signal sn of reset signal generating circuit connects；The grid and set-reset signal of the PM45 generates The signal output end of the set signal sn of circuit connects, source electrode external power supply, drain electrode respectively with the drain electrode of NM45, transmission gate The left data input port of TM1 connects；The letter of the reset signal r of the grid and set-reset signal generating circuit of the NM45 The connection of number output end；The grid of the PM48 and the grid of NM49 are with the set signal sn's of set-reset signal generating circuit Signal output end connection, the source electrode external power supply of PM48, drain electrode respectively with the right side data-out port of transmission gate TM1, The drain electrode of NM49 connects；The drain electrode of the source electrode and NM48 of the NM49 connects, and the grid and set-reset signal of the NM48 produces The signal output end connection of the reset signal r of raw circuit；Data-signal m1 is locked to from DICE all the way for the drain electrode output of the PM48 Deposit circuit；The grid of the PM46 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, source Pole external power supply, drain electrode are connect with the left data input port of the drain electrode of NM46, transmission gate TM2 respectively；The grid of the NM46 Pole is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM49 and the grid of NM51 It is extremely connect with the signal output end of the set signal sn of set-reset signal generating circuit, the source electrode external power supply of PM49, Drain electrode is connect with the drain electrode of the right side data-out port, NM51 of transmission gate TM2 respectively；The leakage of the source electrode and NM50 of the NM51 Pole connection, the signal output end of the reset signal r of the grid and set-reset signal generating circuit of the NM50 are connect；It is described The drain electrode output another way data-signal m2 of PM49 is extremely from DICE latch cicuit；The grid and set-reset signal of the PM47 produces The signal output end connection of the set signal sn of raw circuit, source electrode external power supply, drain electrode respectively with the drain electrode of NM47, transmission gate The left data input port of TM3 connects；The letter of the reset signal r of the grid and set-reset signal generating circuit of the NM47 The connection of number output end；The grid of the PM50 and the grid of NM53 are with the set signal sn's of set-reset signal generating circuit Signal output end connection, the source electrode external power supply of PM50, drain electrode respectively with the right side data-out port of transmission gate TM3, The drain electrode of NM53 connects；The drain electrode of the source electrode and NM52 of the NM53 connects, and the grid and set-reset signal of the NM52 produces The signal output end connection of the reset signal r of raw circuit；The drain electrode output another way data-signal m3 of the PM50 is extremely from DICE Latch cicuit；The NM27, NM29, NM31, NM33, NM35, NM37, NM39, NM41, NM43, NM45, NM46, NM47, The source grounding of NM48, NM50, NM52；What the inverted control terminals and clocked inverter chain circuit of the transmission gate TM1 generated The signal output end of inverting clock signal nclk1 connects, and the same phase control end of transmission gate TM1 and clocked inverter chain circuit generate In-phase clock signal bclk1 signal output end connection, the inverted control terminals of the transmission gate TM2 and clocked inverter chain electricity The signal output end connection for the inverting clock signal nclk2 that road generates, the same phase control end of transmission gate TM2 and clocked inverter chain The signal output end of the in-phase clock signal bclk2 of circuit evolving connects；The inverted control terminals and clock of the transmission gate TM3 are anti- The signal output end connection for the inverting clock signal nclk3 that phase device chain circuit generates, the same phase control end of transmission gate TM3 and clock The signal output end of the in-phase clock signal bclk3 of chain of inverters circuit evolving connects.

By Fig. 1, Fig. 6 as it can be seen that the slave DICE latch cicuit of the present embodiment be by 15 PMOS tube PM51, PM52, PM53, PM54, PM55, PM56, PM57, PM58, PM59, PM60, PM61, PM62, PM63, PM64, PM65 and 15 NMOS tube NM54, NM55, NM56, NM57, NM58, NM59, NM60, NM61, NM62, NM63, NM64, NM65, NM66, NM67, NM68 composition；Institute The signal output end for stating the grid of PM51 and the reset signal r of set-reset signal generating circuit is connect, source electrode external power supply, leakage The connection of the source electrode of pole and PM52；The grid of PM52 grid with the drain electrode of PM62 and NM65, the grid of NM63 and PM63 respectively The connection of the grid of pole and NM66, drain electrode are connected with the source electrode of PM53；The grid and clocked inverter chain circuit of the PM53 The signal output end of the in-phase clock signal bclk1 of generation connects, the grid with the drain electrode of NM56, PM54 respectively that drain of PM53 Pole, NM65 grid with the output end of data-signal m1 connects all the way in main DICE latch cicuit；The grid of the NM56 and when The signal output end of the inverting clock signal nclk1 of clock chain of inverters circuit evolving connects, and source electrode is connected with the drain electrode of NM55； The grid of the NM55 is connect with the grid of the drain electrode of PM54 and NM57, the grid of PM56 and PM65 and NM68 respectively, source Pole is connected with the drain electrode of NM54；The signal of the set signal sn of the grid and set-reset signal generating circuit of the NM54 exports End connection；The source electrode external power supply of the PM54, drain electrode are connect with the drain electrode of NM57；The grid of the NM57 respectively with PM57 and The drain electrode of NM60, PM58 grid with the output end of data-signal m2 connects all the way in main DICE latch cicuit；The PM55's Grid is connect with the signal output end of the reset signal r of set-reset signal generating circuit, source electrode external power supply, drain electrode and PM56 Source electrode connection；The drain electrode of the PM56 is connected with the source electrode of PM57；The grid and clocked inverter chain circuit of the PM57 is raw At in-phase clock signal bclk2 signal output end connection, the drain electrode of PM57 connect with the drain electrode of NM60；The grid of the NM60 Pole is connect with the signal output end for the inverting clock signal nclk2 that clocked inverter chain circuit generates, the leakage of source electrode and NM59 Extremely it is connected；The source electrode of the NM59 is connected with the drain electrode of NM58；The grid of the NM58 and set-reset signal generating circuit The signal output end of set signal sn connects；The source electrode external power supply of the PM58, drain electrode are connect with the drain electrode of NM61；It is described The grid of NM61 respectively with the drain electrode of PM61 and NM64, PM62 grid and main DICE latch cicuit in data-signal m3 all the way Output end connection；The grid of the PM59 is connect with the signal output end of the reset signal r of set-reset signal generating circuit, source Pole external power supply, drain electrode are connect with the source electrode of PM60；The drain electrode of the PM60 is connected with the source electrode of PM61；The grid of the PM61 It is connect with the signal output end of the in-phase clock signal bclk3 of clocked inverter chain circuit generation, the drain electrode of PM61 is with NM64's Drain electrode connection；The signal output end for the inverting clock signal nclk3 that the grid and clocked inverter chain circuit of the NM64 generates Connection, source electrode are connected with the drain electrode of NM63；The source electrode of the NM63 is connected with the drain electrode of NM62；The grid of the NM62 with set The signal output end connection of the set signal sn of position reset signal generating circuit；The source electrode external power supply of the PM62, drain electrode with The drain electrode of NM65 connects；The source electrode external power supply of the PM63, drain electrode are connect with the source electrode of PM64；The grid of the PM64 with The grid of NM67 connects, and drain electrode is connect with the source electrode of PM65, and the drain electrode of the PM65 is connect with the drain electrode of NM68；The NM68 Source electrode be connected with the drain electrode of NM67, the drain electrode of the source electrode of NM67 and NM66 connect；The drain electrode outputting data signals of the PM65 Q；The source grounding of described NM54, NM57, NM58, NM61, NM62, NM65, NM66.

As seen from Figure 7, the present embodiment generated on timing diagram from reset signal r as can be seen that nclk1 signal be by PM1 and The inverting clock signal that the phase inverter that NM1 is constituted generates, certain delay can be generated relative to CK signal, likewise, bclk1 believes It number is the in-phase clock signal that the phase inverter being made of PM2 and NM2 generates, there is also certain to prolong relative to nclk1 by bclk1 When, the appropriate breadth length ratio that each metal-oxide-semiconductor in clocked inverter chain circuit is arranged, nclk2 can be made with respect to bclk1, and there are one Fixed delay, there is also certain delays with respect to nclk2 by bclk2.

In the present embodiment, if in rising edge clock, when data input pin D receives a SET positive pulse, this positive arteries and veins Punching is possible to that the TICE structure of trigger can be allowed to store the data of this mistake just, but when reset signal r is generated It can be seen that on sequence figure in the period between two dotted lines, D, reverse data signal nd, d1, nclk1 and bclk2 locate The nor gate that NM22 ~ NM26 in low level state, and in Fig. 4 and PM22 ~ PM26 is constituted, and if only if D, nd, d1, When this five signals of nclk1 and bclk2 are low level simultaneously, exporting as r is high level, and when r signal is high level, it can incite somebody to action It main TICE latch cicuit and is resetted simultaneously from TICE latch cicuit, so that it is guaranteed that trigger is not influenced by SET positive pulse.

In the present embodiment, r signal is high level effectively and sn signal is when being that high level is invalid, main TICE and is in from TICE Reset state, the principle resetted are as follows: PM36 and PM45 cut-off, NM45 conducting, so that node a1 be made to be reset to low level. PM40 and PM46 cut-off, NM46 conducting, so that node a2 be made to be reset to low level.PM44 and PM47 cut-off, NM47 conducting, thus Node a3 is set to be reset to low level.

In the present embodiment, PM48 and PM51 cut-off, NM48 and NM49 are connected, so that node m1 be made to be reset to low level. PM49 and PM55 cut-off, NM50 and NM51 conducting, so that node m2 be made to be reset to low level.PM50 and PM59 cut-off, NM52 and NM53 conducting, so that node m3 be made to be reset to low level.When m1, m2 and m3 are reset to low level, by TICE, mutually latch is acted on It influences, q1, q2 and q3 can become high level, be low level so as to cause output Q.

Similar, as seen from Figure 8, if in rising edge clock, when data input pin D receives a SET negative pulse, this A negative pulse is possible to that the TICE structure of trigger can be allowed to store the data of this mistake just, but in set signal sn It generates in the period that can be seen that on timing diagram between two dotted lines, D, nd, d1, CK and nclk2 are all in high level shape State, and the NAND gate that NM17 ~ NM21 in Fig. 4 and PM17 ~ PM21 is constituted, and if only if D, d1, d2, CK and nclk2 this five When a signal is high level simultaneously, exporting as sn is low level, and when sn signal is low level, it can be by main TICE latch cicuit With from TICE latch cicuit simultaneously set, so that it is guaranteed that trigger is not influenced by SET negative pulse.

In the present embodiment, sn signal is low level effectively and r signal is when being that low level is invalid, main TICE and is in from TICE The principle of SM set mode, set is as follows: NM35 and NM45 cut-off, PM45 conducting, to make node a1 set high level. NM39 and NM46 cut-off, PM46 conducting, to make node a2 set high level.NM43 and NM47 cut-off, PM47 conducting, thus Make node a3 set high level.

In the present embodiment, PM48 conducting, NM48, NM49 and NM54 cut-off, to make node m1 set high level.PM49 Conducting, NM50, NM51 and NM58 cut-off, to make node m2 set high level.PM50 conducting, NM52, NM53 and NM62 are cut Only, to make node m3 set high level.When m1, m2 and m3 set are high level, function influence is mutually latched by TICE, Q1, q2 and q3 can become low level, be high level so as to cause output Q.

It mutually latches flip-flop circuit and in the past based on C cell filtering in three tunnels based on SET detection described in the present embodiment Radioresistance trigger is compared, and to more advanced in the SET pulse processing mode of data input pin, be embodied in and withouted waiting for inputting The filtering of data, the data no matter sampled are high level or low level, can all be sent directly into main TICE latches Get up, then judges whether the data being sent into are SET pulse and decide whether pair by set-reset signal generating circuit Trigger carries out set or reset, reduces the biggish settling time of filtering wave by prolonging time generation, to make the timing of trigger Performance is more preferable.

The above is only the embodiments of the present invention, not imposes any restrictions to the utility model, all according to this Utility model technical spirit any simple modification, change and the variation of equivalent method to the above embodiments, still belong to In in the protection scope of technical solutions of the utility model.

Claims (1)

1. flip-flop circuit is mutually latched on a kind of three tunnels based on SET detection, it is characterised in that: the mutual latched flip flop electricity in three tunnels Road includes clocked inverter chain circuit, D input inverter chain circuit, set-reset signal generating circuit, main DICE latch cicuit With from DICE latch cicuit；External clock signal CK is separately input to clocked inverter chain circuit and set-reset signal generates Circuit, external clock signal CK generate three road in-phase clock signal bclk1, bclk2, bclk3 through clocked inverter chain circuit With three road inverting clock signal nclk1, nclk2, nclk3；External data signal D is separately input to D input inverter chain circuit With set-reset signal generating circuit, external data signal D generates two circuit-switched data signal d1, d2 through D input inverter chain circuit Anti-phase data signal nd all the way；Clock signal CK, data-signal D, D input inverter chain circuit generate data-signal d1 all the way Anti-phase data signal nd and two road inverting clock signal nclk1, nclk2 and all the way in-phase clock signal bclk2 warp all the way Set signal sn and reset signal r is exported after set-reset signal generating circuit；The data-signal D, three road in-phase clocks letter Number bclk1, bclk2, bclk3 and three road inverting clock signal nclk1, nclk2, nclk3 and two circuit-switched data signal d1, d2 and Set signal sn and reset signal r is input to main DICE latch cicuit, and three data signal is exported after main DICE latch cicuit m1,m2,m3；The set signal sn and reset signal r, three road in-phase clock signals of the set-reset signal generating circuit output What bclk1, bclk2, bclk3 and three road inverting clock signal nclk1, nclk2, nclk3 and main DICE latch cicuit were exported Three data signal m1, m2 and m3 are input to from DICE latch cicuit, and then output data is believed after from DICE latch cicuit Number Q；

The clocked inverter chain circuit be by 12 PMOS tube PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12 and 12 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12 composition；The PM1 and NM1, PM2 and NM2, PM3 and NM3, PM4 and NM4, PM5 and NM5, PM6 and NM6, PM7 and NM7, PM8 and NM8, PM9 and NM9, PM10 and NM10, PM11 and NM11, PM12 and NM12 respectively constitute a phase inverter, the clock letter Number CK is connect with the input terminal of phase inverter PM1 and NM1, and inverting clock signal nclk1 is generated after inverted device PM1 and NM1；It is described The input terminal of phase inverter PM2 and NM2 are connect with the output end of phase inverter PM1 and NM1, generate same phase after inverted device PM2 and NM2 Clock signal bclk1；The input terminal of the phase inverter PM3 and NM3 is connect with clock signal CK, output end and phase inverter PM4 and The input terminal of NM4 connects, and the input terminal of the phase inverter PM5 and NM5 is connect with the output end of phase inverter PM4 and NM4, exports End is connect with the input terminal of phase inverter PM6 and NM6, after clock signal CK inverted device PM3 and NM3, PM4 and NM4, PM5 and NM5 In-phase clock signal bclk2 is generated after generating inverting clock signal nclk2, then inverted device PM6 and NM6；The phase inverter PM7 It is connect with the input terminal of NM7 with clock signal CK, output end is connect with the input terminal of phase inverter PM8 and NM8, the phase inverter The input terminal of PM9 and NM9 is connect with the output end of phase inverter PM8 and NM8, the input of output end and phase inverter PM10 and NM10 End connection, the input terminal of the phase inverter PM11 and NM11 connect with the output end of phase inverter PM10 and NM10, output end and Phase inverter PM12 is connected with the input terminal of NM12, clock signal CK inverted device PM7 and NM7, PM8 and NM8, PM9 and NM9, When being generated after generation inverting clock signal nclk3, then inverted device PM12 and NM12 with phase after PM10 and NM10, PM11 and NM11 Clock signal bclk3；

The D input inverter chain circuit be by 4 PMOS tube PM13, PM14, PM15, PM16 and 4 NMOS tube NM13, NM14, NM15, NM16 composition；The PM13 and NM13, PM14 and NM14, PM15 and NM15, PM16 and NM16 respectively constitute one Phase inverter；The data-signal D is connect with the input terminal of phase inverter PM13 and NM13, is generated after inverted device PM13 and NM13 anti- To data-signal nd；The anti-phase data signal nd is input to the input terminal of phase inverter PM14 and NM14, inverted device PM14 and Data-signal d1 is generated after NM14；The input terminal of the phase inverter PM15 and NM15 and the output end of phase inverter PM14 and NM14 connect It connects, output end generates reverse data signal nd1, and the anti-phase data signal nd1 is input to the input of phase inverter PM16 and NM16 It holds, data-signal d2 is generated after inverted device PM16 and NM16；

The set-reset signal generating circuit be by 10 PMOS tube PM17, PM18, PM19, PM20, PM21, PM22, PM23, PM24, PM25, PM26 and 10 NMOS tubes NM17, NM18, NM19, NM20, NM21, NM22, NM23, NM24, NM25, NM26 Composition；The grid of the PM21 and NM21 is connect with the output end of clock signal CK；The grid and clock of the PM20 and NM20 The signal output end of the inverting clock signal nclk2 of chain of inverters circuit evolving connects, and the grid and D of the PM19 and NM19 are defeated Enter the signal output end connection of the data-signal d1 of chain of inverters circuit evolving, grid and the D input of the PM18 and NM18 are anti- The grid external data letter of the signal output end connection for the reverse data signal nd that phase device chain circuit generates, the PM17 and NM17 Number D；The equal external power supply of the source electrode of described PM17, PM18, PM19, PM20, PM21；Described PM17, PM18, PM19, PM20, PM21 Drain electrode connect with the signal output end of the set signal sn of set-reset signal generating circuit；The drain electrode of the NM21 with The drain electrode of PM17 connects, and the source electrode of NM21 is connected with the drain electrode of NM20, and the source electrode of NM20 is connected with the drain electrode of NM19, the source of NM19 Pole is connected with the drain electrode of NM18, and the source electrode of NM18 is connected with the drain electrode of NM17, the source electrode ground connection of NM17；The PM22's and NM22 Grid is connect with the signal output end for the inverting clock signal nclk1 that clocked inverter chain circuit generates；The PM23 and NM23 The signal output end of in-phase clock signal bclk2 that generates of grid and clocked inverter chain circuit connect, the PM24 and The grid of NM24 is connect with the signal output end for the data-signal d1 that D input inverter chain circuit generates, the PM25 and NM25 The signal output end of reverse data signal nd that generates of grid and D input inverter chain circuit connect, the PM26 and NM26 Grid external data signal D；The source electrode external power supply of the PM22；The drain electrode of the PM22 is connect with the source electrode of PM23, institute The drain electrode for stating PM23 is connect with the source electrode of PM24, and the drain electrode of the PM24 is connect with the source electrode of PM25, the drain electrode of PM25 and PM26 Source electrode connection, the drain electrode of the PM26 connect with the drain electrode of NM26, the drain electrode of described NM22, NM23, NM24, NM25, NM26 It is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The NM22, NM23, NM24, NM25, The source grounding of NM26；

The main DICE latch cicuit be by 24 PMOS tube PM27, PM28, PM29, PM30, PM31, PM32, PM33, PM34, PM35 、PM36、PM37、PM38、PM39、PM40、PM41、PM42 、PM43、PM44、PM45、PM46、PM47、PM48、PM49、 PM50 and 27 NMOS tube NM27, NM28, NM29, NM30, NM31, NM32, NM33, NM34, NM35, NM36, NM37, NM38, NM39 、NM40、NM41、NM42、NM43、NM44 、NM45 、NM46、NM47、NM48、NM49、NM50、NM51、NM52、NM53 And three transmission gate TM1, TM2, TM3 compositions；The grid external data signal D of the PM27, and be connected with the grid of NM27, The source electrode external power supply of PM27, drain electrode connect with the source electrode of PM28；The grid and clocked inverter chain circuit of the PM28 generates In-phase clock signal bclk1 signal output end connection, PM28 drain electrode respectively with the drain electrode of NM28, PM35 grid, PM34 is connected with the grid of the drain electrode of NM34, NM44；When the reverse phase that the grid and clocked inverter chain circuit of the NM28 generates The signal output end of clock signal nclk1 connects, and source electrode is connected with the drain electrode of NM27；The grid external data signal of the PM29 D1, and be connected with the grid of NM29, the source electrode external power supply of PM29, drain electrode connects with the source electrode of PM30；The grid of the PM30 The signal output end of in-phase clock signal bclk2 generated with clocked inverter chain circuit is connect, the drain electrode of PM30 respectively with The drain electrode of NM30, the grid of NM36, the grid of PM39, PM38 are connected with the drain electrode of NM38；The grid of the NM30 and clock are anti- The signal output end connection for the inverting clock signal nclk2 that phase device chain circuit generates, source electrode are connected with the drain electrode of NM29；It is described The grid external data signal d2 of PM31, and be connected with the grid of NM31, the source electrode external power supply of PM31, the source of drain electrode and PM32 Pole connects；The signal output end for the in-phase clock signal bclk3 that the grid and clocked inverter chain circuit of the PM32 generates connects It connects, the drain electrode of PM32 is connected with the drain electrode of NM32, the drain electrode of the grid of NM40, the grid of PM43, PM42 and NM42 respectively；It is described The grid of NM32 is connect with the signal output end for the inverting clock signal nclk3 that clocked inverter chain circuit generates, source electrode with The drain electrode of NM31 is connected；The grid of PM33 grid with the drain electrode of the drain electrode of PM44 and NM44, PM47 and NM47, NM41 respectively Extremely it is connected, the source electrode external power supply of PM33, drain electrode connects with the source electrode of PM34；Grid and clocked inverter the chain electricity of the PM34 The signal output end connection for the inverting clock signal nclk1 that road generates, the drain electrode of PM34 are connected with the drain electrode of NM34 respectively；It is described The grid of NM34 is connect with the signal output end for the in-phase clock signal bclk1 that clocked inverter chain circuit generates, source electrode with The drain electrode of NM33 is connected；The leakage with the drain electrode of the grid of PM37, PM36 and NM36, PM45 and NM45 respectively of the grid of the NM33 Extremely it is connected；The drain electrode of the source electrode external power supply of the PM35, PM35 is connected with the source electrode of PM36；The grid of the PM36 and set The signal output end of the reset signal r of reset signal generating circuit connects, and the drain electrode of PM36 is connect with the drain electrode of NM36 respectively；Institute The drain electrode for stating the source electrode and NM35 of NM36 connects, the grid of the NM35 and the set signal sn of set-reset signal generating circuit Signal output end connection；The drain electrode of the source electrode external power supply of the PM37, PM37 is connected with the source electrode of PM38 respectively；It is described The grid of PM38 is connect with the signal output end for the inverting clock signal nclk2 that clocked inverter chain circuit generates, the leakage of PM38 Pole is connect with the drain electrode of NM38 respectively；The in-phase clock signal that the grid and clocked inverter chain circuit of the NM38 generates The signal output end of bclk2 connects, the drain electrode connection of source electrode and NM37；The source electrode external power supply of the PM39, the leakage of PM39 Pole is connected with the source electrode of PM40；The signal of the reset signal r of the grid and set-reset signal generating circuit of the PM40 exports End connection, the drain electrode of PM40 are connect with the drain electrode of NM40 respectively；The drain electrode of the source electrode and NM39 of the NM40 connects, the NM39 Grid connect with the signal output end of the set signal sn of set-reset signal generating circuit；The external electricity of the source electrode of the PM41 The drain electrode in source, PM41 is connected with the source electrode of PM42 respectively；The reverse phase that the grid and clocked inverter chain circuit of the PM42 generates The signal output end of clock signal nclk3 connects, and the drain electrode of PM42 is connect with the drain electrode of NM42 respectively；The grid of the NM42 with The signal output end connection for the in-phase clock signal bclk3 that clocked inverter chain circuit generates, the drain electrode of source electrode and NM41 connect It connects；The drain electrode of the source electrode external power supply of the PM43, PM43 is connected with the source electrode of PM44；The grid and set-reset of the PM44 The signal output end of the reset signal r of signal generating circuit connects, and the drain electrode of PM44 is connect with the drain electrode of NM44 respectively；It is described The drain electrode of the source electrode and NM43 of NM44 connects, the set signal sn's of the grid and set-reset signal generating circuit of the NM43 Signal output end connection；The signal output end of the set signal sn of the grid and set-reset signal generating circuit of the PM45 connects It connects, source electrode external power supply, drain electrode is connect with the left data input port of the drain electrode of NM45, transmission gate TM1 respectively；It is described The grid of NM45 is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM48 and The grid of NM49 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, and the source electrode of PM48 is external Power supply, drain electrode are connect with the drain electrode of the right side data-out port, NM49 of transmission gate TM1 respectively；The source electrode of the NM49 with The drain electrode of NM48 connects, and the signal output end of the reset signal r of the grid and set-reset signal generating circuit of the NM48 connects It connects；The drain electrode output of the PM48 all the way data-signal m1 to from DICE latch cicuit；The grid and set-reset of the PM46 The signal output end of the set signal sn of signal generating circuit connects, source electrode external power supply, drain electrode respectively with the drain electrode of NM46, The left data input port of transmission gate TM2 connects；The reset of the grid and set-reset signal generating circuit of the NM46 is believed The signal output end connection of number r；The set of the grid of the PM49 and the grid of NM51 with set-reset signal generating circuit The signal output end of signal sn connects, the source electrode external power supply of PM49, and drain electrode is exported with the right side data of transmission gate TM2 respectively The drain electrode connection of port, NM51；The drain electrode of the source electrode and NM50 of the NM51 connects, and the grid and set-reset of the NM50 is believed The signal output end connection of the reset signal r of number generation circuit；The PM49 drain electrode output another way data-signal m2 to from DICE latch cicuit；The signal output end of the set signal sn of the grid and set-reset signal generating circuit of the PM47 connects It connects, source electrode external power supply, drain electrode is connect with the left data input port of the drain electrode of NM47, transmission gate TM3 respectively；It is described The grid of NM47 is connect with the signal output end of the reset signal r of set-reset signal generating circuit；The grid of the PM50 and The grid of NM53 is connect with the signal output end of the set signal sn of set-reset signal generating circuit, and the source electrode of PM50 is external Power supply, drain electrode are connect with the drain electrode of the right side data-out port, NM53 of transmission gate TM3 respectively；The source electrode of the NM53 with The drain electrode of NM52 connects, and the signal output end of the reset signal r of the grid and set-reset signal generating circuit of the NM52 connects It connects；The drain electrode output another way data-signal m3 of the PM50 is extremely from DICE latch cicuit；The NM27, NM29, NM31, The source grounding of NM33, NM35, NM37, NM39, NM41, NM43, NM45, NM46, NM47, NM48, NM50, NM52；It is described The signal output end for the inverting clock signal nclk1 that the inverted control terminals and clocked inverter chain circuit of transmission gate TM1 generate connects It connects, the signal output end of the in-phase clock signal bclk1 of the same phase control end of transmission gate TM1 and the generation of clocked inverter chain circuit Connection, the signal for the inverting clock signal nclk2 that the inverted control terminals and clocked inverter chain circuit of the transmission gate TM2 generate The letter for the in-phase clock signal bclk2 that output end connection, the same phase control end of transmission gate TM2 and clocked inverter chain circuit generate The connection of number output end；The inverting clock signal that the inverted control terminals and clocked inverter chain circuit of the transmission gate TM3 generate The signal output end of nclk3 connects, and the in-phase clock of the same phase control end of transmission gate TM3 and the generation of clocked inverter chain circuit is believed The signal output end connection of number bclk3；

It is described from DICE latch cicuit be by 15 PMOS tube PM51, PM52, PM53, PM54, PM55, PM56, PM57, PM58, PM59, PM60, PM61, PM62, PM63, PM64, PM65 and 15 NMOS tube NM54, NM55, NM56, NM57, NM58, NM59, NM60, NM61, NM62, NM63, NM64, NM65, NM66, NM67, NM68 composition；The grid and set-reset signal of the PM51 The signal output end of the reset signal r of generation circuit connects, source electrode external power supply, and drain electrode is connect with the source electrode of PM52；It is described The grid of PM52 is connect with the grid of the drain electrode of PM62 and NM65, the grid of the grid of NM63 and PM63 and NM66 respectively, Drain electrode is connected with the source electrode of PM53；The in-phase clock signal bclk1 that the grid and clocked inverter chain circuit of the PM53 generates Signal output end connection, PM53 drain electrode respectively with the drain electrode of NM56, the grid of PM54, the grid of NM65 and main DICE latch The output end connection of data-signal m1 all the way in circuit；When the reverse phase that the grid and clocked inverter chain circuit of the NM56 generates The signal output end of clock signal nclk1 connects, and source electrode is connected with the drain electrode of NM55；The grid of the NM55 respectively with PM54 and The drain electrode of NM57, the grid of PM56 and PM65 are connected with the grid of NM68, and source electrode is connected with the drain electrode of NM54；The NM54 Grid connect with the signal output end of the set signal sn of set-reset signal generating circuit；The external electricity of the source electrode of the PM54 Source, drain electrode are connect with the drain electrode of NM57；The grid of the NM57 respectively with the drain electrode of PM57 and NM60, the grid of PM58 and master The output end connection of data-signal m2 all the way in DICE latch cicuit；The grid and set-reset signal generating circuit of the PM55 Reset signal r signal output end connection, source electrode external power supply, drain electrode connect with the source electrode of PM56；The drain electrode of the PM56 It is connected with the source electrode of PM57；The letter for the in-phase clock signal bclk2 that the grid and clocked inverter chain circuit of the PM57 generates The connection of number output end, the drain electrode of PM57 are connect with the drain electrode of NM60；The grid and clocked inverter chain circuit of the NM60 generates Inverting clock signal nclk2 signal output end connection, source electrode is connected with the drain electrode of NM59；The source electrode of the NM59 with The drain electrode of NM58 is connected；The signal output end of the set signal sn of the grid and set-reset signal generating circuit of the NM58 connects It connects；The source electrode external power supply of the PM58, drain electrode are connect with the drain electrode of NM61；The grid of the NM61 respectively with PM61 and NM64 Drain electrode, PM62 grid with the output end of data-signal m3 connects all the way in main DICE latch cicuit；The grid of the PM59 It is connect with the signal output end of the reset signal r of set-reset signal generating circuit, source electrode external power supply, the source of drain electrode and PM60 Pole connection；The drain electrode of the PM60 is connected with the source electrode of PM61；What the grid and clocked inverter chain circuit of the PM61 generated The signal output end of in-phase clock signal bclk3 connects, and the drain electrode of PM61 is connect with the drain electrode of NM64；The grid of the NM64 with The signal output end connection for the inverting clock signal nclk3 that clocked inverter chain circuit generates, the drain electrode phase of source electrode and NM63 Even；The source electrode of the NM63 is connected with the drain electrode of NM62；The set of the grid and set-reset signal generating circuit of the NM62 The signal output end of signal sn connects；The source electrode external power supply of the PM62, drain electrode are connect with the drain electrode of NM65；The PM63's Source electrode external power supply, drain electrode are connect with the source electrode of PM64；The grid of the PM64 and the grid of NM67 connect, drain electrode and PM65 Source electrode connection, the drain electrode of the PM65 connect with the drain electrode of NM68；The source electrode of the NM68 is connected with the drain electrode of NM67, NM67 Source electrode and NM66 drain electrode connect；The drain electrode outputting data signals Q of the PM65；The NM54, NM57, NM58, NM61, The source grounding of NM62, NM65, NM66.