CN207218665U - A Radiation Resistant Latch Circuit Based on C Cell and Transmission Gate - Google Patents

Abstract

The utility model discloses a kind of radioresistance latch circuit based on C cell and transmission gate, the radioresistance latch circuit is made up of clock generation circuit, D input filter circuits, multichannel latch cicuit, C cell circuit and voting circuit；The C cell circuit is made up of three tunnel same circuits；Outside clock signal CK generates clock signal and external data signal D through clock generation circuit and generates data-signal after multichannel latch cicuit and C cell circuit through D input filter circuits, and the data-signal of output exports the output signal Q of whole trigger through voting circuit.The technical solution of the utility model uses multichannel latch technique, and the upset probability of Latch output signal can be made to decline to a great extent, while reduces the chip area of trigger, reduces power consumption, and the anti-SET abilities of circuit greatly improved.

Description

A Radiation Resistant Latch Circuit Based on C Cell and Transmission Gate

technical field

The utility model relates to the design of an anti-radiation circuit, in particular to an anti-radiation latch circuit based on a C unit and a transmission gate for single event flipping.

Background technique

With the progress of integrated circuit manufacturing process, the reduction of device size and the improvement of working speed, the influence of radiation on circuits has become more and more serious. The main impact of radiation on digital circuits is reflected in single event effect (Single Event Effect, SEE) and total dose effect (Total Ionizing Dose, TID). At that time, the single event effect has become the most important radiation effect affecting MOS devices. Single event effects are mainly divided into single event transient (Single Event Transient, SET) and single event upset (Single Event Upset, SEU).

In a radiation environment, MOS integrated circuits are bombarded by high-energy charged particles. When charged particles bombard the drain region of the originally cut-off MOS transistor, due to the energy transfer of high-energy charged particles, a large number of freely movable carriers, namely holes and electrons, will be generated in a short period of time, so that the originally cut-off MOS transistor conducts pass, thereby changing the output level of the device. Since the carriers generated by high-energy particles will quickly recombine or discharge over time and return to the carrier concentration state before the bombardment, the MOS tube that is hit will have a process from cut-off to conduction to cut-off again , reflected on the output of the MOS tube, a positive or negative pulse waveform will be generated. This transient pulse effect is called a single event transient. For combinational logic circuits, single event transient effects can affect the output of the circuit. In a sequential circuit, when the positive pulse or negative pulse generated by a single event transient is received by a flip-flop or other storage circuit, or the storage part of the circuit is directly hit by a high-energy particle and flips, due to the memory function of the circuit, this This flip cannot be recovered, so that the output of the entire circuit is wrong. This effect is called a single event flip.

Both the single event transient effect and the single event reversal effect will affect the normal operation of the circuit, so it is necessary to strengthen the MOS integrated circuit working in the radiation environment (Radiation Harden). The current hardening schemes for sequential circuits mainly include system-level hardening, circuit-level hardening, and layout-level hardening, or use SOI and other processes for hardening. For circuit-level hardening of flip-flops in sequential circuits, Triple Modular Redundancy (TMR) and Dual Interlocked Storage Cell (DICE) technologies are currently used for hardening.

The main principle of the TMR reinforcement technology is to duplicate the flip-flops in three copies, and pass the outputs of the three flip-flop circuits through the voting circuit to form a final output, because the voting circuit has the function of selecting two out of three. Therefore, even if one flip-flop flips, it will not affect the output of the entire circuit. The principle of the DICE reinforcement technology is to add a double interlock structure to the flip-flop. There is a pair of sensitive nodes in the double interlock structure, and the overall output of the flip-flop depends on the level of the pair of sensitive nodes. In the absence of irradiation, the levels of this pair of sensitive nodes are consistent. When receiving irradiation, the output of the circuit can remain unchanged when one of a pair of sensitive nodes is flipped by high-energy particles, and at the same time, under the action of another sensitive node, the flipped node will quickly recover to Normal state, so that the entire circuit remains stable and is not affected by radiation. However, the main disadvantage of TMR circuit reinforcement technology and DICE circuit reinforcement technology is that the reliability is not high enough. Assuming that the flip-flop probability without circuit-level reinforcement technology is , under the premise of not considering the correlation of sensitive nodes and the tolerance difference of nodes to injected charges, after adopting TMR reinforcement, the flip-flop output flip probability drops to , and the flip-flop probability using DICE hardening technology is . Therefore, in order to ensure the normal operation of the circuit for a long time, a combination of circuit-level DICE reinforcement and system-level triple-mode redundancy reinforcement is generally used, and this method will inevitably lead to a double increase in circuit area and power consumption. , and at the same time, the timing performance of the circuit will deteriorate, and the operating frequency will drop.

Contents of the invention

The purpose of this utility model is to provide a kind of anti-radiation latch circuit based on C unit and transmission gate. The flip-flop probability of the output signal of the flip-flop is greatly reduced, and at the same time, the layout area of the flip-flop is reduced, the power consumption is reduced, and the anti-SET capability of the circuit is greatly improved.

In order to achieve the above object, the technical solution adopted by the utility model to solve the technical problem is: a radiation-resistant latch circuit based on C unit and transmission gate, including clock generation circuit, D input filter circuit, C unit circuit and voting circuit, the C unit circuit is composed of three identical circuits; it is characterized in that: the anti-radiation latch circuit also includes multiple latch circuits; the external clock signal CK generates three in-phase clock signals bclk1, bclk2 and bclk3 and three-way inverting clock signals nclk1, nclk2 and nclk3; external data signal D passes D input filter circuit to generate three-way data signals D1, D2 and D3; three-way in-phase clock signals bclk1, bclk2 and bclk3, and three-way inversion The phase clock signals nclk1, nclk2 and nclk3 and the three data signals D1, D2 and D3 are input to the multi-channel latch circuit, and the three-channel data signal T1, T2 and T3 are output after passing through the multi-channel latch circuit; the output of the multi-channel latch circuit The two-way data signals T1 and T2, T1 and T3, T2 and T3 are respectively input to the three-way C unit circuit, and the three-way C unit circuit generates data signals Q3, Q2 and Q1 respectively, and the data signals Q1, Q2 and Q3 are input Output the output signal Q of the entire flip-flop to the voting circuit;

The multi-way latch circuit is composed of 12 PMOS tubes PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12 and 12 NMOS tubes NM1, NM2, NM3, NM4, NM5 , NM6, NM7, NM8, NM9, NM10, NM11, NM12 and three transmission gates TM1, TM2, TM3; the PM7, PM8, NM7, NM8 and PM9, PM10, NM9, NM10 and PM11, PM12, NM11, NM12 constitutes three C units respectively;

In the C unit that described PM7, PM8, NM7, NM8 form, the gate stage of PM7 is connected with the signal output terminal of the in-phase clock signal bclk1 that clock generation circuit generates, and the drain electrode of PM7 is connected with the source electrode of PM8, and described PM8 The gate of the gate is connected with the gate of NM7, and is connected with the signal output end of the data signal D1 of the D input filter circuit; the drain of the PM8 is connected with the drain of NM7 respectively, and the gate of the NM8 is connected with the clock generation circuit The signal output terminal of the generated inverse clock signal nclk1 is connected, the drain of NM8 is connected with the source of NM7, and the source of NM8 is grounded;

In the C unit composed of PM9, PM10, NM9, and NM10, the gate of PM9 is connected to the signal output end of the in-phase clock signal bclk2 generated by the clock generation circuit, and the drain of PM9 is connected to the source of PM10. The PM10 The gate of the gate is connected to the gate of NM9, and is connected to the signal output end of the data signal D2 of the D input filter circuit; the drain of the PM10 is connected to the drain of the NM9 respectively, and the gate of the NM10 is connected to the clock generation circuit The signal output terminal of the generated inverse clock signal nclk2 is connected, the drain of NM10 is connected with the source of NM9, and the source of NM10 is grounded;

In the C unit composed of PM11, PM12, NM11, and NM12, the gate of PM11 is connected to the signal output end of the in-phase clock signal bclk3 generated by the clock generation circuit, and the drain of PM11 is connected to the source of PM12. The PM12 The gate of the PM12 is connected to the gate of the NM11, and is connected to the signal output end of the data signal D3 of the D input filter circuit; the drain of the PM12 is connected to the drain of the NM11 respectively, and the gate of the NM12 is connected to the clock generation circuit The signal output terminal of the generated inverse clock signal nclk3 is connected, the drain of NM12 is connected with the source of NM11, and the source of NM12 is grounded;

The in-phase control ends of the transmission gates TM1, TM2, and TM3 are respectively connected to the signal output ends of the in-phase clock signals bclk1, bclk2, and bclk3 generated by the clock generation circuit, and the inversion control ends are respectively connected to the inversion clock signal nclk1 generated by the clock generation circuit. , The signal output terminals of nclk2 and nclk3 are connected;

The left side bidirectional data port of described transmission gate TM1 is connected with the drain level of PM1 and NM1 respectively, and the right side bidirectional data port is connected with the drain level of PM8 and the gate level of PM2 respectively; The left side bidirectional data port of described transmission gate TM2 respectively connected to the drains of PM3 and NM3, and the right bidirectional data ports are respectively connected to the drains of PM10 and the grid of PM4; the left bidirectional data ports of the transmission gate TM3 are respectively connected to the drains of PM5 and NM5, and the right The side bidirectional data ports are respectively connected to the drain level of PM12 and the gate level of PM6;

Described PM7, PM8, NM7, NM8 and PM9, PM10, NM9, NM10 and PM11, PM12, NM11, NM12 form three C units respectively, three groups of clock signals nclk1, bclk1, nclk2 that are output by clock generation circuit respectively, bclk2 and nclk3, bclk3 control, when the clock signal is valid, that is, when nclki=1 and bclki=0, the three sets of data signals D1, D2 and D3 are transmitted to the multi-channel latch circuit for storage, when nclki=0 and bclki=1 When , the latch signal in the multi-channel latch circuit remains unchanged and is transmitted to the three nodes T1, T2 and T3 in reverse and input to the three C unit circuits;

The gate of the PM1 is connected to the drains of PM6 and NM6 and the gate of NM5 respectively, the source of PM1 is connected to an external power supply, the drain is connected to the drain of NM1, and the drains of PM6 and NM6 output the data signal T3; The gate of PM2 is connected to the right side bidirectional data port of transmission gate TM1, the source of PM2 is connected to an external power supply, and the drain is respectively connected to the gate of NM1 and the drain of NM2; the gate of PM3 is connected to PM2 and NM2 The drain of PM2 is connected to the gate of NM1, the source of PM3 is connected to an external power supply, the drain is connected to the drain of NM3, and the drains of PM2 and NM2 output data signal T1; the gate of PM4 is connected to the right side of the transmission gate TM2 The source of PM4 is connected to an external power supply, and the drain is connected to the gate of NM3 and the drain of NM4 respectively; the gate of PM5 is connected to the drains of PM4 and NM4 and the gate of NM3, and PM5 The source of the source is connected to an external power supply, the drain is connected to the drain of NM5, and the drains of PM4 and NM4 output the data signal T2; the gate of the PM6 is connected to the right bidirectional data port of the transmission gate TM6, and the source of PM6 is externally connected to The power supply and the drain are respectively connected to the gate of NM5 and the drain of NM6;

The sources of NM1, NM2, NM3, NM4, NM5, and NM5 are all grounded.

In the above technical solution, the three output signals T1, T2 and T3 of the radiation-resistant latch circuit, assuming that T1 and T2 are overturned under the action of particles, then according to the working principle of the C unit circuit, Q1 and Q2 remain the same Change, the output of Q3 is reversed, and after Q1, Q2 and Q3 are input into the voter circuit, the output Q of the whole circuit remains unchanged. Therefore, even if two of the three sensitive nodes of the flip-flop are knocked over, the circuit output remains unchanged. This circuit has the following beneficial effects: First, this circuit adopts a new type of multi-channel latch technology, and a group of three sensitive nodes is set in the circuit structure. When two nodes in the three sensitive nodes are irradiated When flipped, the output of the circuit can remain unchanged, so that the flip probability of the latch output signal is greatly reduced; second, the circuit adopts multi-channel latch technology, which reduces the layout area of the flip-flop and reduces power consumption; Three, this circuit adopts multi-channel latch technology, which greatly improves the anti-SET capability of the circuit.

Description of drawings

Fig. 1 is a block diagram of the principle structure of a radiation-resistant latch circuit based on C unit and transmission gate of the utility model;

Fig. 2 is the circuit schematic diagram of the clock generation circuit in a kind of anti-radiation latch circuit based on C unit and transmission gate of the utility model;

Fig. 3 is the circuit schematic diagram of D input filter circuit in a kind of anti-radiation latch circuit based on C unit and transmission gate of the utility model;

Fig. 4 is a circuit schematic diagram of a multi-channel latch circuit in a radiation-resistant latch circuit based on C unit and transmission gate of the utility model;

Fig. 5 is a circuit schematic diagram of the C unit circuit in a radiation-resistant latch circuit based on the C unit and transmission gate of the utility model;

FIG. 6 is a schematic circuit diagram of a voting circuit in a radiation-resistant latch circuit based on a C unit and a transmission gate of the present invention.

Detailed ways

A radiation-resistant latch circuit based on the C unit and the transmission gate of the present invention will be further described in detail in conjunction with the accompanying drawings and embodiments. The accompanying drawings constituting this application are used to provide further understanding of the utility model, and the schematic embodiments of the utility model and their descriptions are used to explain the utility model, and do not constitute improper limitations to the utility model.

As can be seen from Figures 1 to 6, a radiation-resistant latch circuit based on a C unit and a transmission gate in this embodiment is composed of a clock generator, a D input filter, and a multi-channel latch Circuit, C unit circuit (C element) and voting circuit (voter). The unit C circuit in this embodiment is composed of three identical circuits. In this embodiment, the external clock signal CK generates three in-phase clock signals bclk1, bclk2 and bclk3 and three inverting clock signals nclk1, nclk2 and nclk3 through the clock generation circuit. The external data signal D passes through the D input filter circuit to generate three data signals D1, D2 and D3; three in-phase clock signals bclk1, bclk2 and bclk3, three inverse clock signals nclk1, nclk2 and nclk3, and three data signals D1 and D2 and D3 are input to the multi-channel latch circuit, and three data signals T1, T2 and T3 are output after passing through the multi-channel latch circuit; two data signals T1 and T2, T1 and T3, T2 and T3 output by the multi-channel latch circuit They are respectively input to the three C unit circuits, and the three C unit circuits respectively generate data signals Q3, Q2 and Q1, and the data signals Q1, Q2 and Q3 are input to the voting circuit to output the output signal Q of the entire flip-flop.

It can be seen from Figure 2 that the clock generator of this embodiment is responsible for generating three clock signals and corresponding inverted clock signals through the external CK signal through the inverter chain. The device chain will have different delays. The main purpose is to make the SET (Single Event Transient, SET) pulse input from the CK terminal reach the DICE (Dual Interlocked Storage Cell, DICE) circuit part at different times. Through the interlocking mechanism of DICE, the circuit is not affected by the SET on the CK signal, and the circuit can also increase the driving ability of the clock signal.

It can be seen from FIG. 3 that the D input filter circuit (D input filter) of this embodiment is responsible for passing the input D signal through the inverter and the C unit circuit to generate three signals D1, D2 and D3 for use by the DICE circuit. In this embodiment, by properly setting the width-to-length ratios of the two inverters in the circuit, different time delays can be obtained, so that the SET pulse at the D input terminal can be filtered out.

It can be seen from Fig. 1 and Fig. 4 that the multi-channel latch circuit of this embodiment is composed of 12 PMOS transistors PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12 and 12 NMOS transistors. It consists of tubes NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12 and three transmission gates TM1, TM2, TM3. In this embodiment, PM7, PM8, NM7, NM8 and PM9, PM10, NM9, NM10, and PM11, PM12, NM11, and NM12 form three C units respectively.

In the C unit composed of PM7, PM8, NM7 and NM8 of the present embodiment, the grid level of PM7 is connected to the signal output end of the in-phase clock signal bclk1 generated by the clock generation circuit, and the drain of PM7 is connected to the source of PM8. The gate of PM8 is connected with the gate of NM7, and is connected with the signal output terminal of the data signal D1 of the D input filter circuit; the drain of PM8 is connected with the drain of NM7 respectively, and the gate of NM8 is connected with the clock The signal output terminal of the inverted clock signal nclk1 generated by the generating circuit is connected, the drain of NM8 is connected with the source of NM7, and the source of NM8 is grounded.

In the C unit composed of PM9, PM10, NM9, and NM10 of the present embodiment, the grid level of PM9 is connected to the signal output end of the in-phase clock signal bclk2 generated by the clock generation circuit, and the drain of PM9 is connected to the source of PM10. The gate of the PM10 is connected with the gate of the NM9, and is connected with the signal output end of the data signal D2 of the D input filter circuit; the drain of the PM10 is connected with the drain of the NM9 respectively, and the gate of the NM10 is connected with the clock The signal output terminal of the inverted clock signal nclk2 generated by the generating circuit is connected, the drain of NM10 is connected with the source of NM9, and the source of NM10 is grounded.

In the C unit composed of PM11, PM12, NM11, and NM12 in this embodiment, the gate of PM11 is connected to the signal output end of the in-phase clock signal bclk3 generated by the clock generation circuit, and the drain of PM11 is connected to the source of PM12. The gate of the PM12 is connected with the gate of the NM11, and is connected with the signal output end of the data signal D3 of the D input filter circuit; the drain of the PM12 is connected with the drain of the NM11 respectively, and the gate of the NM12 is connected with the clock The signal output terminal of the inverted clock signal nclk3 generated by the generating circuit is connected, the drain of NM12 is connected with the source of NM11, and the source of NM12 is grounded.

The in-phase control ends of the transmission gates TM1, TM2, and TM3 of the present embodiment are respectively connected to the signal output ends of the in-phase clock signals bclk1, bclk2, and bclk3 generated by the clock generating circuit, and the inverting control ends are respectively connected to the inverting clock generated by the clock generating circuit. The signal output terminals of the signals nclk1, nclk2, nclk3 are connected.

In this embodiment, the left bidirectional data port of transmission gate TM1 is connected with the drains of PM1 and NM1 respectively, and the right bidirectional data port is connected with the drain of PM8 and the gate of PM2 respectively; the left bidirectional data port of transmission gate TM2 The ports are respectively connected to the drains of PM3 and NM3, and the right bidirectional data port is respectively connected to the drain of PM10 and the gate of PM4; the left bidirectional data port of the transmission gate TM3 is respectively connected to the drains of PM5 and NM5, and the right The bidirectional data port is connected with the drain level of PM12 and the gate level of PM6 respectively.

PM7, PM8, NM7, NM8 and PM9, PM10, NM9, NM10 and PM11, PM12, NM11, NM12 of the present embodiment form three C units respectively, three groups of clock signals nclk1, bclk1, bclk1, bclk1, nclk2, bclk2 and nclk3, bclk3 control, when the clock signal is valid, that is, when nclki=1 and bclki=0, the three sets of data signals D1, D2 and D3 are transmitted to the multi-channel latch circuit for storage, when nclki=0 and bclki =1, the latch signal in the multi-channel latch circuit remains unchanged and is transmitted to the three nodes of T1, T2 and T3 in reverse and input to the three C unit circuits. In this embodiment, the anti-SEU principle of the circuit is similar to DICE. When any sensitive node of the circuit is overturned, the three outputs of T1, T2 and T3 will recover quickly due to the interlock mechanism of the circuit.

In this embodiment, the gate of PM1 is connected to the drains of PM6 and NM6 and the gate of NM5 respectively, the source of PM1 is connected to an external power supply, the drain is connected to the drain of NM1, and the drains of PM6 and NM6 output data signals T3; the gate of the PM2 is connected to the right bidirectional data port of the transmission gate TM1, the source of the PM2 is connected to an external power supply, and the drain is connected to the gate of the NM1 and the drain of the NM2 respectively; the gate of the PM3 is connected to the drain of the NM2 The drains of PM2 and NM2 are connected to the gate of NM1, the source of PM3 is connected to an external power supply, the drain is connected to the drain of NM3, and the drains of PM2 and NM2 output data signal T1; the gate of PM4 is connected to the transmission gate The right side of TM2 is connected to the bidirectional data port, the source of PM4 is connected to an external power supply, and the drain is connected to the gate of NM3 and the drain of NM4 respectively; the gate of PM5 is connected to the drains of PM4 and NM4 and the gate of NM3 connected, the source of PM5 is connected to an external power supply, the drain is connected to the drain of NM5, and the drains of PM4 and NM4 output data signal T2; the gate of PM6 is connected to the right bidirectional data port of transmission gate TM6, and PM6 The source is connected to an external power supply, and the drain is respectively connected to the gate of NM5 and the drain of NM6. In this embodiment, the sources of NM1, NM2, NM3, NM4, NM5, and NM5 are all grounded.

Figure 5 is the C element circuit (C element) of this embodiment. It can be seen from Figure 5 that when the two signals of D1 and D2 are the same, the C element circuit is equivalent to an inverter, and the output Y is inverted from the input signals D1 and D2. When the two signals of D1 and D2 are different, the pull-up network and the pull-down network are disconnected at the same time, and the output Y relies on the charge stored in the capacitor to maintain the output signal unchanged.

Fig. 6 is the voting circuit (Voter) of this embodiment, it can be seen from Fig. 6 that when two or more signals of Q1, Q2 and Q3 are at high level, the output Q is at high level; When two or more signals in the signal are at low level, the output Q is at low level.

It can be seen from Fig. 1 of this embodiment that the radiation-resistant latch circuit of this embodiment is compared with the DICE structure latch, the three output signals T1, T2 and T3 of the radiation-resistant latch circuit of this embodiment, assuming T1 and T2 are overturned under the action of particles, then according to the working principle of the C unit circuit, Q1 and Q2 remain unchanged, and the output of Q3 is reversed, and after Q1, Q2 and Q3 are input into the voter circuit, the output Q of the entire circuit remains unchanged. Change. Therefore, even if two of the three sensitive nodes of the flip-flop are knocked over, the circuit output remains unchanged.

The above is only an embodiment of the utility model, and does not limit the utility model in any way. All simple modifications, changes and equivalent method changes made to the above embodiments according to the technical essence of the utility model still belong to the utility model. Within the scope of protection of utility model technical solutions.

Claims (1)

1. a kind of radioresistance latch circuit based on C cell and transmission gate, including clock generation circuit, D input filter circuits, C cell circuit and voting circuit, the C cell circuit are made up of three tunnel identical circuits；It is characterized in that：The radioresistance latch Circuit also includes multichannel latch cicuit；Outside clock signal CK generates three road in-phase clock signals through clock generation circuit Bclk1, bclk2 and bclk3 and three road inverting clock signal nclk1, nclk2 and nclk3；External data signal D inputs through D Filter circuit generates three circuit-switched data signal D1, D2 and D3；Three road in-phase clock signal bclk1, bclk2 and bclk3, three tunnels are anti-phase Clock signal nclk1, nclk2 and nclk3 and three circuit-switched data signal D1, D2 and D3 are input to multichannel latch cicuit, through multichannel Three circuit-switched data signal T1, T2 and T3 are exported after latch cicuit；Multichannel latch cicuit output two paths of data signal T1 and T2, T1 and T3, T2 and T3 are separately input to three road C cell circuits, and the road C cell circuits of Bing You tri- produce data-signal Q3, Q2 and Q1 respectively, Data-signal Q1, Q2 and Q3 are input to the output signal Q that voting circuit exports whole trigger；

The multichannel latch cicuit be by 12 PMOS PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12 and 12 NMOS tubes NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12 with And three transmission gate TM1, TM2, TM3 compositions；Described PM7, PM8, NM7, NM8 and PM9, PM10, NM9, NM10 and PM11, PM12, NM11, NM12 separately constitute three C cells；

In the C cell of PM7, PM8, NM7, NM8 composition, PM7 grid level and the in-phase clock of clock generation circuit generation are believed Number bclk1 signal output part connection, PM7 drain electrode connect with PM8 source electrode, the grid of the PM8 and NM7 grid level phase Even, and it is connected with the data-signal D1 of D input filter circuits signal output part；The drain electrode drain electrode with NM7 respectively of the PM8 It is connected, the signal output part for the inverting clock signal nclk1 that grid and the clock generation circuit of the NM8 generate is connected, NM8's Drain electrode is connected with NM7 source electrode, NM8 source ground；

In the C cell of PM9, PM10, NM9, NM10 composition, PM9 grid level and the in-phase clock of clock generation circuit generation Signal bclk2 signal output part connection, PM9 drain electrode connect with PM10 source electrode, the grid of the PM10 and NM9 grid level It is connected, and is connected with the data-signal D2 of D input filter circuits signal output part；The drain electrode of the PM10 is respectively with NM9's Drain electrode is connected, and the signal output part for the inverting clock signal nclk2 that grid and the clock generation circuit of the NM10 generate is connected, NM10 drain electrode is connected with NM9 source electrode, NM10 source ground；

In the C cell of described PM11, PM12, NM11, NM12 composition, during the same phase that PM11 grid level generates with clock generation circuit Clock signal bclk3 signal output part connection, PM11 drain electrode connects with PM12 source electrode, the grid of the PM12 and NM11's Grid level is connected, and is connected with the data-signal D3 of D input filter circuits signal output part；The drain electrode of the PM12 respectively with NM11 drain electrode is connected, the signal output of the grid and the inverting clock signal nclk3 of clock generation circuit generation of the NM12 End connection, NM12 drain electrode are connected with NM11 source electrode, NM12 source ground；

The in-phase clock signal that described transmission gate TM1, TM2, TM3 same phase control end generate with clock generation circuit respectively Bclk1, bclk2, bclk3 signal output part connection, inverted control terminals respectively with clock generation circuit generation it is anti-phase when Clock signal nclk1, nclk2, nclk3 signal output part connection；

Drain of the left side bidirectional data port of the transmission gate TM1 respectively with PM1 and NM1 is connected, right side bidirectional data port It is connected respectively with PM8 drain and PM2 grid level；The left side bidirectional data port of the transmission gate TM2 respectively with PM3 and NM3 Drain be connected, right side bidirectional data port is connected with PM10 drain and PM4 grid level respectively；A left side of the transmission gate TM3 Drain of the side bidirectional data port respectively with PM5 and NM5 is connected, the right side bidirectional data port drain and PM6 with PM12 respectively Grid level be connected；

Described PM7, PM8, NM7, NM8 and PM9, PM10, NM9, NM10 and PM11, PM12, NM11, NM12 are separately constituted In three C cells, respectively by three groups of clock signal nclk1, bclk1, nclk2 of clock generation circuit output, bclk2 and Nclk3, bclk3 are controlled, when clock signal is effective, i.e., nclki=1 and bclki=0 when, three groups of data-signal D1, D2 and D3 transmission Saved into multichannel latch cicuit, as nclki=0 and bclki=1, the latch signal in multichannel latch cicuit is kept not Become and anti-phase tri- nodes of T1, T2 and T3 that are delivered to are input in three C cell circuits；

The grid of the PM1 is connected with PM6 and NM6 drain electrode and NM5 grid respectively, PM1 source electrode external power supply, drain electrode Connect with NM1 drain electrode, PM6 and NM6 drain electrode outputting data signals T3；The grid of the PM2 is double with transmission gate TM1 right side It is connected to FPDP, PM2 source electrode external power supply, the drain electrode respectively with NM1 grid and NM2 that drains connects；The PM3's Grid is connected with PM2 and NM2 drain electrode and NM1 grid, PM3 source electrode external power supply, and drain electrode connects with NM3 drain electrode, PM2 and NM2 drain electrode outputting data signals T1；The grid of the PM4 is connected with transmission gate TM2 right side bidirectional data port, PM4 source electrode external power supply, the drain electrode respectively with NM3 grid and NM4 that drains connect；The grid of the PM5 and PM4 and NM4 Drain electrode and NM3 grid be connected, PM5 source electrode external power supply, drain electrode connects with NM5 drain electrode, PM4 and NM4 drain electrode Outputting data signals T2；The grid of the PM6 is connected with transmission gate TM6 right side bidirectional data port, the PM6 external electricity of source electrode Source, the drain electrode respectively with NM5 grid and NM6 that drains connect；

Described NM1, NM2, NM3, NM4, NM5, NM5 source grounding.