CN207218665U - A kind of radioresistance latch circuit based on C cell and transmission gate - Google Patents
A kind of radioresistance latch circuit based on C cell and transmission gate Download PDFInfo
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- 210000003771 C cell Anatomy 0.000 title claims abstract description 53
- 230000005540 biological transmission Effects 0.000 title claims abstract description 42
- 230000002457 bidirectional effect Effects 0.000 claims description 23
- 239000000203 mixture Substances 0.000 claims description 13
- 230000005611 electricity Effects 0.000 claims description 6
- 241000396836 Trinodes Species 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 17
- 230000007423 decrease Effects 0.000 abstract description 2
- 239000002245 particle Substances 0.000 description 14
- 230000000694 effects Effects 0.000 description 13
- 230000001052 transient effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000002787 reinforcement Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000001934 delay Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 210000000352 storage cell Anatomy 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 210000001367 artery Anatomy 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- RFHAOTPXVQNOHP-UHFFFAOYSA-N fluconazole Chemical compound C1=NC=NN1CC(C=1C(=CC(F)=CC=1)F)(O)CN1C=NC=N1 RFHAOTPXVQNOHP-UHFFFAOYSA-N 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
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Abstract
The utility model discloses a kind of radioresistance latch circuit based on C cell and transmission gate, the radioresistance latch circuit is made up of clock generation circuit, D input filter circuits, multichannel latch cicuit, C cell circuit and voting circuit；The C cell circuit is made up of three tunnel same circuits；Outside clock signal CK generates clock signal and external data signal D through clock generation circuit and generates data-signal after multichannel latch cicuit and C cell circuit through D input filter circuits, and the data-signal of output exports the output signal Q of whole trigger through voting circuit.The technical solution of the utility model uses multichannel latch technique, and the upset probability of Latch output signal can be made to decline to a great extent, while reduces the chip area of trigger, reduces power consumption, and the anti-SET abilities of circuit greatly improved.
Description
Technical field
The utility model is related to the design of radiation-hardened ic, be specifically related to single-particle inversion one kind be based on C cell and
The radioresistance latch circuit of transmission gate.
Background technology
With the progress of integrated circuit fabrication process, the diminution of device size and the lifting of operating rate, radiate to circuit
Influence also become increasingly severe.Radiate the main influence on digital circuit and be presented as single particle effect (Single Event
Effect, SEE) and total dose effect (Total Ionizing Dose, TID), as Deep Submicron MOSFETs turn into master
Stream, when the process node of especially MOS circuits reaches below 65nm, it is main that single particle effect has become influence MOS device
Radiation effect.Single particle effect is broadly divided into single-ion transient state (Single Event Transient, SET) and simple grain
Son upset (Single Event Upset, SEU).
Under radiation environment, MOS integrated circuits are by the charged particle bombardment of high energy.When charged particle bombardment ends to script
Metal-oxide-semiconductor drain region when, due to the energy transmission of high energy charged particles, the current-carrying that can largely move freely can be produced in the short time
Son, i.e. hole and electronics, so that the metal-oxide-semiconductor conducting of cut-off originally, so as to change the output level of device.Due to high energy particle
Caused carrier over time can be compound quickly or the carrier concentration state releasing and return to before bombardment, therefore is hit
Metal-oxide-semiconductor have one from by the end of being conducting to the process ended again, be reflected in metal-oxide-semiconductor output, a positive arteries and veins will be produced
Punching or the waveform of negative pulse.The pulse effects of this transient state is referred to as single-ion transient state.For combinational logic circuit, single-particle
Transient effect can influence the output of circuit.And in sequence circuit, when positive pulse caused by single-ion transient state or negative pulse are touched
Send out device or other storage circuits receive, or the storage part of circuit is directly hit by high energy particle and produces upset, due to electricity
The memory function on road so that this upset can not recover, so that the output of whole circuit produces mistake, this effect is referred to as single
Particle is overturn.
Either single-ion transient state effect or Single event upset effecf can all influence the normal work of circuit, therefore have must
The MOS integrated circuits to be worked under radiation environment are reinforced（Radiation Harden）.Sequence circuit is added at present
Gu scheme mainly includes system-level reinforcing, circuit-level is reinforced and domain level is reinforced, or is reinforced using techniques such as SOI.And
Circuit-level reinforcing is carried out for the trigger in sequence circuit, mainly uses triplication redundancy (Triple Modular at present
Redundancy, TMR) and double interlocking deposit structure (Dual Interlocked Storage Cell, DICE) technology and added
Gu.
The cardinal principle of TMR reinforcement techniques is that trigger is replicated into three parts, and the output of three flip-flop circuits is passed through into table
Certainly circuit formed a final output, due to voting circuit have three select two function.Therefore, even if there is trigger generation all the way
Upset, does not interfere with the output of whole circuit yet.And the principle of DICE reinforcement techniques is one double interlocking of addition in trigger
Structure is deposited, there are a pair of sensitive nodes in double interlocking deposits structure, the overall output of trigger is depending on this pair of sensitive nodes
Level.In the case of no irradiation, the level of this pair of sensitive nodes is consistent.And when receiving irradiation, a pair are sensitive
The output of circuit is able to maintain that constant when a node in node is produced upset by the effect of high energy particle, while another
In the presence of one sensitive nodes, the node of upset can be promptly restored to normal condition, so that whole circuit keeps stable, no
Irradiated influence.But the major defect of TMR circuits reinforcement technique and DICE circuit reinforcement techniques is that reliability is not high enough, it is assumed that
Do not use the upset probability of the trigger of circuit-level reinforcement technique for, do not considering sensitive nodes correlation and node to note
On the premise of entering electric charge tolerable differences, after being reinforced using TMR, the upset probability of trigger output drops to, and adopt
It is with the trigger upset probability of DICE reinforcement techniques.Therefore, in order to ensure the long-time normal work of circuit, general meeting
Reinforced using the DICE of circuit-level and system-level triplication redundancy reinforces the method combined, and will necessarily brought in this way
The rising at double of circuit area and power consumption, while can also cause the timing performance of circuit to deteriorate, working frequency declines.
The content of the invention
The purpose of this utility model is to provide a kind of radioresistance latch circuit based on C cell and transmission gate, and this is anti-
Radiation latch circuit overcomes the deficiencies in the prior art, employs multichannel latch technique, can make turning over for Latch output signal
Turn probability to decline to a great extent, while reduce the chip area of trigger, reduce power consumption, the anti-SET energy of circuit greatly improved
Power.
To reach above-mentioned purpose, technical scheme is used by the utility model solves its technical problem：One kind is mono- based on C
The radioresistance latch circuit of member and transmission gate, including clock generation circuit, D input filter circuits, C cell circuit and voting electricity
Road, the C cell circuit are made up of three tunnel identical circuits；It is characterized in that：The radioresistance latch circuit also includes multichannel and locked
Deposit circuit；Outside clock signal CK through clock generation circuit generate three road in-phase clock signal bclk1, bclk2 and bclk3 with
And three road inverting clock signal nclk1, nclk2 and nclk3；External data signal D generates three circuit-switched datas through D input filter circuits
Signal D1, D2 and D3；Three road in-phase clock signal bclk1, bclk2 and bclk3, three road inverting clock signal nclk1, nclk2
Multichannel latch cicuit is input to nclk3 and three circuit-switched data signal D1, D2 and D3, three ways are exported after multichannel latch cicuit
It is believed that number T1, T2 and T3；Two paths of data signal T1 and T2, T1 and T3, T2 and the T3 that multichannel latch cicuit exports are separately input to
Three road C cell circuits, the road C cell circuits of Bing You tri- produce data-signal Q3, Q2 and Q1 respectively, and data-signal Q1, Q2 and Q3 are defeated
Enter to voting circuit to export the output signal Q of whole trigger；
The multichannel latch cicuit be by 12 PMOS PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9,
PM10, PM11, PM12 and 12 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11,
NM12 and three transmission gate TM1, TM2, TM3 composition；Described PM7, PM8, NM7, NM8 and PM9, PM10, NM9, NM10 with
And PM11, PM12, NM11, NM12 separately constitute three C cells；
In the C cell of described PM7, PM8, NM7, NM8 composition, during the same phase that PM7 grid level generates with clock generation circuit
Clock signal bclk1 signal output part connection, PM7 drain electrode connect with PM8 source electrode, the grid of the PM8 and NM7 grid level
It is connected, and is connected with the data-signal D1 of D input filter circuits signal output part；The drain electrode leakage with NM7 respectively of the PM8
Extremely it is connected, the signal output part for the inverting clock signal nclk1 that grid and the clock generation circuit of the NM8 generate is connected, NM8
Drain electrode be connected with NM7 source electrode, NM8 source ground；
In the C cell of described PM9, PM10, NM9, NM10 composition, same phase that PM9 grid level and clock generation circuit generate
Clock signal bclk2 signal output part connection, PM9 drain electrode connects with PM10 source electrode, the grid of the PM10 and NM9's
Grid level is connected, and is connected with the data-signal D2 of D input filter circuits signal output part；The drain electrode of the PM10 respectively with
NM9 drain electrode is connected, the signal output part of the grid and the inverting clock signal nclk2 of clock generation circuit generation of the NM10
Connection, NM10 drain electrode are connected with NM9 source electrode, NM10 source ground；
In the C cell of described PM11, PM12, NM11, NM12 composition, PM11 grid level and clock generation circuit generate same
Clock signal bclk3 signal output part connection, PM11 drain electrode connects with PM12 source electrode, the grid of the PM12 and
NM11 grid level is connected, and is connected with the data-signal D3 of D input filter circuits signal output part；The drain electrode of the PM12 point
It is not connected with NM11 drain electrode, the signal of the grid and the inverting clock signal nclk3 of clock generation circuit generation of the NM12
Output end is connected, and NM12 drain electrode is connected with NM11 source electrode, NM12 source ground；
The in-phase clock signal that described transmission gate TM1, TM2, TM3 same phase control end generate with clock generation circuit respectively
Bclk1, bclk2, bclk3 signal output part connection, inverted control terminals respectively with clock generation circuit generation it is anti-phase when
Clock signal nclk1, nclk2, nclk3 signal output part connection；
Drain of the left side bidirectional data port of the transmission gate TM1 respectively with PM1 and NM1 is connected, right side bi-directional data
Port is connected with PM8 drain and PM2 grid level respectively；The left side bidirectional data port of the transmission gate TM2 respectively with PM3 and
NM3 drain is connected, and right side bidirectional data port is connected with PM10 drain and PM4 grid level respectively；The transmission gate TM3's
Drain of the left side bidirectional data port respectively with PM5 and NM5 is connected, right side bidirectional data port respectively with PM12 drain and
PM6 grid level is connected；
Described PM7, PM8, NM7, NM8 and PM9, PM10, NM9, NM10 and PM11, PM12, NM11, NM12 difference
Form in three C cells, respectively by three groups of clock signal nclk1, bclk1, nclk2 of clock generation circuit output, bclk2 and
Nclk3, bclk3 are controlled, when clock signal is effective, i.e., nclki=1 and bclki=0 when, three groups of data-signal D1, D2 and D3 transmission
Saved into multichannel latch cicuit, as nclki=0 and bclki=1, the latch signal in multichannel latch cicuit is kept not
Become and anti-phase tri- nodes of T1, T2 and T3 that are delivered to are input in three C cell circuits；
The grid of the PM1 is connected with PM6 and NM6 drain electrode and NM5 grid respectively, PM1 source electrode external power supply,
Drain electrode connects with NM1 drain electrode, PM6 and NM6 drain electrode outputting data signals T3；The grid of the PM2 and the transmission gate TM1 right side
Side bidirectional data port is connected, PM2 source electrode external power supply, and the drain electrode respectively with NM1 grid and NM2 that drains connects；It is described
PM3 grid is connected with PM2 and NM2 drain electrode and NM1 grid, PM3 source electrode external power supply, drain electrode and NM3 drain electrode
Connect, PM2 and NM2 drain electrode outputting data signals T1；The grid of the PM4 and transmission gate TM2 right side bidirectional data port
It is connected, PM4 source electrode external power supply, the drain electrode respectively with NM3 grid and NM4 that drains connects；The grid and PM4 of the PM5
The grid of drain electrode and NM3 with NM4 is connected, PM5 source electrode external power supply, and drain electrode connects with NM5 drain electrode, PM4 and NM4's
Drain outputting data signals T2；The grid of the PM6 is connected with transmission gate TM6 right side bidirectional data port, outside PM6 source electrode
Power supply is connect, the drain electrode respectively with NM5 grid and NM6 that drains connects；
Described NM1, NM2, NM3, NM4, NM5, NM5 source grounding.
In the above-mentioned technical solutions, three output signals T1, T2 and T3 of this radioresistance latch circuit, it is assumed that in particle
The lower T1 and T2 of effect is overturned, then and according to the operation principle of C cell circuit, Q1 and Q2 keep constant, Q3 output switching activities, and
After Q1, Q2 and Q3 input voting machine circuit, the output Q of whole circuit keeps constant.Therefore, three sensitive nodes of the trigger
Even if being overturned two, circuit output still keeps constant.This circuit has the advantages that：First, this circuit employs
A kind of new multichannel latch technique, one group of three sensitive nodes is provided with circuit structure, when in three sensitive nodes
When two nodes are overturn by irradiation, the output of circuit can remain unchanged, so that the upset probability of Latch output signal is big
Width declines；Second, this circuit uses multichannel latch technique, reduces the chip area of trigger, reduces power consumption；3rd, this
Circuit uses multichannel latch technique, greatly improves the anti-SET abilities of circuit.
Brief description of the drawings
Fig. 1 is a kind of theory structure block diagram of the radioresistance latch circuit based on C cell and transmission gate of the utility model；
Fig. 2 is clock generation circuit in a kind of radioresistance latch circuit based on C cell and transmission gate of the utility model
Circuit theory diagrams；
Fig. 3 is D input filter circuits in a kind of radioresistance latch circuit based on C cell and transmission gate of the utility model
Circuit theory diagrams；
Fig. 4 is multichannel latch cicuit in a kind of radioresistance latch circuit based on C cell and transmission gate of the utility model
Circuit theory diagrams；
Fig. 5 is the electricity of C cell circuit in a kind of radioresistance latch circuit based on C cell and transmission gate of the utility model
Road schematic diagram；
Fig. 6 is the electricity of voting circuit in a kind of radioresistance latch circuit based on C cell and transmission gate of the utility model
Road schematic diagram.
Embodiment
It is a kind of to the utility model based on the radioresistance latch of C cell and transmission gate electricity with reference to the accompanying drawings and examples
Road is described in further detail.The accompanying drawing for forming the application is used for providing further understanding to of the present utility model, and this practicality is new
The schematic description and description of type is used to explain the utility model, does not form to improper restriction of the present utility model.
From Fig. 1-Fig. 6, a kind of radioresistance latch circuit based on C cell and transmission gate of the present embodiment be by
Clock generation circuit（Clock generator）, D input filter circuits（D inputfilter）, multichannel latch cicuit, C cell
Circuit（C element）And voting circuit（voter）Composition.The tunnel identical circuit groups of C cell circuit Shi You tri- of the present embodiment
Into.In the present embodiment, outside clock signal CK through clock generation circuit generate three road in-phase clock signal bclk1, bclk2 and
Bclk3 and three road inverting clock signal nclk1, nclk2 and nclk3.External data signal D generates through D input filter circuits
Three circuit-switched data signal D1, D2 and D3；Three road in-phase clock signal bclk1, bclk2 and bclk3, three road inverting clock signals
Nclk1, nclk2 and nclk3 and three circuit-switched data signal D1, D2 and D3 are input to multichannel latch cicuit, through multichannel latch cicuit
After export three circuit-switched data signal T1, T2 and T3；Multichannel latch cicuit output two paths of data signal T1 and T2, T1 and T3, T2 and
T3 is separately input to three road C cell circuits, and the road C cell circuits of Bing You tri- produce data-signal Q3, Q2 and Q1, data-signal respectively
Q1, Q2 and Q3 are input to the output signal Q that voting circuit exports whole trigger.
From Figure 2 it can be seen that the clock generation circuit of the present embodiment（clock generator）It is responsible for leading to the CK signals of outside
Cross chain of inverters and generate three tunnel clock signals and corresponding inverting clock signal, three tunnel clock signals are due to by different anti-phase
Device chain has a different delays, its main purpose be in order that the input of CK ends SET (Single Event Transient,
SET) pulse reaches DICE at different moments (double interlocking deposits structure, Dual Interlocked Storage Cell, DICE)
Circuit part, by DICE mutual latch mechanism, circuit is set not influenceed by the SET on CK signals, while the circuit can also increase
The driving force of clock signal.
As seen from Figure 3, the D input filter circuits of the present embodiment（D input filter）It is responsible for leading to the D signals of input
Phase inverter and C cell circuit evolving three road signal D1, D2 and D3 is crossed to use for DICE circuits.The appropriate setting circuit of the present embodiment
In two phase inverters breadth length ratio, different delays can be obtained, so as to filter out the SET pulse of D inputs.
From Fig. 1, Fig. 4, the multichannel latch cicuit of the present embodiment be by 12 PMOS PM1, PM2, PM3, PM4,
PM5, PM6, PM7, PM8, PM9, PM10, PM11, PM12 and 12 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7,
NM8, NM9, NM10, NM11, NM12 and three transmission gate TM1, TM2, TM3 compositions.In the present embodiment, PM7, PM8,
NM7, NM8 and PM9, PM10, NM9, NM10 and PM11, PM12, NM11, NM12 separately constitute three C cells.
In the C cell of PM7, PM8, NM7, NM8 composition of the present embodiment, PM7 grid level and clock generation circuit generation
In-phase clock signal bclk1 signal output part connection, PM7 drain electrode connect with PM8 source electrode, the grid and NM7 of the PM8
Grid level be connected, and be connected with the data-signal D1 of D input filter circuits signal output part；The drain electrode of the PM8 respectively with
NM7 drain electrode is connected, the signal output part of the grid and the inverting clock signal nclk1 of clock generation circuit generation of the NM8
Connection, NM8 drain electrode are connected with NM7 source electrode, NM8 source ground.
In the C cell of PM9, PM10, NM9, NM10 composition of the present embodiment, PM9 grid level and clock generation circuit generate
In-phase clock signal bclk2 signal output part connection, PM9 drain electrode connects with PM10 source electrode, the grid of the PM10
It is connected with NM9 grid level, and is connected with the data-signal D2 of D input filter circuits signal output part；The drain electrode of the PM10
It is connected respectively with NM9 drain electrode, the signal of the grid and the inverting clock signal nclk2 of clock generation circuit generation of the NM10
Output end is connected, and NM10 drain electrode is connected with NM9 source electrode, NM10 source ground.
In the C cell of PM11, PM12, NM11, NM12 composition of the present embodiment, PM11 grid level and clock generation circuit are given birth to
Into in-phase clock signal bclk3 signal output part connection, PM11 drain electrode connects with PM12 source electrode, the grid of the PM12
Pole is connected with NM11 grid level, and is connected with the data-signal D3 of D input filter circuits signal output part；The leakage of the PM12
Pole is connected with NM11 drain electrode respectively, and the grid of the NM12 is with the inverting clock signal nclk3's of clock generation circuit generation
Signal output part is connected, and NM12 drain electrode is connected with NM11 source electrode, NM12 source ground.
During the same phase that transmission gate TM1, TM2, TM3 of the present embodiment same phase control end generate with clock generation circuit respectively
Clock signal bclk1, bclk2, bclk3 signal output part connection, what inverted control terminals generated with clock generation circuit respectively
Inverting clock signal nclk1, nclk2, nclk3 signal output part connection.
In the present embodiment, the drain of transmission gate TM1 left side bidirectional data port respectively with PM1 and NM1 is connected, and right side is double
It is connected respectively with PM8 drain and PM2 grid level to FPDP；Transmission gate TM2 left side bidirectional data port respectively with PM3
It is connected with NM3 drain, right side bidirectional data port is connected with PM10 drain and PM4 grid level respectively；A transmission gate TM3 left side
Drain of the side bidirectional data port respectively with PM5 and NM5 is connected, the right side bidirectional data port drain and PM6 with PM12 respectively
Grid level be connected.
PM7, PM8, NM7, NM8 and PM9 of the present embodiment, PM10, NM9, NM10 and PM11, PM12, NM11,
NM12 is separately constituted in three C cells, respectively by clock generation circuit output three groups of clock signals nclk1, bclk1,
Nclk2, bclk2 and nclk3, bclk3 controls, when clock signal is effective, i.e., nclki=1 and bclki=0 when, three groups of data-signals
D1, D2 and D3 are sent in multichannel latch cicuit and saved, as nclki=0 and bclki=1, in multichannel latch cicuit
Latch signal keeps constant and anti-phase tri- nodes of T1, T2 and T3 that are delivered to be input in three C cell circuits.The present embodiment
In, the anti-SEU principles of circuit are similar to DICE, when any sensitive nodes of circuit are overturned, due to the mutual latch mechanism of circuit,
The output of the tunnel of T1, T2 and T3 tri- can recover rapidly.
In the present embodiment, PM1 grid is connected with PM6 and NM6 drain electrode and NM5 grid respectively, outside PM1 source electrode
Power supply is connect, drain electrode connects with NM1 drain electrode, PM6 and NM6 drain electrode outputting data signals T3；The grid and transmission gate of the PM2
TM1 right side bidirectional data port is connected, PM2 source electrode external power supply, drain electrode respectively with NM1 grid and NM2 drain electrode phase
Connect；The grid of the PM3 is connected with PM2 and NM2 drain electrode and NM1 grid, PM3 source electrode external power supply, drain electrode and NM3
Drain electrode connect, PM2 and NM2 drain electrode outputting data signals T1；The grid of the PM4 and the transmission gate TM2 two-way number in right side
It is connected according to port, PM4 source electrode external power supply, the drain electrode respectively with NM3 grid and NM4 that drains connects；The grid of the PM5
The grid of drain electrode and NM3 with PM4 and NM4 is connected, PM5 source electrode external power supply, drain electrode connect with NM5 drain electrode, PM4 with
NM4 drain electrode outputting data signals T2；The grid of the PM6 is connected with transmission gate TM6 right side bidirectional data port, PM6's
Source electrode external power supply, the drain electrode respectively with NM5 grid and NM6 that drains connect.The NM1, NM2 of the present embodiment, NM3, NM4,
NM5, NM5 source grounding.
Fig. 5 is the C cell circuit of the present embodiment（C element）, as seen from Figure 5, when two signals of D1 and D2 are identical
When, C cell circuit exports Y and input signal D1, D2 is anti-phase equivalent to phase inverter.When D1 with D2 two paths of signals differences, pull-up
Network and pulldown network simultaneously switch off, and output Y relies on the electric charge of electric capacity storage, maintain output signal constant.
Fig. 6 is the voting circuit of the present embodiment（Voter）, as seen from Figure 6, when have in Q1, Q2 and Q3 two or two with
When upper signal is high level, output Q is high level, conversely, being low level when having two-way or two-way above signal in three road signals
When, output Q is low level.
Fig. 1 of the present embodiment can be seen that the radioresistance latch circuit of the present embodiment compared with DICE structure latch,
Three output signals T1, T2 and T3 of the present embodiment radioresistance latch circuit, it is assumed that T1 and T2 is overturned under particle effect,
Constant, Q3 output switching activities are so kept according to the operation principle of C cell circuit, Q1 and Q2, and Q1, Q2 and Q3 input voting machine are electric
Lu Hou, the output Q of whole circuit keep constant.Therefore, even if three sensitive nodes of the trigger are overturned two, circuit is defeated
Go out and still keep constant.
It is described above, only it is embodiment of the present utility model, not the utility model is imposed any restrictions, it is every according to this
Any simple modification, change and the change of equivalent method that utility model technical spirit is made to above example, still belong to
In in the protection domain of technical solutions of the utility model.
Claims (1)
1. a kind of radioresistance latch circuit based on C cell and transmission gate, including clock generation circuit, D input filter circuits,
C cell circuit and voting circuit, the C cell circuit are made up of three tunnel identical circuits；It is characterized in that：The radioresistance latch
Circuit also includes multichannel latch cicuit；Outside clock signal CK generates three road in-phase clock signals through clock generation circuit
Bclk1, bclk2 and bclk3 and three road inverting clock signal nclk1, nclk2 and nclk3；External data signal D inputs through D
Filter circuit generates three circuit-switched data signal D1, D2 and D3；Three road in-phase clock signal bclk1, bclk2 and bclk3, three tunnels are anti-phase
Clock signal nclk1, nclk2 and nclk3 and three circuit-switched data signal D1, D2 and D3 are input to multichannel latch cicuit, through multichannel
Three circuit-switched data signal T1, T2 and T3 are exported after latch cicuit；Multichannel latch cicuit output two paths of data signal T1 and T2, T1 and
T3, T2 and T3 are separately input to three road C cell circuits, and the road C cell circuits of Bing You tri- produce data-signal Q3, Q2 and Q1 respectively,
Data-signal Q1, Q2 and Q3 are input to the output signal Q that voting circuit exports whole trigger；
The multichannel latch cicuit be by 12 PMOS PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9, PM10,
PM11, PM12 and 12 NMOS tubes NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12 with
And three transmission gate TM1, TM2, TM3 compositions；Described PM7, PM8, NM7, NM8 and PM9, PM10, NM9, NM10 and
PM11, PM12, NM11, NM12 separately constitute three C cells；
In the C cell of PM7, PM8, NM7, NM8 composition, PM7 grid level and the in-phase clock of clock generation circuit generation are believed
Number bclk1 signal output part connection, PM7 drain electrode connect with PM8 source electrode, the grid of the PM8 and NM7 grid level phase
Even, and it is connected with the data-signal D1 of D input filter circuits signal output part；The drain electrode drain electrode with NM7 respectively of the PM8
It is connected, the signal output part for the inverting clock signal nclk1 that grid and the clock generation circuit of the NM8 generate is connected, NM8's
Drain electrode is connected with NM7 source electrode, NM8 source ground；
In the C cell of PM9, PM10, NM9, NM10 composition, PM9 grid level and the in-phase clock of clock generation circuit generation
Signal bclk2 signal output part connection, PM9 drain electrode connect with PM10 source electrode, the grid of the PM10 and NM9 grid level
It is connected, and is connected with the data-signal D2 of D input filter circuits signal output part；The drain electrode of the PM10 is respectively with NM9's
Drain electrode is connected, and the signal output part for the inverting clock signal nclk2 that grid and the clock generation circuit of the NM10 generate is connected,
NM10 drain electrode is connected with NM9 source electrode, NM10 source ground；
In the C cell of described PM11, PM12, NM11, NM12 composition, during the same phase that PM11 grid level generates with clock generation circuit
Clock signal bclk3 signal output part connection, PM11 drain electrode connects with PM12 source electrode, the grid of the PM12 and NM11's
Grid level is connected, and is connected with the data-signal D3 of D input filter circuits signal output part；The drain electrode of the PM12 respectively with
NM11 drain electrode is connected, the signal output of the grid and the inverting clock signal nclk3 of clock generation circuit generation of the NM12
End connection, NM12 drain electrode are connected with NM11 source electrode, NM12 source ground；
The in-phase clock signal that described transmission gate TM1, TM2, TM3 same phase control end generate with clock generation circuit respectively
Bclk1, bclk2, bclk3 signal output part connection, inverted control terminals respectively with clock generation circuit generation it is anti-phase when
Clock signal nclk1, nclk2, nclk3 signal output part connection；
Drain of the left side bidirectional data port of the transmission gate TM1 respectively with PM1 and NM1 is connected, right side bidirectional data port
It is connected respectively with PM8 drain and PM2 grid level；The left side bidirectional data port of the transmission gate TM2 respectively with PM3 and NM3
Drain be connected, right side bidirectional data port is connected with PM10 drain and PM4 grid level respectively；A left side of the transmission gate TM3
Drain of the side bidirectional data port respectively with PM5 and NM5 is connected, the right side bidirectional data port drain and PM6 with PM12 respectively
Grid level be connected；
Described PM7, PM8, NM7, NM8 and PM9, PM10, NM9, NM10 and PM11, PM12, NM11, NM12 are separately constituted
In three C cells, respectively by three groups of clock signal nclk1, bclk1, nclk2 of clock generation circuit output, bclk2 and
Nclk3, bclk3 are controlled, when clock signal is effective, i.e., nclki=1 and bclki=0 when, three groups of data-signal D1, D2 and D3 transmission
Saved into multichannel latch cicuit, as nclki=0 and bclki=1, the latch signal in multichannel latch cicuit is kept not
Become and anti-phase tri- nodes of T1, T2 and T3 that are delivered to are input in three C cell circuits；
The grid of the PM1 is connected with PM6 and NM6 drain electrode and NM5 grid respectively, PM1 source electrode external power supply, drain electrode
Connect with NM1 drain electrode, PM6 and NM6 drain electrode outputting data signals T3；The grid of the PM2 is double with transmission gate TM1 right side
It is connected to FPDP, PM2 source electrode external power supply, the drain electrode respectively with NM1 grid and NM2 that drains connects；The PM3's
Grid is connected with PM2 and NM2 drain electrode and NM1 grid, PM3 source electrode external power supply, and drain electrode connects with NM3 drain electrode,
PM2 and NM2 drain electrode outputting data signals T1；The grid of the PM4 is connected with transmission gate TM2 right side bidirectional data port,
PM4 source electrode external power supply, the drain electrode respectively with NM3 grid and NM4 that drains connect；The grid of the PM5 and PM4 and NM4
Drain electrode and NM3 grid be connected, PM5 source electrode external power supply, drain electrode connects with NM5 drain electrode, PM4 and NM4 drain electrode
Outputting data signals T2；The grid of the PM6 is connected with transmission gate TM6 right side bidirectional data port, the PM6 external electricity of source electrode
Source, the drain electrode respectively with NM5 grid and NM6 that drains connect；
Described NM1, NM2, NM3, NM4, NM5, NM5 source grounding.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109361387A (en) * | 2018-08-02 | 2019-02-19 | 合肥工业大学 | A kind of low cost triplication redundancy latch |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109361387A (en) * | 2018-08-02 | 2019-02-19 | 合肥工业大学 | A kind of low cost triplication redundancy latch |
| CN109361387B (en) * | 2018-08-02 | 2022-02-22 | 合肥工业大学 | Low-cost triple-modular redundancy latch |
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